(Ebook - Electronics) - Principles of PLL - Tutorial (Kroupa 2000)
(Ebook - Electronics) - Principles of PLL - Tutorial (Kroupa 2000)
(Ebook - Electronics) - Principles of PLL - Tutorial (Kroupa 2000)
(PLL)
(TUTORIAL)
VĚNCESLAV F. KROUPA
I. Principles
The task of the phase locked loops is to maintain coherence between input
(reference) signal frequency, fi, and the respective output frequency, fo, via
phase comparison. The theory is explained in many textbooks [e.g., 1, 2] and
practically in all books on frequency synthesis. [3 through 10]. Here, we shall
repeat, in short, all major features with some new achievements.
A/ Basic equations
Each PLL loop works as a feedback system shown in Fig. 1.
1
To get more insight into the PLL properties, we shall simplify,
without any loss of generality, the block diagram to that shown in Fig. 2.
and introduce the Laplace transfer functions of the individual building
circuits - suitable for investigation of small signal properties.
Investigation of the above figure reveals that the input phase Œi(t) is
compared with the output phase Œo(t) in phase detector (ring modulator,
sampling circuit, etc.).
(1)
2
Next, vd(t) passes the loop filter, F(s)
(2)
where hf(t) is the time response of the loop filter. After applying v2(t) on
the frequency control element of the voltage controlled oscillator (VCO) we
get the output phase
(3)
the relation between input and output phase in the Laplace transform
(4)
(5)
(6)
B/ Order of PLL
3
In the simplest case there are no filters both in forward and feedback paths.
(7)
C/ Type of PLL
The number of poles in the transfer function G(s), i.e. the number of
integrators in the loop define the
type of the loop
(8)
where
(9)
(10)
4
By assuming the gain, G(s), as a ratio of two polynomials
(11)
(12)
(13)
After introducing any of the respective steps into (10 or 12) and performing
the inverse Laplce transform we find the respective transients
With the assistance of the Laplace limit theorem we get for the final value
of the phase error
(14)
5
F/ Block diagram algebra
Actual PLLs are often much more complicated than block diagrams in
Fig. 1 or 2
(15)
or
(16)
6
Fig. 3 Simplification of the block diagrams of PLL: a/ series connection, b/ parallel
connection, c/ and d/ feedback arrangement, e/ more complicated system.
7
The most common PLLs are those of the 2nd order. Their advantage is the
absolute stability and simple theoretical and practical design.
(17)
(18)
Note that DC gain KA can be used for changing the corner frequency, of this simple
PLL, to any desired value - Fig. 4.
Since the open loop gain K has dimension of the 2_Hz normalization of the
8
input or reference frequency in respect to it provides nearly all information
about the behaviour of the PLL.
(19)
10
10
10
Hi
m
Ho
m
20
[dB]
30
40 40
0.01 0.1 1 10 100
0.01 x 100
m
9
B/ PLLs of the 2nd order.
1st order PLL has only one degree of freedom, namely the DC gain
K=KdKoKA
This last problem can be removed with introduction of a suitable low pass
filter into the forward path.
10
The open loop gain is
(20)
(21)
(22)
(23)
(24)
11
After normalization of the frequency q in respect to the natural frequency
(25)
(26)
(27)
10
10
Hi 20
m
Ho
m
30
dB 40
.
50
60
0.01 0.1 1 10 100
x
m
80
100
120
ψ
m
140
160
180
0.01 0.1 1 10 100
x
m
12
with a simple RC filter.
(2) Phase lag-lead or RRC filter (Fig. 8)
(28)
(29)
(30)
13
We can again introduce the natural frequency and the damping factor
(31)
(32)
and to
(33)
Note that the freedom for independent choice of qn and K resulted in reduced slope of
the stop band of H(jx) on one hand and in a reduced phase margin on the other hand
10
10
Hi 20
m
Ho
m
30
[dB]
40
50
60
0.01 0.1 1 10 100
x
m
90
100
110
120
ψ 130
m 140
150
160
170
180
0.01 0.1 1 10 100
x
m
Fig. 9(a)
Transfer functions Hi(jx) = 20log(|H(jx)|) and Ho(jx) = 20log(|1-H(jx)|), (b)
phase characteristic of the open loop gain G(jx) of the 2nd order PLL loop
with an RRC filter.
14
C/ PLLs of the 2nd order of the type 2.
The loop contains two integrators, the second one in the loop filter
Fig. 10 2nd order PLL loop filters: active phase-lag lead network
( dashed is one of the 3rd order loop configuration).
(34)
(35)
(36)
15
=KdKAKoA The PLL transfer function
(37)
(38)
from which
(39)
(40)
After plotting the transfer functions Hi(x) and Ho(x) we find out that they
coincide with those plotted in Fig. 9 for the PLL with the gain K (high gain
loops). However, we find a substantial difference with the phase
characteristic which starts, due to the two integrators in G(s), at nearly -
180 degrees. This is very important in instances with unintentionally
introduced poles or delays, due to the use of sampled phase detectors, into
the loop gain G(s) since the stability of the system deteriorates. The
problem will be discussed in the next sections.
16
10
10
Hi 20
m
Ho
m
30 a)
40
[dB]
50
60
0.01 0.1 1 10 100
x
m
90
100
110
120
130
ψ
m 140 b)
150
160
170
180
0.01 0.1 1 10 100
x
m
17
III. Phase locked loops of the 3rd order type 2.
Investigation of Figs 7, 9, and 11 reveals PLL of the 2nd order with simple
RC filter exhibits the slope of the transfer function
Hi(jx) in the stop band of -40 dB/dec.
But the high gain RRC loops have the slope
of 40 dB/dec. in the stop band of the Ho(jx) transfer function.
(41)
Note that even this 3rd order loop is unconditionally stable since G(s)
exhibits a positive phase margin.
(42)
(43)
The transfer functions together with the phase margin are plotted in Fig. 12
18
20
20
10
10
Hi
m
20
Ho
m
30
ψ 100
m
Go 40
m
50
60
70
80 80
0.01 0.1 1 10 100
0.01 x 100
m
Fig. 13 Properties of the 3rd order PLL for different damping constants of
the original 2nd order loop and for different S of the additional RC section:
a) phase of the open loop gain; b) magnitude of the overshoot Mp of the
transfer function 20log(|H(jx)|2).
19
IV. Time delays in PLL.
A/ Simple time delay
Simple time delay, g, is respected by multiplying the open loop gain by the factor
(44)
Evidently it only changes the phase margin. From Fig. 14 we see that its influence
might be considerable [11].
20
B/ Sampling
In modern technology many analog processes are replaced with digital processing
The proper approach would be the investigation with the assistance of the z-
transform .
The other possibility is to modify the original Laplace transform of G(s)
(45)
where
(46)
and
(47)
Evidently
(48)
and
(49)
21
Fig. 15 a) block diagram of the PLL with sampling phase detector;
b) the simulating analog system
He
m
Hf
m
10
ψe
m
ψf
m
20
30 30
0.1 1 10 100
.1 x 100
m
22
20
20
10
Hi 10
m
Ho 20
m
ψ 100
m 30
Go
m 40
χ
m
50
60
70
80 80
0.01 0.1 1 10 100
0.01 x 100
m
Note the reduced phase margin for the case where the
ratio of the natural frequency qn to sampling frequency qs is
1:10
23
V. Responses of PLL to the step and periodic phase and
frequency changes.
The information provides the phase difference at the output of the phase
detector je(s) or more exactly Œe(t). Since je(s)/ji(s) = 1-H(s) we must
investigate the following relation
(50)
A) Step changes
(1) Phase step Fki at the input of the phase detector (ji(s)=F ji/s).
(51)
(52)
After application of the Laplace transform tables (e.g. [12]) and the above roots we get
(53)
24
Fig. 18 Normalized transients Fke1(t)/Fki due to the phase step
Fki for different damping factors K ;
a) for simple RC loop filter;
25
b) for high gain loop with lag lead RC filter.
(2)Frequency step Fqi at the input of the phase detector (qi(s)=F qi/s2).
After a step change of the division ratio N in the feedback path by FN the
effective change of the “feedback reference frequency “ is Ffr = fr FN/N. The
consequence is the transient in the output phase ke(t).
(54)
Application of the roots from (52) and of the Laplace transform tables gives
(55)
Which simplifies for very high gain and the type 2 loops
(56)
26
Fig. 19 Normal
ized transie
nts Fke2(t)/(Fqi/qn) due to the frequency step Fqi for different damping
factors K for high gain loop with lag lead RC filter; a) for simple RC loop
filter; b) for high gain loop with lag lead RC filter.
27
In this case we get
(57)
(58)
Fig.
20
Nor
maliz
2
ed transients Fke3(t)/(F i/qn ) due to the frequency ramp F i for
different damping factors K for high gain loop (DC phase error is retained).
28
2) Periodic changes.
In these instances we are interested in settled or steady states
(59)
(60)
In instances where PLL should be used as phase detector then the desired
information must be recovered at the output of the loop detector, however,
only for frequencies outside of the pass band ,i.e. for }>qn.
(61)
(62)
29
VI. Stability of PLL
Since PLL are feedback systems with the feedback transfer function G(s)
they will oscillate whenever the gain G(s) is equal to minus 1, i.e.
(63)
(64)
i.e. for
(65)
and
(66)
Investigation of the 1st and 2nd order loops reveals unconditionally stabile.
However, this need not be the case with higher order loops.
(68)
(69)
30
A) Hurwitz criterion of stability
(70)
(71)
31
Root-locus method of the function 1+G(s) is intended to find location
of the respective roots in the complex plain.
At present computer solution of the polynomial of Pn(s), with the
changing parameter K or any other, provides us with a set of roots which
can be thereafter plotted in the complex plain.
Example: We will plot roots of the 2nd order PLL with the open loop gain
(72)
(73)
The above equation is that of the circle with the center, -1/T2, 0, and the
radius r2 = 1/T22 - 1/T1T2. After introducing the loop parameters qn and K
the root locus is their function.
32
Transfer functions of individual PLL blocks provide information about all
important properties of
33
Fig. 26 Bode plots for 1/ Frequency independent gain K=KdKAKo ,
2/ Factor with one zero in the origin jq, 3/ Factor with one pole in the origin
1/jq: A/ Decibel gain, B/ phase
34
Fiug. 27 Bode plot of the function 1+jqTo
35
In Fig. 29 we compare an old Bode plot construction with
a)
20
20
10
10
20
20 .log G
m
30
ψ 100
m
40
50
60
70
80 80
0.1 1 10 100
.1 x 100
m
36
VII. Phase locked loops of the 4th and higher orders.
We have seen that the 2nd and 3rd order loops were unconditionally stable
A/ Twin-T RC filter
(74)
(75)
37
we get for the “resonant” frequency, qrf,
(76)
For the input resistance Ri << R and the output resistance Rout >> R
(77)
0
0
18
27
36
20 .log G2
m
45
ψ2
m
54
63
72
81
90 90
0.1 1 10
.1 x 10
m
38
Investigation of the properties of these PLL will be started with the normalized open loop
gain of the second order loop-type two, G2(jx),
(78)
(79)
where we have introduced the “resonant” frequency frf and the sampling frequency fs
(80)
(81)
39
The transfer functions Hi(x) and Ho(x) are plotted in Fig. 32 togther with
the open loop gain G(jx) and the phase margin |(jx) for L =.1 and T = .05;
Note that the phase margin is small, 20 deg., only. In addition both transfer
functions have peaks of about 10 dB which indicates under damping.
10
10
10
Hi 20
m
Ho 30
m
ψ 100
m 40
20 .log G
m
50
60
70
80 80
0.1 1 10 100
0.1 x 100
m
40
From different configurations we shall investigated the only one shown
Its transfer function with a very large gain of the operation amplifier is
(82)
(83)
and damping d
(84)
41
(85)
which is plotted in Fig. 34 for different damping constants together with the respective
phase characteristics.
Fig. 34 a/ Transfer functions of the active 2nd order low pass filter; b/ its phase
characteristics.
42
20
20
10
10
Hi
m
20
Ho
m
30
ψ 100
m
20 .log G 40
m
50
a)
60
70
80 80
0.01 0.1 1 10 100
0.01 x 100
20 m
20
10
10
Hi
m
20
Ho
m
30
ψ 100
m
20 .log G 40
m
50
60
70 b)
80 80
0.01 0.1 1 10 100
0.01 x 100
m
Loop of the type 3 are encountered rarely for special services only. For the sake of
43
simplicity we will consider two active RRC filters (see Fig. 10) in series.
(86)
After introducing the natural loop frequency qn and the damping factor K we can change
the above relation into
(87)
20
0 ψ [degrees]
20
40 -160
Hi
m
60
Ho
m
80 -180
ψ 100
m
20 .log G 100
m
120
-200
140
160 -220
180
0.01 0.1 1 10 100
x
m
44
generators are often limiting factors for many applications even in PLL’s.
(88)
(89)
where
(90)
1) Phase measures
(91)
(92)
45
(93)
2) Frequency measures
(94)
However, this is not the case with the 2nd moment which can be defined as
(95)
(96)
(97)
46
problem is solved with sample variances which provide other and very
effective frequency stability measures. Nevertheless, in actual practice we
encounter the Allan variance ( two sample variance) defined as
(98)
(99)
where
(100)
Frequency stability defined in the frequency and time domain measures are
related with the assistance of a transfer function
(101)
The difficulty is that we can evaluate the integral in (102), in the closed form,
only for a very particular form of Sy(f), namely a piece-wise linearized
(102)
47
Fig. 37 Piece- wise
linearized noise characterist
ic of a 5 MHz crystal
oscillator
Note two dB measures on the vertical axis: the on the r.h. side are values of
Sk (f), however, that on the l.h. side retains slopes of the Sk (f), but it is
invariant in respect to the carrier frequency as Sy (f). Consequently we can
compare noise characteristics of different generators in one and the same figure.
48
All important noise processes, generally encountered
by evaluating the frequency instability, are
ho ho/2g Kho/4ngo
49
C/ Noise in oscillators
1/ Crystal oscillators
The resonator circuit exhibits the flicker and white noise
(104)
(105)
(106)
(107)
and the plateau in the Allan variance is approximately for all quartz crystal
resonators (since generally ar > ae)
(108)
50
2/ LC oscillators
The relation (106) is also valid for LC oscillators. For the mean values we
can write
(109)
Note that the coefficients hi (see 103) are mean values form experimental
measurements. Actual noise coefficients can differ by -2 to +1 order
51
D/ Noise in digital frequeny dividers
(110)
For GaAs divider family the above relation requires only a small correction
in the first term
(111)
We expect that these formulae can be also used for appreciation of the noise
quality of actual devices.
a) b)
Fig. 38 a) Flicker phase noise of TTL and ELC digital dividers b) white
phase noise of TTL and ELC digital dividers.
52
E/ Noise in Phase detectors and amplifiers
For a preliminary estimation we can apply an experimentally found relation
(112)
(113)
orders higher; the reason is Johnson noise generated in the filter resistors.
Consequently
Example : K = .1, Kd = 5/2_, Cmax = 10-6, T1/T2 = 10: S K 10 -
k,L
13/f
n
Fig. 39 PSD Sk,L of the additive noise of different PLL’s together with
practical (full line) and theoretical limits (R).
53
G/ Noise in PLL
54
By assuming a locked loop we can write with the assistance of the Laplace
transform for the linearized arrangement
(114)
where
(115)
Since most of the noise components are random by nature and uncorrelated
the PSD of the PLL output phase is
(116)
All the additive noises, due to the phase detector, loop frequency dividers,
loop amplifiers, and loop filters can be summarized into a PSD SL(f)
(117)
55
6 7
Phase locked loop fi = 9.976.10 fo = 9.491.10
fn = 861.078
1.9 fo
ζ .7 Kd Ko M 0 δ .1 κ .2 Kd = 0.302
2 .π 10.Qo 4
Ko = 1.898.10
4 .r fi fo
r 2 Dr a fr N
Dr fr Dr = 4
α 0.15 d 0.6 6
fr = 2.494.10
fm j .xm .2 .ζ 1 1
xm Gm Gam j .x .δ
m
fn 2 2 Gem 1 .e
j .xm 1 j .xm .α .2 .d j .xm .α 1
g3m
G5m 1 2 .j .ζ .xm .κ
G5m Gm .Gam .Gem .g3m H5m
1 G5m
13 9
10 10
Sφ m 2
fm fn N
Hφ m 10.log Sφ m .
2 2 2
fo
N . fi N 2 2.
hv m him . M Sφ m . .1 . H5
m
ho m . 1 H5m 1
Dr fo fo
hout m 10.log hv m
2
Sout m hout m 10.log fo
10
10
Sout 30
m
Si 50
m
So 70
m
10 .log Sφ
m 90
20 .log H5
m
110
20 .log 1 H5
m
130
150
170
3 4 5 6 7
0.01 0.1 1 10 100 1 .10 1 .10 1 .10 1 .10 1 .10
f
m
56
IX. Acquisition
Working ranges of PLL
(115)
Let us assume that the difference between the reference frequency qi and
the free running VCO frequency qc is larger than FqP the result is a beat
(116)
evidently
(117)
After taking into account the feedback properties of PLL and the principle
of the harmonic balance we get for the 2nd order type 2 loops
(118)
57
(120)
(121)
(122)
(123)
Note that it exists certain delay for which the pull-in range is zero. This is
illustrated with Fig. 42 and 43. The oscillating branch in Fig. 42 indicates
the possibility of false locks.
58
Fig. 42 Normalized detuning xc=ic/qn as function of x=i/qn for PLL of
the 2nd order type 2 for two amplifier gains and different delays
59
Fig. 43 Normalized pull-im range xP = FqP/qn for PLL of the 2nd order
type 2 for two amplifier gains and normalized delay
(points were found by computers).
(125)
(126)
(127)
c) PLL of the 2nd order with RRC filter (high gain loops)
(128)
From investigation of the transients due to the frquency step we get for its
maximum
(129)
60
and finally
(130)
5) False locks
(131)
Additional filtering or time delays may cause n >_ /2 which will change
the sign of the slowly varying tuning voltage u2(t) and starts to push the
loop out of lock and in some instances lock the VCO on a false frequency cf.
Fig.45
61
Fig. 45 The DC component Fq/K in the pull-in process:
a)PLL of the 4th order Type 2 with two additional sections RC;
b) PLL of the 3rd order Type 2 with additional time delay
(K=.7, S=.3).
6) Pull-in time
Solution will start with the simplified block diagram in Fig. 44. Note that
the AC path is responsible for the magnitude of the beat note Yc.
Furthermore we will assume the 2nd order loop with RRC filter with the
reduced gain
(132)
62
Finally we arrive at an approximate pull-in time for the sine wave PD
(133)
with sligh
tly diffe
rent value
s for other
types of
phase detec
tors - see
Fig. 46
63
Fig. 46 Asymptotic approximations of the pull-in time for PLL
of the 2nd order : a) for a simple phase detector; b) for a phase-frequency
detector for two different damping constants
References:
[1] F.M. Gardner: Phaselock Techniques. New York: J. Wiley, 1966, 2nd
ed 1979
[2] W.F. Egan, Frequency Synthesis by Phase Lok, New York: J. Wiley,
1998, 2nd ed. 2000.
[3] V. F. Kroupa, Frequency Synthesis: Theory, Design et Applications.
London: Ch. Griffin, 1973; New York: J. Wiley, 1973.
[4] V. Manassewitsch, Frequency Synthesizers, Theory and Design. New
York: Wiley, 1976, 1980.
[5] W.F. Egan, Frequency Synthesis by Phase Lock. New York: Wiley 1981.
[6] U.L. Rohde, Digital PLL Frequency Synthesizers, Theory and Design.
Englewood Clifs: Prentice Hall, 1983.
[7] J.A. Crawford, Frequency Synthesizer Design Handbook.
Boston/London: Artech House, 1994.
[8] Bar-Giora Goldberg, Digital Techniques in Frequency synthesis. New
York: MacGraw-Hill, 1996.
[9] U.L. Rohde, Microwave and Wireless Synthesizers, Theory and Design.
John Wiley 1997. [10] V.F. Kroupa , ed. Direct Digital Frequency
Synthesizers. IEEE Press 1999.
[11] V.F. Kroupa, Theory of Phase-Locked Loops and Their Applications
in Eectronics, Praha: Academia 1995 (in Czech).
[12] G.A. Korn and T.M. Korn: Mathematical Handbook for Scientists
and Engineers. New York : McGraw-Hill, 1961.
[13] E.J. Angelo, “A Tutorial Introduction to Digital Filtering,” The Bell
System Technical Journal, Vol. 60, No. 7, September 1981.
Acknowledgment.
This work has been supported by the Grant Agency of the Czech republic
64
under the contract No. 102/00/0958.
65