Digital Control Board For Phased Array Antenna Beam Steering in A

DIGITAL CONTROL BOARD FOR PHASED ARRAY ANTENNA BEAM
STEERING IN ADAPTIVE COMMUNICATION APPLICATIONS
A Thesis
presented to
the Faculty of California Polytechnic State University
San Luis Obispo
In Partial Fulfillment
of the Requirements for the Degree
Master of Science in Electrical Engineering
by
Mayur Bansal
November 2013
c 2013

Mayur Bansal
ALL RIGHTS RESERVED
ii
COMMITTEE MEMBERSHIP
TITLE:
Digital Control Board for Phased Array

Antenna Beam Steering in Adaptive Communication Applications
AUTHOR:
Mayur Bansal
DATE SUBMITTED:
November 2013
COMMITTEE CHAIR:
Bryan Mealy, Ph.D.

Associate Professor
Electrical Engineering Department
COMMITTEE MEMBER:
Lynne Slivovsky, Ph.D.

Professor
COMMITTEE MEMBER:
Dennis Derickson, Ph.D.

Department Chair
iii
ABSTRACT
Digital Control Board for Phased Array Antenna Beam Steering in Adaptive
Communication Applications
Mayur Bansal
The application of adaptive communication techniques for mobile communications has attracted considerable interest in the last decade. One example of
these techniques is spatial filtering through planar antenna array beam forming.
This thesis describes the development of a digital system that adaptively
controls a phased array antenna. The radiating structure of the phased antenna
array is tetrahedral-shaped and contains four antenna elements on each of its
three faces. The overall system comprises of a digital control board with an
external computer interface, an RF control board, and the phased antenna array.
The RF controls the main lobe direction on the phased array antenna. This thesis
describes the design and implementation of the digital control board.
The digital control boards primary responsibilities are implementing interfaces between the external computer and the RF board, which results in two
operational modes: the MATLAB graphical user interface (GUI) mode and the
adaptive receive mode. The GUI mode allows users to input parameters that
provide interactive control of the phased antenna array by interfacing with an
external computer and the RF control board. The adaptive receive mode implements an algorithm for an adaptive receive station. This algorithm uses a
58-point scanning technique that locates the maximum receive power direction.
Test results show that the digital control board successfully manages the RF
board control voltage with an nominal error of less than 1%, which subsequently
iv
allows for precise control of the antennas active face. Additionally, testing of
the GUI demonstrated the successful interactive application of various system
control parameters.
ACKNOWLEDGMENTS
I would like to thank my parents, Meenakshi and Bharat, for encouraging and
allowing me to pursue my ambitions. I am also grateful to my entire family for
their continual support.
I would like to thank my advisor, Dr. Dean Arakaki, for his guidance and
support. I would also like to thanks my project partner Steve Brockhoff for his
hard work and help, which made this thesis possible.
vi
TABLE OF CONTENTS
LIST OF TABLES
ix
LIST OF FIGURES
1 INTRODUCTION
2 SYSTEM DESIGN
2.1
2.2
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1
GUI Control . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2
Adaptive Receive Mode . . . . . . . . . . . . . . . . . . .
System Sub-blocks . . . . . . . . . . . . . . . . . . . . . . . . . .
10
2.2.1
RF Power Detector . . . . . . . . . . . . . . . . . . . . . .
10
2.2.2
Interrupt Feedback Loop . . . . . . . . . . . . . . . . . . .
10
3 RF POWER DETECTOR
12
3.1
LT-5534 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
3.2
LT-5538 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
3.3
Log-Amp Power Detector Analysis . . . . . . . . . . . . . . . . .
18
4 INTERRUPT FEEDBACK LOOP
19
4.1
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
4.2
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
4.3
DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
4.4
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
5 RF SYSTEM INTEGRATION
29
5.1
Phase Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
5.2
RF Single Pole Double Throw (SPDT) Switch . . . . . . . . . . .
34
5.3
RF Single Pole Triple Throw (SP3T) Switch . . . . . . . . . . . .
35
5.4
Voltage Control Oscillator (VCO) Control Line . . . . . . . . . .
36
vii
6 PRINTED CIRCUIT BOARD DESIGN
39
6.1
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
6.2
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
7 GRAPHICAL USER INTERFACE (GUI) CONTROL SYSTEM

7.1
42
GUI Inputs and Features . . . . . . . . . . . . . . . . . . . . . . .
43
7.1.1
Drop Down Menus . . . . . . . . . . . . . . . . . . . . . .
43
7.1.2
Edit Text . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
7.1.3
Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . .
49
7.1.4
Additional Figure Checkboxes . . . . . . . . . . . . . . . .
50
7.2
Communication Protocol . . . . . . . . . . . . . . . . . . . . . . .
51
7.3
Test and Results . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
8 ADAPTIVE RECEIVE MODE
58
8.1
Adaptive Receive Algorithm . . . . . . . . . . . . . . . . . . . . .
58
8.2
Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
9 CONCLUSIONS AND FUTURE WORK
65
BIBLIOGRAPHY
67
APPENDICES
69
2013 IEEE APS Student Design Challenge: Reconfigurable Antennas 69
Contest Proposal . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
LT 5534 Demo Board Schematic . . . . . . . . . . . . . . . . . . .
75
LT 5538 Demo Board Schematic . . . . . . . . . . . . . . . . . . .
77
Microcontroller Code . . . . . . . . . . . . . . . . . . . . . . . . .
79
PCB Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
Bill Of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
viii
LIST OF TABLES
2.1
16-Pin IDC Pin-out Between Digital Control Board and RF Board
4.1
ADC Conversion Time . . . . . . . . . . . . . . . . . . . . . . . .
22
4.2
ADC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
23
4.3
Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . .
23
4.4
DAC Command Codes . . . . . . . . . . . . . . . . . . . . . . . .
26
4.5
DAC Address Codes . . . . . . . . . . . . . . . . . . . . . . . . .
26
5.1
Truth Table for SPDT, VHIGH = 2V to 5V, VLOW = 0V Insertion

Loss = 0.5dB, and Isolation = 22dB . . . . . . . . . . . . . . . .
34
5.2
SPDT, Antenna Mode Truth Table . . . . . . . . . . . . . . . . .
35
5.3
Truth Table for HMC245QS16 and the Active Antenna Face . . .
36
5.4
VCO Tuning Circuit Result . . . . . . . . . . . . . . . . . . . . .
38
7.1
Hexadecimal Notation for ASCII Decimal Characters to 8-bit Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
7.2
GUI Test Result . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
8.1
Test Data for Adaptive Receive Mode Test Procedure . . . . . . .
63
ix
LIST OF FIGURES
1.1
A Radiation Diagram with Main Lobe . . . . . . . . . . . . . . .
2.1
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Tetrahedron Antenna Model . . . . . . . . . . . . . . . . . . . . .
2.3
Digital Control Board Block Diagram . . . . . . . . . . . . . . . .
2.4
IDC connector Pin Positions . . . . . . . . . . . . . . . . . . . . .
2.5
Screen shot of MATLAB GUI . . . . . . . . . . . . . . . . . . . .
2.6
Adaptive RX, Example System Configuration . . . . . . . . . . .
2.7
Inner Feedback Loop Block Diagram . . . . . . . . . . . . . . . .
11
3.1
DC log-amp BJT implementation . . . . . . . . . . . . . . . . . .
13
3.2
Demo Board DC748A . . . . . . . . . . . . . . . . . . . . . . . . .
14
3.3
LT-5534 log-amp Characteristics . . . . . . . . . . . . . . . . . . .
15
3.4
Demo Board DC1120A . . . . . . . . . . . . . . . . . . . . . . . .
16
3.5
LT-5538 Output characteristics . . . . . . . . . . . . . . . . . . .
17
4.1
Analog to Digital Converter Timing Diagram for Single Conversion

Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
4.2
LTC2656 DAC Load Sequence . . . . . . . . . . . . . . . . . . . .
25
4.3
LM339 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . .
28
5.1
JSPHS-2484+ Phase Shifter, Interpolated Data . . . . . . . . . .
30
5.2
Operational Amplifier in Non-Inverting Configuration . . . . . . .
30
5.3
LTSpice Simulation Schematic, LT6005 Non-Inverting Gain OpAmp Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
LTSpice Simulation results, LT6005 Op-amp Non-Inverting Gain

Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
5.4
5.4
LTSpice Simulation results, LT6005 Op-amp Non-Inverting Gain

Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
5.5
Monte Carlo Analysis for Amplification Circuit, Expanded View .
33
5.6
AS179-92LF, SPDT, Pin-out and Block Diagram . . . . . . . . .
34
5.7
HMC245QS16 SP3T RF Switch Pin-out and Functional Diagram
35
5.8
JTOS-2700V, VCO, datasheet characteristic . . . . . . . . . . . .
37
5.9
VCO tuning Schematic, R5 is the tunable resistor . . . . . . . . .
38
6.1
PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
7.1
RS-232, 9-pin D-sub connector pinout
. . . . . . . . . . . . . . .
42
7.2
MATLAB GUI main screen . . . . . . . . . . . . . . . . . . . . .
43
7.3
MATLAB GUI screen with Face drop down menu . . . . . . . . .
44
7.4
MATLAB GUI Screen with Mode Drop-Down Menu . . . . . . . .
45
7.5
TRENDnet TU-S9, USB to RS-232 Converter Cable
. . . . . . .
45
7.6
Device Manager screen shot with COM port highlighted . . . . .
46
7.7
MATLAB GUI screen with COM drop down menu . . . . . . . .
47
7.8
Antenna Radiation Pattern Coordinate system . . . . . . . . . . .
48
7.9
MATLAB GUI Screen Shot, and Control Variables . . . . . .
49
7.10 Phase Shifter JSPHS-2484+ Interpolated Data
. . . . . . . . . .
50
7.11 Checkbox Selected Images, with = 30 and = 45 . . . . . . .
51
7.12 RS-232 Frame
51
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13 Communication Packet Frame
. . . . . . . . . . . . . . . . . . .
7.14 Microcontroller, MATLAB GUI Mode Flowchart
52
. . . . . . . . .
53
7.15 Status LEDs for Mode and Face value . . . . . . . . . . . . . . .
55
7.16 GUI Test Measured Radiation Patterns . . . . . . . . . . . . . . .
56
7.16 GUI Test Measured Radiation Patterns . . . . . . . . . . . . . . .
57
8.1
Adaptive Receive scan plot . . . . . . . . . . . . . . . . . . . . . .
59
8.2
Raster Scan Pattern . . . . . . . . . . . . . . . . . . . . . . . . .
60
8.3
Adaptive Receive Flowchart . . . . . . . . . . . . . . . . . . . . .
61
8.4
ISR Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
xi
I.1
Schottky Diode Chip Model . . . . . . . . . . . . . . . . . . . . . 100
I.2
ATmega2560 Block Diagram . . . . . . . . . . . . . . . . . . . . . 101
I.3
Analog to Digital Converter Block Schematic . . . . . . . . . . . . 102
I.4
LTC2656 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 103
xii
CHAPTER 1
INTRODUCTION
An adaptive communication system was proposed as a contest entry to the 4th

IEEE Antenna Design Challenge, sponsored by the Antenna and Propagation
Society (AP-S). This thesis describes an adaptive communication system, which
was developed as a contest entry. The main challenge of the contest was to
develop an antenna system with reconfigurable antenna elements that can adapt
to different propagation conditions (e.g. line-of-sight versus non-line-of-sight).
The IEEE contest rules are shown in Appendix A. The two page proposal for the
design challenge is shown in Appendix B.
A phased adaptive antenna array was proposed for the contest entry. Adaptive phased array antennas can change their radiation pattern electronically or
mechanically. In electrically configurable radiation pattern antenna, elements
have a relative phase difference while the antenna elements remain stationary.
Whereas in mechanical reconfigurable radiation patterns, antenna elements are
placed relative to each other but the antenna elements are movable. A tetrahedral structure with four patch antennas on each face of the antenna is developed,
as shown in Figure 2.2. Only one face is active at any given moment. A relative
phase difference in the four patch antenna changes the radiation patterns main
lobe direction, which is referred to as beam steering. The main lobe of an antenna
radiation pattern contains the maximum power. Figure 1.1 shows a main lobe
for a radiation pattern.
1
Figure 1.1: A Radiation Diagram with Main Lobe
The goal of this thesis is to design and implement a Digital Control System to
control the Electronically-Steered Phased Array Antenna described in [1]. The
controllable fields for the RF front-end system include the active antenna face,
two communication modes (transmit or receive), and control voltages for a phase
shifter that sets the main beam direction. The digital control board components
include:
RF Power Detector
The RF power detector measures the power received from the RF system.
The received power is interpreted by the microcontroller using an ADC,
which is further explained in Chapter 8.
Microcontroller
A microcontroller provides a communication interface between the computer and RF system; see Chapter 7 for additional details. The microcontroller also executes adaptive communication algorithms, as explained in
2
Chapter 8.
Digital Peripherals
The digital peripherals include a digital-to-analog converter (DAC), a comparator, and an analog-to-digital converter (ADC). The ADC is an internal
peripheral of the microcontroller. The DAC output voltages control the
phase shifters (via an SPI bus) to steer the antenna beam. The ADC measures received power by sampling the RF power detector output voltage.
The comparator checks the receive power level against a reference level set
by the DAC; this level is the previously received maximum power and is
discussed further in Chapter 4. A feedback loop is implemented using an
ADC, DAC and a comparator. The feedback loop improves the time required to find the receive direction with maximum power. The feedback
loop is explained in Chapter 4.
CHAPTER 2
SYSTEM DESIGN
An AVR-based microcontroller serves as the system controller. The AVR model

is an 8-bit Reduced Instruction Set Computer (RISC) single-chip microcontroller
developed by Atmel. Figure 2.1 shows the system basic block diagram.
Figure 2.1: System Block Diagram
The adaptive antenna system is a tetrahedron shaped structure (Figure 2.2)

with 2X2 patch arrays on each of the three faces. Only one face is active at a
time. The system is half duplex in that it can both transmit and receive, but not
simultaneously.
Figure 2.2: Tetrahedron Antenna Model
Figure 2.3 is the level-1 block diagram for the system. The block diagram
shows the main system blocks and the associated data flow. The yellow blocks
correspond to the RF components on the board. The purple blocks correspond
to the analog system on the board. The pink blocks are the USART support
components.
Figure 2.3: Digital Control Board Block Diagram
Table 2.1: 16-Pin IDC Pin-out Between Digital Control Board and RF
Board
PIN #
Control Line
Function
GND
Ground Connection
GND
Ground Connection
CTRL1
Unused
CTRL0
Unused
SPDT0
Control line for Single pole double throw
PS1
SPDT1
PS2
SP3T0
10
PS3
11
SP3T1
12
PS4
13
GND
Ground Connection
14
VCO
Control Voltage for the Voltage Control oscillator
15
GND
Ground Connection
16
GND
Ground Connection
Control Voltage Phase Shifter 1

Control line for Single pole double throw
Control line for Single pole triple throw
Control line for Single pole triple throw
Figure 2.4: IDC connector Pin Positions
The control board and RF system communicate via a 16-pin insulation displacement connector (IDC). The IDC pinout is defined in Table 2.1 and pin
positions are shown in Figure 2.4. System requirements for the digital control
board include:
1. Graphical User Interface (GUI) Controlled System

A MATLAB-based GUI tests the systems beam steering. The GUI communicates with the digital control board via a Universal Asynchronous Receiver/Transmitter (USART) using a RS-232 protocol. All antenna system
variables are defined through the GUI; see Chapter 7.
2. Adaptive RX
An adaptive receive station directs the systems radiation pattern in the
maximum receive power direction. The scan algorithm for finding this
direction is explained in Chapter 8.
2.1
2.1.1
System Requirements
GUI Control
The first project goal is to interface the system with the MATLAB GUI that
defines phase shifter voltages, mode, and face; see Figure 2.5.
Figure 2.5: Screen shot of MATLAB GUI

Phase Shifter Voltages
Voltage controlled phase shifters in the RF front-end are used to direct the
radiation patterns main beam [1].
Mode
The system has two modes: transmit and receive. Single pole double throw
(SPDT) switches control the modes; see Section 5.2.
Face
The tetrahedral antenna structure has three faces. The active face is controlled using single pole triple throw (SP3T) switches; see Section 5.3.
A USART is used for MATLAB GUI and system communications. The Voltage Controlled Oscillator (VCO) output frequency is controlled by an external
potentiometer for fine adjustments. Detailed GUI information is provided in
Chapter 7.
8
2.1.2
Adaptive Receive Mode
The second system goal is to operate as an adaptive receive station, which tracks a
transmitting signals location. A scan algorithm determines the maximum power
direction and is described in Chapter 8. Figure 2.6 shows two RX antenna
placements and how the radiation patterns adapt to the optimum direction. Additional information appears in Chapter 8.
Figure 2.6: Adaptive RX, Example System Configuration
2.2
2.2.1
System Sub-blocks
RF Power Detector
The RF power detector converts the received RF power to a DC voltage. Most RF

power detectors are Schottky diode-based topologies; they exhibit an exponential
relation between input power and output voltage, Vout (V ) ePin (W ). Another
common implementation is a log-amp based topology, which exhibits a linear
relationship between input power and output voltage, Vout (V ) Pin (W ). RF
power detector information appears in Chapter 3.
2.2.2
Interrupt Feedback Loop
The block diagram of the Interrupt Feedback Loop is shown in Figure 2.7. The
Interrupt Feedback Loop improves system efficiency by reducing the number of
required ADC samples at every step. The ADC samples only when hardware
interrupts are triggered; i.e.: when a power level that exceeds the previous maximum is detected. When an interrupt is triggered, the received power is saved in
memory as the new maximum value. The feedback loop includes a comparator,
the RF power detector and the microcontroller. The microcontroller uses a DAC
to set the comparators reference level, which represents the previous maximum
received power. Interrupt feedback loop information is provided in Chapter 4.
10
Figure 2.7: Inner Feedback Loop Block Diagram
11
CHAPTER 3
RF POWER DETECTOR
An RF power detector monitors the RF circuits output and develops a DC

voltage proportional to the received power in Watts [2]. Equation 3.1 shows
power in decibels relative to 1mW (dBm), commonly used by RF and wireless
engineers.
P (dBm) = 10logP (mW )
(3.1)
An operational amplifier (op-amp) with a PN junction diode as negative feedback is a classical implementation for a log-amp [3]. The logarithmic relationship
between diode voltage and current yields a linear relationship between input
power (dB scale) and output voltage (linear voltage scale). A bipolar junction
transistor (BJT) generates the logarithmic I vs V relation in place of a diode.
Figure 3.1 shows implementation examples for the single stage NPN and PNP
log-amp. Equation 3.2 defines RF power detector output voltage (Vout ) as a
function of the input power (Iin ).
Vout =
kT IIn
kT IC
ln
ln
q
IS
q
IS
12
(3.2)
(a) Basic NPN log-amp
(b) Basic PNP log-amp
Figure 3.1: DC log-amp BJT implementation
Two Linear Technology Corp. (LTC) log-amps were compared to maximize

dynamic range and output voltage slope. Log-amp datasheet characteristics include:
1. LT 5534
RF Frequency Range: 50MHz to 3GHz
Linear Dynamic Range: 60dB
Supply Voltage: 2.70V to 5.25V
Low Supply Current: 7mA [4]
2. LT 5538
RF Frequency Range: 40MHz to 3.8GHz
Linear Dynamic Range: 75dB
Supply Voltage: 3.00V to 5.25V
Low Supply Current: 29mA [5]
13
The log-amps were compared to the required dynamic range, 60dB, and
the output slope of the linear Vout (V ) vs input power(dBm) relationship, >
20mV /dB. Comparison results are shown in Section 3.3.
3.1
LT-5534
The LT-5534 is a monolithic RF power detector capable of measuring RF signals

over a dynamic range of -63dBm to 3dBm at 2.5GHz [6]. A Linear Technology
Corp log-amp demo board DC748A enabled LT-5534 characterization, as shown
in Figure 3.2 The demo boards schematic is shown in Appendix C [7].
Figure 3.2: Demo Board DC748A
The log-amp, LT-5534, output characteristics were compared to datasheet values. Figure 3.3a shows measured output voltage Vout (V ) vs Input Power (dBm)
at 2.4GHz, Figure 3.3b shows the same plot provided by the datasheet. The
measured output slope is 0.0373V /dB compared to 0.0366V /dB in the datasheet
[6]. The minimum detectable signal power is -60dBm.
14
Vout (V )
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
-75 -65 -55 -45 -35 -25 -15 -5
InputP ower(dBm)
(a) Measured
(b) Datasheet
Figure 3.3: LT-5534 log-amp Characteristics
15
3.2
LT-5538
The LT-5538 is a monolithic RF power detector capable of measuring RF signals

over a dynamic range of -72dBm to 10dBm at 2.7GHz [8]. The demo board
DC1120A, Figure 3.4 schematic can be found in Appendix D [9].
Figure 3.4: Demo Board DC1120A
The LT-5538 log-amps output characteristics are compared to datasheet values. Figure 3.5a shows the measured output voltage Vout (V ) vs. Input Power
(dBm) at 2.4GHz. Figure 3.5b shows the same plot provided by the datasheet.
The measured output slope is 0.0180V /dB compared to the datasheet value of
0.0176V /dB [8]. The minimum detectable signal power is -68dBm.
16
1.75
1.50
Vout (V )
1.25
1.00
0.75
0.50
0.25
-90-80-70-60-50-40-30-20-10 0 10 20
InputP ower(dBm)
(a) Measured
(b) Datasheet
Figure 3.5: LT-5538 Output characteristics
17
3.3
Log-Amp Power Detector Analysis
From the previous sub-sections, the LT-5534 and LT-5538 have output slopes
of 37.3mV /dB and 18.0mV /dB, respectively. For an 8-bit ADC with reference
voltage of 5V , a quantum is 19.6mV , as shown in Equation 3.3.
quanta =
5V
= 19.6mV
1
28
(3.3)
Thus the LT-5534 is the best option, since the dynamic range satisfies the
required range (60dBm to 30dBm) and the output slope is greater than one
quanta (19.6mV /dB).
18
CHAPTER 4
INTERRUPT FEEDBACK LOOP
Microcontrollers are widely used in communication applications. The AT-mega2560

AVR architecture [12], microcontroller is the main system controller for the system. Key features include:
Flash : 256 Kbytes (kB)

Static Random Access Memory (SRAM): 8 kB
Maximum Operating Frequency: 16 MHz
Serial Peripheral Interface (SPI): 5 channels
Analog-to-Digital Converter: 16 channels, 10-Bit Resolution
Real Time Clock (RTC)
Flash memory stores the boot loader and firmware. The boot loader is a
program that loads the firmware, or runtime environment, for the processor following self-test completion. SRAM microcontroller memory used for system variable declaration and firmware operation. An algorithm with multiple subroutines
requires an extensive (>128kB) flash memory (see Section 8.1 for algorithm).
Status variables are required for each algorithm branch; thus, greater than 2kB
of SRAM must be available. Many current digital peripherals use a communication protocol (SPI, CAN, I2C, USART, etc.) for intercommunication. SPI and
19
USART are the two communication buses used in this system. ADC converts the
RF peak detector DC output voltage into a digital value. A 2% output accuracy
and resolution greater than eight bits is required to capture a 0.25dBm change
in received power level. Real time clock (RTC) compatibility is preferred for systems synchronization. Figure I.2 (Appendix I) shows the microcontrollers block
diagram.
The inner feedback loop (Figure 2.7) consists of an ADC, DAC, and a comparator. The DAC sets the reference input to the comparator. The peak detector
output is connected to both the positive input terminal of the comparator and
the microcontrollers ADC input.
When the peak detector output is greater than the comparators reference
voltage, the comparator output changes to logic high, triggering a microcontroller interrupt. The microcontroller is notified that a new maximum power
has been received and is sampled by the microcontrollers ADC. In this case, a
new reference value is set by the DAC, and microcontroller stores the face and
phase counters (see Section 8.1). This loop eliminates redundant power detector
output voltage sampling in each algorithm step. Only voltage levels greater than
the previously received maximum power are sampled. Lock time is defined as the
time required to find the optimal receive direction.
4.1
ADC
The microcontrollers ADC samples the power detectors output voltage. Figure
I.3 (Appendix I) shows the microcontrollers ADC block schematic. Key features
include:
10-bit resolution
20
13s - 260s conversion time

0V VCC ADC input voltage range, VCC = 5V
Free running or single conversion mode
The ATmega2560 uses a 10-bit successive approximation ADC that can be

configured as either a single-ended or a differential input. A single-ended ADC
is preferable since negative voltages are not sampled. Equation 4.1 defines the
digital output for a single-ended conversion, where VIN is the voltage at the
selected input and VREF is the selected voltage reference.
ADCout = f loor
V
IN .1024
VREF
(4.1)
The 10-bit ADC resolution results in a quanta of (VCC = 5V ):
quanta =
VCC
5V
= 10
= 4.9mV
n
2 1
2 1
(4.2)
The ADC is configured in single conversion mode since samples are recorded only
upon interrupt triggers. As specified in Table 4.1, the first conversion requires 25
clock cycles, while subsequent conversions require 13 clock cycles.
21
Table 4.1: ADC Conversion Time

Condition
Sample
&
Hold
Conversion
(Cycles
from
Start
(Cycles)
Time
of Conversion)
First conversion
13.5
25
Subsequent
1.5
13
conver-
sions, single end
The ADC conversion timing diagram is shown in Figure 4.1. Table 4.2 shows
ADC register definitions and functions. The Application Programming Interface
(API) for the ADC is listed in Appendix E.
Figure 4.1: Analog to Digital Converter Timing Diagram for Single

Conversion Mode
22
Table 4.2: ADC Configuration

ADC
Microcontroller
Parameter
Register and Bit(s)
Reference Value
ADMUX(REFS1:0)
Value
Value Interpretation
b01
AVCC with external capacitor at AREF pin, 5V
ADC Clock
ADCSRA(ADPS2:0)
b010
XTAL/4
ADC Trigger
ADCSRA(ADATE)
b0
ADC auto trigger disable
ADC Input Pin
ADCSRB(MUX5) +
b000000
ADC0
ADMUX(ADLAR)
b1
ADC left adjust result
ADCSRA(ADIE)
b0
ADC interrupt disables
ADMUX(MUX4:0)
ADV value justification
ADC Interrupt
4.2
Interrupt
An external microcontroller interrupt triggers the Interrupt Service Routine (ISR)

(see Chapter 8). The interrupt configuration for the microcontroller in shown in
Table 4.3.
Table 4.3: Interrupt Configuration
Interrupt
Microcontroller
Value
Value Interpretation
Parameter
Register and Bit(s)
Active Interrupt
EIMSK(INT0)
b1
Enable INT0
EICRA(ISC10:00)
b011
Rising edge triggered
pin
Interrupt trigger
edge
23
4.3
DAC
The LTC2565 is an Octal 12-bit rail-to-rail DAC. The DAC block diagram is
shown in Figure I.4 (Appendix I). Key features include:
8 individually configurable DAC units
Synchronous or asynchronous update on each DAC
Precision 10ppm/ C Max Deviation from Reference Voltage
Selectable Internal or External Reference
Power-On-Reset to Zero-Scale (0V )/Mid-scale (half of reference voltage)
In the internal feedback loop, one DAC output channel is set to the comparator reference input. The other four output channels are used to set the four phase
shifters control voltages, which are further described in Section 5.1. The DAC
has a resolution defined in Equation 4.3
DACresl =
2 Vref
2 2.5
=
= 1.2mV /quanta
2bits
212
(4.3)
The comparator has an internal error of 6mV, or 5 quanta. The RF Power

Detectors output slope is 37.3 mV/dBm, thus the DAC resolution with respect
to power is provided by Equation 4.4:
37.3mV
1quanta
31quanta/dB
1dB
1.2mV
(4.4)
The DAC uses an SPI bus to communicate with the microcontroller. The LTC2656
24
can operate with clock speeds up to 50MHz; however, the DAC operates at a clock
speed of 4MHz. The maximum clock frequency for the SPI is one quarter the
microcontrollers clock frequency,
fosc
.
4
The microcontrollers operating frequency
is 16MHz.
The load sequence timing diagram is shown in Figure 4.2. The data word is
16-bits in length since the DAC is available in both 12 and 16 bits. The system
only uses a 12 bit DAC: thus, the four Least Significant Bits (LSB) are not used.
Figure 4.2: LTC2656 DAC Load Sequence
The DAC has a 24-bit input word, but the ATmega2560 is an 8-bit microcontroller (Figure 4.2). Each time a load sequence is sent to the DAC, the SPI
Data Register (SPDR) is loaded sequentially three times. Tables 4.4 and 4.5
show the DAC command and address codes, respectively. For DAC and ADC
API, refer to files: SPI API.h, SPI API.c and DAC SPI.h in Appendix E.
25
Table 4.4: DAC Command Codes

Command
Operation
C3
C2
C1
C0
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All
Write to and Update (Power Up) n
Power Down n
Power Down Chip (All DACs and Reference)
Select Internal Reference (Power-Up Reference)
Select External Reference (Power-Down Reference)
No Operation
Table 4.5: DAC Address Codes

Address n
Operation
A3
A2
A1
A0
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
26
4.4
Comparator
A high-precision comparator enables voltage comparison between two signals with

difference in mV range; the voltages used in the system are 20mV apart. The
LM339 is a Low Power Low Offset Voltage Quad Comparator. Key features
include:
Supply voltage 2 to 36 VDC

Low input biasing current: 25nA
Low supply current drain (0.8mA) independent of supply voltage
Output voltage compatible with TTL, DTL, ECL, MOS and CMOS logic
systems
Response time of 1.3s
The simplified schematic of a single LM339 comparator is shown in Figure

4.3. The open collector comparator output requires a pull-up resistor to the 5V
rail; a 3.3k resistor is used.
27
Figure 4.3: LM339 Schematic Diagram
A 0.1F capacitor is used at the comparator output to remove high frequency

glitching caused when inputs are within 20mV of each other. Although a capacitor
delays the comparator output rise time, it is required to avoid output glitching.
The comparator output triggers the microcontroller interrupt. A context switch
is the process of storing and restoring the state (context) of a process so that
execution can be resumed from the same point at a later time. If an interrupt
triggers multiple times within a single context switch, the microcontroller keeps
track of the trigger counts, and causes the microcontroller to go in multiple nested
context switches. These multiple context switching cause the system to become
unstable. The system unsuitability is due to the unknown and unstable state
of the system variables. If the microcontroller enters an unstable state, a power
cycle is executed.
28
CHAPTER 5
RF SYSTEM INTEGRATION
This chapter describes the microcontroller control lines for the RF system. A
16-pin IDC interfaces the RF board to the digital board. The connector pinout
(Table 2.1) and control lines are described in the following subsections.
5.1
Phase Shifters
Phase shifters control the four-patch inter-element phase shift to steer the radiation beam. The JSPHS-2484+ (MiniCircuits) is a 50 matched, 0 to 180
voltage-controlled phase shifter operating in the frequency range 2150MHz to
2484MHz. The datasheet provides voltage-to-phase data at 2150MHz, 2300MHz
and 2484MHz.
Linear interpolation between 2300MHz and 2484MHz yields
voltage-to-phase data at 2400MHz as shown in Figure 5.1.
29
Figure 5.1: JSPHS-2484+ Phase Shifter, Interpolated Data
Individual phase shifters control the relative signal phase with respect to each
path. The DAC was initially intended to set control voltages for the phase shifters
directly. This requires DAC analog output voltages from 0V to 15V. DACs with
15V output capability are limited, thus a 5V rail DAC was chosen. The LTC2656
DAC was selected to set phase shifter control voltages. An op-amp is required to
increase the DAC output voltage range from 0 5V to 0 15V ; thus a gain of +3
is required. Figure 5.2 shows an op-amp in a non-inverting gain configuration.
Equation 5.1 shows the input and output voltage relationship.
Figure 5.2: Operational Amplifier in Non-Inverting Configuration

30

Rf
Vout = Vin 1 +
Rg
(5.1)
For improved system performance a stable rail-to-rail op-amp was used. Each
of the phase shifters require a voltage control line and an op-amp. To reduce
component count, a quad pack op-amp (LT6005) was selected. Key Features of
the LT6005 include:
Wide supply range 1.6V to 16.0V

Low supply current, 1 A
Low input bias current, 90pA
Figure 5.3: LTSpice Simulation Schematic, LT6005 Non-Inverting Gain

Op-Amp Circuit
Figure 5.3 shows an LT6005 op-amp LTspice simulation. The simulation in

Figure 5.3 assumes ideal resistors and capacitors. To model a practical circuit,
a Monte Carlo Analysis was completed using variable resistor and capacitors
values. Variations in resistor values cause control voltage deviations and phase
offset errors, which will affect the beam direction.
31
Analyses with resistor tolerances ranging from 5% to 0.01% were completed.

The 0.01% tolerance had the best performance; the most cost effective option
utilizes 0.5% tolerance resistors. The Monte Carlo analysis schematic and results
are displayed in Figure 5.4. The response is expanded to highlight the area
of maximum error, which occurs when input voltages are close to the 5.0V rail.
Figure 5.5 shows results from 4.95V to 5.00V. The measured output saturation
voltage for the op-amp is 14.97V for a 15.00V rail. The extreme cases are:
Vout = 14.97V at Vin = 4.95V
Vin = 5.00V outputs Vout = 14.92V
This Monte Carlo Analysis was iterated 50 times, which constitutes 85% of
the Gaussian distribution at 0.5% tolerance. [10]
(a) Schematic
Figure 5.4: LTSpice Simulation results, LT6005 Op-amp Non-Inverting

Gain Circuit
32
(b) Result
Figure 5.4: LTSpice Simulation results, LT6005 Op-amp Non-Inverting

Gain Circuit
Figure 5.5: Monte Carlo Analysis for Amplification Circuit, Expanded

View
33
5.2
RF Single Pole Double Throw (SPDT) Switch
SPDT switches determine the Antenna and RF system modes: transmit or receive. Two control lines control the SPDT switch position. The AS179-92LF
is a 20MHz to 3.0GHz GaAs SPDT switch. The AS179-92LFs pinout and block
diagram is shown are Figure 5.6.
(a) Pinout
(b) Block Diagram
Figure 5.6: AS179-92LF, SPDT, Pin-out and Block Diagram
Table 5.1 shows the SPDT truth table. As defined in Figure 5.6b, V1 and V2
are control lines while J1, J2, and J3 are RF lines. J1 is the common line while
J2 and J3 are selectable. Table 5.2 shows the system truth table for the receive
(RX) and transmit (TX) modes. For the transmit (TX) mode, J1 is connected
to J3; for receive (RX) mode, J1 is connected to J2.
Table 5.1: Truth Table for SPDT, VHIGH = 2V to 5V, VLOW = 0V
Insertion Loss = 0.5dB, and Isolation = 22dB
V1
V2
J1 to J2 connection
J1 to J3 connection
VHIGH
Isolation
Insertion Loss
VHIGH
Insertion Loss
Isolation
34
Table 5.2: SPDT, Antenna Mode Truth Table
5.3
SPDT1(V1)
SPDT0(V2)
Mode
TX
RX
RF Single Pole Triple Throw (SP3T) Switch
The SP3T switches determine the tetrahedral structures active face. The HMC245QS16
is a SP3T RF switch is a GaAs-based monolithic microwave integrated circuit
(MMIC) operating in the frequency range DC to 3.5 GHz. The SP3T switchs
pinout and functional diagram is shown in Figure 5.7.
Figure 5.7: HMC245QS16 SP3T RF Switch Pin-out and Functional

Diagram
Table 5.3 shows a truth table for the HMC245QS16 SP3T RF switch. Control
lines A and B are compatible with both TTL (Transistor-Transistor Logic) and
CMOS (Complementary Metal-Oxide Semiconductor) logic levels. Voltage ranges
are defined as 0 to 0.8V for LOW and 2.0V to 5.0V for HIGH. The MMIC exhibits
an insertion loss of 0.6dB and isolation of 35dB between RF ports at 2.4GHz.
35
Table 5.3: Truth Table for HMC245QS16 and the Active Antenna Face
Control Input
5.4
Signal Path State
RF COM to:
Active Face
Low
Low
RF1
High
Low
RF2
Low
High
RF3
High
High
All Off
All Off
Voltage Control Oscillator (VCO) Control Line
The JTOS-2700V is a linearly tunable voltage controlled oscillator (VCO) for

the frequency range 2050 to 2700 MHz. VCO Frequency Tuning and output
power data are shown in Figure 5.8.
36
(a) Frequency Tuning
(b) Output Power
Figure 5.8: JTOS-2700V, VCO, datasheet characteristic
Figure 5.8a shows that a control voltage of 9.18V is required to produce

a 2.4GHz signal, the RF systems operating frequency. The antenna resonance
frequency has an engineering tolerance of 5% at 2.4GHz [1], which requires a
tunable VCO control line. Figure 5.9 shows the VCO tuning circuit with output
voltages from 7.5V to 10V . Table 5.4 shows output voltages when the tunable
potentiometer is in the range 1 to 5k. A 14-turn tunable 5k potentiome37
ter provides fine adjustment for the VCO output frequency. High tolerance 1%
resistors are used for R1 through R4.
Figure 5.9: VCO tuning Schematic, R5 is the tunable resistor
Table 5.4: VCO Tuning Circuit Result

Potentiometer resistance ()
VCO control voltage (V)
7.50
1k
8.18
2k
8.75
3k
9.23
4k
9.64
5k
10
38
CHAPTER 6
PRINTED CIRCUIT BOARD DESIGN
CadSoft EAGLE PCB Design Software was used to design the printed circuit
board (PCB) schematic and layout. PCB schematic and layout can be found in
Appendices F and G, respectively.
6.1
Schematic
The schematic was created to add the maximum testability in the PCB. The
following are some of the key testability features added to the PCB design:
Zero ohm resistors to isolate power supplies and ICs

Zero ohm resistors to isolate outputs and inputs for testability
DIP switch and header pins to set SPDT and SP3T control signal manually
and LEDs to show the status
Test points at most microcontroller input/outputs (I/Os)
LED Display Driver(LM3914) to show the received power RF power detector.
LEDs to check the power statuses
On broad ISP programmer pinout
39
The ICs used required 5V and 15V power rails. To avoid the need for two
power supplies, a 20V AC to DC wall transformer was used with power regulators.
A barrel connector was used to connect the 20V power supply to the board. ON
Semis NCP1117ST50T3G was used to achieve 5V rail and Texas Instrument part
LM3480 was used to achieve 15V rail. Linear Technology LT1761 was used to
set the 2.5V DAC reference voltage.
6.2
Layout
A two-layer PCB was chosen for the layout. A full copper pour on the top and
bottom layers was used as the ground. The advantage of large group plane is
its low inductance and resistance. Routing the signals and power lines in the
group pour helps maintain a good signal value by creating capacitance between
the signal or power and the ground signal. A section of copper pour was cut out
from the full copper pour to act as analog ground. The full ground plane and
analog ground plane were connected via 22nH inductor, which prevents the high
frequency switching ground plane currents from affecting the analog voltages.
The analog plane was used under the DAC and the Amplifier. The layout was
designed so that traces would have a minimal number of vias.
40
Figure 6.1: PCB layout
Figure 6.1 shows the layout of the subsequent PCB. All the main components
are marked in the Figure with accompanying text. All connectors were placed so
that they are as close to their mates as possible.
41
CHAPTER 7
GRAPHICAL USER INTERFACE (GUI) CONTROL SYSTEM
The MATLAB GUI is designed to test system functionality. The GUI configures
all system variables for beam steering and can be set to transmit or receive mode.
MATLAB uses RS-232, a serial protocol, to communicate between the computer
and control board. A 9-pin D-subminiature (D-sub) connector is used for RS-232
communication; the pinout is shown in Figure 7.1.
Figure 7.1: RS-232, 9-pin D-sub connector pinout
MATLAB has a built-in serial communication library. Data is sent from the
MATLAB GUI to the microcontroller via a one-way data link. The microcontroller interprets the RS-232 data and sets the system variables accordingly. The
GUI screen is shown in Figure 7.2.
42
Figure 7.2: MATLAB GUI main screen
7.1
GUI Inputs and Features
MATLAB GUI has four user interface fields.

1. Drop down menus: Face, Mode and COM
2. Edit Text: Theta and Phi
3. Push Buttons: Reset, Close, Phase Shifter Data, Send and Update
4. Checkbox: Radiation Pattern, Element Pattern, Array Factor and E and
H Planes
7.1.1
Drop Down Menus
The three drop down menus are Face, Mode and COM port. The Face drop-down
menu has three options: 1, 2, or 3. Figure 7.3 shows the GUI screen-shot with
43
user options. The selection controls the adaptive antenna face. The antenna face
is controlled using SP3T switches. The antenna faces 1, 2, and 3 are labeled on
the tetrahedral antenna structure.
Figure 7.3: MATLAB GUI screen with Face drop down menu
The Mode drop down menu has two options; TX (transmit) or RX (receive),
which are controlled by SPDT switches. Figure 7.4 shows the GUI screen-shot
with the Mode drop down menu open.
44
Figure 7.4: MATLAB GUI Screen with Mode Drop-Down Menu
RS-232 uses the COM port set by the COM drop down menu. A TRENDnet
TU-S9 (Figure 7.5) USB to RS-232 converter cable connects the PC to the
Control Board. On Microsoft Windows, the Device Manager shows the COM
port that the converter cable is connected to on the computer. As shown by the
red highlighted box in Figure 7.6.
Figure 7.5: TRENDnet TU-S9, USB to RS-232 Converter Cable
45
Figure 7.6: Device Manager screen shot with COM port highlighted
Once the COM port is known, the COM drop-down menu sets the COM port
value. The blue highlighted box in Figure 7.7 shows the default range of COM
port values, while the red highlighted box shows the serial connection details.
The BAUD rate (pulses per second) of 57600, eight data bits, and one stop bit
is used.
46
Figure 7.7: MATLAB GUI screen with COM drop down menu
7.1.2
Edit Text
Theta () and Phi () are two editable text fields. Figure 7.8 shows theta and
phi in the spherical coordinate system. The limits on are 0 to 90 or 0 to
radians because it is impractical to direct radiation below the antenna plane.
The limits on are 0 to 360 or 0 to 2 radians.
47
Figure 7.8: Antenna Radiation Pattern Coordinate system
and set the antenna beam direction, or its radiation patterns main lobe.
The calculated control angles and phase shifter voltages from the and fields
are shown in the green highlighted box in Figure 7.9. The antenna radiation
pattern is displayed in the GUI right panel, highlighted with a red box. The blue
highlighted box shows the achievable main beam direction in and coordinates.
The offset between theoretical and achievable is due to phase shifter limitations
[1].
48
Figure 7.9: MATLAB GUI Screen Shot, and Control Variables
7.1.3
Push Buttons
There are five GUI push buttons: Reset, Close, Phase Shifter Data, Send, and
Update. The Reset button returns the GUI to its default state. The Close
button closes the MATLAB GUI, but maintains all open figures defined in Section
7.1.4. The Phase Shifter Data button shows the Phase Shifter JSPHS-2484+
characteristic data interpolated from the associated datasheet, which is shown in
Figure 7.10.
49
Figure 7.10: Phase Shifter JSPHS-2484+ Interpolated Data
The Update button initiates phase shifter control voltage and angle value calculations from theta and phi values. The Update button also refreshes the Value
and Radiation Pattern panel, and creates the plots selected from the Additional
Figures panel. In addition to Update buttons function, theSend Button also
transmits the data packet to the microcontroller. Transmit data packet structure
is described in Section 7.2.
7.1.4
Additional Figure Checkboxes
The four checkboxes that create additional information plots for antenna radiation pattern are Radiation Pattern, Element Pattern, Array Factor and E and
H Planes. Figure 7.11 shows all the additional plots for = 30 and = 45 .
The E and H planes checkbox creates an addition plot for all previously selected
options in the Additional Figures panel.
50
(a) Element Pattern
(b) Array Factor
(c) Total Pattern
(d) E and H planes, Ele-
(e) E and H planes, Array
(f) E and H planes, Total
ment Pattern
Factor
Pattern
Figure 7.11: Checkbox Selected Images, with = 30 and = 45
7.2
Communication Protocol
Figure 7.12 shows a single RS-232 physical frame. The protocol consists of a
start bit, eight data bits, and one stop bit. The start bit is usually HIGH. Data
bits are in order of least significant bit (LSB) to most significant bit (MSB). The
stop bit is usually LOW.
Figure 7.12: RS-232 Frame
51
The protocol data packet for communication between the microcontroller and
MATLAB GUI include mode value, face value and four phase shifter control
voltages. Figure 7.13 shows the timing diagram for a data packet. RS-232
data bits are transmitted as an 8-bit American Standard Code for Information
Interchange (ASCII) character. Therefore, conversion is performed from decimal
ASCII characters to 8-bit integer values, conversion chart is shown in Table 7.1.
Figure 7.13: Communication Packet Frame
Table 7.1: Hexadecimal Notation for ASCII Decimal Characters to

8-bit Integers
Data in Hexadecimal
ASCII Character
8-bit integer value
0x30
0x00
0x31
0x01
0x32
0x02
0x33
0x03
0x34
0x04
0x35
0x05
0x36
0x06
0x37
0x07
0x38
0x08
0x39
0x09
The flowchart in Figure 7.14 shows microcontroller received data packet processing methods. The C code implementing the algorithm is provided in Appendix E.
52
Figure 7.14: Microcontroller, MATLAB GUI Mode Flowchart
7.3
Test and Results
The board was initially tested with the RF system disconnected. Status LEDs
were checked for SPDT and SP3T control lines. Set line or logic high is indicated
by an illuminated LED; clear line or logic low is shown by a dark LED. The
highlighted box in Figure 7.15 shows status LED locations. The phase shifter
control voltages were measured using a digital multimeter. Table 7.2 shows the
53
measured control voltages for three test cases:

1. = 30 = 0
2. = 0 = 0
3. = 15 = 0
Radiation patterns were collected for antenna Face-3 in transmit mode. The
radiation pattern plots are shown in Figure 7.16. The offset angle in all the
radiation patterns is explained in [1].
Table 7.2: GUI Test Result
Theta
-30
15
Phi
Expected Phase
Measured Phase
Shifter Control
Shifter Control
Voltage(V)
Voltage (V)
7.98
7.96
-0.25%
7.98
7.94
-0.50%
0.01
NA
0.01
NA
0.01
NA
0.01
NA
0.01
NA
0.01
NA
0.01
NA
0.01
NA
5.64
5.62
-0.35%
5.64
5.61
-0.53%
54
Percent Error
Figure 7.15: Status LEDs for Mode and Face value
55
(a) Radiation Pattern, = 30 = 0
(b) Radiation Pattern, = 0 = 0
Figure 7.16: GUI Test Measured Radiation Patterns

56
(c) Radiation Pattern, = 15 = 0
Figure 7.16: GUI Test Measured Radiation Patterns
57
CHAPTER 8
ADAPTIVE RECEIVE MODE
In receive mode, an adaptive antenna performs a scan to determine the maximum

receive power direction. This mode to used to maintain a lock on a receiving signal
from a transmitting antenna.
8.1
Adaptive Receive Algorithm
For the search algorithm, a 58-point scan on each antenna face is performed.
Figure 8.1 shows the location of the points used in the the adaptive receive scan.
The points are scanned using a raster scan technique, which is a line-by-line
rectangular sweep as shown in Figure 8.2. Power is received for each scan point.
If the received power at the current point is greater than the power received at any
previous point, the new maximum is stored. This continues until the scanning is
complete. Following scan completion, the beam is reset to the maximum power
direction. The scan direction is maintained until the receive power level decreases
below -50dBm. This level is chosen because the RF system has a noise floor of
-60dBm.
58
Figure 8.1: Adaptive Receive scan plot

59
Figure 8.2: Raster Scan Pattern
The flowchart in Figure 8.3 shows the scan algorithm in the adaptive receive
mode. Upon scan completion, if the lock flag is set, the maximum beam direction
is initialized. If the flag was not set in the previous scan, the scan repeats itself.
The lock flag is initially set when the receive power is greater than -50dBm, or
subsequently if the received power is greater than the previously received maximum power. The interrupt service routine (ISR) flowchart for the microcontroller
is shown in Figure 8.4. Figure 8.4 shows the flowchart for the interrupt service
routine (ISR), which is triggered when the comparator output changes to logic
high.
60
Figure 8.3: Adaptive Receive Flowchart
61
Figure 8.4: ISR Flowchart
8.2
Testing
The system was tested without the RF board and antenna connected to the
digital control board. A Wiltron (Model 68147A) RF source was used to simulate
the received power. A delay of 100ms was set between scan points to facilitate
observation of the working algorithm. Table 8.1 shows adaptive receive mode
test procedure data. The following test procedure was performed:
1. Apply -60dBm power to the receive port
2. Change the power to -30dBm at a single scan point and then back to
62
60dBm, to set the trigger

3. Observe when Lock LED status turns on
4. Revert back to -30dBm power
5. Reduce the power from -30dbm in 2dB steps and observe lock LED turn
off once -50dBm is reached
Table 8.1: Test Data for Adaptive Receive Mode Test Procedure
Receive Power (dBm)
Lock LED status
-30
ON
-32
ON
-34
ON
-36
ON
-38
ON
-40
ON
-42
ON
-44
ON
-46
ON
-48
ON
-50
OFF
-52
OFF
-54
OFF
-56
OFF
-58
OFF
-60
OFF
63
The data in Table 8.1 proves that system operates in the specification, maintaining lock for power level greater than -50dBm. The complete system test was
not performed due to RF PCB manufacturing problems [1].
64
CHAPTER 9
CONCLUSIONS AND FUTURE WORK
The system shows a successful implementation of the digital control board for
beam steering and adaptive communications. The digital control board controls the antenna face and mode as described in [1]. Each sub-block of the digital controlled board was tested in order to verify that specifications were met.
The MATLAB graphical user interface successfully controlled the digital control
board. An adaptive communication system was implemented to demonstrate
a working example. The system autonomously locked to the maximum receive
power using the 58-point scan, for the power levels above -50dBm.
The RF power detector used a logarithmic amplifier-based design, which provides a linear relation between input power and output voltage. The RF power
detector has a slope of 37.3mV /dB with a minimum detectable power of 60dBm
and maximum detectable power of 0dBm.
An ATmega2560 is used as the microcontroller for the system. The built-in
ADC was used to measure the receive power. The microcontroller is also used
to communicate with MATLAB, which allows it to set the output voltages for
the phase shifters as well as the control signals that set the antenna face and
the mode. The microcontroller can be configured in MATLAB GUI mode or the
adaptive receive mode.
The system successfully controls the SP3T and SPDT switches, which control
65
active antenna face and mode selection, respectively. The system also successfully
sends control voltages to the phase shifter within 0.53% of expected values. The
control board demonstrates a working bench test for an adaptive receive station.
The PCB design shows improved performance with a separate analog and
digital plane and reduces the noise on the analog signal. The digital control
board was designed for in system test and debugging. The digital control board
has features for future expandability.
Future work:
Re-test the digital control board with a fully operational RF board
Develop a half duplex adaptive receive and transmit communication system
Digital communication (16-QAM, APSK, LTE, etc.) implementation on
the control board
66
BIBLIOGRAPHY
[1] S. Brockhoff, Electronically-Steered Tetrahedral-Structured Phased Array

2.4 GHz Transceiver Design Applied to Adaptive Communications, Masters thesis, California Polytechnic State University, 2013.
[2] Louis
less
E.
Frenzel,
Devices.
http
Design
:
FAQ:
RF
Detector
for
Wire-
//www.analog.com/static/imported
f iles/f aqs/201551981DetectorF AQ.pdf .

[3] Integrated DC Logarithmic Amplifiers, Dallas Semiconductor, Maxim Engineering Journal, vol. 56, 2005.
[4] LT5534 - 50MHz to 3GHz RF Power Detector with 60dB Dynamic Range.
http : //www.linear.com/product/LT 5534.
[5] LT5538 - 40MHz to 3.8GHz RF Power Detector with 75dB Dynamic
Range. http://www.linear.com/product/LT5538.
[6] LT5534 Datasheet. http : //cds.linear.com/docs/en/datasheet/5534f c.pdf .
[7] LT5534 Demo Board. http : //www.linear.com/demo?demob oard =
partn umber = 5534categoryi d = 0companionb oard = sof twarei d =.
[8] LT5538 Datasheet. http : //cds.linear.com/docs/en/datasheet/5538f.pdf .
[9] LT5538 Demo Board. http : //www.linear.com/demo?demob oard =
partn umber = 5538categoryi d = 0companionb oard = sof twarei d =.
67
[10] Morris R. Driels and Young S. Shin, DETERMINING THE NUMBER

OF ITERATIONS FOR MONTE CARLO SIMULATIONS OF WEAPON
EFFECTIVENESS, Tech. Rep. NPS-MAE-04-005, Naval Postgraduate
School, MONTEREY, CALIFORNIA, April 2004.
68
APPENDICES
2013 IEEE APS Student Design Challenge: Reconfigurable Antennas
69
2013 IEEE APS Student Design Challenge:

Reconfigurable Antennas
Traveltothe2013IEEEAntennasandPropagationSymposium
Win$1500,$750,$250
Join the 4th IEEE APS Antenna Design Challenge! Build an antenna system with reconfigurable antenna
elements that can adapt to different propagation conditions (e.g. lineofsight versus nonlineofsight).
Thetopthreeteamswillreceiveupto$2,500(USdollars)intravelfundstoattendtheIEEEAntennasand
PropagationSymposiuminOrlando,FL,USA,July713,2013todemonstratetheirworkingsystems.From
thesetopteams,first,second,andthirdplacewinnerswillbeannouncedatthe2013IEEEAPSAwards
Banquetandwillreceivecashawardsof$1500,$750,and$250,respectively.
ImportantdeadlinesareNovember30,2012andApril26,2013.Seebelowfordetails.
GoalsandSpecifications:
1. Design an antenna system with reconfigurable antenna elements that can adapt to different
propagationconditionsinordertoachievethebestlinkperformance.Theperformancecanbeshown
intermsofreceivedpowerorhigherlevelsystemmetricsuchassymbolerrorrate.
2. The antenna system should be used to teach how antennas work. Such a system might be used in
collegeundergraduateorgraduatecourses,andinprecollege(HighSchool)physicscourses.
3. Thesystemmustbesafeanddurable,easilyreproduciblebyothers,inexpensive,andportablesothat
itcanbedemonstratedattheSymposium.
4. Thesystemmustoperateat2.4GHz,haveitsownsource(i.e.nocommercialsignalgeneratorcanbe
used),andfitonatabletop(roughly24x40)ortwocloselyspacedtables.Readilyavailablesoftware
(e.g.,studentversionsofC,Matlab,VisualBasic,LabView)orfreesoftwarepackagesmaybeused.All
softwaremustbeincludedinthebudget.
5. Thetotalcostforreproductionofthesystemmustbelessthan$1,500.Theuseofalaptopcomputeris
allowedanddoesnothavetobeincludedinthe$1,500limit.
Eligibility:
Theteamshouldconsistof2to5persons,withamajorityofundergraduatestudents.Eachteamshould
beadvisedbyaprofessionalmentorwhoisamemberoftheAPSociety.Nostudentormentorshouldbe
involvedinmorethanoneteam.
TheApplicationandReviewProcess:
1.AllapplicantsmustsubmitapreliminarydesignbyNovember16,2012.Itmustinclude:
a.Aproposallimitedtotwopagesandin12ptTimesNewRomanfontthatincludes
i.Adetaileddescriptionofthesystemtobebuilt.
ii.Thestepsthatwillbetakentoensuretheaccuracyofthesystem.
iii.Abillofmaterials(upto$1,500).
b.Aletterfromaprofessionalmentorsuchasaprofessororengineerinindustryindicatingagreement
tosupervisetheproject.ThementormustbeanIEEEAPSmemberandmustverifythatallmembers
oftheteamaregraduateand/orundergraduatestudentsatauniversity,college,ortechnicalschool.
TheproposalandlettermustbeintegratedintoasinglepdffilenamedTeamName.pdf.Theproposal
shouldprecedetheletter.
2. The Design Contest Committee will assess each preliminary design based on creativity, likelihood of
achievingthedesigngoals,educationalvalue,andqualityofwrittenmaterials.Sixsemifinalistteams
willbeselectedbyNovember30,2012andwillreceive$1,500eachtobuildandtesttheirdesigns.
3. Each of the six semifinalist teams must submit its final design by April 26, 2013. It must be
accompaniedbyavideodemonstrationofitsworkingsystem,andafinalreportinpdfformatusingthe
template available at the APS website. Submission instructions for the video demonstration will be
providedlater.Thereportmustbelimitedto10pagesandinclude:
a.Adetaileddescriptionofthesystem(includingschematicandotherdiagrams).
b.Alistofpartsandmaterialsrequired,includingwheretoobtainthemandcosts.
c.Photosofthefinalsystem(includingascaletoshowhowlargeitis).
d.Assemblyandoperatinginstructionsforthesystem.
e.Asetofmeasurementsobtainedusingthesystemwithanexampletestantenna.
f.Biographies(100wordsorlesseach)andphotosofalldesignteammembers.
g.Allsoftwarenecessarytobuildand/oroperatethesysteminaseparatefile(s).
4.TheDesignContestCommitteewillassesseachsemifinalistsdesignbasedoncreativity,completeness
of the description, functionality of the system as determined by the video, educational value, and
quality of written materials. Three finalist teams will be selected by May 10, 2013 and will receive
stipends of up to $2,500 per team to travel to and attend the IEEE APS Symposium. The stipend is
intended to cover equipment shipping costs and all of the expenses for one team representative;
however,itmaybedividedamongmultipleteammembers.
5.ThefinalistswillbeexpectedtodemonstratetheirworkingsystemsduringtheSymposiumandattend
theAwardsCeremonyatthebanquet.PowersupplieswillbemadeavailableattheSymposium.Each
teamisresponsibleforbringingallothernecessaryequipmentforasuccessfuldemonstration.
6.TheDesignContestCommitteewilljudgethefinaldemonstrationsandselectthefirst,second,andthird
prizewinnerstoreceive$1,500,$750and$250,respectively.Theprizewinnerswillbeannouncedat
theAPAwardsBanquet.
7.AftertheSymposium,thefinalistswillberequiredtorevisethefinalreportforpublicationintheIEEE
APMagazineundertheEducationColumn.
HowtoSubmitMaterials:
Send all materials to [email protected] with the subject line 2013 IEEE APS Design Contest
Submission.Questionsmaybesenttothesameaddress.Allsubmittedmaterialsmustbeinpdfformat
accordingtotheguidelinesabove.
Contest Proposal
72
IEEE Antenna Design Contest

By: Steve Brockhoff, Mayur Bansal
Objective
We plan to build an electrically reconfigurable antenna system
to demonstrate line-of-sight and non-line-of-sight
transmission. The physical structures of both transmit and
receive antenna systems will be a triangular-based pyramidal
structure. Each face of the structure has three probe-fed
triangular microstrip patch antennas See Figure 1 for the
general structure.
This structure has two levels of precision. The face and patch
antenna arrangement creates a three dimensional phased array
Figure 1: Triangular-based
in which array elements are phase-controlled to direct a beam to
pyramidal structure.
three-dimensional sectors. Two elements on one face could be
activated and one on another to optimize beam-steering to maximize signal reception.
Transmit and receive antenna systems are completely isolated and are identical, both capable of
transmitting and receiving. Two-way communication enables transmission beam directing to
maximize receive antenna reception.
Preliminary Design
The 2.4 GHz signal is generated using an Analog Devices integrated synthesizer (CC2500).
Three 2.4GHz amplifiers amplify signals for transmission and after reception. Three 2.4 GHz
bandpass filters suppress out-of-band power by at least 10dB. Each bandpass filter will be a
cascaded combination of Chebyshev low-pass and high-pass filters with cutoff frequencies of
2.35GHz and 2.45GHz, respectively. Amplifier placement before the filters minimizes noisefigure.
The signal is applied to a distribution network, which includes four phase-shifters controlled by
an Arduino microcontroller, see Fig. 2. The Arduino controls the antenna and active face by
controlling RF switches in order coarsely scan for the optimal transmit direction. Multiple faces
can be active at one time. The design utilizes three phase-shifters to control three patch antennas
on
three
Figure 2: System Block Diagram
different structure faces. Three of the nine patch antennas will be active at
any one time.
To maximize received signal strength, the microcontroller selects
combinations of faces and active patches to direct the transmit signal.
Concurrently, the receive antenna scans in a similar fashion in a two-step
process. First, all phase-shifters are set to zero and the signal is applied to
different three-element combinations of the TX patch antennas. The
system then waits for an acknowledgement (ACK) signal from the RX
antenna. The TX system measures the ACK signal power and saves it in
the Arduino memory and associates the recorded power level with the
specific three-element combination. Second, the Arduino recalls each
three-element combination, then controls the phase-shifters to change the
beam direction to finely scan for the optimal transmit direction. The TX
antenna waits for an ACK signal, as before, but will now store the phaseshift values in memory as well, in order to recall the coarse and fine
directions for optimal transmission.
The first scan determines the general direction to establish a link (both the
TX and RX directions)Then, the phase-shifters are adjusted to finely scan
in each direction that received an ACK message, starting with the
Figure 3: Algorithm
Flow Chart
strongest sector direction. After all antenna combinations and fine
scanning is completed, the three-element array and phase-shift values that
correspond to the maximum signal strength is chosen as the optimum transmission direction.
Component
Antenna
Part
PCB
SMA Connector
Motherboard PCB
Microcontroller
Crystal
Transreciever
Power detector
RF Amp
Active Phase Shifter
RF Switch ( SP3T)
RF Switch ( SP2T)
R,L,C,D
LCD 16X2 character
SMA Connector
SMA male to male cable
Accessories
MATLAB Student Version
Total
Unit Price
$ 45.00
$
2.50
$ 75.00
$ 30.00
$
0.35
$
4.76
$ 19.42
$
1.50
$
5.35
$
8.36
$
0.52
$ 13.95
$
2.00
$ 12.96
$ 100.00
Qty Cost
6 $ 270.00
9 $
22.50
2 $ 150.00
2 $
60.00
2 $
0.70
2 $
9.52
2 $
38.84
20 $
30.00
8 $
42.80
42 $ 351.12
18 $
9.36
$
50.00
2 $
27.90
18 $
36.00
18 $ 233.28
1 $ 100.00
$ 1,432.02
Notes
PCBExpress
DigiKey
PCBExpress
Arduino
Analog Device
Texas Instruments
Analog Device
Analog Device
Mini Circuits
HMC245QS16
AS179
DigiKey
Sparkfun
DigiKey
DigiKey
LT 5534 Demo Board Schematic
75
U1
LT5534ESC6
RF in
C1
EN
1
E4
R2
Vout
E2
EN
RF
GND
GND
VOUT
VCC
J1
1nF
R1
47
Vcc
C5
opt.
C3
100pF
Gnd
E1
C2
0.1uF
E5
Vcc
2.7V to 5.25V
Gnd
E3
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
CONTRACT NO.
APPROVALS
DRAWN
DATE
June Wu
12/17/03
CHECKED
TECHNOLOGY
TITLE
LT5534ESC6, RF Power Detector w/60dB Range
APPROVED
ENGINEER
1630 McCarthy Blvd.

Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
V. Dvorkin
12/17/03
DESIGNER
Thursday, December 18, 2003

3
SIZE CAGE CODE
SCALE:
DWG NO
FILENAME:
2
REV
A
DC748A
SHEET
OF
1
1
LT 5538 Demo Board Schematic
77
E5
C4
1nF
L1
1.5 nH
RF in
J1
C8
1pF
U1
LT5538EDD
1
ENBL
2
R1
56
CAP+
IN-
CAP-
VEE
VCC
C5
1nF
R5
0
GND
C7
1pF
C6
DNI
OUT
E4
GND
E2
C10
100pF
C9
DNI
IN+
OUT
GND
EN
R4
4.99K
E6
VCC
C2
100pF
C1
0.1uF
E1
VCC
4.75V - 5.25V
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A
CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS;
HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO
VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL
APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR
TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND

SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
5
CONTRACT NO.
APPROVALS
DRAWN
A. Karpova
DATE
6/12/06
CHECKED
TECHNOLOGY
TITLE
LT5538EDD
50MHz to 3.8GHz DETECTOR
APPROVED
ENGINEER
D.Stuetzle
6/12/06
DESIGNER
Thursday, November 15, 2007

3
SIZE
1630 McCarthy Blvd.

Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
CAGE CODE
SCALE:
FILENAME:
2
DWG NO
REV
DC1120A
SHEET
3
1
1
OF
Microcontroller Code
79
/*******************************************************
* File
: Thesis_Spring_STK_600.c
*
* Description : brief description of file purpose
*
* Author
: Mayur Bansal (mb)
*
* Revisions : 1.00 6/27/2013 (mb) First release
*
* "THE BEER-WARE LICENSE" (Revision 42):
* <[email protected]> wrote this file. As long as you
* retain this notice you can do whatever you want with
* this stuff. If we meet some day, and you think this
* stuff is worth it, you can buy me a beer in return
* Mayur Bansal
*
********************************************************/
/*******************#define Declarations****************/
# define F_CPU
16000000UL
#define SET
#define CLEAR
1
0
#define PDOUT
#define LOCK
#define SP3TUC0
#define SP3TUC1
#define SPDTUC0
#define SPDTUC1
#define TESTDIP0
#define TESTDIP1
#define CMPOUT
#define CTRL0
#define CTRL1
PF0
PA7
PC0
PC1
PC2
PC3
PC6
PC7
PD0
PD6
PD7
#define TESTMODEMASK
#define TESDTMODEMATLAB
#define TESTMODEADAPTIVERX
#define TESTMODEADAPTIVETXRX
#define MATLABGUI
#define ADAPTIVERX
#define ADAPTIVETXRX
#define ERRORTESTMODE
0xC0
0x00
0x40
0x80
0
1
2
3
/******************#include Declarations****************/
#include <avr/io.h>
#include <util/delay.h>
#include <avr\interrupt.h>
#include "ADC_API.h"
#include "SPI_API.h"
#include "interrupt_API.h"
#include "Master_algorithm.h"
#include "USART_API.h"
#include "DAC_API.h"
/**************Global Variable Declarations*************/

volatile uint16_t g_ADC_value = 0x00;
volatile int g_ADC_math = 0x0000;
volatile uint8_t
volatile uint8_t
volatile uint8_t
volatile uint8_t
volatile uint8_t
volatile uint8_t
g_collect = 0;
g_testmode = 0;
g_mode = 0;
g_face
= 0;
g_phase = 0;
g_lock
= 0;
volatile uint8_t g_facevalue = 0;

volatile uint8_t g_phasevalue = 0;
volatile uint8_t g_modevalue = 0;

uint16_t g_phs1v = 0;
uint8_t g_phs1_v[] = {0,0,0,0};
uint8_t g_phs2_v[] = {0,0,0,0};
uint8_t g_phs3_v[] = {0,0,0,0};
uint8_t g_phs4_v[] = {0,0,0,0};
volatile uint16_t g_phs1_v_rx[] =
{0xFFF0,
0xFFF0, 0xCBC0,
0x0000, 0x9990, 0xCBC0,
0xFFF0, 0xED80, 0xD1E0,
0x51E0, 0x76C0, 0x76C0,
0x0000, 0x0000, 0x0000,
0x6040, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000,
0xB220, 0x9680, 0x70A0,
0x0000, 0x0000, 0xB740,
0x0000, 0x9BA0, 0x9990,
0x0000, 0x0000, 0xFFF0,
0xFFF0, 0x0000, 0xFFF0,
};
{0x9EB0,
0x9470, 0x0000,
0xE970, 0x0000, 0x5A10,
0x9260, 0xB220, 0x9680,
0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000,
0x6040, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000,
0xED80, 0xD1E0, 0xA8F0,
0x76C0, 0x76C0, 0xFFF0,
0x9680, 0xFFF0, 0xF6C0,
0xB220, 0x9990, 0x000,
0x0000, 0xD4F0, 0x0000
};
{0x9EB0,
0x0000, 0x5A10,
0x0000, 0xF6C0, 0x0000,
0x0000, 0x76C0, 0x76C0,
0xA8F0, 0xD1E0, 0xED80,
0xD4F0, 0xDA10, 0xE970,
0x0000, 0x0000, 0x6040,
0xC070, 0xCFD0, 0xD4F0,
0x0000, 0x0000, 0x0000,
0x9680, 0xB220, 0x0000,
0x76C0, 0xFFF0, 0x0000,
0x76C0, 0x9990, 0x9260,
0x9470, 0x0000, 0x0000
};
{0x0000,
0xFFF0, 0xFFF0,
0xE970, 0x9990, 0xFFF0,
0xFFF0, 0x0000, 0x0000,
0x70A0, 0x9680, 0xB220,
0xD4F0, 0xDA10, 0xE970,
0x0000, 0x0000, 0x6040,
0xC070, 0xCFD0, 0xD4F0,
0x76C0, 0x76C0, 0x70A0,
0xD1E0, 0xED80, 0x8410,
0xD1E0, 0x0000, 0x9990,
0xED80, 0xF6C0, 0xFFF0,
0xFFF0, 0xD4F0, 0xA7E0
};
int main(void)
{
0xB740,
0x2E10,
0xA8F0,
0x72B0,
0xA8F0,
0x0000,
0x51E0,
0x0000,
0x76C0,
0x76C0,
0x0000,
0xF6C0,
0x9680,
0x8830,
0x51E0,
0x8830,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x9BA0,
0x0000,
0x2E10,
0x70A0,
0x51E0,
0xA8F0,
0x0000,
0x72B0,
0x8830,
0xD1E0,
0xED80,
0xCFD0,
0x9990,
0x0000,
0x0000,
0x0000,
0x8830,
0x0000,
0x51E0,
0x70A0,
0xA8F0,
0xC070,
0xFFF0,
0xFFF0,
0x2E10,
0x70A0,
0x51E0,
0x0000,
0x8830,
0x0000,
0x0000,
0x0000,
0x0000,
0x0000,
0x9990,
0xD1E0,
0x8830,
0x72B0,
0x0000,
0xA8F0,
0x51E0,
0x70A0,
0x0000,
0x0000,
0xFFF0,
0x8410,
0x0000,
0x0000,
0x0000,
0x0000,
0x8830,
0x51E0,
0x8830,
0x9680,
0xB220,
0xCFD0,
0x0000,
0x76C0,
0x0000,
0x51E0,
0x0000,
0xA8F0,
0x72B0,
0xA8F0,
0xA8F0,
0xC070,
0x0000,
// Set the different I/O's

// set Lock as Output
DDRA |= (1 << LOCK);
// set peak detector output as input to ADC0
DDRA &= ~(1 << PDOUT);
// set the SPDT as outputs
DDRC |= ( 1 << SPDTUC0) | ( 1<< SPDTUC1);
// set the SP3T as outputs
DDRC |= ( 1 << SP3TUC0) | ( 1<< SP3TUC1);
// set the TESTDIP as inputs
DDRC &= ~(1 << TESTDIP0) & ~( 1 << TESTDIP1);
// set Comparator out as input
DDRD &= ~(1 << CMPOUT);
// set CTRL line as GPIO for RF board for future use.
//DDRD |= (1 << CTRL0 ) | (1 << CTRL1);
// convert the recive characters to number value

g_mode = char_to_num(g_mode);
g_face = char_to_num(g_face);
// convert the recieve character phase value to voltage
value
g_phs1v = convert_data_voltage(g_phs1_v);
g_phs1v = (g_phs1v << 4);
// set the system variables
set_face(g_face);
set_mode(g_mode);
SPI_MasterTransmit_DAC(setDACE,(g_phs1v >> 8),
/* test CODE */
// Initialize all the Peripherals required
g_phs1v);
// Initialize ADC
initialize_ADC_single_conv();
set_ADC_clock();
enable_ADC();
set_ADC_trigger_source();
// Initialize SPI
SPI_MasterInit();
// Initialize USART
USART_init();
// disable the Semaphore
g_collect = 0;
// Check to see what test mode the uC should be on
// MATLAB GUI mode
if ( (PINC & TESTMODEMASK) == TESDTMODEMATLAB )
{
SPI_MasterTransmit_DAC(set_pwrDACA,0xff,0xff);
while(1)
{
// receive the mode
g_mode = USART_rx();
// receive the face
g_face = USART_rx();
// receive the phase 1 value
g_phs1_v[1] = USART_rx();
SPI_MasterTransmit_DAC(setDACF,(g_phs2v >> 8),

g_phs2v);
SPI_MasterTransmit_DAC(setDACG,(g_phs3v >> 8),
g_phs3v);
SPI_MasterTransmit_DAC(setDACHpwrALL,(g_phs4v >> 8),
g_phs4v);
}
}
// Adaptive RX
else if ( (PINC & TESTMODEMASK) ==
TESTMODEADAPTIVERX )
{
// set the mode to receive
set_mode(RX);
// clear the semaphore
g_collect = CLEAR;
// set the comparater refrence to -50dBm
SPI_MasterTransmit_DAC(set_pwrDACA,(MINPWRLVL
>> 8), MINPWRLVL);
// Initialize Interrupts
enable_interrupts();
enable_int0_rising_edge();
while (1)
{
// semaphore check
if(g_collect == CLEAR)
{
// clear lock semaphore
g_lock = CLEAR;
clr_lock();
// start the face loop
for (g_facevalue = 0; g_facevalue <
NUMBEROFFACES; g_facevalue++)
{
set_face(g_facevalue+1);
// start the phase loop
for (g_phasevalue = 0; g_phasevalue <
NUMBEROFPOINTSRX; g_phasevalue++ )
{
SPI_MasterTransmit_DAC(setDACE,(g_phs1_v_rx[g_phasevalue
] >> 8), g_phs1_v_rx[g_phasevalue] );
g_collect = SET;
SPI_MasterTransmit_DAC(setDACF,(g_phs2_v_rx[g_phasevalue]
>> 8), g_phs2_v_rx[g_phasevalue] );
SPI_MasterTransmit_DAC(setDACG,(g_phs3_v_rx[g_phasevalue
] >> 8), g_phs3_v_rx[g_phasevalue] );
SPI_MasterTransmit_DAC(setDACHpwrALL,(g_phs4_v_rx[g_ph
asevalue] >> 8), g_phs4_v_rx[g_phasevalue] );
_delay_ms(DELAYTIME*20);
}
}
}
if ( g_collect == SET)
{
// set the lock semaphore
g_lock = SET;
set_lock();
// clear semaphore
g_collect = CLEAR;
// set the face and phase count
g_facevalue = g_face;
g_phasevalue = g_phase;
// set the beam direction
set_face(g_face+1);
SPI_MasterTransmit_DAC(setDACE,(g_phs1_v_rx[g_phase] >>
8), g_phs1_v_rx[g_phase] );
SPI_MasterTransmit_DAC(setDACF,(g_phs2_v_rx[g_phase] >>
SPI_MasterTransmit_DAC(setDACG,(g_phs3_v_rx[g_phase] >>
SPI_MasterTransmit_DAC(setDACHpwrALL,(g_phs4_v_rx[g_ph
ase] >> 8), g_phs4_v_rx[g_phase] );
//delay
_delay_ms(DELAYTIME*20*5);
}
}
}
// Future work
else if ( (PINC & TESTMODEMASK) ==
TESTMODEADAPTIVETXRX )
{
g_testmode = ERRORTESTMODE;
}
else
{
g_testmode = ERRORTESTMODE;
}
}
/*----------------------------------------------------* Function: ISR
*
* Description: Interrupt service routine for a external
*
hardware interrupt. This interrupt is
*
triggered on a rising edge. The trigger
*
is output of the comparator.
*
* param vector address : interrupt 0 vector address
*--------------------------------------------------------*/
ISR (INT0_vect)
{
// Set the Semaphore
// Save the Important values

g_face = g_facevalue;
// The face of Antenna used
g_phase = g_phasevalue; // The Phase index
if ( g_lock == CLEAR)
{
start_conversion_ADC();
while(!(ADCSRA & 0x10));
ADCSRA|=(1<<ADIF);
g_ADC_value = ADC;
SPI_MasterTransmit_DAC(set_pwrDACA,(g_ADC_value
>> 8) , g_ADC_value);
}
else
{
SPI_MasterTransmit_DAC(set_pwrDACA, (MINPWRLVL
>> 8) , MINPWRLVL);
}
}
/*******************************************************
* File
: ADC_API.h
*
*
* Author
: Mayur Bansal (mb)
*
*
* Mayur Bansal
*
********************************************************/
#ifndef ADC_API_H_
#define ADC_API_H_
/*******************Function Prototypes*****************/
/*----------------------------------------------------* Function: initialize_ADC_single_conv
*
* Description: Initialize the ADC
*--------------------------------------------------------*/
void initialize_ADC_single_conv();
/*----------------------------------------------------* Function: enable_ADC
*
* Description: enable the ADC
*--------------------------------------------------------*/
void enable_ADC();
/*----------------------------------------------------* Function: start_conversion_ADC
*
* Description: start a single conversation of the ADC
*--------------------------------------------------------*/
void start_conversion_ADC();
/*----------------------------------------------------* Function: set_ADC_clock
*
* Description: set the ADC clock to OSC/4
*--------------------------------------------------------*/
void set_ADC_clock();
/*-----------------------------------------------------
* Function: set_ADC_trigger_source
*
* Description: set the ADC trigger to free running
*--------------------------------------------------------*/
void set_ADC_trigger_source();
#endif /* ADC_API_H_ */
/*******************************************************
* File
: ADC_API.c
*
*
* Author
: Mayur Bansal (mb)
*
*
* Mayur Bansal
*
********************************************************/
#include <avr/io.h>
#include "ADC_API.h"
/*----------------------------------------------------* Function: initialize_ADC_single_conv
*
* Description: Initialize the ADC
*--------------------------------------------------------*/
void initialize_ADC_single_conv()
{
// Reference to AREF, Internal VREF turned off
ADMUX &= ~(1 << REFS1);
ADMUX |= (1 << REFS0);
//
// Left justified on result

ADMUX |= (1 << ADLAR);
//
// Single ended input to ADCO located PORTA0

ADMUX &= ~(1 << MUX5);
ADMUX &= ~(1 << MUX4);
ADMUX &= ~(1 << MUX3);
ADMUX &= ~(1 << MUX2);
ADMUX &= ~(1 << MUX0);
}
/*----------------------------------------------------* Function: set_ADC_clock
*
* Description: set the ADC clock to OSC/4
*--------------------------------------------------------*/
void set_ADC_clock()
{
// Setting a division factor of 4
ADCSRA &= (0 << ADPS2);
ADCSRA |= (1 << ADPS1);
ADCSRA &= (0 << ADPS0);
}
/*----------------------------------------------------* Function: set_ADC_trigger_source
*
* Description: set the ADC trigger to free running
*--------------------------------------------------------*/
void set_ADC_trigger_source()
{
// Free Running mode
ADCSRB &= (0 << ADTS2);
}
/*******************************************************
* File
: DAC_API.h
*
*
* Author
: Mayur Bansal (mb)
*
*
* Mayur Bansal
*
********************************************************/
#ifndef DAC_API_H_
#define DAC_API_H_
}
/*----------------------------------------------------* Function: enable_ADC
*
* Description: enable the ADC
*--------------------------------------------------------*/
void enable_ADC()
{
// set the ADC enable bit
ADCSRA |= (1 << ADEN);
//Auto Trigger based in ADCSRB
ADCSRA |= (1 << ADATE);
/*
DAC Command and Address Codes
C3 | C2 | C1 | C0 |
0 | 0 | 0 | 0 | Write to Input Register n
0 | 0 | 0 | 1 | Update(Power up ) DAC Register n
0 | 0 | 1 | 0 | Write to Input Register n, Update ( Power up) All
0 | 0 | 1 | 1 | Write to and Update (power up) n
0 | 1 | 0 | 0 | Power Down n
0 | 1 | 0 | 1 | Power Down Chip ( All DACs and References)
0 | 1 | 1 | 0 | Select Internal Reference ( Power-up Reference)
0 | 1 | 1 | 1 | Select External Reference ( Power-Down Reference)
1 | 1 | 1 | 1 | No Operation
}
/*----------------------------------------------------* Function: start_conversion_ADC
*
* Description: start a single conversation of the ADC
*--------------------------------------------------------*/
void start_conversion_ADC()
{
// set the converstion bit of ADC
ADCSRA |= (1 << ADSC);
A3 | A2 | A1 | A0 |
0 | 0 | 0 | 0 | DAC A
0 | 0 | 0 | 1 | DAC B
0 | 0 | 1 | 0 | DAC C
0 | 0 | 1 | 1 | DAC D
0 | 1 | 0 | 0 | DAC E
0 | 1 | 0 | 1 | DAC F
0 | 1 | 1 | 0 | DAC G
0 | 1 | 1 | 1 | DAC H
1 | 1 | 1 | 1 | All DACs
*/
#ifndef INTERRUPT_API_H_
#define INTERRUPT_API_H_
/*
24-Bit input Protocol
C3-C2-C1-C0-A3-A2-A1-A0-D15-D14-D13-D12-D11-D10-D9-D8D7-D6-D5-D4-D3-D2-D1-D0
Command Address Data
DAC_API_H_
/*----------------------------------------------------* Function: enable_interrupts

*
* Description: Enable all interrupts
*--------------------------------------------------------*/
void enable_interrupts ();
*/
#define setDACA
#define setDACB
#define setDACC
#define setDACD
#define setDACE
#define setDACF
#define setDACG
#define setDACH
#define pwrDACA
#define pwrDACB
#define pwrDACC
#define pwrDACD
#define pwrDACE
#define pwrDACF
#define pwrDACG
#define pwrDACH
#define pwrALL
#define setREF
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x1F
0x74
#define setDACApwrALL 0x20

#define setDACBpwrALL 0x21
#define setDACCpwrALL 0x22
#define setDACDpwrALL 0x23
#define setDACEpwrALL 0x24
#define setDACFpwrALL 0x25
#define setDACGpwrALL 0x26
#define setDACHpwrALL 0x27
#define set_pwrDACA
#define set_pwrDACB
#define set_pwrDACC
#define set_pwrDACD
#define set_pwrDACE
#define set_pwrDACF
#define set_pwrDACG
#define set_pwrDACH
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
#endif
/*******************************************************
* File
: interrupt_API.h
*
*
* Author
: Mayur Bansal (mb)
*
*
* Mayur Bansal
*
********************************************************/
/*----------------------------------------------------* Function: enable_int0_rising_edge

*
* Description: sets the interrupt on the rising edge
*
for INT0
*--------------------------------------------------------*/
void enable_int0_rising_edge();
#endif /* INTERRUPT_API_H_ */
/*******************************************************
* File
: interrupt_API.c
*
*
* Author
: Mayur Bansal (mb)
*
*
* Mayur Bansal
*
********************************************************/
#include <avr/io.h>
#include "interrupt_API.h"
#include <avr\interrupt.h>
/*----------------------------------------------------* Function: enable_interrupts

*
* Description: Enable all interrupts
*--------------------------------------------------------*/
void enable_interrupts()
{
sei();
}
/*----------------------------------------------------* Function: enable_int0_rising_edge
*
* Description: sets the interrupt on the rising edge
*
for INT0
*--------------------------------------------------------*/
void enable_int0_rising_edge()
{
//Trigger on rising edge of INT0
EICRA |= (1 << ISC00) | (1 << ISC01);
//Enable INT0
EIMSK |= (1 << INT0);
}
/*******************************************************
* File
: Master_algorithm.h
*
*
* Author
: Mayur Bansal (mb)
*
*
* Mayur Bansal
*
********************************************************/
#ifndef MASTER_ALGORITHM_H_
#define MASTER_ALGORITHM_H_
#define TX_FC1 0x04
#define TX_FC2 0x05
#define TX_FC3 0x06
#define RX_FC1 0x08
#define RX_FC2 0x09
#define RX_FC3 0x0A
#define TX 0x01
#define RX 0x02
#define FC1 0x01
#define FC2 0x02
#define FC3 0x03
#define NUMBEROFMODES 2
#define NUMBEROFFACES 3
#define NUMBEROFPOINTSRX 50
#define DELAYTIME
50
#define MINPWRLVL 0x1410 // set the DAC to 0.392V appx -50dBm
power
/*----------------------------------------------------* Function: set_phases
*
* Description: Set the control voltage for the phase
*
shifters. The voltage is set as 1/3 the
*
value using DACs.
*
* param phase1: uint16_t: phase 1 control voltage
*--------------------------------------------------------*/
*
*
*
value using DACs.
*
*--------------------------------------------------------*/
void set_phases(uint16_t phase1, uint16_t phase2, uint16_t phase3,
uint16_t phase4);
/*----------------------------------------------------* Function: set_face

*
* Description: Sets the Single pole triple throw switch
*
control voltages. PORTC0:1
*
* param face: uint8_t: the face value FC1, FC2, or FC3
*--------------------------------------------------------*/
void set_face (uint8_t face);
/*----------------------------------------------------* Function: set_mode
*
* Description: Sets the Single pole double throw switch
*
*
* param face: uint8_t: the face value FTX, or RX
*--------------------------------------------------------*/
void set_mode (uint8_t mode);
/*----------------------------------------------------* Function: set_lock
*
* Description: Turn on the lock LED when adaptive mode is
*
in lock. PORT7
*--------------------------------------------------------*/
void set_lock();
/*----------------------------------------------------* Function: clr_lock
*
* Description: Turn off the lock LED when adaptive mode is
*
in lock. PORT7
*--------------------------------------------------------*/
void clr_lock();
/*----------------------------------------------------* Function: char_to_num
*
* Description: convert a ASCII decimal character to a
*
integer number in uint8_t
*
* param character: uint8_t: ASCII character
*
* return uint8_t: the actual decimal value number
*--------------------------------------------------------*/
uint8_t char_to_num (uint8_t character);
/*----------------------------------------------------* Function: convert_data_voltage
*
* Description: converts a 4 character decimal value to
*
interger value in uint16_t
*
* param v[]: uint8_t: array of ASCII character
*
* return uint16_t: the actual decimal voltage value
*--------------------------------------------------------*/
uint16_t convert_data_voltage(uint8_t v[]);
#endif /* MASTER_ALGORITHM_H_ */
/*******************************************************
* File
: Master_algorithm.c
*
*
* Author
: Mayur Bansal (mb)
*
*

* Mayur Bansal
*
********************************************************/
# define F_CPU 16000000UL
#include <avr/io.h>
#include "Master_algorithm.h"
#include "DAC_API.h"
*
*
*
value using DACs.
*
*--------------------------------------------------------*/
void set_phases(uint16_t phase1, uint16_t phase2, uint16_t phase3,
uint16_t phase4)
{
SPI_MasterTransmit_DAC(setDACE,(phase1 >> 8), phase1);
SPI_MasterTransmit_DAC(setDACF,(phase2 >> 8), phase2);
SPI_MasterTransmit_DAC(setDACG,(phase3 >> 8), phase3);
SPI_MasterTransmit_DAC(setDACHpwrALL,(phase4 >> 8),
phase4);
}
/*----------------------------------------------------* Function: set_face
*
* Description: Sets the Single pole triple throw switch
*
*
* param face: uint8_t: the face value FC1, FC2, or FC3
*--------------------------------------------------------*/
void set_face (uint8_t face)
{
if( face == FC1)
{
PORTC &= ~(1 << PC0);
PORTC &= ~(1 << PC1);
}
else if (face == FC2)
{
PORTC &= ~(1 << PC1);
PORTC |= (1 << PC0);
}
else if (face == FC3)
{
PORTC &= ~(1 << PC0);
PORTC |= (1 << PC1);
}
// error mode
else
{
PORTC |= (1 << PC0);
PORTC |= (1 << PC1);
}
}
/*----------------------------------------------------* Function: set_mode

*
* Description: Sets the Single pole double throw switch
*
*
* param face: uint8_t: the face value FTX, or RX
*--------------------------------------------------------*/
void set_mode (uint8_t mode)
{
if( mode == TX)
{
PORTC &= ~(1 << PC2);
PORTC |= (1 << PC3);
}
else if (mode == RX)
{
PORTC &= ~(1 << PC3);
PORTC |= (1 << PC2);
}
//error mode
else
{
PORTC |= (1 << PC2);
PORTC |= (1 << PC3);
}
}
/*----------------------------------------------------* Function: set_lock
*
* Description: Turn on the lock LED when adaptive mode is
*
in lock. PORT7
*--------------------------------------------------------*/
void set_lock()
{
PORTA |= (1 << PA7);
}
/*----------------------------------------------------* Function: clr_lock
*
* Description: Turn off the lock LED when adaptive mode is
*
in lock. PORT7
*--------------------------------------------------------*/
void clr_lock()
{
PORTA &= (0 << PA7);
}
/*----------------------------------------------------* Function: char_to_num
*
* Description: convert a ASCII decimal character to a
*
integer number in uint8_t
*
* param character: uint8_t: ASCII character
*
* return uint8_t: the actual decimal value number
*--------------------------------------------------------*/
uint8_t char_to_num (uint8_t character)
{
uint8_t value = 0;
if(character == 0x20) // Decimal 0
return value;
else if (character == 0x31) // Decimal 1
return value = 0x01;

else
return value;
}
/*----------------------------------------------------* Function: convert_data_voltage
*
* Description: converts a 4 character decimal value to
*
interger value in uint16_t
*
* param v[]: uint8_t: array of ASCII character
*
* return uint16_t: the actual decimal voltage value
*--------------------------------------------------------*/
uint16_t convert_data_voltage(uint8_t v[])
{
// 4 temp var
uint8_t t_1, t_2, t_3, t_4;
t_1 = char_to_num(v[1]);
uint16_t value = 0;
// convert to voltage value
value = (t_1*1000)+(t_2*100)+(t_3*10)+t_4;
return value;
}
/*******************************************************
* File
: SPI_API.h
*
*
* Author
: Mayur Bansal (mb)
*
*
* Mayur Bansal
*
********************************************************/
#ifndef SPI_API_H_
#define SPI_API_H_
// PB0 -- ~SS
// PB1 -- SCK
// PB2 -- MOSI
// PB3 -- MISO
#define SETTLING_TIME 0x05
/*----------------------------------------------------* Function: SPI_MasterInit

*
* Description: Initialize the SPI in the master mode.
*
with clock speed OSC/4
*--------------------------------------------------------*/
void SPI_MasterInit(void);
/*----------------------------------------------------* Function: SPI_MasterTransmit_DAC
*
* Description: Send the voltage set command to DAC.
*
send the packet in the protocol stated
*
DAC_API.h
*
* param cDataH: char: upper 8bits
* param cDataM: char: middle 8bits
* param cDataL: char: lower 8bits
*
* return: uint8_t
*--------------------------------------------------------*/
void SPI_MasterTransmit_DAC(char cDataH, char cDataM, char
cDataL);
#endif /* SPI_API_H_ */
/*******************************************************
* File
: SPI_API.c
*
*
* Author
: Mayur Bansal (mb)
*
*
* Mayur Bansal
*
********************************************************/
# define F_CPU 16000000UL
#include <avr/io.h>
// PB0 -- ~SS
// PB1 -- SCK
// PB2 -- MOSI
// PB3 -- MISO
/*----------------------------------------------------* Function: SPI_MasterInit
*
* Description: Initialize the SPI in the master mode.
*
with clock speed OSC/4
*--------------------------------------------------------*/
void SPI_MasterInit(void)
{
/* Set ~SS, MOSI and SCK output, all others input */
DDRB = (1<<DDB0)|(1<<DDB1)|(1<<DDB2);
/* Enable SPI, Master, set clock rate fck/4 */
SPCR = (1<<SPE)|(1<<MSTR);
// MSB first
}
/*----------------------------------------------------* Function: SPI_MasterTransmit_DAC
*
* Description: Send the voltage set command to DAC.
*
send the packet in the protocol stated
*
DAC_API.h
*
* param cDataH: char: upper 8bits
* param cDataM: char: middle 8bits
* param cDataL: char: lower 8bits
*
* return: uint8_t
*--------------------------------------------------------*/
void SPI_MasterTransmit_DAC(char cDataH, char cDataM, char
cDataL)
{
PORTB &= (0 << PB0);
/* Start transmission */
SPDR = cDataH;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)))
;
SPDR = cDataM;
;
SPDR = cDataL;
;
PORTB |= (1 << PB0);
// wail 5mS for the DAC settling time
_delay_ms(SETTLING_TIME);
}
/*******************************************************
* File
: USART_API.h
*
*
* Author
: Mayur Bansal (mb)
*
*
* Mayur Bansal
*
********************************************************/
#ifndef USART_API_H_
#define USART_API_H_
*
* Description: send the data on the transmit line
*
* param data: uint8_t: data to be sent
*--------------------------------------------------------*/
void USART_tx( uint8_t data);
/*----------------------------------------------------* Function: USART_rx
*
* Description: receive the data on the receive line
*
* return uint8_t: data to be sent
*--------------------------------------------------------*/
uint16_t USART_rx( void);
#endif /* USART_API_H_ */
/*******************************************************
* File
: USART_API.c
*
*
* Author
: Mayur Bansal (mb)
*
*
* Mayur Bansal
*
********************************************************/
#include <avr/io.h>
#include "USART_API.h"
/*----------------------------------------------------* Function: USART_init
*
* Description: Initializer the USART
*
BAUD 57600
*
Data bits: 8
*
Stop bits: 1
*--------------------------------------------------------*/
void USART_init( void)
{
/* Set baud rate */
UBRR0H = (unsigned char)((unsigned int)(MYUBRR)>>8);
UBRR0L = (unsigned char)(unsigned int)(MYUBRR);
#define F_CPU 16000000UL
#define BAUD 57600
#define MYUBRR (F_CPU/16/BAUD-1)
/*----------------------------------------------------* Function: USART_init
*
* Description: Initializer the USART
*
BAUD 57600
*
Data bits: 8
*
Stop bits: 1
*--------------------------------------------------------*/
void USART_init( void);
/*----------------------------------------------------* Function: USART_tx
/* Enable receiver and transmitter */

UCSR0B = (1<<RXEN0)|(1<<TXEN0);
/* Set frame format: 8data, 1stop bit, parity Disable, Asynchronous
Mode */
UCSR0C = (3<<UCSZ00);
// USART_Init
}
/*----------------------------------------------------* Function: USART_tx
*
* Description: send the data on the transmit line
*
* param data: uint8_t: data to be sent
*--------------------------------------------------------*/
void USART_tx(uint8_t data)
{
/* Wait for empty transmit buffer */

while ( !( UCSR0A & (1<<UDRE0)) )
;
/* Put data into buffer, sends the data */
UDR0 = data;
}
/*----------------------------------------------------* Function: USART_rx
*
* Description: receive the data on the receive line
*
* return uint8_t: data to be sent
*--------------------------------------------------------*/
uint16_t USART_rx( void)
{
/* Wait for data to be received */
while ( !(UCSR0A & (1<<RXC0)) )
;
/* Get and return received data from buffer */
return UDR0;
}
PCB Schematic
90
VCC
0
16 MHz 34
AREF 98
100
AVCC
RFC L1
99
N$2
10
31
61
80
11
32
62
81
N$2
N$2
C1 C2 C3 C4 C5
0.1u 0.1u0.1u0.1u0.1u
RESET
XTAL2
XTAL1
AREF
AVCC
AGND
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
42
41
40
39
38
37
36
35
PL7
PL6
PL5(OC5C)
PL4(OC5B)
PL3(OC5A)
PL2(T5)
PL1(ICP5)
PL0(ICP4)
A15
A14
A13
A12
A11
A10
A9
A8
82
83
84
85
86
87
88
89
PK7(ADC15/PCINT23)
PK6(ADC14/PCINT22)
PK5(ADC13/PCINT21)
PK4(ADC12/PCINT20)
PK3(ADC11/PCINT19)
PK2(ADC10/PCINT18)
PK1(ADC9/PCINT17)
PK0(ADC8/PCINT16)
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
TX3
RX3
79
69
68
67
66
65
64
63
PJ7
PJ6(PCINT15)
PJ5(PCINT14)
PJ4(PCINT13)
PJ3(PCINT12)
PJ2(XCK3/PCINT11)
PJ1(TXD3/PCINT10)
PJ0(RXD3/PCINT9)
PH7
PH6
PH5
PH4
PH3
PH2
TX2
RX2
27
18
17
16
15
14
13
12
PH7(T4)
PH6(OC2B)
PH5(OC4C)
PH4(OC4B)
PH3(OC4A)
PH2(XCK2)
PH1(TXD2)
PH0(RXD2)
ATMEGA2560V
(AD7)PA7
(AD6)PA6
(AD5)PA5
(AD4)PA4
(AD3)PA3
(AD2)PA2
(AD1)PA1
(AD0)PA0
71
72
73
74
75
76
77
78
(OC0A/OC1C/PCINT7)PB7
(OC1B/PCINT6)PB6
(OC1A/PCINT5)PB5
(OC2A/PCINT4)PB4
(MISO/PCINT3)PB3
(MOSI/PCINT2)PB2
(SCK/PCINT1)PB1
(SS/PCINT0)PB0
26
25
24
23
22
21
20
19
PB7
PB6
PB5
PB4
(A15)PC7
(A14)PC6
(A13)PC5
(A12)PC4
(A11)PC3
(A10)PC2
(A9)PC1
(A8)PC0
60
59
58
57
56
55
54
53
(T0)PD7
(T1)PD6
(XCK1)PD5
(ICP1)PD4
(TXD1/INT3)PD3
(RXD1/INT2)PD2
(SDA/INT1)PD1
(SCL/INT0)PD0
50
49
48
47
46
45
44
43
LOCK
ERROR
PA5
PA4
PA3
PA2
PA1
PA0
H2
MOUNT-PAD-ROUND2.8
H3
MOUNT-PAD-ROUND2.8
H4
MOUNT-PAD-ROUND2.8
PORTB
MISO
MOSI
SCK
~SS
8
7
6
5
4
3
2
1
TESTDIP1
TESTDIP0
PC5
PC4
SPDTUC1
SPDTUC0
SP3TUC1
SP3TUC0
8
7
6
5
4
3
2
1
PORTC
8
7
6
5
4
3
2
1
PORTD
8
7
6
5
4
3
2
1
PORTE
8
7
6
5
4
3
2
1
PORTF
CTRL1
CTRL0
PD5
PD4
TX1
RX1
SDA
CMPOUT
9
8
7
6
5
4
3
2
PE7
PE6
PE5
PE4
PE3
PE2
(ADC7/TDI)PF7
(ADC6/TDO)PF6
(ADC5/TMS)PF5
(ADC4/TCK)PF4
(ADC3)PF3
(ADC2)PF2
(ADC1)PF1
(ADC0)PF0
90
91
92
93
94
95
96
97
A7
A6
A5
A4
A3
A2
A1
PDOUT
(OC0B)PG5
(TOSC1)PG4
(TOSC2)PG3
(ALE)PG2
(RD)PG1
(WR)PG0
1
29
28
70
52
51
PG5
PG4
PG3
PG2
PG1
PG0
(CLKO/ICP3/INT7)PE7
(T3/INT6)PE6
(OC3C/INT5)PE5
(OC3B/INT4)PE4
(OC3A/AIN1)PE3
(XCK0/AIN0)PE2
(TXD0)PE1
(RXD0/PCIN8)PE0
8
7
6
5
4
3
2
1
TX
RX
GND
Reset Circuit
RESET
R3
N$71
10k D1
N$2
C7 C6
GND
20p 20p
RESET 30
CSM-7X-DU 33
Q1
H1
MOUNT-PAD-ROUND2.8
PORTA
VCC
UC1
R47
R55
Mounting Holes
RESET
470
PWR
0.1u
C35
GND
ISP Header
ISP-PROG
RESET
GND
VTG
RST
GND
2
5
6
1
4
3
MISO
MOSI
SCK
MISO
MOSI
SCK
AVR ISP
Microcontroller
B
REFLO
VOUTA
VOUTB
VOUTC
VOUTD
VOUTE
VOUTF
VOUTG
VOUTH
PDOUT5
2
3
5
6
15
16
17
18
0.1u
R4
100p
GND
3
7.5K
C10
R21
R22
R23
R24
R25
R26
R27
R28
0
0
0
0
0
0
0
0
DACA 4
DACA
DACB
DACC
DACD
DACE
DACF
DACG
DACH
LM339D
CMPA 2
R20
C8
CMPOUT
1u
GND
AGND
GND0
GND1
~CS
SCK
SDO
SDI
20
21
SDI_DAC
9
10
12
11
N$23 C9
12
R2
REFCOMP
REFIN
~LDAC
PROSEL
VCC
~CLR
~SS
SCK_DAC
C37
0.1u 100p
VREF
R57
3.3k
AGND
C11
4
7
8
14
19
13
0.1u
AGND
1
2
C36
MOSI_JP
MOSI
SDI_DAC
R56
AGND
1
2
VCC
SCK_JP
SCK
SCK_DAC
Comparator
VCC
Ocal DAC
Peak Detector
VCC
R58
N$96
C16
Phase Shifter Control line Amplifier
10k
R33
10k
R38
20k
AMPB
LT6005
7
DACH
R39
PS2
R30
10k
R36
20k
14
AMPD
LT6005
16
15
0
R32
10k
R40
PS4
1n
R5 C26
RF
4
1
C27 C38
AMPPWR
1u 100p
C17
GND
0.1u
VCC
EN VOUT
RF GND1
GND0
5
2
R19
0
PDOUT
C40
100p
GND
GND
GND GND
AGND
AGND
AGND
DACF
R35
X1
49.9
PS3
R31
R59
13
20k
10
11
AGND
PS1
R29
1
2
DACG
R37
AGND
AGND
DACE
R34
AMPC
LT6005
12
+15V
AMPA
LT6005
3
LTI-SASF54GT
100p
Peripherals
20k
Input Voltage
IN
P$1*2
P$3
P$4
VIN
PJ-002AH-SMT
GND
2.5V DAC Reference
NCP1117
VIN
C24
IN
10u 1
OUT
TAB
2
TAB
0.5A
N$26
C25
GND
+3V3
VCC
5V System
VREF
LT1761
VIN
C14
FUSE
10u
1u
GND
IN
SHDN
GND
OUT
BYP
GND
5
4
C15
10u
GND
GND
Current Limit: 1000mA
15 Volt Amplifier Rails

+15V
Connecting Grounds
LM3480
VIN
OUT
0.1u
GND
RFC
+15V
IN
C21
0.1u
GND
L2
AGND
C20
GND
GND
Power
B
Signal Strength Display

VCC
Control Lines
R61
JP_RF
0
CTRL1
SPDT0
SPDT1
SP3T0
SP3T1
SSD
3
6
Status LED
R1
RED
VIN
GND
R12
LOCK
470
TX
R54
GREEN
LOCK
VCC
GREEN
VREF
RX
GND
GREEN
VCC
470
R49
+15V
470
R53
R7
SP3T0
SP3T1 470
GND
GREEN
+15V
R8
R6
SPDT0
SPDT1 470
ERROR
470
R51
TESTDIP0
470
GND
R52
TESTDIP1
470
10k
RSSI9
RED
LED2
20
RSSI8
RED
LED3
19
RSSI7
RED
LED4
18
RSSI6
RED
LED5
17
RSSI5
YELLOW
LED6
16
RSSI4
YELLOW
LED7
15
RSSI3
Green
LED8
14
RSSI2
Green
LED9
13
RSSI1
Green
LED10
12
RSSI0
Green
RHI
REFOUT
REFADJ
RLO
MODE
SIGIN
V-
LM3914V
VCO Tunning
YELLOW
RX
GND
GREEN
SP3T0
10k
R14
10k
R13
GREEN
SP3T1
GND
VCO
P$2
10k
R18
10k
R17
GND
GREEN
SPDT0
GREEN
SPDT1
470
RED
ERROR
GND
LED1
GND
470
GND
10u PDOUT
YELLOW
TX
470
R9
R63
11
GND
470
R10
C29
470
R11
VREF
470
10
+15V
VIN
10k
R16
R15
GND
V+
P$3
1
3
5
7
9
11
13
15
RT1
3224W-1-502E
2
4
6
8
10
12
14
16
P$1
CTRL0
PS1
PS2
PS3
PS4
VCO
GND
GREEN
TESTDIP0
GREEN
TESTDIP1
RF Interface
B
GND
DIP Pins
1u
TX
RX
C2+
R46
GND
C2-
11
10
12
9
T1IN
T2IN
R1OUT
R2OUT
T1OUT
T2OUT
R1IN
R2IN
14
7
13
8
ON
10k
R41
10k
R44
R42
10k
10k
6
7
8
9
3
2
1
GND
15
R43
10k
DB1
1
2
3
4
5
MAX232TSSOP
10k
GND
R45
GND
V-
1u
C1-
C34
VCC
V+
C33
C31
C1+
GND
1u
1u
U1
C30
ON
16
ON
GND
219-02
TESTDIP1 4
1
TESTDIP0
TEST_MODE
GND
1u
219-02
C32
SP3TDIP1 4
1
SP3TDIP0
ANT_FACE
219-02
R62
VCC
SPDTDIP1 4
1
SPDTDIP0
ANT_MODE
VCC
RS-232 DRIVER
SP3TDIP0
SP3T0
SP3TUC0
3
2
1
SPDTDIP0
SPDT0
SPDTUC0
GND
JP-SP3T0
ANT MODE
SPDT[1]
SPDT[0]
MODE
RX
TX
ANT FACE
3
2
1
JP-SPDT0
SP3TDIP1
SP3T1
SP3TUC1
3
2
1
SPDTDIP1
SPDT1
SPDTUC1
JP-SPDT1
JP-SP3T1
TEST MODE
SP3T[1]
SP3T[0]
FACE
TEST[1]
TEST[0]
MODE
MATLAB GUI
ADAPTIVE RX
ADAPTIVE TX/RX
UNUSED
TEST MODE
B
PCB Layout
96
Bill Of Materials
The complete electrical bill of materials (BOM) is presented below for the Digital
Control Board.
98
Part
Crystal
Microcontroller (ATmega2560)
LT1761(2.5V)
NCP1117ST50T3G
LM3480(+15V)
LTC2656
LT5534
LT6005
LM339
LM3914
MAX232
16 Pin Conn (16 POS)
AVR-ISP-header (6POS)
SPI Jumpers (2POS)
DB-9
DIP- 2 POS
Jumper
SMA
16 PIN IDC Cable
PWR70Q2S
LED Green
LED Red
LED Yellow
0 Ohm
49.9 ohm
7.5k
3.3k
470 ohm
20k ( 0.5%)
10k (0.5%)
10K
5K POT
CER 0.1uF
CER 20pF
CER 100pF 16V
CER 1uF 16V
TANT 0.1uF 35V
TANT 1uF 16V
TANT 10uF 20V
Fuse
RFC
Diode
20V
Power Jack
Manufacturer
ECS Inc
Atmel
Linear Technology
ON Semi
Texas Instuments
Linear Technology
Linear Technology
Linear Technology
Texas Instuments
Texas Instuments
Texas Instuments
FCI
FCI
FCI
TE Connectivity
CTS Electrocomponents
TE Connectivity
TE Connectivity
TE Connectivity
C & K Components
OSRAM Opto Semiconductors Inc
Yageo
Rohm Semiconductor
Panasonic Electronic Components
Stackpole Electronics Inc
Vishay Dale
Vishay Dale
Bourns Inc.
Kemet
Yageo
Kemet
TDK Corporation
Kemet
Kemet
Kemet
TE Connectivity
TDK Corporation
Micro Commercial Co
CUI Inc
CUI Inc
Distributor
Digikey
Digikey
Digikey
Digikey
Digikey
http://www.linear.com
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Model Number
ECS-160-20-5PXDU-TR
ATMEGA2560-16AU
LT1761IS5-2.5#TRMPBF
NCP1117ST50T3G
LM3480IM3-15/NOPB
LTC2656IFE-L12#PBF
LT5534ESC6#TRMPBF
LT6005CGN#PBF
LM339ADR
LM3914VX/NOPB
MAX232ECPW
67996-216HLF
67996-206HLF
67996-104HLF
1734351-1
219-2LPST
2-382811-1
2081233-1
A3DDH-1606G
PWR70Q2S
LG Q971-KN-1
LS Q976-NR-1
LY Q976-P1S2-36
RC0402JR-070RL
MCR01MRTF49R9
ERJ-2GEJ752X
ERJ-2GEJ332X
RMCF0402JT470R
CRCW040220K0DHEDP
CRCW040210K0DHEDP
ERJ-2RKF1002X
3224W-1-502E
C0402C104K8PACTU
CC0402JRNPO9BN200
C0402C101K4GACTU
C1005X5R1C105K050BC
T491A104M035AT
T491A105K016AT
T494A106M020AT
0603SFF050F/32-2
MLK1005S22NJ
1N4148X-TP
ETSA200200UDC-P5P-SZ
PJ-002AH-SMT-TR
Unit Price ($)

Qty/Board
Total
$1.46
1
$1.46
$18.19
1 $18.19
$2.62
1
$2.62
$0.49
1
$0.49
$0.97
1
$0.97
$14.37
1 $14.37
$6.50
1
$6.50
$2.06
1
$2.06
$0.41
1
$0.41
$3.66
1
$3.66
$1.34
1
$1.34
$4.90
2
$9.80
$0.29
6
$1.74
$0.27
1
$0.27
$1.18
1
$1.18
$0.60
3
$1.80
$0.09
4
$0.36
$1.65
1
$1.65
$7.19
1
$7.19
$3.89
1
$3.89
$0.07
16
$1.09
$0.09
8
$0.72
$0.09
3
$0.27
$0.01
20
$0.24
$0.10
1
$0.10
$0.10
2
$0.20
$0.10
4
$0.40
$0.02
10
$0.17
$0.28
4
$1.10
$0.28
4
$1.10
$0.10
11
$1.10
$3.64
1
$3.64
$0.10
9
$0.90
$0.10
2
$0.20
$0.10
4
$0.40
$0.12
7
$0.84
$0.38
2
$0.76
$0.34
1
$0.34
$1.02
3
$3.06
$0.35
1
$0.35
$0.10
2
$0.20
$0.20
1
$0.20
$24.23
$0.00
$1.89
1
$1.89
Block Diagrams
(a) Electrical Model
(b) Spice Netlist
Figure I.1: Schottky Diode Chip Model
100
Figure I.2: ATmega2560 Block Diagram
101
Figure I.3: Analog to Digital Converter Block Schematic
102
Figure I.4: LTC2656 Block Diagram
103

Digital Control Board For Phased Array Antenna Beam Steering in A

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Digital Control Board For Phased Array Antenna Beam Steering in A

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Digital Control Board For Phased Array Antenna Beam Steering in A

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DIGITAL CONTROL BOARD FOR PHASED ARRAY ANTENNA BEAM

STEERING IN ADAPTIVE COMMUNICATION APPLICATIONS

Digital Control Board for Phased Array

Bryan Mealy, Ph.D.

Lynne Slivovsky, Ph.D.

Dennis Derickson, Ph.D.

Adaptive Receive Mode . . . . . . . . . . . . . . . . . . .

Interrupt Feedback Loop . . . . . . . . . . . . . . . . . . .

Log-Amp Power Detector Analysis . . . . . . . . . . . . . . . . .

4 INTERRUPT FEEDBACK LOOP

RF Single Pole Double Throw (SPDT) Switch . . . . . . . . . . .

RF Single Pole Triple Throw (SP3T) Switch . . . . . . . . . . . .

Voltage Control Oscillator (VCO) Control Line . . . . . . . . . .

6 PRINTED CIRCUIT BOARD DESIGN

7 GRAPHICAL USER INTERFACE (GUI) CONTROL SYSTEM

GUI Inputs and Features . . . . . . . . . . . . . . . . . . . . . . .

Drop Down Menus . . . . . . . . . . . . . . . . . . . . . .

Additional Figure Checkboxes . . . . . . . . . . . . . . . .

Test and Results . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 ADAPTIVE RECEIVE MODE

Adaptive Receive Algorithm . . . . . . . . . . . . . . . . . . . . .

9 CONCLUSIONS AND FUTURE WORK

2013 IEEE APS Student Design Challenge: Reconfigurable Antennas 69

LT 5534 Demo Board Schematic . . . . . . . . . . . . . . . . . . .

LT 5538 Demo Board Schematic . . . . . . . . . . . . . . . . . . .

Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

16-Pin IDC Pin-out Between Digital Control Board and RF Board

ADC Conversion Time . . . . . . . . . . . . . . . . . . . . . . . .

DAC Command Codes . . . . . . . . . . . . . . . . . . . . . . . .

DAC Address Codes . . . . . . . . . . . . . . . . . . . . . . . . .

Truth Table for SPDT, VHIGH = 2V to 5V, VLOW = 0V Insertion

SPDT, Antenna Mode Truth Table . . . . . . . . . . . . . . . . .

Truth Table for HMC245QS16 and the Active Antenna Face . . .

VCO Tuning Circuit Result . . . . . . . . . . . . . . . . . . . . .

Hexadecimal Notation for ASCII Decimal Characters to 8-bit Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GUI Test Result . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Data for Adaptive Receive Mode Test Procedure . . . . . . .

A Radiation Diagram with Main Lobe . . . . . . . . . . . . . . .

System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .

Tetrahedron Antenna Model . . . . . . . . . . . . . . . . . . . . .

Digital Control Board Block Diagram . . . . . . . . . . . . . . . .

IDC connector Pin Positions . . . . . . . . . . . . . . . . . . . . .

Screen shot of MATLAB GUI . . . . . . . . . . . . . . . . . . . .

Adaptive RX, Example System Configuration . . . . . . . . . . .

Inner Feedback Loop Block Diagram . . . . . . . . . . . . . . . .

DC log-amp BJT implementation . . . . . . . . . . . . . . . . . .

Demo Board DC748A . . . . . . . . . . . . . . . . . . . . . . . . .

LT-5534 log-amp Characteristics . . . . . . . . . . . . . . . . . . .

Demo Board DC1120A . . . . . . . . . . . . . . . . . . . . . . . .

LT-5538 Output characteristics . . . . . . . . . . . . . . . . . . .

Analog to Digital Converter Timing Diagram for Single Conversion

LTC2656 DAC Load Sequence . . . . . . . . . . . . . . . . . . . .

LM339 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . .

JSPHS-2484+ Phase Shifter, Interpolated Data . . . . . . . . . .

Operational Amplifier in Non-Inverting Configuration . . . . . . .

LTSpice Simulation Schematic, LT6005 Non-Inverting Gain OpAmp Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LTSpice Simulation results, LT6005 Op-amp Non-Inverting Gain

LTSpice Simulation results, LT6005 Op-amp Non-Inverting Gain

Monte Carlo Analysis for Amplification Circuit, Expanded View .