MMI PAL Handbook 5ed 1986
MMI PAL Handbook 5ed 1986
MMI PAL Handbook 5ed 1986
Programmable
Logic Array
Handbook
FIFTH EDITION
Monollthlom
• •morl••
PAL®, HAL®,PALASM®, and SKINNYDIP® are registered trademarks of Monolithic Memories Inc.
PLer'" I MegaPAL"", ZHAL YII , ProPALTM I and SMACTM are trademarks of Monolithic Memories Inc.
Logic Cell ArrayTM is a trademark of XILINX.
@Copyright1978, 1981, 1983, 1985, 1986 Monolithic Memories Inc .
• 2175 Mission College Boulevard. Santa Clara, CA 95054-1592. (408) 970-9700. (910) 339-9220
T~ble of Contents
PAL® DeVice Introduction ........................... 1·2
PAL®/HAL® Device Specifications .................... 2·1
Table of Contents for Section 2 ............................................. , ........... , .. 2-2
PAL/HAL pevices ......... , ............................................2-3
Small 20 Series: 10H8, 12H6, .14H4, 16H2, 16Cl,10L8, ~2L6, 14L4, 16L2 , ....... 2-5
20 (standard) ................................. , .................................................2-8
20-2 (half power) .........................•............................................ : ....... 2-9
Medium 20 Series: 16L8, 16R8, 16R6, 16R4 ............................................ 2-19
20 (standard) •......................... : ...................................................... 2-21
20A (high speed) ............................................................................ 2-22
20A-2 (high speed and half power) ...................................................... 2-24
20A-4 (high speed and quarter power)' .................................................. 2-25
208 (very high speed) .................... : ................................................. 2-26
208-2 (very high speed and half power) ................................................ 2-27
208-4 (very high speed and quarter power) ... ," .......... : ......... c....... ::; ....... 2-28
200 (ultra high speed)· .......................... " .......................................... 2-29
Medium 2QPA Series: 16P8A, 16RP8A, 16RP6A,16RP4A ........................... 2-37
Lar.ge 20 Series: 16X4, 16A4 ................................................................ 2-45
Large 20RA: 16RA8 ........................................................................... 2-51
Small 24 Series: 12L 10, 14L8, 16L6, 18L4, 20L2, 20Cl .............................. 2-55
Small 24A Decoder Series: 6L 16A, 8L 14A .............................................. 2-65
Medium 24 Series:20L8, 20R8, 20R6, 20R4 ............................................ 2-70
24A (high speed) ............................................................................ 2-73
24A-2 (high speed and half power) ...................................................... 2-75
248 (very high speed) ...................................................................... 2-76
Medium 24X Series: 20L 10, 20X10, 20X8, 20X4 ....................................... 2-81
24X (standard) ............................................................................... 2-83
24XA (high speed) .......................................................................... 2-85
Large 24RS Series: 20S10, 20RS10, 20RS8, 20RS4 ................................... 2-90
Large 24RA: 20RA 10 ................................ , ......... , ............................... 2-98
PAL32VX10/A ................................................................................. 2-103
PMS14R21/A .................................................................................. 2-113
PAL lOH20P8 ........................ : .......................................................... 2-115
MegaPAL.devices: 32R16, 64R32 ........................................................ 2-119
fMAXParameters ............................................................................. 2-126
Waveforms .............. , ...................................................................... 2-127
Test Load ................... : .................................................................. 2-128
ii Monolithic m Memories
Table of Contents
MMI PAL® Device Programmer Reference Guide ...... 3·1
Data 1/0 Corporation
20 Pin Device Families .......................................................................3-3
24 Pin and MegaPAL Device Families .....................................................3-4
Digelec
20 Pin Device Families .......................................................................3-5
24 Pin and MegaPAL Device Families .....................................................3-6
Kontron
20 Pin Device Families .......................................................................3-7
24 Pin and MegaPAL Device Families .....................................................3-8
Micropross
20 Pin Device Families ... , .......................•...........................................3-9
24 Pin and MegaPAL Device Families .................................................... 3-10
Promac
20 Pin Device Families ..................................................................... 3-11
24 Pin and MegaPAL Device Families ................................................... 3-12
Stag Microsystems
20 Pin Device Families ..................................................................... 3-13
24 Pin and MegaPAL Device Families ................................................... 3-14
Storey Systems
20 Pin Device Families ..................................................................... 3-15
24 Pin and MegaPAL Device Families ....................................•.............. 3-16
Structured Design
20 Pin Device Families ............................................................•........ 3-17
24 Pin and MegaPAL Device Families ................................................... 3-18
Valley Data Sciences
20 Pin Device Families ..................................................................... 3-19
24 Pin and MegaPAL Device Families ....................•.............................. 3-20
Varix
20 Pin Device Families ..................................................................... 3-21
24 Pin and MegaPAL Device Families ................................................... 3-22
iv IIIIonoIlthit: m Memories
Tabl. of Cont...ts
:~i~:=~~~~~~~;~i~;::::::::::::::::::::.::::::::~:::.:.::::::::::::::~:::;:::;::::::::.•. E~:
4.7 ~dder ................................ :: ... : ..............................:.: .......... c.. iJ~i7
4.a Unlocked Flip·Flops - Hazards .................................................. a·11
5.0 $equentlal' LogiC " .' • .
5.1.lntroduction ......................... : .... :....................., .... , .........; .... : ..... '8·21
·~.2 Unclocked Flip-Flops...,. Latches ..........................•................... 'i;.·· 8·21
5.2.1 $-R Latch .... :.................................................................. Ij~2'1
5.2.2 D-Type Latch ........ ;; ..... ; ... : ..... : ...... ;: .... ::.: ...................... :. 8·22
.5.2.3 J.KLatch ; ............. ; ....... : ........... ;,.:: ......; .. ~ ......'\..;: ...... ~ ..' ....::.:,( .. ~8-22.
5.2.4 T·Type Latcl).. ... : ............. : .. ,,: .. , •.,~, ..., ............:: .••~ .•• :,' .... , .• : a-2~.
5.3 Clocked Flip-Rops":" Registers .: ....... ~: ..'............. ::: ...... :: ......... : ... : 8~l!3
5.3.1 Characteristic,Equations .;;'.::·i~:' .. ::..
\t.;.~.\: .. ;;;: .. " .. ,;.i.:\:>.';).;·.' 8"2$'
5.4 Designing Synchrono~s Sequential Circuits ........ ................... ......... 8.23
5.4.t State Tran.itiOllTables ........... , ................... : ..... :................ 8·24
5.4.2 State Tilbles and State Diagrams .: ............. : ....................... ;. a·24
5.4.3 Design Examples ..............................................................' 8·25
5.5 Counters .................................... ; .................... : ...........~......... a·29·
Table of Contents
PLE'" Devices 9-1
Contents for Section 9 . . .. . . . . . .. . . . . . .. . . . . .. . . . . .. . . . . . . . . . . . .. . . . . .. . . . .. . . . . .. .. . . . . . . 9-2
PlE to PROM Cross Reference Guide ................ : .................'............... 9-3
Selection Guide ..........................................................................•. ' 9-4
PLE means Programmable Logic Element .................................,...... ..... 9-5
Registered PLE ............................................................................ , 9-5
PLEASMTM ......... ...... ........... .... ..... .. ........ ..... .. ....... ............ ...... ..... 9-6
Logic Symbols .............................................................................. 9-7
Specifications .. . .. .. .. .. .. .. .. . .. .. .. .. .. .. . .. .. .. .. .. .. .. .. . . .. .. . .. .. . .. . .. .... .. .. .. .. . 9-10
PLE Family ,Block Diagrams ...................................................... ;..... 9-16
PLE Programmer Reference Chart .................................... ; .............,.. 9-20
vi Mono/ilhicURMemorles
Table of Contents
The PAL@ Device Concept The designer is confronted with another problem when a
Monolithic Memories' family of PAL devices gives designers a product is designed. Often the funGtion is well defined and
powerful tool with unique capabilities for use in new and could derive significant benefits from fabrication as an inte-
existing logic designs. The PAL device saves time and money grated circuit. However, the design cycle for a custom circuit is
by solving many of the system partitioning and interface long and the costs can be vel}' high. This makes the risk
problems brought about by increases in semiconductor device significant enough to deter most users. The technology to
technology. support maximum flexibility combined with fast turnaround on
custom logic has simply not been available. Monolithic Memo-
Rapid advances in large scale integration technology have led ries offers the programmable solution.
to larger andlarger standard logic functions; single I.C.s now
perform functions that formerly required complete circuit The PAL device family offers a fresh approach to using fuse
cards. While LSI offers many advantages, advances have programmable logic. PAL circuits are a conceptually unified
been made at the expense of device flexibility. Most LSI group of devices which combine programmable flexibility with
devices· still require large numbers of SSIIMSI devices for high speed and. an extensive selection of interface options.
interfacing with user systems. Designers are still fOrced to turn PAL devices can lower inventol}', cut design cycles and
to random logic for many applications. provide high complexity with maximum flexibility. These fea-
tures, combined with lower package count and high reliability,
truly make the PAL device a ci(cuit designer's best friend.
Monolithic LJJJ]N/emories
PAL® Device Introduction
The PAL Device - Teaching Old PROMs Figure 1 shows the basic PAL device structure for a two-input,
New Tricks one-output logic segment. The general logic equation for this
segment is:
Output = (1 1 + 1";")(T;" + 12)(1 2 + 1;)(1; + 1,;) + (11 + ~)
(T;" + ~)(12 + ~) (i"2 + fa)
where the "f" terms represent the state of the fusible links in
the PAL device AND array. An unblown link represents a logic
r 1. Thus:
fuse blown, f = 0
\ fuse intact, f = 1
An unprogrammed PAL device has all fuses intact.
OUTPUT
n~ ~
"OR" ARRAY
(PROGRAMMABLE)
jv7 7 7
OUTPUT
i'I IV IV
r'\
F<
F<
Figure 3 F<
=<
"
=<
As a simple PAL device example, consider the implementation
of the transfer function: =<
Output = 11G +1112 =<
The normal combinatorial logic diagram fOr this function is
=<
shown in Figure 4, with the PAL device logic equivalent shown
in Figure 5, =<
=<
=<
=<
Figure 4
=<
F=<
F=<
~
"AfjO" ARRAY
(FIXEO) VVVV
Figure 6
1-4 MonoIithlt:'WMemories
PAL ® Device Introduction
,Iv7'IV IV7nrv
10
, , 7~ 7' 7
"OR" ARRAY
(PROGRAMMABLE)
IV rv
"OR" ARRAY
7'
IV ~
(FIXED)
~
'""""
K F<
K F<
K F=<
F< F=<
F< F=<
F< I=<
K F<
F< I=<
I=< F=<
~ F=<
~ F=<
~ ~
F=< ::::::
F< ::::::
F<
~
::::::
L-.
"AND" ARRAY
(FIXED) 99YY "AND" ARRAY
(PROGRAMMABLE) 9YYY
Figure 7
Figure 8
Table 1,
PAL Devices For Every Task PAL device logic arrays are available in sizes from 6 x16 (6
The members of the PAL device family and their characteris, input terms, 16 output terms) to 64 X 32, with both active high
tics are summarized in the PAL device menu. They are and active low output confiljurations available (ref. PAL device
designed to cover the spectrum of logic functions at reduced menu). This wide variety of input! output formats allows the
cost and lower package count. This allows the deSigner to PAL device to replace many different sized blocks of logic with
select the PAL device that best fits his application. PAL device single packages.
units come in the following basic configurations:
MonoIlthleWMemorleS 1-5
McmolithicMemories PAL® Device Menu
DESCRIPTION MAXIMUM
DESCRIPTION MAXIMUM
Medium 20AP
PAL16P8A 16 8 -
Programmable
PAL16RP8A
20N, J, NL
16 - 8
25/30·· 180
PAL16RP6A 16 2 6
Polarity
PAL16RP4A 16 4 4
Large 20 PAL16X4 20N, J, NL, 16 4 4 225
40
Arithmetic PAL16A4 F, L 16 4 4 240
*
Large 20RA
Asynchronous
PAL16RA8 20N, J, NL
PAL12L10 10 10 -
PAL14L8 14 8 -
SmaU 24 PAL16L6 24NS, JS, W, 16 6 - 40 100
Combinatorial PAL18L4 28NL,28L 18 4 -
PAL20L2 20 2 -
PAL20Cl 20 2 -
Small 24A PAL6L16A 24NS, JS, 6 16 - 25 90
Decoder PAL8L14A 28NL 8 1.4 -
PAL20L8A 20 8 -
Medium 24A PAL20R8A 24NS, JS, W, 20 - 8
25 210
Standard PAL20R6A 28NL,28L 20 2 6
PAL20R4A 20 4 4
PAL20L8A-2 20 8 -
Medium 24A-2 PAL20R8A-2 24NS, JS, W, 20 - 8
35 105
Standard PAL20R6A-2 28NL,28L 20 2 6
PAL20R4A-2 20 4 4
PAL20L8B 20 8 -
Medium 24B PAL20R8B 24NS, JS, W, 20 - 8
15 210
Standard PAL20R6B 28NL,28L 20 2 6
PAL20R4B 20 4 4
PAL20L10 20 10 - 165
Medium 24X PAL20Xl0 24NS, JS, W, 20 - 10
50
180
Exclusive OR PAL20X8 28NL,28L 20 2 8 180
PAL20X4 20 4 4 180
PAL20L10A 20 10 - 165
Medium 24XA PAL20Xl0A 24NS, JS, W, 20 - 10
30
180
Exclusive OR PAL20X8A 28NL,28L 20 2 8 180
PAL20X4A 20 6 4 180
Large 24RS
PAL20S10 20 10 - 35/40** 240
Shared Product
PAL20RS10 24NS, JS, W, 20 - 10 35 240
PAL20RS8 28NL,28L 20 2 8 35/40** 240
Terms
PAL20RS4 20 6 4 35/40** 240
Large 24RA 24NS, JS, W,
Asynchronous
PAL20RA10
28NL,28L
20 - 10 30/35** 200
24NS, JS,
ECl PAL10H20P8
28NL
20 8 - 6 210
Icc
mA
1·8 MonoIilhlcWMemories
PAL® Device Introduction
I I II I
J
~\
~
I I iI I
Figure 9
Programmable 1/0 also fed back into the PAL device array as an input. Thus the
A feature of the high-end members of the PAL device family is PAL device cjrives the 110 pin when the three-state gate is
programmable input/output. This allows the product terms to enabled; the I/O pin is an input to the PAL device array when
directly control the outputs of the PAL device (Figure 10). One the three-state gate is disabled. This feature can be used to
product term is used to enable the three-state buffer, which in allocate available pins for I/O functions or to provide bi-
turn gates the summation term to the output pin. The output is directional output pins for operations such as shifting and
rotating serial data.
1~~iljllllliillmllllllllll!lllill3EJ
110
Figure 10
Registered Outputs with Feedback In addition to being available for transmission, the Q output is
Another feature of the high-end members of the PAL device fed back into the PAL device array as an input term. This
family is registered data outputs with registered feedback. feedback allows the PAL device to "remember" the previous
Each product term is summed into a D-type output flip-flop on state, and it can alter its function based upon that state. This
the rising edge of the system clock (Figure 11). The Q output allows the designer to configure the PAL device as a state
of the flip-flop can then be gated to the output pin by enabling sequencer which can be programmed to execute such ele-
the active low three-state buffer. mentary functions as count up, count down, skip, shift, and
branch. These functions can be executed by the registered
PAL device at rates of up to 5S.5MHz.
MonolithicW.Memories 1-9
PAL ® Device IntroCluction
~
r--+---r--t-+-
iii I i j- .
! ! iI
I rlnr-
Figure 11
XOR Outputs 12),' All of the features of the Registered PAL devices are
These PAL devices feature an exclusive-OR (XOR) function. included in the XOR PAL unit. The XOR function provides an
The sum of products is segmented· into two sums which are easy implementation of the HOLD operation used in counters
then exclusive ORed at the input of the D-type flip-flop (Figure and other state sequencers.
CLOCK Oc
I I I I I I I i I: ) I I : I I I
!~[>Ir-
I i I I , I
I I ! II I I, ,i I 1'1 j-{j D Q
b
~
Q
, '
( I, I • II I II Ii! I II ~ - H> Q
l....-
-
I I I I I T I FfH-r--t I I I I I
Figure 12
PAL Device Programming fuse" which can be blown to disable the verification logic. This
PAL devices can be programmed in most standard PROM provides a significant deterrent to potential copiers, and it can
programmers with the addition of a PAL device personality be used to protect proprietary designs.
card. For details on programming equipment, see the PAL PAL Device Part Numbers
Device Programmer Reference Guide in this handbook. The PAL device part number is unique in that the part number
PALASM (PAL Device Assembler) code also defines the part's logic operation. The PAL device
PALASM is the software used to define, simulate, build, and numbering system is shown in Figure 13. For example, a PAL
test PAL device units. PALASM accepts the PAL device 14L4CN would be a 14-input. term, 4-output term, active-low
Design Specification as an input file. It verifies the design PAL device with a commercial temperature range packaged in
a 20-pin plastic DIP.
L
against an optional function table and generates the fuse plot
which is used to program the PAL devices. PALASM is PAL 20 L 8 A ·2 C NS SHRP H01234
available upon request for many computers. PAL = Programmable ~ r-;;;;:AITERN NUMBER
HAL (Hard Array Logic) Device Family
O~T~~~A:. ~~~~~~~~~G
HAL "" Hard Array
The HAL device family is the mask programmed version of a Family
. Reliability
PAL device. The HAL device is to a PAL device just as a ROM .
...
... Enhanced
is to a PROM. A standard wafer is fabricated as far as the NUMBER OF _---,-,------' xxxx = Other
metal mask .. Then a custom metafmask is used to fabricate ARRAY INPUTS
PACK~GE
aluminum links for a HAL device instead of the programmable OUTPUT TYPE _ _ _----' N = Plastic DIP
TiW fuses used in a PAL device. H = Active High J = Ceramic DIP
L ,.. Active Low F = Flat Pack
PAL Device Technology C .,. Complementary NL "" Plastic Leaded
P = Programmable Chip Carrier
PAL circuits are manufactured using the proven TTL Schottky
R = Registered NS = prastic SKINNYDIP
bipolar TiW fuse process to make fusible-link PROMs. An NPN RA = Registered Asynchronous JS = Ceramic SKtNNYDIP
emitter follower array forms the programmable AND array. S = Shared L = Leadless
X = Exclusive OR Registered Chip Carrier
PNP inputs provide high impedance inputs (O.25mA max) to A = Arithmetic Registered P "" Pin Grid Array
the array. All outputs are standard TTL drivers with internal L -_ _ _ TEMPERATURE CODE
NUMBEA OF OUTPUTS
active pull-up transistors. C = Commercial
SPEED _ _ _ _ _ _ __
M "" Military
PAL Device Data Security A = High Speed
L-_ _ _ _ POWER
The Circuitry used for programming and logic verification can B = Very High Speed
D = Ultra High Speed - 2 = Half Power
be used at any time to determine the logic pattern stored in - 4 = Quarter Power
the PAL device array. For security, the PAL device has a "last
Figure 13
Figure 14
MonolitbicWMemories 1-11
PAL ® Device Introduction
vee
+5V
ROLL
~o-
~ [X
~
IrD -LJ
~1~
r K 22N4402
.~l;f
01
2K 20K 20K 2K
~
t:::=:rJ J ":"
~ 02
12011
rW IA 12011
~
. 1'1
2900
1.11
03 1 I~
M 12011
w-vvv-
::r:> @ i
~
J
,-L.J" ...LJ
05
1
~ ~ ~ 12011
rW I.A 120ll
~ ~-
I~
~I
29011
I.A
r
1'1
1.11 12011
~
~~
:r
W
--[d
Figure 15
MonoIlthiCW Memories
PAL ® Device Introduction
Figure 16
Advantages of Using PAL Devices interfaces required by many LSI functions. The combination of
PAL device flexibility and LSI function density makes a power-
ful team.
Design Flexibility
The PAL device offers the systems logic designer a whole
new world of options. Until now, the decision on logic system
implementation was usually between SSI/MSI logic functions
on one hand and microprocessors on the .other. In many
cases the function required is too awkward to implement the
first way and too simple to justify the second. Now the PAL
device offers the designer high functional density, high speed,
and low cost. Even better, PAL devices come in a variety of
sizes and functions, thereby further increasing the designer's
options.
Space Efficiency
The PAL device has a unique place in the world of logic
design. Not only does it offer many advantages over conven-
tional logic, it also provides I)'lany features not found anywhere
else. Among the benefits of the PAL device family:
• Programmable replacement for conventional TTL logic.
• Reduces IC inventories substantially and simplifies their
control.
• Reduces chip count by at least 4 to 1.
• Expedites and simplifies prototyping and board layout
• Saves space with 20-pin and 24-pin SKINNYDIP packages,
and surface-mount PLCC packages.
• High speed: 10ns maximum propagation delay, on D series.
• Programmed on standard PROM programmers.
• Programmable three-state outputs.
• Special feature eliminates possibility of copying by
competitors.
All of these features combine together to lower product
development costs and increase product cost effectiveness.
The bottom line is that PAL devices save money. By allowing designers to replace many simple logic functions
Direct Logic Replacement with single packages, the PAL device allows more compact
P.C. board layouts. The PAL device space-saving 20-pin and
24-pin SKINNYDIP packages help to reduce board area
further while simplifying board layout and fabrication. This
means that many multi-card systems can now be reduced to
one or two cards, and that can make the difference between a
profitable success or an expensive disaster.
Smaller Inventory
The PAL device family can be
used to replace up to 90% of
the conventional TTL family.
This considerably lowers both
shelving and inventory
cataloging requirements. In
addition, small custom
modifications to the standard
functions are easy for PAL
device users, but not so easy for ~ - - -.......,~8~~"
standard TTL users.
In both new and existing designs, the PAL device can be used
to replace various logic functions. This allows the designer to
optimize a circuit in many ways never before possible. The
PAL device is particularly effective when used to provide
The PAL device family runs faster than or equal to the best of
bipolar logic circuits. This makes the PAL device the ideal CD00970M
choice for most logical operations or control sequences which The PAL device verification logic can be completely disabled
require a medium complexity and high speed. Also, in many by blowing out a special "last link". This prevents the unau-
microcomputer systems, the PAL device can be used to thorized copying of valuable data, and makes the PAL device
handle high-speed data interfaces that are not feasible for the perfect for use in any application where data integrity must be
microprocessor alone. This can be used to significantly extend
carefully guarded.
the capabilities of the low-cost, low-speed NMOS micropro-
cessors into areas formerly requiring high-cost bipolar micro- Summary
processors. The PAL devicefarnily of logic d.eVices offers logic designers
new options in the implementation of sequential and combina-
Easy Programming
torial logic designs. The family is fast, compact, flexible, and
The members of the PAL device family can be quickly and easy to use in both new and existing designs. It promises to
easily programmed using standard PROM programmers. This
reduce costs in most areas of design and production with a
allows designers to use PAL devices with a minimum invest-
corresponding increase in product profitability.
ment in special equipment. Many types of programmable logic,
such as the PLA, require an expensive, dedicated program'
mer.
A Great Performer!
Mono/ithicWMemories· 1·15
PAL ®. Device Introduction
CIRCUIT
IDENTIFICATION
OUTPUT
BUFFERS
CURRENT SOURCE
AND PROGRAMMABLE
CIRCUITRY
REGISTERS
MISCELLANEOUS
ANOTESTING
CIRCUITRY
THREE-STATE
Table of Contents
TWX: 910-338-2376
Monolithic re'1!n
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374 Memories InJrW
2-3
PAL/HAL Dev.ces
Small 20 Series
STANDARD HALF POWER
INPUTS OUTPUTS POLARITY
tpo Icc tpD Icc
(ns) (mA) (ns) (mA)
..
PAL10H8 10 8 HIGH 35 90 65 40
PAL12H6 12 6 HIGH 35 90 65 40
PAL14H4 14 4 HIGH 35 90 65 40
PAL16H2 16 2 HIGH 35 90 65 40
PAL16C1 16 2 BOTH 40 90 65 40
PAL10L8 10 8 LOW 35 90 65 40
PAL12L6 12 6 LOW 35 90 65 40
PAL14L4 14 4 LOW 35 90 65 40
PAL16L2 16 2 LOW 35 90 65 40
Description Performance
The Small 20 Series is made up of nine combinatorial 20-pin Two performance options are available. The standard series
PAL devices. They implement simple combinatorial logic, with has a propagation delay (tpd) of 35. nanoseconds (ns), except
no feedback. Each has sixteen product terms total, divided for the 16C1 at 40ns. Standard supply current is 90 milliamps
among the outputs, with two to sixteen product terms per (mA). The half-power version consumes only 40mA, with a
output. speed of 65ns.
Polarity
Both active high and active low versions are available for each
architecture. The 16C10ffers both polarities of its single
output.
MonoIn,,/c·W Memories
Small 20 Series
.10H8, 12H6, 14H4, 16H2, 16C1, 10L8, 12L6, 14L4, 16L2
DIP Pinouts
10HS/-2 12H6/-2 14H4/-2 16H2/-2 16C1/-2
Monolil.ic WMemories
Small 20 Series
10H8, 12H6, 14H4, 16H2, 16C1, 10L8, 12L6, 14L4, 16L2
PLCC Pinouts
10H8/·2 12H6/·2
10L8/·2
16H2I·2
Operating Conditions
MILITARY COMMERCIAL
SYMBOL, PARAMETER UNIT
I , MIN TYP MAX MIN TYP MAX
,; Supply voltage 4.5 5 ,5.5 4.75 5 5.25 V
Vee
"
TA Operating' fr.~e-air 't~mperature -55 0 75 °C
Switching Characteristics
, ,
TEST MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX
Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TVP MAX MIN TVI' ~MAX
, ,
Vee Supply voltage 4.5 5 5.5 4;75 5 5.25 V
10H8
• 1 2' I ., II 1213 •• n ....
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:r
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1 '"
2
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3 ...
r
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5
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6
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'"
• 1 2':1 • & I •
." 1111 21 .. .... 21213111
2-10
Small 20 Series
12H6 Logic Diagram
12H6
1123451' I. 1213 .&n
.." 24252121 21213031
1
..
..
'----f
2
----1
...
r
.
~
111
•0
, "
"
11 -'
J ..
r
..
11
- -- 17
4 ...
'----f
16
""
5 ..
"----f
.- 15
"
3l
6
~
r
.
40
~ 14
7
...
~
co
13
co
so
" "
...
~~ . ~
12
9 ... ... 11
r
'1234511 It 1213 lin 20" 24HIUl ZUUIl31 -
14H4
1 ... 1.21 "" ,.,811 lnJ 1817 Z021U23 2425212'1 2.28.31
2
----t
.
3 ... ~
...
"'------i
....
19
4 . .A I.
"'" ~
\I .......
.
11
11
- "
./
11
5
----t.
...
~
.
"
16
"" ./
"
3Z ....... .
",. . ""'"
./
15
"
6 ...
~
.
.."
41 "
./
I'
7 ..
~
...
....
13
• .. .. .. .A 12
"'"
. ...
...
"'------i
Ot23 451' ,.1111 1213 lin ZOJl IU) MZSZl27 2U• • 31
..
....
11
2·12 MonoIithiCWMemories
Small 20 Ser•••
16H2 Logic Diagram
16H2
I . 012:1 4 S' 7 .I'ln 12131415 1IU.11I 20nuZI 2nU127 21213031
I ' ,
~
2 .. I.
----t
~ , "
3 ..
... , "
4
... ~
f1
..". :~
" .--' :-"- •
.
II,
II
11
....:::./
5 ...
----t,
~
."
..".... :H:--"
15
"
II
i ,
L--.f... .... " 14
. ....
,
7 , .
...
:
.... 13
.... "
, .,
' .
;i
• r
"
: 1
'Ii
..
, ,
"
It
'"
2-13
Small 20 Series
16C1Logic Diagram
16C1
011.1 • S 67 • 91011 111314" ti17tlll 20211223 2425Zi2J 2I2IlO31
1
.
.,.-
2 19
r
3 ....
r .,. 18
• ..... ~
17
"""
21
"",.
.. 31
16
5
.. '2 I•
""...
""
"""
6 .. ....
..
"-----I .
"'C
14
7 .. .... U
...
"-----1 .
.
..
8 ... ..
.... , 12
... ~
9 ..
r .,. 11
MonoIithiclHlJ! Memories
Small 20 Series
10L8 Logic Diagram
a1 2 3 .. i .. 1211 I,n
10L8
,." "25 21zt3l:n
1
----I
..
..
•, ~ 11
.
2
..
-
I 11
•
3 •
11
""
• •
.
-
16
"
~
..
.. 15
" -
6
.
..
" - "
..
!..-....t
... ~
13
~
..
II 12
"
!..-...,
... ,
11
• 1 2 l .. 5 I. 1213 1111
. " .... IU13.31
MOnoIlthicW.emor/e. 2-15
Small 20 Series
16L6 Logic Diagram
16L6
1 .. ~
.1 2: 1 "" 1 I' lZn tin 20" 24ZU6Z7 21213031
...
2
.... 19
....
..
. ""'-
.••
11
. ./
18
3 .....
"
17
- -- 17
.
"'----I
.
- --
2. 16
"
5 ..
=------t
....
32 15
"
6 ..... ~
.." ~ ,.
7 ....~
......
.
41
sa
51
I
"'"
./
13
8 12
~
9 11
.... ~
D 1 2: 3 4; i I 7 I. 1213 tin ..21 242SZl21 2121303'
14L4
... 0123 4S61 l'le11 1213 1611 20212223 2425.2121 2tDlG31
1
..
2 ...
... ,
1 ... .... 19
,
• .. , "
1&
17
."
II
-
"-
..
5 ..
~
24
""
,
,./
I.
"
"
33 --.. 15
"
35
- . ,./
• ...
..
41
.J
"- "
42
" - . ,./
. ... 13
1
. ,
8 .... ... 12
... . ....
...
9
. o1 2 1 "S' 7 • 9 1011 121~ 11'7 202U223 M2S2627 HZl3G31
,
11
161:.2
.1 Z I 4 ,. J '1'011 Izlh,.,· .IU1.1I' 21212223 24112121 Zl2tJ031
L-.t...
,
1
, ,
2 ..
,
19
--------t ' ,
,,,,"
3 ..
18
...
--------t
,
4·
...
... ..
,
17
. ,.~..
..
"
....
21
3D '"
""\. It>
.
5 ..
-------tp
...
..
IS 15
."
"
II
"
6
"'---f
..
...
..., 14
., ,
~.
7
... ... ... 13
,
8 ...
...
.,
12
,
,
9 .... 11
Medium 20 Series
OUTPUTS
DEDICATED INPUTS
COMBINATORIAL REGISTERED
'.
PAL16L8 10 8 (61/0) 0
PAL16R8 . 8 0 8
PAL16R6 8 21/0 6
PAL16R4 a 41/0 4
Description
The M8dium2o. Series' offers the four most popular PAL Suffix
t,o Icc
(ns) (mA)
device architectures.. It also provides the Jastest PAL devices
in the industry.
(standard) 35 180
The. MEldium' 20 . Series consists of four devices, eaCh ,with A 25 180
sixteen array inputs and eight outputs.• T,he devices have A-2 35 90
either 0, 4, 6, or 8 registered outputs, with the remaining being A-4 55 50'
cornf?inatorial. Each o( the registered outputs feeds back into 6 or Bp· 15 180
the. array, fotsequential deSigns. Thecombinatorialoiitputs B-2 25 90
also feed back into the array, except for tw:o of the outputs on 6-4 35 .55
the 16L8,.This feedback allows the output to also operate as D 10 180 .
an input if the Qutput. is disabled.
• contact MonolithIc Memonesfor·(jatasheet
Enable
The o Series offers the fastest TTL programmable logic
The combipatorial, outputs ,are enabled by a product term, The ,de'{ices in the industry, at 10nstPd.,'.
reglsteredoutp~tS areer'iabl",d' by a common enab)epln.
Cc' C
DIP Pinouts
181A/AiA~2/A-41 18R8/A/A-2lA-4I 18R4/A/A-2/A-4l
B/B~2/B-4lD( ,;; B/B-2/B-4lD B/B-2/B-4ID
""""'.
PLCC'Plnouts
10R8/AIA-21A-41 18*/AIA~IA-41
'81B-21B-41O B/B-2IB-4/D
CD00512M
Medium 20 Se'I••
i6La,' i6Ra, i6R6, i6R4
COMMERCIAL1
SYMBOL PARAMETER UNIT
, ,
MIN TYP MAX ,
Vee Supply voltage .., 4.75 S. 5.25 e" V
low 25 10
1w Width of clock ns
High ,
~,5 , 1°"
Set up time from input
tau or feedback to clock
16RB, 16R6, 16R4 35 25,' ns
..
th Hold time 0 -15 ,~ns
, , ".'"
tclK
output
Clock to output or feedback
e'
15
. '
'25
0""
'"
ns,
tpzx Pin 11 to output enable except 16LB , ,15 25 ns
tpxz Pin ,11 to output disable except 16lB R1 - 200n 15 25 ns,
tpzx Input to output enable 16R6, 16R4, 1616 Rli =S90n 25 35 ,ns
tpxz Input to output disable 16R6, 16R4, 1618 25 35 ',ns
tMAX Maximum frequency 16RB, l6R6, 16R4 16 25 MHz
1. '. ..
The PAL20 Series IS desogned to operate over the full military operating COnditions., For 8V8Ilabilily and .pec~lcaUons. contact Monol~hic Memories., '
2, These are absolute voltaQes with respect to the groUnd pin on,the device and include all overshoots due to systam and/or testar noise: Do,not allemptto test
theSe values ~hOUj suitable equipment. "
3. I/O pill,leaI\age is the worst case of I,L and 1= (ot'I'H and 1Q2H)'
4. No more then 'one output should be'shorted at a lime and duration of the short circuli should not exceed one seCOnd.
,1
Medium 20A Series
16L8A, 16R8A, 16R6A, 16R4A
Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
Sitch"
W In9 Characteristics over 0 peratl n9 CondHlons
Input or
16R6A, 16R4A,
tpD feedback to 15 30 15 25 ns
16L8A
output
tpxz
Pin. 11 to output disable except R1 = 2000 11 25 11 20 ns
16L8A R2 = 3900 '.
Input to 16R6A, 16R4A,
tpzx 10 30 10 25 ns
output enable 16L8A
Input to 16R6A, 16R4A,
tpxz 13 30 13 25 ns
output disable 16L8A"
Maximum 16R8A, 16R6A,
f MAX 20 40 28.5 40 MHz
frequency 16R4A
2-23
Medium 20A-2 Series
16L8A.2, 16R8A-2. 16R6A.2, 16R4A-2
Operating Conditions
MILITARY COMMERCIAL
SYMBOL F'ARAMETER UNIT
MIN TYP MAX MIN TYP MAX
Input or
16L8A-2, 16R6A-2,
tpD feedback to 25 50 25 35 ns
16R4A-2
output I
teLK Clock to output or feedback 15 25 15 25 ns
--
Pin 11 to output disable/enable
tpxZlZX R1 = 200n 15 25 15 25 ns
except 16L8A-2
Input to 16L8A-2, 16R6A-2,
tpzx R2 = 390n 25 45 25 35 ns
output enable 16R4A-2
Input to 16L8A-2, 16R6A-2,
tpxz 25 45 25 35 ns
output disable 16R4A-2
Maximum 16R8A-2, 16R6A-2,
'MAX 14 25 16 25 MHz
frequency 16R4A-2
1. These are absolute voltages with respect to the ground Pin on the device and Include all overshoots due to system andlor tester nOIse. Do not attempt to test
these values without suitable equipment.
2. 110 pin leakage is the worst case of IlL and IOZl (or IIH and IOZH)'
3. No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
, MIN TYP MAX MIN TYP MAX
~ . Supply voltage 4.5 5 5.5 4.75 5: ' 5.25 V
Vee
lw Width of clock
I Low 40 20 30 20
ns
I High 40 20 30 20
t"..
Set up time from input I 16R8A-4, 16R6A-4i 90 45 60 45 ns
or feedback to clock 16R4A-4 "
th Hold time 0 -15 0 -15 ns
TA Operating free-air temperature -55 125 0 75 ·C
',:
MH 10H = -lmA
VOH High-level output voltage Vee = MIN 2.4 2.8 V
, . '
Com 10H = -lmA
IOZl2 V6 = O.4V -100 p.A
Off-stale output current Vee = MAX,
IOZH2 , Vo= 2.4V 100 p.A
IOS3 , ,
Output short-circuit current' Vee = 5V Vo':" OV -30 -70 -130 rnA
Icc Supply current Vee = MAX 30 50 mA
-.1
TEST MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
""
CONDITIONS MIN TYP MAX MIN TYP MAX
Input or I".
16R6A-4, 16R4A-4, I
tpo feedback to 35 )5 35 55 ns
16L8A-4 )
output
,Maximum". 16RBA~4••16R8A;4;
~MAx frequency 16R4A-4
8 18 11 18 .MHz
1. These are absolute voHages with respect to the gro~nd:. PIn an .lI)e dey,,,,, and ,nclude all ov<!rShOOls due to system and/or tester noose. Do not attempt to test
these values without suitable equipment. . ' " . .
2. I/O pin leakage is the worst case of IlL and 10Zl (ot I'H and 10zO<>· I
3. No mote than one. output should be shorted at a time and duration. of the short circuit should not exceed one second.
2-25
Medium 20B Series
16L8B, 16R8B, 16R6B, 16R4B
Operating Conditions
COMMERCIAL 1
SYMBOL PARAMETER UNIT
MIN TYP MAX
COMMERCIAL
SYMBOL PARAMETER TEST CONDITION UNIT
MIN TYP MAX
TEST COMMERCIAL
SYMBOL PARAMETER UNIT
CONDITIONS MIN TYP MAX
Operating Conditions
COMMERCIAL 1
SYMBOL PARAMETER UNIT
MIN TYP MAX
COMMERCIAL
SYMBOL PARAMETER TEST CONDITION UNIT
MIN TYP MAX
VOL Low-level output voltage Vee = MIN IOL = 24mA 0.3 0.5 V
VOH High-level output voltage Vee = MIN IOH = -3.2mA 2.4 2.8 V
IOZL 3 Vo = O.4V -100 !1A
Off-state output current Vee = MAX
IOZH 3 Vo = 2.4V 100 /lA
105 4 Output short-circuit current Vee = 5V Vo = OV -30 -100 -250 mA
lee Supply current Vee = MAX 60 90 mA
TEST COMMERCIAL
SYMBOL PARAMETER UNIT
CONDITIONS MIN TYP MAX
MonolithicWMemOrieS 2·27
Medium 20..48erl••
16L88~4,.16Rea-4, i6R6..4, 16R4....4
Operating Conditions
COMMERCIAL1
SYMBOL PARAMETER UNIT
: MIN TYP MAX
, :: 4;75
VCc .
.
; Supply volta:!je
Width· of clock
Low ?5
····5
10
5.25 V
fw . High 25 10
ns
..
.Setup time from input or
16RB8·4 ' .
tsu: 16R68·4 35 :;!'5 ns
feedback to clock
16R48·4 "
COMMERCIAL
SYMBOL ,PARAMETER TEST CONDITION UNIT
MIN TYP : MAX
VIl 2 Low-level input voltage I, O.B V
V2
IH High-level input voltage '.2,' V
VIC Input clamp voltage Vee = MIN II = -18r\1A -1>.B -1.5 V
. '1 IL 3 Low,level input current "Icc = MAX VI" O.4V .' . -0.02 -0.25 rnA
IIH 3 High~level input ,current VI - 2.4V 25 p.A
II' Maximl,lm input current
Vee - MAX
Vcc = MAX VI'" 5.5V . 1 rnA
VOL Low·level output voltage Vee = MIN 10l = SmA 0.3 0.5 V;
.
TEST COMMERCIAL
',SYMBOL . PARAMETER UNIT
, "~./ CONDiTIONS MIN TYP MAX
Inpl,lt feedback to outp~t 16LBa~4, 16R48-4,and '
Or ;0;
ns;
tpO' 16R68·4 ",~5 35
Operating Conditions
',," COMMERCIAL 1,
SYMBOL "PARAMETER UNIT
, MIN TYP MAX
Width of clock
I Low 8 6
ns
Iw I High 8 5
Electrical Characterlsttes
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
V IL2 " Low-level input voltage ",
'.'
0.8 .V
V IH 2 High-level input voltage 2 V
VOL Low-level output voltage Vee = MIN IOL - 24mA 0.3 0.5 V
VOH High-level output voltage Vee = MIN IOH" -3.2mA 2.4 3.4 V
,
IOZL3
Off-state output current Vee = MAX
I Vo = 0.4V -100 PA
IOZH3 .'
I Vo = 2.4V 100 pA
1084 '. Output shor1~circuit current ,Vcc = 5V Vo =,OV -30 -70 -130 'rnA
TEST COMMERCIAL
SYMBOL PARAMETER UNIT
CONDITIONS MIN TYP MAX
f MAX
Maximum frequency I Feedback 55.5 70
MHz
l6R8D, l6R6D, l6R4D I No feedback 62.5 75
1. The PAL20D Serie~ is desjg~ned to ope~ate over the full military operating conditions. FQr availability and specifications, contact MonolithiC Memories.
2. These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not a~empt to test
these values without suitable equipment. '
3. 1/0 pin leakage is the worst case of I,l and 10Zl (or I'H and 10ZH).
4. No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
Monolithic m Memories
Medium 20D Serle.
16L8D, 16R8D, 16R6D, 16R4D
Metastability tion lasts until the flip-flop falls into one of its two stable
Metastability is a condition which can occur in any latch or flip- states, which can take longer than the normal response time.
flop if the minimum setup or hold times are violated. In most The PAL20D Series exhibits better metastability characteris-
cases, the flip-flop will either react to the input or remain in its tics than most other registered devices. It is less likely to enter
current state, both of which are stable results. The flip-flop the metastable state and recovers faster to a stable state. As
can also reach an "in-between" condition called the metasta- a result, the PAl20D Series can make an excellent synchro-
ble state, which is stable only if there.is no noise in the system nizer circuit, and the metastability characteristics have been
and the flip-flop is perfectly balanced. This metastable condi- specified for designs in which the setup and hold times may
not always be met.
TEST COMMERCIAL
SYMBOL PARAMETER UNIT
CONDITIONS MIN TYP MAX
MTBF = 10 years
tMET Minimum recovery time in asynchronous mode 20 30 ns
fd = (1/3)f d = 3
MTBF = 10 years
fMET Maximum frequency in asynchronous mode 21 26 MHz
fd = (1/3)f d = 3
EQUATIONS
16L8
• 1 2 J .1 • J •• 1111 12111415 1117'''' Zl21DD ,u'2In UIIIU'
~
I
••
4
11
••
I "
2' ..
"-----t
... ....' I - - -
••
~
"
"
II
II
14,
~....... 18
I.
----...
3
,
...' "
n
\I
..
\I
I.
, J 17
II
Il f0- ........, ~"
• .... II
,
' ,
, .... ::
.•• ~"""':'
I.
:
II
~
II
It
It
10 ~ "~ -:,'
i .. " , "
,
' ,
J'--'-
. ..,:...;.;.
"
.. :
33
M
."
,..:;...
"
......... ~"'''''
:'
J. tIi
...."
"
, " I. '",
" :
......•• ..~~
7
. '
41
',' ,- S
,;
"r
,
"
"'",, ....~
~
.... , ' " "
"
II
,....,...~,: ..f..:,
.' '""'c
13,
...."
12
"
:,'
. i', ,
I' I: , }i:J :~:,; '):
I i
. "
'/;,
..., , ,I" "
,
I, 'f '"
" " ' i , '•
It
"U:"
II
:
,
'";:.t"':""
'.,~,,' ,11
<:-
,/J"":'~"
"
II
II
f
,"': ..... ,.
t ... ' "
",
: "
'i i 11
... IC',
' <_.,,' , .". '. , """, ":'", ,', ',,",
'i',
Medium 20 Series
16R8Logic Diagram
16R8
,
.... 0123 4511 .9M" 1213MIS 1&171'" ~rinn ~HD27 HHU~
•
I
:D]~
2
1 ""'\.
,•
• 1
Lb- ....
••
""
~
3
.""
---t
..
"
./
.... :D]
""
~
~
18
,." "
./
21
22
21
4 ...
24
~
"'"
.
~
21
211 "
""
5 ...
....
32
33
~
~
34
",. "
"
.
31
6
" ...
....
~
.
...."
4Z
43
" ~
~
. ,/
...
~
50
"" "
"
~
54
55
........
8 ... .....
~ ....
56
, .."
51
" ~~
~~
j
"""
•
0123 .5.7 • ''In 12131415 11111111 20212223 24ZUS2J inU03' ""
16R6
1
,,
~
1
~
19
••
•, 1
1
Lb:=: ....
.r - -
••
"
11
""
~
./
;;ar--~
"
IS
... ~~
3
"'"
""
~
11
Ol
~
"" ./
"
.. ""
• p
..
"" t;J..
"" 16
'"
~
"" ~
""
5 .. ....
~
"..
l2
Q 15
"" '"
. ...
~
p
"
""
...." ....
fUl ~
..." , Q "
rvv-
~
./
"
J .. ....
...
p ~
~
so
U
51
"55"
54
""""
./
e .... ....
., ,
56
"
.
so
59
.."
II >-t1 12
9 ...
...
=---t .~
, L<\,....!!
~
01'21 4 &., 8.'011 t2131415 llUll11 20212223 ZU5l121 21213031
16R4
I
•,
J
1
·••
1
7
.....
I.
.
3--t~
...s - -
·""•
10
r-d 18
.
13
"
---.
3 .. A
to
"to
~~
18
"
21 "
./
"
21
4 .....
...
""
""
" ~
tul
28
"
3G
31
5
~
..
JIIO
...
~
"
II
""
r-;J. 15
"' rvo-
fUl
38
37
..
38
, " A
~
. ~
......
41
42
"' Q14
..
~
./ ~
1 ...
" ...,
.
..
II
51
..
12
53 r-J 13
I
.... II
...
.~
...," ~
II
II 12
12
II
t ..
""-1
• 1 2:1 '5' 7 . . . . 11 12131411 llnlll. HZlUZl ZUS2I21 llZ.lOll
....~t--- ~
ARRAY INPUTS
OUTPUTS
tpD
(n5)
. Icc
(mA)
COMBINATORIAL REGISTERED
Monolithic WMemories
Medium 20PASeries
16P8A, 16RP8A, 16RP6A, 16RP4A
DIP Pinouts
16P8A 16RPSA 16RP6A 16RP4A
PLCC. Pinouts
16PSA 18RPSA 16RP6A
16RP4A
Operating Conditions
COMMERCIAL 1
SYMBOL PARAMETER UNIT
MIN TYP MAX
COMMERCIAL
SYMBOL PARAMETER TEST CONDITION UNIT
MIN TVP MAX
TEST COMMERCIAL
SYMBOL PARAMETER UNIT
CONDITIONS MIN TYP MAX
Monolithic W Memories
Medium 20PA Series
16P8A Logic Diagram
16P8A
oI 2 3 .. 5 8 7 -allIDII 12131415 161718111 20212223 24252827 28293031
0
1....
I
2
3
4 19
s
I .,~U
7
2 ...
... ~
1....
9
10
\I
12 18
13
14'
1&
.,~U
3 ..
...
I.
1
17
18
19
!O
21
22
23
"'"~L> ......
17
4 ....
24
J_
25
28
27
28
29
30
31
""~L.) ....
16
S
~
32
J
33
34
33
36 IS
37
38
38
.J~L>
6 .. ....
40 -
j....
41
.
42
43
46
48
"'.J~U 14
47
7
. '"
48
J1>o---J
49
10
51·
st 13
53
54
8
55
.
51
1
&7
51
11\
60 12
II
112 .,~U .......
13
9
..
... 11
~
16RP8A
....
I ....
nl.l
DI2a • 5• 7 • liD 11 12131416 11S171.il 202U223 2U52U7 28213031
•
I
2
3
4 19
5
•
7 ~L>- D Q ....
is
2 .... ...
.......
I
n
8
10
Q ....
.."
12 18
13
15 ~L>-
3 .. ...
..
18
n
17
18
"" ~.... 17
20
21
22
23
----, -' ~L>-
4 ....
..
24
21
"" =tt.~
27
21
....
5--
.
28
30
31
32
/~L>-
... fa
. 34
35
~ 15
~Lr
U ....
37
31
31
6 ...
I
..
411
.. ~~
n
42
43
~ 14
45
48
47
./ ~L>- ....
1 ...
r
48
• ....-
10
SJ.
~
51
~
Ii2
53
54 2~#L.>- ......
115
81
57
81
..
&I
SJ.
J~fa
10 12
12
....
13
t .A.. II
... ....
01 23 45.7 ,.10 11 12131415 l1U1811 20212223 24252627 282931131
16RP6A
' ....
.... 01 !S 4 t. 7 1"011 11111415 11171111 '!'21ZZ,:, 2421i1lZ7 11111111
0
I '"'-'
Z --:l
3
4 II
5
• .... ~U ....
2.."
~
7
. J
I
1
10
~~
II
:=:; ./ ~U-
II I--J
13
14
15
3 ...
II
17
II
11
~-~L>- 0......
~
20
17
21
zz
23
4 ... ....
24
25
II' ~i-.
0
~
...
Z7 16
!-./~L>-
28
II
..
30
31
31
33
34 Hi-.
0 ...
. ~
3Ii
,...-, 15
~L>-
38
37
38 ....
311
6
40
41
...
42
~
~
...
~
43
45 ~~~U-
47
7 ....
..
8 ..
"
ID
51
82
SlI
54
16
r--~
r-:
pttl
- i j
...
t=JJ....
I~
13
II
~
51
II
iii
10 , 12
~~
II
I~
82
fl3
'.'
e ..
aI Z3 .. 5 • 1 • liD 11 12131415 .1171811 ZOtl2223 242&2121 28213031
....
16RP4A
I ....
01 23 4 II 1 1110 n 12131415 1117111' 111212213 14aZUl 212131131
l.-.,
--'
..,....., .......
--'I ~L>
'iB_ _~
~
11
II
13
14 " 1 ~
>----i ~ ~l..) JI'"
18
I
1&
4 ..
5 ..
6 ...
14
7 ..
12
MonoIithlcWMem",./es
Large 20 Arithmetic Series
16X4, 16A4
PAL16X4 16 4 4 64
PAL16A4 16 4 4 74
Description XORed with two variable sums generated by the PAL device
The PAL16X4 and PAL16A4 have arithmetic gated feedback. array. The flip-flop Q output is fed back to be gated with input
These are specialized devices for arithmetic applications. terms A (Figure 13). This gated feedback provides anyone of
the sixteen· possible Boolean combinations which are mapped
Arithmetic Gated Feedback in the Karnaugh map (Figure 14). Figure 15 shows how the
The arithmetic functions (add, subtract, greater than, and less PAL device array can be progr~mmed to perform these
than) are implemented by addition of gated feedback to the sixteen operations. These features provide for versatile opera-
features of the XOR PAL device. The XOR at the input of the tions on two variables and facilitate the parallel generation of
D-type flip-flop allowscarrys from previous operations to be carrys necessary for fast arithmetic operations.
)0- ~
A
;:::
B
T
-
~ l
Figure 13
MonoIltll;cUJ1Memor/e. 2-45
Large 20 Arithmetic, Series
16X4, 16A4
A--~------.---~~---.
B---+~--~r----rr---.
i':f'
r.,~~
'~~r.,-
:r., • •~ -x xx x-
~ }------A:+B
l-----AoB
-x A+B A:+:B AoB B
r-,----A:+:B
Figure 14 \-----AoB
}-----Aojj
}-----l!
)----A+l!
Figure 15
2-46 MonolithlcWMemoriss
Larg. 20. Arithmetic Series
16X4, 16A4
DIP Pinouts
16X4 16A4
PLCC Pinouts
18X4 18A4
c000560t.j
Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
MIN UP MAX MIN UP MAX
tw Width of clock
I Low 25 10 25 10
ns
I High 25 10 25 10
tsu Set up time from input or feedback to dock 55 30 45 30 ns
th Hold time .... 0 -15 0 -15 ns
..
TA Operating free-air temperature -55 0 75 °C
Te Operating case temperature 125 °C
Electrical Characteristics
SYMBOL PARAMETER TEST CONDITIONS MIN UP MAX UNIT
Vil l Low-level input voltage 0.8 V
VIH 1 High-level input voltage 2 V
VIC Input clamp voltage Vee = MIN 11 = -18mA -0.8 -1.5 V
IIl 2 Low-level input current . Vee = MAX VI = O.4V -0.02 -0.25 mA
2 High-level input current V,=2.4V 25
IIH Vee = MAX /lA
II Maximum input current Vee = MAX VI = 5.5V 1 mA
Mil 10l = 12mA
Val Low-level output voltage Vee = MIN 0.3 0.5 V
. Com IOl=24mA
Mil 10l= -2mA
VOH High-level oiJtput voltage Vee = MIN 2.4 2.8 V
Com 10l = -3.2mA
IOZl 2 Va = O.4V -100 jJ.A
IOZH2
Off-state output current Vee = MAX
Va = 2.4\1
... 100 jJ.A
IOS3 Output short-circuit current Vee = 5V Va = OV -30 -70 -130 mA
16X4 160 225
Icc Supply current Vee = MAX mA
16A4 170 240
2-48 Mono/ithlcWMemories
Large 20 Arithmetic Series
16X4 Logic Diagram
16X4
I
~I
I
3 19
•,
,
1
2 ...
.r----'
r
••
3 ...
10
11
"
13
t4
"
r-J
~;J
18
...
"11
~~
"" ;}I=>
""
4 ""
1
[ti ~
14 ~
~I=>
""
"
~
~
--'"""
,
.""
-
"
1r , ..
.'
"
~I=>
33
rb4 ~
"",. =
37
31
It
rj> Q
6
....
I
[t::!!.
~
..
~t6
41
""
..... ;::::;
Q.... ,0
-
. 'J
41
I
1
t ..
[ t::!Io;
~ ...
~b-J~
so
""53 13
. ~ ',,. I
8 ....
... "
II
~Db--J
\1
.."
II
12
9 .. ""
53
A ·1> 11
r
-
Monolithic WM8mCJries
Large 20 Arithmetic Series
16A4 Logic Diagram
16A4
1113 .," .,.111 taUMt, U11"" aHUB KHan • • • ~
2 ..
.••
.""
11
----.
3 ..
.
"
II
17
."
II
•T
."
21
I ..
II
."
II
30
II
1I
--"
.
"
.
"
.
17
II
6
I
m_ ...
.
...."
•7
,
tI
- .....
.,"
..
u
I
"--t
. .
..
•"
••
. .... II
II
II
MonolllhlcW Memories
Large 20RA Series
16RA8
DIP Pinout
16RA8
Pi:
10
11
12
13
14
15
16
17
GND
PLCC Pinout
18RA8
3 2 1 19
Operating Conditions
COMMERCIAL!
SYMBOL PARAMETER UNIT
MIN TYP MAX
Iw Width of clock 20 13 ns
~
TA Operating free-air temperature 0 75 ·C
Te Operating case temperature ·C
TEST COMMERCIAL
SYMBOL PARAMETER UNIT
CONDITIONS MIN TYP MAX
1 Polarity fuse intact 20 30
tpo Input or feedback to output ns
I Polarity fuse blown 25 35
telK Clock to output or feedback 10 17 ao ns
Is Input to asynchronous set 22 35 ns
tR Input to asynchronous reset Rt = 560Q 27 40 ns
tpzx Pin 11 to output enable R2 = 1.lKQ 10 20 ns
tpxz Pin 11 to o\ltpul disable Hi 20 ns
tpzx Input to output enable 18 30 ns
tpxz Input to output disable 15 30 ns
f MAX Maximum frequency 20 .35 MHz
1. The PAL20RA Series is designed to operate over the full military op~rating conditions. For availability ~nd speqifications, contact Monolithic Memories.
2. These are absolute voltages with respect to the ground pin on the. device and include all overshoots due to- system and/of-tester noise. Do not attempt to test
these values without suitable equipment.
3. 1/0 pin leakage is the worst case of I'L and 10Zl (or I'H and lazH)'
4. No more than one output should be shorted at a time and duration of the short Circuit should not exoeed one seoond.
16RA8
1
•,
I
3
, ~~
,•
~~
./
•,
Lb
...
...
••
10
L.......
~
11
"".. "'"
./
15
3
---t
.. ....
r
""
11
L
~
"
"
20
12
"
./ ~ .
"
!........t...
"'"
..
24
n
L"
~
",.
21
30
" .....
5 .. 31
.c:
32
"""
,."
" " ~
[Jl
31
,."
.... a .
31
6 .....
...
...
...""•• ~
~
"
./
7 ..
" ...
'---Ir
... "'"
50
~
~
51
52
"'"
.../ .....
. ."
54
...
•
so
"",
"..
....." "'"
~~
51
./
9
'--I
.. ... L<t,.....!!
... ~
01 Z I .. i 67 • lIon 12131415 111711't 20212223 24252n7 2UUUl """
Small 24 Series
TpD Icc
INPUTS OUTPUTS POLARITY
(ns) (rnA)
Description Performance
The Small 24 Series is made up of six combinatorial 24-pin
PAL devices. They implement simple combinatorial logic, with
no feedback.
The standard series has a propagation delay (tpd) of 40
nanoseconds (ns). Standard supply current is 100 milliamps
(mA).
-=--
-..:.
DIP Pinouts
12L10
20C1
PLCC Pinouts
12L10 14L8 16L6
EJI
18L4 2OL2 2OC1
INPUT ACTIVE
AND LOW
OR OUTPUT
LOGIC CELLS
ARRAY
2-57
Small 24 Series
12.L10, 14L8, 16L6, 18L4, 20L2,20C1
Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
IlL Low-level input current Vee = MAX VI = O.4V -0.02 -0.25 rnA
Rl = 560n
tpD Input or feedback to output 25 45 25 40 ns
R2 = .1.lkn
1. These are absolute values with respect to the ground pin on the device and include all overshoots due to system and!or tester noise. Do not attempt to test these
values without suitable equipment.
2. No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
012 1 .. $
•• ItU ,,,,12L10 un lI313131
1611
""
L-.b"
I I
•,
I 23
-Q-l
.... -
2 .........
to'I>-
•
• .... - 22
.L '>
"
"
.....
.... -
- 21
,.
5
"
-Q-l
- 20
~
19
"
" "'1...r
..
"
.....
-O-L
- 18
.... .....
....-
to<J
- 17
. ..n. 16
" .... -
9
..
IS
.......
....
-- 15
10
"
.....
....
- ./"
14
"
..
II 13
~
e lil1l131;
123 1811
"" "" ""
14L8
o 1 2 l 4 ~ ., ., 1611 2021
.....,... "" ""
-
1
2
~
23
~
--
..
Of
......
-t"S---J .
2•
11
4
"
" --
...... ~ 21
,.
--
~
20
""'-
"
~
- I.
6
"
II
~
--
......
..
-- - J
18
... --
-o-L.
17
- --
56 16
"
•
----t~
. ......
.." -M-j- "
" -
10 14
~ ~
" ~
13
23
22
Small 24Serie.
18L4. Logic Diagram
18L4
012 1 • s .. , a 9. '\111 1211141$ 1&11
""
~ I
I
2 """'-
. .,......
3 23
...~
4 22
=-=:J:l
21
L
"
" 20
"",.
"
~
.......
,."" 19
" :ill-
-
......
..," 18
7
" -.
R-l-
....
8
so
"
"" -
1C:
17
16
15
~~
14
~ 1C:
11 I 13
---I~
...
o , 2 3 • S .. 1 • t 1011 1213 M IS II 11
.."
20L2
0123 '511 '11111 121114ts 16171"1 20n22Zl NZS21Zl U ZllO 31 D»MJ5 Jlll3lll
I
~
I
~
23
3 ... 22
4 A 21
5 20
" }--'
""
35 19
" r--
""
..
6
.....
.
4J
r-
18
.."
.2-
" .A 17
,
8
----!. i
16
II
9 .. II I I
A 1S
!i
10
I II,II 1~
.~
" ,
13
MonoillhicWMemorles 2-63
Small 24 Serle.
20C 1 Logic Diagram
20C1
o I 1 J ,,$' 7 • t 1011 12 IS 14·15 11 11 I' ,t zo 21 II 23 24 H tI U :rt 21 31 31 3Z 13 M lS '31 11 3t 31
1 .......
~
23
3
... 22
4 .... 21
....
~ .... 20
,......,
""
"
"" ""'>-
"
""
6 ~ 19
J .l.. 18
...
~
,......,
.,
42
. 1~
... ,......,
"
7 17
----t~
8 16
----t
....
9 .... 15
10 ~ ..... 14
.
II .< 13
....
o I 1 1 ,,$ Ii 1 • t 10 n 11 13 '4 IS'S 11 .. 11 20 :1 U 2l 24 2S H 27 21 2. 10 Jl l2:n l4 H 3& 31 31 It
MonolithIc IHIFJIMemories
Small 24A Decoder Series
6L16A, 8L14A
INPUTS OUTPUTS
tpD Icc
(ns) (mA)
PAL6L16A 6 16 25 90
PAL8L14A 8 14 25 90
Description Performance
The Small 24A Decoder Series provides a wide number of These devices offer 25ns speed at only 90mA supply current.
outputs, especially useful in decoding applications. These two
parts implement simple combinatorial logic.
DIP Pinouts
8L16A 8L14A
PLCC Pinouts
8L16A 8L14A
INPUT o
AND OUTPUT OUTPUT
LOGIC CELLS 0 CELLS 0
ARRAY o
2-66
Small 24A Decoder Series
SLiSA, 8Li4A
Operating Conditions
COMMERCIAL1
SYMBOL PARAMETER UNIT
MIN TYP MAX
VOL Low-level output voltage Vee = MIN 10L = BmA 0.3 0.5 V
VOH High-level output voltage Vee = MIN 10H = -3.2mA 2.4 2.B V
IOS3 Output short-circuit current Vee = 5V Vo = OV -30 -70 -130 mA
TEST COMMERCIAL
SYMBOL PARAMETER
CONDITIONS
r-' UNIT
MIN TYP MAX
R1 = 560n.
tpD Input to output propagation delay 15 25 ns
R2 = 1..1Kn.
1. The PAL24A Decoder Series is designed to operate over the full military operating conditions. For availability and specifications, contact Monolithic Memories.
2. These are absolute voltages wfth respect to the ground pin on the device and include an overshoots due to system and/or tester noise. Do not attempt to test
these values without suitable equipment.
3. No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
6L16A
23 61 89 10 II 1213
II
•
•
It
• ..
21
•
II
!...
"
1... ...
II
• .
17
•
"
"
II
14
II
..
• I ., .,
8L14A
• I
•• .. " M"
I
,,'
,.
•
I .
r ",,'
"
•
.
• "
,e ,"". '
,,' : ';
..
,
1·:",' I:·
I "':::., .:cc
, ',,/:, "
,',"" ",'
II
,
,:,'
' .. : "
' " ,,:, ,',
I,
r
I,
",,> .
I
..
,
• -::
,
-"-
"
• ..
.
,
It
II
,
.
,"
I
"
' ..
, ,
I
It
"
"
",
",
'c. "
II
"
Medium 24 Serle.
20L8,20R8,20R6,20R4
Medium 24 Series
OUTPUTS
DEDICATED INPUTS
COMBINATORIAL REGISTERED
PAL20L8 12 8 (6 I/O) 0
PAL20R8 10 0 8
PAL20R6 10 21/0 6
PAL20R4 10 41/0 4
Description
The Medium 24 Series consists of four devices, each with Suffix tpD Icc
(n8) (mA)
twenty array inputs and eight outputs. The devices have either
0, 4, 6, or 8 registered· outputs, with the remaining being
A 25 210
combinatorial. Each of the registered outputs feeds back into
A-2 35 105
the array, for sequential designs. The combinatorial outputs
B 15 210
also feed back into the array, except for two of the outputs on
B-2 • 25 105
the 20L8. This feedback allows the output to also operate as
an input if the output is disabled. • contact Monolithic Memories for datasheet
Enable Preload and Power-up Reset
The combinatorial outputs are enabled by a product term. The The B-2 Series offers register preload for device testability.
registered outputs are enabled by a common enable pin. The registers can be pre loaded from the outputs by using
Polarity supervoltages (see waveforms at end of section) in order to
simplify functional testing. The B-2 Series also offers Power-
All outputs are active low.
up Reset, whereby the registers power up to a logic LOW,
Performance setting the active-low outputs to a logic HIGH.
Several speed/power versions are available:
CMOS ZPALTM 24 Series The devices have HC and HCT compatible inputs and outputs
for use in CMOS and TTL systems. This feature. allows the
Features/Benefits
ZPAL circuits' to be used for direct replacement of discrete
• CMOS technology provides zero standby· power· .' CMOS as well as TTL logic.
• Lowest poWer 2~-pin PAL® device: family; consul11esonly
3mA/MHz Areas of' Application
• 35ns maximum propagation delay • Portable computerS
• BattetY~op~rated instrumentation
• PrqgrammabJe replacement for CMOS/TTL logic
• Reduces chip count by greater than six to one • LOW-POWer industrial !;Iquipment
• .Stand8rd CMOS/TTLIogic replacement
• Instant prototyping and easier board layout .
• HC/HCT compatible for use. in CMOS or'TTL systems Featl,lre~~'
• Offered over:;.both the Commercial and Inc:histrial ThetMOS ;ZPAL24 Series includes the four standard 24-pin
temperature ranges PAL deilice architectUre$. All four d8v1ces have twenty array
• Low-cost; one-time programmable SKINNYDIP® and PLCC inputs and $ight outputs, with varying numbers of registers:
packages save board. space • !
zero' '(20L8). :four (2084), six (20RI); alid eight (20R8). The
combinatorial outputSOfl' the registered devices, and six of the
D~$~riptlon " , t;' outpUts ori th.e 20L8,are I/O pins that can beinpividually
The CMOS 'ZPAL24' Series offers the first family of PAL progr'am"l1edas inputs.or outputs. Each output register, a D-
devices with tr\le CMOS' power consumption. Uhder standby type flip-flop, also feeds back intot,l:ie array, tor implementa-
con.dltlons (inputs and clock not changing), the devises, con- tion of; Synchronous state machine·designs. Registered out-
sume a maximumcurrent of 100MA, less than 1%th~t of the puts are enabled byari external input,while the. combinatorial
quarter-power' PAL devices. This low power consumption outputs use a product term to control the enable function.
allows the devices to be powered by a battery almost indefi- The. basic PAL device architecture is a programmable AND
nitely. array feeding a fixed OR array. The programmable AND array
While operating; the devices consume additional power only COnsists of a set of cells similar to, those· used in EPROMs.
when the :i!lputs~ •. or clock··QIlang,e. Power consumRtiofl:is Erasable by UV light, the FSlls. can be programmed and
directly proPorti~al to the freq~elicy: of change!! .to theilnputs: erased;in the factory to en'sure :1.00%, programming and
IcC is therefore specified as 3mA 'p~r 1M~ ofop9rliting !\lnctional yieiO~. . ,.' . , .'
frequency; starting from 5mA at 1114Hz. Th\l~the' maximum Windowed p!i,ckages:will be made available in the future,
currimtat
~..,' .,
8114Hz would be 5mA +.7x3mA, ;
O(26mA
,
.. allowing erasl;lre,jn till! fiell!, Windowed packages allow easy
pro!olYpe testii!g. and t:econfiguration.
2·71
Medium 24 Series
20L8, 20R8, 20R6, 20R4
DIP Pinouts
20LBAIA-2/B 20RSAIA-2/B 2OR6AIA-2/B 2OR4A1A-2/B
PlCC Pinouts
2OLSAlA-2/B 2OR8A1A-2/B 2OR6AlA-2/B
2OR4A1A-2/B
INPUT REG
AND
OR OUTPUT REG
CELLS
LOGIC
ARRAY REG
2-72 MonoilthlcWMemorles
Medium 24A Series
20L8A,20R8A,20R6A,20R4A
Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
MonolithlcWMemories 2-73
Medium 24A Series
20L8A, 20R8A, 20R6A, 20R4A
Input or
20R6A 20R4A
tpo feedback to 15 30 15 25 ns
20L8A
output
Monolithic W Memories
Medium 24A·2 Series
20L8A-2, 20R8A·2, 20R6A.2, 20R4A·2
Operating Conditions
COMMERCIAL I
SYMBOL PARAMETER UNIT
MIN TYP MAX
tsu Setup time from input or feedback to clock 20RSA-2, 20R6A-2, 20R4A-2 35 25 ns
th Hold time 0 -15 ns
TA Operating free-air temperature 0 25 75 °C
10Zl
3
OIl-state output current Vee = MAX I Vo.= O.4V -100 p.A
IOZH 3
I Vo = 2.4V 100 p.A
105 4 Output short-circuit current Vee = 5V Va =OV -30 -70 -130 mA
lee Supply current Vee = MAX 80 105 mA
Operating Conditions
COMMERCIAL 1
SYMBOL PARAMETER UNIT
MIN TYP MAX
COMMERCIAL
SYMBOL PARAMETER TEST CONDITION UNIT
MIN TYP MAX
VIl 2 Low-level. input voltage O.B V
VIH 2 High-level input voltage 2 V
Vie Input clamp voltage Vee = MIN 'I = -1BmA -O.B -1.5 V
IlL 3 Low-level input current Vcc= MAX VI = O.4V -0.02 -0.25 mA
VOL Low-level outPllt voltage Vee = MIN IOl = 24mA 0.3 0.5 V
VOH High-level output voltage Vee = MIN IOH= -3.2mA 2.4 2.8 V
IOZL 3 Vo = 0.4V -100 !lA
Off-state output current Vee = MAX
IOZH 3 Vo= 2.4V 100 !lA
IOS4 Output short-circuit current Vee = 5V Vo = OV -30 -70 -130 mA
TEST COMMERCIAL
SYMBOL PARAMETER UNIT
CONDITIONS MIN TYP MAX
f MAX
Maximum frequency
....
I Feedback 37 40
MHz
20RBB, 20R6B, 20R4B I No feedback 45 50
1. The PAL24B-Senes IS deSigned to operate' over the full
..
mlhtary operating
..
conditions. For availability-and
..
specifications, contact' Monohthlc Memories-,
2. These ars absolute voltages with respect to the ground pin on the device and include alt overshoots due to system and/or' tester noise. Do not attempt to test
these values without -suitable equipment.
3. 110 pin leakage is the worst case of 'iland 10Zl (or IIH and 10ZH).
4. No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
2-76 MonolithicWMemories
Medium 24 Series
20L8 Logic Diagram
20L8
,
., • • 45.7 • 11011 11131415 II n III• .2122D 2411.". Zla»:n 3281135 all • •
I
z~
~
~ r - - - ' II
~
•
~
""
..
IS
"
./
tL
•
...> IS
...
.... ~
""
"
"
.."". "
./
J. Z1
•
.> n
-~
...
...
"N
"" ..L ..
""
". "' ./
... "
..
.
.. rl
"
."
53 ./ " V
17
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rl
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<
.... "
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.
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• t r I
Medium 24 Series
20R6 Logic Diagram
20R6
o I I I .. , • 7
""U 12111415 IInll .. .112221' 2UI.n ..... llaMa _If ••
...
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~
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.........
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...
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f- r-... r--
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.. 31
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.-_ 1-1 S " I • J 12131411 11111111 zanru3 24212127 sa30SI luaaUI .31 • •
"""",..
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< II
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. ~
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17
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11
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n
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t!1J
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r .....
• I t I 41'7 • • • ,. dgMa II» • • Dlta • • • • 11' .............
L(J- II
Description Polarity
The,fAL24X Series offers Exclusive-OR (XOR) gates preced- All outputs are active low.
ing eacfiregister. The XOR gate has as'its inputs two sums,
Prel9ad. 811d Power-up Re$et
eachoi two product terms. The XOR. gate is very efficient. for .
couriting applicEitions." . The 24XASeries offers register pr918~d for device testability.
Theregi~ers can I:!epreloaded ftom the outputs by using
Enable . supe~oltag9$ (see waveforms at end of section) in order to
The cOmbinatorial outpUts are enabled bY a "product term. The simplify functional testing. The 24XA.§eries also offers Power-
registered outputs .are enabled by a common enable pin. up Reset, whereby the registers pPwef up to a logic LOW,
setting the "8cDve-low outputs to a h;)gI6 HIGH: .
2-81
M.d....m 24X .......
20L 10,/ .20X 10,' 20X8.· 20X4
DIP Pinouts
2OL101A 2OX10/A 20XBlA 2OX4/A
PLCC Pinouts
2OL101A 2OX101A 20XBlA
2OX4IA
ilEG
O~REG
REG
2-82
Medium 24X Series
20L10, 20X10,20Xa, 20X4
Operating Conditions
MILITARY COMMERCIAL
SY.MBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
lee. Supply current Vee -MAX; 20X10 20X8 ." 20X4 120 180 mA
Operating Conditions
COMMERCIAL 1
SYMBOL PARAMETER UNIT
MIN TYP MAX
VOL Low-level output voltage Vee = MIN IOl = 24mA 0.3 0.5 V
VOH High-level output voltage Vee = MIN 10H = -3.2mA 2.4 2.S V
IOZl 3 Vo = 0.4V -100 p.A
Off-state output current Vee = MAX
IOZH 3 Vo = 2.4V 100 p.A
COMMERCIAL
SYMBOL PARAMETER TEST CONDITIONS UNIT
MIN TVP MAX
20L10
0121 • S, 1 . , 1011 U 131415 " 11 'I't 2611 n 23 M 2~ 26 21 :II 2t JO 11 1211:MlS JIi lI3811
··,
,
,.....
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,
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1 ....
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20X4
1 ....
.,
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t
0 t 23
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• 1 Z 1 4;"" • 11011 12131415 .tin .. " za:nnn MKMn Ila3l1t nUll" 31U1IlI
MonoIlth/C·WMemories 2·89
Large 24RS .58rle.
20S10; 20RS10,. 20RS8, 20RS4
ARRAY INPUTS
COMBINATORIAL
OUTPUTS
REGISTERED
tpo
(ns)
.
STANDARD
Icc
(rnA)
Description pair has a total of sixteen product terms; thus, one output can
The Large 24RS Series offers product term sharing, which use zero to sixteen terms while the other has sixteen to zero.
allows up to sixteen product terms to be used at a single Product terms can only be shared mutually exclusively, If both
output. outputs need the same term, it must be created twice, once
for each output.
Enable
The combinatorial outputs are enabled by a product term. The
Preload and Power-up Reset
registered outputs are enabled by a common enable pin. ·The 24RS Series offers register preload for device testability.
The registers can be preloaded from the outputs by using
Programmable Polarity supervoltages (see waveforms at end of section) in order to
Each flip-flop has individually programmable polarity. The simplify functional testing. The 24RS Series also offers Power-
unprogrammed state is active low. up Reset, whereby the registers power up to a logic LOW,
Product Term Sharing setting the active-low outputs to a logic HIGH.
Product term sharing allows each pair of outputs to share its
product. terms with one output or the. other (not both). Each
DIP Pinouts
2OS10 2ORS10 20RSS 2ORS4
PLCC Pinouts
2ORS4
INPUT REG
AND OUTPUT
OR CELLS REG
LOGIC
REG
ARRAY
Mono/itblcWMemortes 2-91
Large 24RS Serle.
20S10, 20RS10, 20RS8, 20RS4
Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
Low 20 10 15 10
lw Width of clock ns
High 20 10 15 10
20RS10
Setup time from input or .
tsu 20RS8 40 25 35 25 ns
feedback to clock
20RS4
Monolithic WMamoria.·
Large 24RS Series
20S 1 0 Logic Diagram
20S10
'..J'o.
.....
0
·,, r-H:>--
r- '~J...) .l
III
·••
....
...
~
I" A
..•• ~ :-
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012 J 4 Ii I J • t ton tz1314U 1117181' 20unn Z4UH27 2U.30JI U3UU5 31313131
2-94 MonolithicWMemories
Large 24RS Series
20RS10 Logic Diagram
20RS10
• too.,
y • 1 2I • t tOil
JI"111111111:!~=>t'~n"=i~fD~:
4' I 7 lUI .... 111 1 1 .,UZD 2411 f1 ••••
11 It
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Large 24RS Serie.
20RS8Logic Diagram
20RS8
....
'Jo..
• • II • 1.7 ...... ..,," "
, .tuz. ... II •• ,ull
"
•,
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ft
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Large 24RS Series
20RS4 Logic Diagram
20RS4
' .....
... 01 :z3 • nQWl5 dlldl' mhUD umav a •
,, • 5'7 '~Il 31 annUl 3i17 •
,, )n~J .
·•• ~- ....
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51
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11
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·L~~'"
J' ,. ---<)2
Ie
DIP Pinout
2ORA10
PLCCPinout
2ORA10
Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
,MIN TYP MAX MIN TYP MAX
tw Width of clock
I Low 25 13 20 13
ns
I High 25 13 20 13
Hold time
I Polarity fuse intact 10 -2 10 -2
ns
th
I Polarity fuse blown 0 -6 0 -6
t hp Preload hold time 30 5 25 5 ns
Vie Input clamp voltage Vee = MIN II'" -lSmA -O.S -1.5 V
IlL 2 Low-level input current Vee= MAx VI = O.4V -0.02 -0.25 rnA
IIH2 High-level input current Vee = MAX VI = 2.4V 25 !lA
II Maximum input current Vee = MAX VI = 5.5V 1 rnA
VOL Low-level output voltage Vee = MIN 10L" SmA 0.3 0.5 V
VOH High-level output voltage Vee"': MIN 10H: MiI-2mA Com-3.2mA 2.4 2.S V
IOZ2 Off-state output current Vee = MAX Vo = 2.4 VIVo = 0.4V -100 100 !lA
IOS3 Output short-circuit current Vee = 5V Vo= OV -30 -70 -130 rnA
Monolithic W ••mor/es
Large 24RA
20RA10
Polarity fuse
Input or 20 35 20 30
intact
tpD feedback to ns
output Polarity fuse
25 40 25 35
blown
20RA10
I ...
....
0
~JF-~
I
II -r.;t:1
1_ 23
2..,
I
~~
.... -
•
:J;f"- ~
II 1.
r:r;;1
~
22
3
15
~
~.
1&
21
II -W
4'
23
.. :JF- U: ~ r3B
.. ~
~ IF-- ~ ~
II r;;t:'I ~ . 20
5 " ~
32
II
:JF- U: ~
~
1_ 19
RP
~
39
6
1
40
I
18
W
II
J'F- U: ::i~P~
~
41
7, ~
1.
48
17
II ~
65 ~F-U: ~~
8
~
156
I;f"
II 1_
tr;;l 16
U: ~ ~
111
9
It
II W
[1 15
r-r-~ ~~Pl-
~
II
10 ~
19 ~;f"
II
I
r;;rJ
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1. 14
\I ......
o •• 7 a 1112 us II!! 1928 23241128 3132 353& 39
""" A 13
'"'"
Monolithic W MSlDorles
High Speed Programmable Array Logic
PAL32VX10,PAL32VX10A
MonoIithlcWMemories
High Speed Ptdgrammable Arrav Logic
PAt3!2;VXtG;'PAL32VX10A
LDO.....
High Speed Programmable Array Logic
PAL32VX10, PAL32VX10A
11 15
110 1/09
(13) (18)
13
111 14 Figure 1. PAL32VX10 Macrocell
(16) 1/010
(17)
MonoIlthlcWMemor/ea
High Speed Programmable Array Logic
PAL32VX10, PAL32VX10A
Dropping the ( + ) for simplicity, the equivalent Boolean Table 1. J-K Flip-Flop Transfer Functions
expression for a + is:
a: = R*a + J*O
In general, J and K can be sum-of-product expressions which S-R Flip-Flop. The S-A flip-flop has a truth table identical to
are provided in the PAL architecture only in active-high form. that of the J-K flip-flop, with the exception that the J = K = 1
Thus, a direct implementation of K expressions must invoke a (toggle) condition is not allowed. The S-A flip-flop implementa-
DeMorgan transformation, which can use excessive product tion is identical to that of the J-K flip-flop, with J-K replaced by
terms. This can be avoided by rewriting the equation for a S-R, and the S = A = 1 condition avoided.
without inversions on the J or K inputs. T Flip-Flop. A T (toggle) flip,flop either holds its state or
The XOA gate can be used to construct a logically equivalent toggles, depending on the logic state of the T input. The T flip-
expression without any inversions on the J or K inputs. The flop is a subset of the J-K flip-flop and can be considered
rewritten Boolean expression is: equivalent to a J-K type with J = K. The general transfer
~ function and its active-low T equivalent are both given in Table
a: = a: + :(J*O + K*a)
2.
To check that these expressions are logically equivalent,
change the XOR to its equivalent sum of products form
(remember A: +: B = A*S + A*B) and reduce (using DeMor- a: = a: +:T
gan's theorem): a: = a: + :T
a: = a*(J*o + K*a) +9*(J:9 + ~*a)
a: = a*«J + a)*(K + a» +a*J*a + a*K*O Note: T -= sum of products T1 + T2 + T3 + ... + Tn
a: = a*(J*K + J*o + a*K + 0*0) + J*O Table 2. T Flip-Flop Transfer Functions
a: = J*R*a + K*a + J*O
which simplifies to a: = K*a + J*O.
Summary to the XOR gate controlling the invert/not invert function. With
The.pAL32VX10 can synthesize J-K, S-R, T, and 0 flip-flops, all fuses intact, there is no inversion through the XOR gate,
whichever is most convenient for the application, without creating an active low output. Opening all fuses forces the
sacrificing product terms. Additionally, the synthesized equa- product term high, inverting data and creating an active high
tions can use the active-high or active-low forms of the inputs, output.
allowing the designer to minimize product term requirements. Registered Outputs. Output polarity for registered outputs
can be determined in two ways. For Ootype registered outputs,
Flip-Flop Bypass polarity can be set by the XOR gate, as is the case with
Any output in the PAL32VX10 can be configured to be combinatorial outputs. USing this method to set polarity, preset
combinatorial by bypassing the output flip-flop. This is done by and reset will not be affected.
setting the output multiplexer to the appropriate state. The
Polarity, as observed from the output pin, can also be deter-
multiplexer is controlled by a product term which can be set
mined by the flip-flop output multiplexer. Note that this does
unconditionally for a permanent combinatorial (all. fuses
not affect the polarity of the register feedback signal, but does
opened, product term high) or registered (all fuses intact,
affect preset and reset. By changing the flip-flop output
product term low) output configuration, or can be programmed
multiplexer, the preset and reset functions are exchanged,
to bypass the output flip-flop "on the fly, "allowing signals to
relative to the controlling product terms.
be routed directly to output pins under user-specified condi-
tions. With the multiplexer fuse intact, the Q output is routed to the
output pin, configuring an active low output. With the multi-
Varied Product Term Distribution plexer fuse opened, Q is routed to the output pin, and
An increased number of product terms has been provided in synchronous reset becomes synchronous preset. Similarly,
the PAL32VX10 over previous generation PAL devices. These asynchronous reset becomes asynchronous preset.
terms are distributed among the ten macrocells in a varied Polarity options for J-K, S-R, and T flip'flops have been
manner,rangingfrom eight to sixteen terms per output. The discussed in the section on programmable flip-flops.
five output pairs have 8, 10, 12, 14, or 16 product terms
available for the OR gate within each macrocell.ln addition, Power-Up Preset
each macrocell has one XOR product term and two architec- All flip-flops power up to a logic high for predictable system
ture control productterms. initialization. Outputs of the PAL32VX10 witlbe high or low
depending on the state of the register output multiplexers.
Programmable 110
Each macrocell has a three-state output buffer with program- Register Preload
mabie three-state control. Control is implemented by a single The register on the. PAL32VX1 0 can be preloaded to facilitate
product term, allowing specification of enable/disable func- functional testing of complex state machine designs. This
tions controlled by any device input or output. Each macrocell feature allows direct loading of arbitrary states, thereby mak-
can be configured as a dedicated input by disabling the· buffer ing it unnecessary to cycle through long test vector sequences
drive capability, When this is done, the associated register can to reach a· Qesired. state. In· addition, transitions from illegal
still be used as ali input register or buried state register, due states can be verified by loading in illegal states andobserv-
to the independent register feedback path. iligproper recovery,
Programmable Preset and Reset Security· Fuse
The ten macrocell flip-flops share common programmable After programming and verification, a PAL32VX10 design can
preset and reset controLlor easy system initialization. The Q be secured by programming . the security fuSes. Once pro-
outputs of the register will go to the logic low state following a grammed, these fuses defeat readback of the internal fuse
low-to-high transition on pin .1 (IO/CLK) when the synchronous pattern by a device programmer, making proprietary designs
reset (SR) product term is asserteQ, The register will.be forced very difficult to copy.
to the logiC high state independent of the clock. when the Quality and Testability
asynchronous preset (AP) product term is asserted.
The PAL32VX10 offers a very high level' of bui.lt-in quality.
Programmable Polarity . SpeCial on-Chip test circuitry provides a means of verifYing
The polarity of each macroceli output can be set active high or performance of all AC and DC parameters prior to program-
active low. ming. In addition, these built-in. test paths verify complete
Combinatorial Outputs. The XOR gate provides polarity functionality of each device to provide the highest post-
control for combinatorial outputs, with the single product term programming functional yields iii the industry;
MonoiithleWMemor/es 2-107
High. Speed Programmable Array Logic
PAL32VX10,PAL32VX10A
Operating Conditions
COMMERCIAL 1
IlL 3 Low-level input current Vee';;; MAX VI = 0.4V -0.02 "':0.25 rnA
IOll 3
OIl-state. output current Vee = MAX
I Vo = O.4V -:-100 pA
IOZH3 ..
I Vo = 2.4V 100 /JA
IOS4 Output short-circuit current Vee = 5V Vo = OV -30 -70 -130 mA
2-108 MonoIlthlcWMemorles
High Speed Programmable Array Logic
PAL32VX10, PAL32VX10A
Input or feedback to
I Product terms Pt-Pn 15 30 15 25
tpD output I Product term XOR 25 35 20 30
ns
8 KUIiOU
Rt
OUTPUT .......--+-,-'-'[email protected]
NOles: L !po Js 1 _ with sWitch.8, cIOBed.GL =5QPF 'and measur9d at 1.5V 9utpJJI·~vel., , . ",'
2. !Pzx is measured at the 1.5V output level with Ci, =50pF. 8, ~'Open fo'high impedance 1ll"!.Htesr~nd glOBed for high impedance to "O"test
3 \pxz iBtested with c.. - 5pE 8,iS open for "t",,! hj~h impedance.!est. measur"l!",,! VOff-O.~Y:P~,~ lEiv~liS, is closed lor ."0" to high impedance test
. measured at VOL +0.5'1 output I~. ' . . • : ' Y '.....' , " " ,',,' ": . '
2~10!r
High Speed Programmable Array Logic
PAL32VX10,PAL32VX10A
Switching Waveforms
INPUTS, 1/0, ~---3V
REGISTERED
FEEDBACK,
SYNCHRONOUS '-----0 V
RESET
-'s,
ClK
ASYNCHRONOUS
PRESET
REGISTERED
OUTPUTS _ _ _LIIlIIIiIIlII'
COMBINATORIAL
OUTPUTS ~ ________________ww
DON'TCARE: CHANGING;
CHANGE PERMITTED STATE UNKNOWN
f MAX Parameters is employed (Figure 1). Under these conditions, the frequency
The parameter fMAX is the maximum speed at which the PAL of operation is limited by' the greater of the data setup time
device is guaranteed to operate. Because flexibility inherent to (tsu) or the minimum clock period (tw high + tw low, or tP2).
PAL devices allows a choice ,of clocked flip·flop designs, for This, parameter is designated fMAX (no feedback).
the convenience of the user, fMAX is specified to address two For synchronous sequential designs, i.e., state machines,
major classes of synchronous designs. ' where logical feedback is required, inputs to flip·flop data
The simplest type of synchronous design can be described as terminals originate from the device input pins or flip· flop
'a data path application. In this case, data is presented to the outputs via the internal feedback paths (Figure 2). Under
data terminal of the flip·flop and clocked through; no feedback these conditions,fMAX is defined as the reciprocal of (tsu +
telK), or tP1, and is designated fMAX (feedback).
~
.......
~
- I ~
.
Figure 1. Data Path Register Configuration Without Feedback; Q:
~
=i
"
~
"'" .....
il
...
~
I
.. .l.Dol0B0M
Figure 2. State Machine Configuration With Fe8dback, Q: =I + Q
" "T
input XOR gate,: whose inputs are the OR of the product terms
P1-Pn and the single additional XOR prqduct t~!rn (Figure 3).
!=~! 'Pn : ' '. '" ',' ~'",' D Q "
SPECIFICATION EXPLANATION
tpD , Isu' f MAX (feedblickj"jproduct'termsP1.Pn 'If only the P1-Pn product terms are changing (XOR term is ~otchangingr
'... " I Product term XOR If XOR term is changing ,;
,
Figure 4.
High Speed Programmable Array Logic
PAL32VX10,PAL32VX10A
Features/Benefits Description
• llser-programmable synchronous s~te machine The PMS14R21 programmable sequencer is the first member
• 25MI;tz maximum frequency for compatibility with 12.5MHz of the PROSE (PROgrammable SEquencer) family. The
processors PMS14R21 is a high-speed, 14-input, 8-output state machine.
It consists of a 128x21 PROM array preceded by a 14H2 PAL
• 14 inputs (8 external), 8 outputs, 128 states
array. The PAL array is efficient for a large number of input
• PAL@ array optimizes product "terms and states conditions, while the PROM array is 'optimal for a large
• Internal feedback adds versatility and Control number of product terms and states. The combination allows
• Optimized for four-way branching " a very efficient state machine with a large number of inputs
• User-selectable asynchronous preset or asynchronous and state bits. The PAL array, with eight product terms per
enable function output, operates' on the eight conditional and six state inputs
• Power-up preset for start-up in known state to select two control bits to the PROM. Two Exclusive-OR
gates between the two arrays help to minimize product terms
• Diagnostics-On-Chip™ shadqw register eases chip and
and redundant states. Five lines feed back from the PROM to
board-level testing
form the primary address fOr the next state. The PROM stores
• PfloSETM: deviJ:$software makes it easy to "write your up to 128 statas of eight outputs andthirteen feedback control
sequenc;:er in PRO$E" . signals.' ",
• Programmed on standard logic programmers
Applications
• Security fuse prevents pattern "duplication'
• High speed sequential logic
• Space-saving 24-pin 300-mH SKINNYDIP@and28-pin
PLCC and LCC packages • Peripheral controller
• Cache control sequencer
• Signal procesSing "sequencer
• Industrial control
Block Diagram
DCLK SOl CLK
10
"
12
13
14
15
•
17
2~113
PMS14R21/A
L
PMS 14 R21 A C NS STD PROSE device software from Monolithic Memories provides
PREFIX~ PROCESSING
full support for the PMSI4R21. Based on PALASM@2 syntax,
the software automatically converts a state machine descrip-
PMS = Programmable SrD = Standard
Memory~based XXXX ... Other tion directly into the PAL and PROM array fuse maps, for
Sequencer downloading to a programmer. The syntax supports both
PACKAGE
NUMBER OF NS = Plastic SKINNYDIP Mealy and Moore state machine models, and makes optimal
ARRAY INPUTS JS = Ceramic SKINNYDIP use of the features of the PROSE .device. Simulation support
NL ... Plastic Leaded
is also provided, both for design checking and for generation
OUTPUT TYPE _~_-' Chip Carrier
A .. Regj$tere~ L = Leadless Chjp Carrier of test vectors for device testing. Additional support is avail-
able from third-party software vendors, including the ABEL™
NUMBER OF REGISTERS ' - -_ _ _ OPERATING CONDITIONS
C = O°C to 75°C
package from Data I/O.
PERFORMANCE _ _ _ _---'
Blank = standard
M = _55°C to 125°C
Programming
A "" enhanced Both the PAL and PROM arrays are programmed on standard
logic programmers using the JEDEC programming format. The
Diagnostics-On-Chip Feature
TiW fuses program from the low to the high state. Program-
The PMS14R21 is the newest member of the Diagnostics-On-
ming also sets the architectural fuse which selects between
Chip family. These devices incorporate a serial shadow regis-
asynchronous preset or asynchronous output enable; the
ter on-chip which facilitates board-level testing. The shadow
unprogrammed state is preset. If asynchronous preset is
register has a Serial Data Input (SDI), Serial Data Output
selected, asserting the pin low will set all outputs and feed-
(SDO) and its own clock (DCLK). The MODE control config-
back bits high.
ures the shadow register either in parallel with the output
register or in serial shift mode (see function table). Other Power-up Preset
devices with this feature are listed below. Power-up preset is provided for system start-up in a known
state. It has the same effect as preset; all output register bits
Diagnostics Family Members go high.
PART
DESCRIPTION
NUMBER
L
SOl
X
ClK
t .
OClK Q20 - Qo
an +- PROM
S20 - So
HOLD
SOO
L X · t HOLD
Sn +- Sn_l
So +- SDI S20 Shift shadow register data
H X t . an +- Sn
So +- SDI
HOLD SDI
while shifting shadow register data
Load output register from shadow register
H L
· t HOLD Sn +- an SDI
Load shadow register from output bus
and feedback
H H ·
* Clock must be steady or falling.
t HOLD HOLD SDI t No operation
Features/Benefits Features
• 20 logic inputs: 12 external, 8 feedback Each output has a programmable polarity fuse, allowing for
• 8 outputs with programmable polarity more efficient representation of many logic functions. Each
output is active high with polarity fuse intact, and active low
• ECl technology for ultra-high speed - max tpo = 6ns
with the polarity fuse blown.
• 32 product terms with term sharing
The programmable AND array contains a total of thirty-two
• 10KH ECl compatible product terms. Product terms are arranged in groups of eight.
• Fully AC tested The terms in each group can be shared mutually exclusively
• Input pull-down resistors between two adjacent output cells. If a particular product term
• Voltage compensated is needed for two outputs, then two identical product terms
• Space-saving 24-pin SKINNYDIP® and 28-pin PlCC are generated: one for each output.
packages A security fuse is provided to help protect the fuse pattern
• Programmable using standard TTL programmers with from unauthorized copying. Once the security fuse has been
adapter programmed, it is no longer possible to verify the contents of
the fuse array electrically. The security fuse has no effect on ~
• Greater than 99% programming yield
functionality. ~
• Security fuse prevents unauthorized copying
Description
The PAl10H20P8 is a 10KH family compatible ECl PAL
device having twelve dedicated inputs and eight outputs with
feedback. A programmable AND array and a fixed OR array
make possible the implementation of a wide variety of logic
functions with far fewer packages than with SSI devices. The
logic is implemented by opening metal fuse connections within
the AND array. Designs can be .specified by using any of a
variety of software packages which accept the. design and
assemble a file that can be downloaded into a device pro-
grammer•. Fuses are programmed using any of the qualified
PAL device programmers.
The outputs are equipped with programmable polarity. They
can drive a 50n termination (to Vee - 2.0V). Product term
sharing is provided to allow greater flexibility in assigning
product terms to outputs.
The input pins have 50kninternal pull-down resistors, which
allow u.nused inputs to be left open. Open inputs will assume a
logic low state.
MonoIlthlcfFIJJMemorl•• 2-115
PAL10H20P8
DIP Pinout
PLCC Pinout
COO0880M
MonoIithicm Memories
PAL10H20P8
Operating Conditions
COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX
TEST
DoC 25°C 75°C
SYMBOL PARAMETER UNIT
CONDITIONS MIN MAX MIN MAX MlN MAX
lEE Power supply current Inputs VIN = VIH Max - 210 - 210 .. 210 mA
linH Input current high VIH Min < Yin < VIH Max - 425 - 265 - 265 pA
linL Input current low VIL Min < Yin < VIL Max 0.5 - 0.5 - 0.3 - p.A
VOH High output voltage (See Note 2) -1.02 -0.84 -0.98 -0.81 ...,0.92 -0.735 Vdc
VOL Low output voltage (See Note 2) -1.95 -1.63 ~1.95 -1.63 -'1.95 -1.60 VdC
VIH High input voltage (See Note 2) -1.17 -0.84 -1.13 -0.81 -1.07 -0.735 VdC
VIL Low input voltage (See Note 2) -1.95 -1.48 -1.95 -1.48 -1:95 -1.45 Vdc
Logic Diagram
, VCC3 24
I 281
121
IltS ~ , • 1 •• 1011 lt1SIH5 1fll1," lHUH3 patin ZUUIU! .SUUl .373131
2
>3>
3 ~
141
·,, ~4:>
,
~~
151
, ,
'"
10
112 1
I
Veel i7I
· :R
~sD pU
7
"" ,"
""
pu ,101•
"
"
1131
13
,,' 1
:t
:8~
~
17
~~
"" I 201
···
'-'
" :R~
~ -pu ,111
18
"'"
15
1
VCC2 (231
"
"' 1
·"" ~D -pu I
20
'41
··" -pu 125>
21
16
09~
22
1:i61
23
127>
01!1 4$6J •• 1011 1113141' '111'1'" !II'flnn 24!f>'2111 ZI 2UI 31 '3133:M36 3&31.»
I
12
1t4.~-IJEE
MegaPAL Devices
PAL32R16 32 16 40 280
PAL64R32 64 32 50 640
Monolithic WMemories
MegoaPAL Devices
32R16, 64R32
32R16
64R32
DIP
32R16
2-120 MonoIithlcWMemories
MegaPAL Device.
64R32
Testing Conditions
COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX
Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
Width of clock
I Low 25 20
ns
1w I High 25 20
tpo
Input to I Polarity fuse intact 50 40
ns
output I Polarity fuse blown 55 45
telK Clock to output or feedback 30 25 ns
R, = 560n.
tpzx Output enable R2 = UKn. 25 20 ns
tpxz Output disable 25 20 ns
fMAX Maximum frequency 14 16 MHz
1. These are absolute voltages with respect to the ground pin on the device and Include all overshoots due to system and!or tester nOise. Do not attempt to test
these values without suitable equipment.
2. 1/0 pin leakage is the worst case of I'L and 10ZL lor I," and 10Z")·
3. No more than one output should be shorted at a time and duration of the short circuit should not exceed one second.
Operating Conditions
COMMERCIAL 1
SYMBOL PARAMETER UNIT
MIN TYP MAX
COMMERCIAL
SYMBOL PARAMETER TEST CONDITION UNIT
MIN TYP MAX
COMMERCIAL
SYMBOL PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
Input to output
I Polarity fuse intact 50
ns
tpo
I Polarity fuse blown 55
MonoIlthlcW·.emorles 2-123
MegaPAL Device.
32R16 Logic Diagram
32R16
(18) (17) (16) (15) (14) (13) (12)(11)(10) (9) (8) (7)
16 NC 15
***
14131211109876
p :r t i i i *vcc* r4-'--
NC(&)
5 (5)
~ ~ r.J.
127 0 .J;;"
(19) 17
I
~
Wp
UinrtJ::
-. • ~
~
r.J.~
J
4 (4)
~
(20) 18
.~
'-n. 3(3)
I ..J
~
~
'12 15·
j;
~ ~
.c- ~ 111 16
~ t:J.
(21) 19
I
.r
.Jr. ::f'~
Im~ t-'
-. .- dJim
-9-~
r.L
J
2 (2)
(22)20 ......
~-'fD
0..... ..~ 1 (1)
L..,""
~t:.
L
•• ..;; ~
31·
I~
J
AND
ARRAY
8K
FUSES
~ 95 32
.l:"" ...... $ t.l
trhrtJ: -.
~
w~ r~
(23) 21 40 (44)
I"" II
+
~
H
~-m:: t.l
~
(24) 22
.~ ~J
39(43)
Lf>. -*80
~
47*
~.
~
-"
~
~
~ t-;;1..
79 48 ~ t.l
(25)23
(26) 24
I
~
.~!lJ: -....... ~
.. r-
~
~-m::
J
'J. ,I
38 (42)
I ~ ~ ~
37 (41)
.l
~
~
*64 ~ "'"- ~~
;; ;.;0.
(27)25 -i>-
I
(2I)NC
40 PIN DIP
(44P1NLCC) ~ ~ l ~GND~ ~ ~ ~ ~. r
25 27 28 29 30 31 32 33 34 35 Ne 38
(29) (30) (31) (32)(33)(34) (35) (38) (37) (38)(39) (40)
Lt"",,"
2-124 MonoIlthIcW.emorle.
MegaPAL Devices
64R32 Logic Diagram
64R32
1121 111111111 i91 181 171 161 (51 141 i3I 121 111 (118)(871 (IIIi)(1I51 18411831111211811 (80)(7111 17111
Ne 11 10 9 11 7 6543218483 11211180797877 7675 NC VCC-74(77J
113112
114113
(15)14
~ ffit:. "ty
~-Bi1 ~
0 **************** 256 j~~ 72(l5)
T !1G-lli
73(76)
~ , I 71 (74)
"1 .-
~ ~~ r~
;;;;;
116115 v 1
W-
f:b- 70(73)
~- "'15
r-~
::: ...
-r5 ~1- 1.1
16 231
117116
..AI 89(72)
T 7IciI-l.i ,I
+
~~
"1
1111}17
-J Hh~
~
,~ 1 J"L ~ r v ~ 88(71)
~ .. 224+ ~~
"'31
...
-r§ ~1i ~
32 223 ~
119) 18
en. T~ 67(70)
.- -
120119
~~ i 1 '" Q r ~ ~ 111l1l9I
~
~- ""47
-~
•• -~
~ Kn:.-Bii 'J
48 1O7 ~
(21120 ;.,... 1~ ~
~~
~ F
(22)21
l:~. 84(67)
i 1'
Ir~
~
ARRAY
84
~ ~T
191
I~~ 83II1II
32K
123122
FUSES
~
....
(24123
-r5 ~
~-
~!
1
~
*79
~
in*" -~
;
i~~:m=
I~ 112(651
.;L
80 175
~ Hb.-1iili1 ~
..rfI
125124 ...L 1 '1g. -rn- 6111141
~ F
(211} 25
-J Hh~b ~l ~
~ ~-m::
r ~~ ~I... 11111131
~r- ·95 .. 180·-
-~
~ ...
116 159
.£ tiiLa=1
~ 5911121
-tiiI
(27)28 ...L 1 '1g. -rn-
"1 ~.
Hh~b r ~:m=
-r5 ~l
~r-
~
~
~v =fr-
...
5811111
·111 144·
-~
~ ...
..
112 143
l: lin- ...fI r-:l
tl--IlI'i1 ;.,... T'1g. i "V...J 571801
(30)29
-J ~ nt;;;; • r~
~
:fr 58(59)
~
f MAX Parameters is employed (Figure 1). Under these conditions, the frequency
The parameter f MAX is the maximum speed at which the PAL of operation is limited by the greater of the data setup time
device is guaranteed to operate. Because flexibility inherent to (tsu> or the minimum clock period (tv, high + tv, low). This
PAL devices allows a choice of clocked flip-flop designs, for parameter is designated fMAX (no feedback). .
the convenience of the user. f MAX for the B-speed devices is For synchronous sequential designs, i.e., state machines.
specified to address two major classes of synchronous de- where logical feedback is. required, inputs to flip-flop data
signs. terminals originate from the device input pins of flip-flop
The simplest type of synchronous c!esign can be described as outputs via the internal feedback paths (Figure 2). Under
a data path application. In this case, data is presented to the these conditions, f MAX is defined as the reciprocal of (Isu +
data terminal of the flip-flop and clocked through; no feedback !eLK) and is designated f MAX (feedback).
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~ ~ l[; r-
Figure 1. No Feedback
2.
3.
Disable output registers by setting pin 13 to VIH.
Apply VILIVIH to all registered output pins. VIL~IO
4. Pulse pin 1a to Vp' then back to av. OUTPUT VIH .,--------
REGISTERS V I L · _ _- , - _ , . - _ - - '
5. Remove VILIV IH from all output registers.
6. Lower pin 13 to VIL to enable the output registers.
7. Verify for VOLIVOH at all registered output pins. '0 '0
Power-Up RESET
All devices with this PRELOAD feature also have power-up
RESET. All registers power up to a logic high for predictable
system initialization. PIN 10 V I L - - - - - . . . J
Switching Waveforms
INPUTSI/O r---~~~~ll/-----------------------------------------3V
REGISTERED
FEEDBACK
~---J'I~~~~r~--------------~------------------------ov
CK
ASYNCHRONOUS
PRESET
COMBINATORIAL
OUTPUTS _ _ _ _ _ _ _ _ _ _ ~WKU7
MonoIlthlcWMemorles 2-127
Test Load
8 KllNOM 40 II NOM
Rl
OUTPUT [email protected]
INPUT ~,,-T--;.t--+--
YH--+---o OUTPUT
R2
Notes: 1. tpo is tested with switch S, closed, CL = 50pF and measured at 1.5V output level.
2. tpzx is measured at the 1.5V output level with CL - 50pF. S, is open for high impedance to "I" test, and closed for high impedance to "0" test.
3. tpxz is tested w~h CL = 5pF. S, is open for "I" to high impedance test, measured at VOH -0.5V output level; S, is closed for "0" to high impedance test
measured at VOL + 0.5V output level.
Table of Contents
1
Medium
20B/0 PAl16R6B/D
PAL16R4B/D f
PAL16L8BP 303A-V04 .22 17
Medium
PAl16R8BP 67
20BP
Sl!lndard PAl16R6BP
PAl16R4BP ~
PAl16P8A 30
Medium 20PA
PAl16RP8A 31
Programmable
Polarity PAl16RP6A
PAL16RP4A
PAl16X4 ...
i
Large 20 303A
24
ArHhmetlc
Large 20RA
Asynchronous
PAl16A4
PAl16RA8 l 30
Note: The software and bardware revisions listed are the earliest revisiOns that support these products.
Later SQjtwere and hardware revisions can also be assumed to support these products.
Family Pinout
Series Part Number System LoglcPak™ Adapter Code Code
'x
PAL12L10 Model 60 303A 303A-002-VOB 22 01'::
:'
PAL14lS' Rev. V05 303A-011 AlB-V01 02
' "
03, "
Small 24 PAl16L:6 Models
Combinatorial
PAL1SL4 19 04
"
,PAL20L2 " 29A
.i- .
05
PAL2OC1 29B 12
Small24A PAL6L16A 4S
DeCoder :
PALSL14A' 49
:PAL20LSAI~2/B 26
Medium 24A1 PAL20RSAI-2/B :
27
~
24A-2/B
PAL20R6A1-2/B
Standard
PAL20R4A1-2/B 1
PAL20L10 :' 06
Medium 24X PAL20X10 23
Exclu8lve-OR r"
PAL20XS
PAL20X4 l
PAL20L10A 303A-V04 J~~
Medium 24XA PAL20X10A .,,"
; 36
"
.,Excluslve-OR f'·'
l
:
'pAL20XSA
PAL20X4A
PAL20S10 .. 43
Large 24RS .PAL20RS10 t;
Shared
",pAC20RSS
..."": . ,',.:! I:":' 44
Product Terms
PAL20RS4 I: ,! 46
1 "
Large 24A
PAL22RXSA . 7S
Registered XOR 303A-011 AlB-YOl
·Large24/A
PAL32VX10/A
I,,; i"': 77
Varied XOR /1" :
. Large 24RA ! 303A-002-V08 : • .:.>
PAL20RA10 303A 45:v
Asynchronous 303A-011A/B-VO.1
: .. '
.. '
:
<ECl 303A-ECL" ,.
:PAL1OH20PS1 303A-V04 ..,42.,.
, ·Combinatorlal I',· , ',. '. ,!>~ ',' .'!..' ..:
" .'
: "
NOTE: The software and hardware revisions listed are the earliest revisions that Sl!pport tflese prod!ICIS. "
Later, software and _are revisions can also be _mad to·support tflese produc1ll,
.~, .
j j j
Programmable
PAL16RP6A
Polarity
PAL16RP4A
Large. 20 . PAL16X4 ' .
Arithmetic
PAL16A4
Large ~ORA
PAL16RA8 Under Dev~lopment
Asynchronous
NOTE: The software and hardware
..
revisions
..
l!\Ited are the earliest reVISions that support these products.
La,ter software and hardware revisions can also be assumed to support these products.
I I
Small 24 PAL16L6
J
Combinatorial
PAl18L4
PAL20L2 "
PAL20C1
Smal124A PAL6L16A
, Under Development
'Decoder
PAL8l14A
PAL20L8A1·2/B 5.4 DA55 C-1
Medium 24AI PAL20R8A1·2/B
24A-21B
PAL20R6A/·2/B
Standard
PAL20R4A/·2/B
PAL20L10
Medium 24X PAL20X10
Excluslve-OR
PAL20X8
PAL20X4
..... ,..
PAL20L10A
Medium 24XA PAL20X10A ,
Exclualve-OR
PAL20XBA
PAL20X4A
, q'
PAL20S10
Large 24RS PAL20RS10
Shared
PAL20RSB
Product Terms
PAL20RS4
Large 24A
PAL22RXBA
Registered XOR
" "
" ,"
Large.24/A
PAL32VX10IA
Varied XOR
Large 24RA
PAL20RA10
Asynchronous
ECL
PAL10H20P8 ~, ' .~ .:
Combinatorial '0
"
MegaPALTM, PAL32R16 "
Und~r, De,<~I~,pr"eht
Devices '
PAL64R32
. ".;.
NOTE: The sofIware and hardware '811"1008 Ioslad ara the ,earliest revisions that support th~ products.
, Later sofIwara and hardware revisions can also be assumed to ~upport these products,
.MI.PAL@ Device Programmer Reference Guide
PAL16R4/A!·214/B·2/ 4
PAL16L8B/D
Medium PAL16R8B/D
20B/D Under Development
PAL16R6B/D
~ ,. ~ <,~ '" ,.
PAL16R4B/O "
PAL16L8BP SA·27
Medium
PAL16R8BP Under Development ,J
20BP
Standard PAL16R6BP
".
PAL16R4BP
". ,
Medium 20PA
PAL1.6P8A
PAL16~P8A ....
,
Programmable
Polarity PAL16RP6A ," . ,
','
PAL16RP4A
Large 20 PAL16X4
Arithmetic '. PAL16A4 ''c'
"; ..
Large20RA -,' "'". ,
, pAL16RA8 '. 1.47
Aayflchronou.
..
NOTE: The software and hardware revISIOns listed are the earl,est
...
tevISIOns that support these products.
Later software and hardware revisions can also be assun'iad to, support these po:oducts.: .
3-1
MMI PAL® Device Programmer Reference Guide
1
PAL18L4
PAL20L2
PAL20C1
Smal124A PAL6L16A
Under Development 1.48
Decoder PAL8L14A
PAL20L8A/·2/B SA·27·1 1.44
Medium 24A1
PAL20R8A1·2/B
24A-2/B
Standard PAL20R6A1·2/B
PAL20R4A1·2/B
PAL20L10
Large 20 PAL16X4 c
Arithmetic PAL16A4
Large 20RA
PAL16RA8 Under Development
Asynchronous
NOTE: The software and hardware
..
reVISions
listed are the earliest reVI$lons that support these products.
Later software and hardware revisions can also be assumed to support these products.
1
PAL18L4
PAL20L2
PAL20C1
Small24A PAL6L16A
Under Development
Decoder PAL8L14A
PAL20L8A1-2/B 3.5
Medium 24A1
PAL20R8A1-2/B
24A-2/B
PAL20R6A/-2/B
Standard
PAL20R4A1-2/B
PAL20L10
MegaPAlTM PAL32R16
Under Developm",nt
Devices PAL64R32
NOTE: The software and hardware revisions listed are the earliest rsvisions that support thase products.
Later software and hardware revisions can also be assumed to support thase products.
3-10 MonoIlthlcWMemor/ea
MMI PAL@ Device Programmer Reference Guide
MonoIlthlcWMemorles 3-11
MM. PAL ® Device PrograllJlIJer Reference Guide
~
Ie
Large 24/A
PAL32VX10/A e
Varied XOR
Large 24RA
PAL20RA10 3M
Asynchronous
ECl
PAL10H20PB Undf;lr Df;lvelopment
Combinatorial
MegaPAlTM PAL32R16
Under Development
Devices PAL64R32
.. ..
NOTE: The software and hardware reVISions listed are the earliest reVISions that support these products .
Later software and hardware revisions can also be assumed to support these products.
1 1
Medium PAL16R8B/D 22-30
20B/0
PAL16R68/D 22-31
PAL16R4B/D 22-32
PAL16L8BP 20-29 30-35 14.
Medium PAL16R8BP 20-30 19
20BP
~
..
PAL16R6BP 20-31
Standard
PAL16R4BP 20-32
PAL16P8A 20-38 12
,
1
Medium 20PA PAL16RP8A 20-1.1
Programmable
PAL16RP6A 20-12
Polarity
PAL16RP4A 20-13
Large 20
Arithmetic
PAL16X4
PAL16A4
20-33
20-34
, 14
Large 20RA
PAL16RA8 20-19 30-37 12
Asynchronous
NOTE: The software and hardware reVISions Usted are the earilest reviSIons that support these products.
Later software and hardware revisions can also be assumed to support these products.
Small24A PAL6L16A
Under Development
Decoder PAL8L14A
PAL20L8A1·2/B 21·56 30·35 12
Medium 24A1 PAL20R8A1·2/B 21·57
24A·2/B
PAL20R6A1·2/B 21·58
Standard
PAL20R4A1·2/B 21·59
PAL20L10 21·60
Medium 24X PAL20X10 21·61
Exclusive·OR
PAL20X8 21·62
PAL20X4 21·63
PAL20L10A 21·60
Medium 24XA PAL20X10A 21·61
Excluslve-oR
PAL20X8A 21·62
PAL20X4A 21·63
P~L20S10 21·81 30·39
1
large 24RS PAL20RS10 21·80
Shared
PAL20RS8 21·79
Product Terms
PAL20RS4 21·78
Large 24A
PAL22RX8A Under Development
Registered XOR
Large 24/A
Varied XOR
PAL32VX10/A ~
Large 24RA
PAL20RA10 21·77 30·37
Asynchronous
ECl
PAL10H20P8 Under Development
Combinatorial
MegaPAlTM PAL32R16
Under Development
Devices PAL64R32
, ,
NOTE. The software and hardware revtSlons listed are the earhest reviSions that support these products.
Later software and hardware revisions can also be assumed to support these products.
1
Medium PAL16RSB/D
20B/0
PAL16R6B/D
PAL16R4B/D
PAL16LSBP 2.0
Medium PAL16RSBP
20BP
Standard PAL16R6BP ..UnderDevelopment
PAL16R4BP
PAL16PSA 4.0
Medium 20PA
1
PAL16RPSA
Programmable
PAL16RP6A
Polarity
PAL16RP4A
Large 20 PAL16X4
Arithmetic
2.0
PAL16A4
:
Large ..20RA
PAL16RAS 4;04
Asynchronous
..
NOTE: The software and hardware revISions listed ars the earliest r""'Slons that support these products.
Later software and hardware revisions can also be assumed to support these products.
1
PAL18L4
PAL20L2
PAL20C1
Small24A PAL6L16A
Under Development
Decoder PAL8L14A
PAL20L8A1·2/B 2.0
Medium 24A1 PAL20R8A/·2/B
24A-2/B
PAL20R6A/·2/B
Standard
PAL20R4A1·2/B
PAL20L10
3-18 MonoIlthlcWMemor/es
MMI PAL ® Device Programmer Reference Guide
1
PAL16RP4A
Large 20 PAL16X4
Arithmetic PAL16A4
Large 20RA
PAL16RAS Under Development
Asynchronous
NOTE: The software and hardware revisions listed are the earliest revisions that support these ,products.
Later software and hardware revisions can also be assumed to support these products.
MonoIlthlcWMemories 3-19
MM. PAL@ Device Programmer Reference Guide
1
PAl18L4
PAL20L2
PAL20C1
Small24A PAL6l16A
Under Development
Decoder PAL8l14A
PAL20L8AI ·2/8 1.03
Medium 24A1
PAL20R8A1·2/8
24A-2/B
PAL20R6AI -2/8
Standard
PAL20R4A/-2/8
PAL20X10
3-20 MonoIlthlcWMemor/es
MM. PAL@ Device Programmer Reference Guide
~
Standard PAL16R6BP
PAL16R4BP
PAL16P8A 3.18,
Medium 20PA
PAL16AP8A
Programmable
PAL16RP6A
Polarity
PAL16RP4A
Large 20
Arithmetic
Large 20RA
PAL16X4
PAL16A4
1
PAL16RA8 Under Development
Asynchronous
NOTE: The software and hardware revisions listed afe the earliest revisions that support these products.
Later software and hardware revisions can also be assumed to support these products.
Smal124A PAL6116A
Decoder PAL8L14A
PAL20L8A1·2/S
Medium 24A1 PAL20R8A/·2/S
24A-2/B
Standard PAL20R6A1·2/S
PAl20R4A1·2/S
PAL20L10
Table of Contents
HAL/ZHAL Devices
ProPAL,TM HAL and ZHAL Devices: The Logical Solutions for Programmable
Logic ................................................................................................4-3
ZHAL20A Series - Zero Power CMOS Hard Array Logic .......................... .4-7
ZHAL64R32 - Zero Power CMOS Hard Array Logic ................................ 4-15
ZHAL24A Series - Zero Power CMOS Hard Array Logic ......................... 4-24
So you have discovered the convenience and flexibility of mented in a HAL version, allowing you to move smoothly into
designing with PAL® devices from Monolithic Memories. You volume production. '
have implemented a design using PAL devices, and taken that
design into production. Now may be the time to consider ways
of reducing the efforts you put into programming, testing, and
marking large volumes of PAL devices. Wouldn't it be more
convenient if you could be relieved of the duties and costs of
volume programming and testing and still reap the benefits
afforded by programmable logic?
Or perhaps you are considering a semicustom product, but
you're a little nervous about going to a gate array. Wouldn't it
be preferable if you could find a semicustom product which CD0100qM
without the normal risks inherent in purchasing a semicustom • If you find yourself with an unexpected demand, you need
product. Why? Secause: not turn away business for lack of HAL device .stock. You
• You can prototype your system and initiate production using can always use ProPAL devices to make up for any
standard Monolithic Memories PAL devices. You don't have temporary shortfall.
to worry about making a mistake that could put your design HOw Can You Tak~ Advantage of This?
schedule in jeopardy. The following are some guidelines which you can use to help
• The nominal Non-Recurring Engineering (NRE) charges for convert your designs to ProPAL, HAL or ZHAL devices.
ProPAL and HAL devices are far lower than those normally 1. Send In Your Design
required for a semicustom qircl.lit. And they can even be
You will need to provide your logic equations from either
amortized over your first producti9n quantity.
PALASM@; PALASM 2 or ABELTM on magnetic media'.
Unit When Monolithic Memories generates vectors for use in
Volume functionally testing your pattern, "seed" vectors are helpful ,in
/
providing the foundation upon which the final test vectors will
be based.
A master PAL' device containing your design is needed for
Monolithic Memories to verify that the pattern you submitted
HAL device
has been correctly processed. If you cannot provide a Mono-
lithic Memories master PAL device, Monolithic Memories will
accept your design inputs and provide ProPAL samples for
your approval.
For your convenience, a checklist is included to help you
ProPAL device prepare all of the necessary materials to be submitted to
Monolithic Memories. This will also help Monolithic Memories
process your design, resulting in smoother and faster turn-
around. Copies of this form are available from your Sales
PAL device Representative, or you can simply copy the attached form.
2. MMI Will Verify the Design
Upon receiving your design package, Monolithic Memories will
Monolithic Memories enter your design into their computer and verify that there are
Programmable no format or syntax problems. A fuse map will be generated,
Solutions
and sample Pro PAL devices programmed.
If any questions are encountered at this stage, they will be.
• You save on the costs of programming devices. This will resolvlild with you before any further processing takes place.
also shorten your production cycle, since you can plug the
3. MMI Will Check the Samples
devices into the socket with no additional processing.
If you have approved immediate production of your devices,
• All of the devices are tested for full functionality before they Monolithic Memories will make a fuse for fuse comparison
leave Monolithic Memories. You save on the costs of
between the samples and the master device you provide. If
testing and generating test programs.
there are no discrepancies, test generation will be started
• Monolithic Memories 'is geared towards providing volumes immediately (or upon receipt of your purchase order).
of high quality devices. No' one knows how to test
If you prefer to see programmed sample ProPAL devices prior
programmable logic as well as Monolithic Memories.
to initiating production, Monolithic Memories can provide them
Between" the thorough, efficient testing and marking
for your approval before proceeding further. Sample approval
capabilities and the option to provide bum-in for extra
is also needed when no master devices are provided or when
reliability, ·you can obtain a higher quality device that if you
a discrepancy is found during verification.
did thepr6gramming and testing yourself,
4. MMI Will Generate Test Vectors
• MMI cah provide' custom marking. This saves you the
added expense of stripping ·the mark from standard devices A functional test sequence is generated using TGENTM, a
and then remarking them with your own mark. proprietary software package. Any seed vectors you provide
will be used to help initiate test generation. TGEN will check
• HAL devices are secure by design. If you prefer ProPAL
for hazards and race conditions, monitor fault coverage and
devices, they can also be secured for you at the factory.
systematically add vectors until test coverage goals are met.
• ProPAL device lead time is only 1 t6 2 weeks longer than
Monolithic Memories has a test quality standard that sets as a
thatof unprogrammed PAL devices.
minimum goal 90% coverage of all stuck-at faults. Lower
• HAL device turn-around time. is a mere 6 to 8 weeks or less coverage patterns can sometimes be processed as HAL
from acceptance of your design package to receipt of first devices, or it is possible to handle them as ProPAL devices
units. only, but your approval will be needed. If acceptable coverage
"Floppy disks are accepted in standard DEC@ AT-II (RXOI) or RSX·IIM@, cannot be obtained, ways of increasing the testability of the
files II format, or an IBM pcTM 5-1/4 in. disket1e. IBM' compatible (SOO or 1600
BPI) nipe track magnetic tapes are accepted in unlabeled (card image), files· I I,
deSign may have to be considered before· Monolithic Memo-
or VAY. VMS@ backup formal If magnetic media absolutely cannot be provided, ries can process the pattern.
legible printouts (signed and dated) from PALASM will be accepted. Please note
that magnetic media are required if you have more than 50 vectors.
d
4·4 MonoIlthlcWMemories
ProPAL™,HAL@, and ZHAL™ Devices:
The Logical Solutio'" for Volume Programmable Logic
Tllble 1
The following items are requested but not required. Please check if provided:
_ Seed vectors
_ Master PAL device
OPTIONS
A. _ I want to start production immediately B. _ I want to verify the MMI generated sample
(or upon submittal of purchase order) if: devices prior to production implementation.
1. Design is acceptable; _ I want to approve the test vectors prior to
2. MMI samples match my master device production implementation.
fuse for fuse;
3. Minimum test coverage goals are met.
(Master device must be provided.)
Please complete this form for each pattern submitted to Monolithic Memories, and include it in your design package.
Submitted by: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---,-_ Date: _ _ _ _ _ _ _ _ _ _ _ _ _ __
Title: ________________________________________________________________________________
4-6 MonoIlthlcWMemor/es
Zero Power CMOS Hard Array Logic
ZHALTM 20A Series
ZERO-I~.
lS
whether a design specification will fit within the ZHAL20 ~PAnERN
POWER ~ NUMBER
architecture. For more information on the ZHAL software, HARD ARRAY
refer to the PALASM 2 User Manual. LOGIC
. PR~E~S1~~nd'rd
For evaluation of the ZHAL20A circuit, sampl'il patterns are NUMBER OF
ARRAY. INPUTS PACKAGE
available. See page 4-13 for details. N = Plastic DIP
OUTPUT TYPE NL - Plastic Leaded
L = Active Low Chip Carrier
H ... Active High
P - Programmable '--_ _ _~~ TEMPERATURE RANGE
Polartty C ... O°C to + 75°C
C - Complementary I ... _40°C to + 85°C
R - RegiStered
RP .. Registered ' - - - - - - - - SPiED= High Speed
Programmable
Polarity
'----'------ ~~~~~fsOF
Monolithic l!T!n
Memories wn.u
TWX: 910-338-2376
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 91.0-338-2374
4·7
Zero Power CMOS Hard Ar,a~ Logic
ZHALTII 20A . ., ....'
,~" .. ! . . ,
PIaItleChip carrier Pllltle Chip carrier Plastic Chip carrier Pllltle Chip carrier
PI.astic Chip Carrier Plastic Chip Carrier Plastic Chip Carrier Plastic Chip Carrier.
Plastic Chip Carrier Plastic Chip Carrier Plastic Chip Carrier Plastic Chip carrier
Operating Conditions
INDUSTRIAL COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
Iw Width of clock 15 10 15 10 ns
16R4A, 16R6A, 16R8A,
Setup time from input or
tou 16RP4A, 16RP6A, 20 13 20 13 ns
feedback to clock
16RP8A
th Hold time 0 -10 0 -10 ns
Monollthii:W'lIIIemories 4·11
Zero Power CMOS Hard Arra, Logic
ZHAL™ 20A Serle.
FROM OUTPUT
UNDER TEST
(SEE NOTEeL
1)
H
TE5POINT
I
RL 51
vee
1 (SEE NOTE 2)
OUTPUT
CONTROL
(Low-Ievet
~abling)
WAVEFORM 1
(See Note 3)
VT
~----:-----'7----- V,L
~tpZL""""
VT
.-tpZH .....
"::" -::-
WAVEFORM 2
(See Note 3) VT
Notes: 1. CL includes probe and iig .capacitance.
2. When measuring tpLZ and tpZ,L' 81 is tied to Vee. When measuring
tpHZ and IpZH' St is tied to ground. Ipzx is measured with CL -
50pF. tpxz is measured with CL = 5pF. When measuring
Schematic of Inputs and Outputs
propagation delay times of 3-state outputs. St is open. i.e.. not
connected to Vcc or ground.
3. Waveform 1 is for an output with internal conditiQrls such that the
output is Low except when disabled by the output control.
~ ••• ~vee
'--8c['" ~rf~
Waveform 2 is for an output with internal conditions such that .the
output is High except when disabled by the output control.
Output Register PRELOADt
The PRELOAD function allows the register to be loaded from
-::- -=-
data placed on the output pins. This feature aids functional
testing of state sequencer designs by allowing direct setting of
output states for improved test coverage. The procedure for
PRELOAD is as follows:
~N1 w---------------:-____
VIH , . - - - - -_ _ _ _ _ _ _'"\
1. Raise Vee to 4.5V.
PIN 11 "I \
2. Disable output registers by setting pin 11 to V IH' Set pin 1 VIL.-../ ~
to OV.
3. Apply VIL/VIH to all registered output pins.
4. Pulse pin 8 to Vp (12V). then back to OV. ~--.,.--.,...--_>-C
5. Remove VIL/VIH from all registered output pins.
6. Lower pin 11 to V IL to enable the output registers. 'sup
vp I-I-Iw+*hp
7. Verify for VOL/VOH at all registered outpUt pins.
t Note: Only applies to parts with output registers. PIN 8
Typical tsup = 50ns
I,.p = tOOns
thP = 50ns
I'H = 301lA (Pin 8) ylL------:I
H X X X Z High-Z L X X Z Z Z High-Z
L H L t Q plus 1 Increment H L L D2 D1 DO No operation
L L L t Q minus 1 Decrement H L H DO D2 D1 Shift by one
L X H t High Reset H H L D1 DO D2 Shift by two
H=HIGH voltage level
L= LOW voltage level
X=Don't care
Z=High impedance (off) state
f= LOW·lo·HIGH clock transilion
EQUATIONS SETf III /10 /02 /01 /00 Y2 'il 'iQ /CNTRSET UP
CLOCKF eLK
YO - /ll"'/10*/00:,
C!f~CIC /03 ./02 /01 /00
: lii:/ig:~gf SETF III 10 02 /Dl DO /'l2 IYl YO
YO.TRST - EN·
CLOCKF eLK
Yl ,. /Il.;Id·i/~l" CHECK /03 /02 /01 QO
+ Ill. IO*/D2 '
+ Il*/IO*/DO' SETF Il /10 /02 01 /DO IV2 'il YO
Yl.TRST ., EN ,. CLOCRF eLK
4-14
Zero Power CMOS Hard Array Logic
ZHAL64R32
Features/Benefits load pin allows test vectors to be loaded directly into the
registers for control of present state conditions for testing.
• Cost-effective mask-programmable complement to
PAL64R32 user-programmable device Design Procedures
• CMOS technology provides zero standby power The zero-power ZHAL64R32 device is a CMOS, mask-pro-
grammable version of the bipolar PAL64R32 circuit. Prototyp-
• High speed with 55ns maximum propagation delay
ing can be done with the user-programmable PAL@ circuit
• High density with 32 highly-flexible macrocells and global before committing to a dedicated mask. Thus the Mega-
connectivity PALTM/MegaHAL products combine the instant prototyping of
• Product term sharing, selectable output polarity, and the PAL circuit with the cost-effective, zero power ZHAL™
register bypass for high logic efficiency circuit.
• Individual clocks for 4 banks of 8 registers To initiate a design with the ZHAL64R32 device, the
• Register preload for easier test generation PAL64R32 circuit is used to program and debug the design
• HC/HCT level compatible for use in CMOS/TTL systems with PALASM@2 software_ The resulting "PAL Device Design
Specification" is submitted to Monolithic Memories, and the
Description ZHAL Circuit option is produced. A ZHAL32R16 option is also
The ZHAL64R32 circuit is a high-density logic device with available. For details contact a Monolithic Memories represen-
thirty-two flexible macrocells. Each macrocell consists of a tative.
registered sum of products with feedback, forming a one-bit
state machine. The PALlZHAL64R32 device can implement Ordering Information
over 1500 equivalent logic gates.
The MegaHALTM circuit (eatures product term sharing be-
tween output pairs. This. allows sixteen product terms to be
ZHAL ~ z.ro-pOW::JJJr~..
Hard Array
Logic
64 R. 32
r.' I.: NUMBER
HOC£;T PATIERN
PROCESSING a
shared mutually exclusively between outputs. Selectable po- ARRAY INPUTS STD ~ Standard
larity allows the output to be either active low or active high, XXXX'" Other
OUTPUT TYPE PACKAGE TYPE
depending on the sense of the equation. Registers can be R = Registered NL II: Plastic I
bypassed in banks of eight, leaving combinatorial outputs. Leaded Chip
NUMBER OF Carrier
Each register bank has its own clock, preset, preload, and OUTPUTS p= Pin Grid
Array
enable controls for independent operation. The register pre- TEMPERATURE
RANGE
C = ooe to 75°C I - -40°C. to ~5°C
MonoIlthicWMemorielfl 4-15
ZHAL64R32
70(731
117116
681711
67 (701
66(691
65(681
64(671
AND
ARRAY
63(681
(24123 62(651
125124 61 (64)
(26125
159
(27)211 58(62)
(28127 58(611
131lI29
(31)30
(33)32-VCC Nt 3334
(34) 13511361
")', ....
Operating Conditions
COMMERCIAL INDUSTRIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
Active
Input or feedback to low
tpD 1 34 55 34 58 ns
output Active
high
1
FROM OUT,PUT (SEE NOTE 2)
UNDER TEST ....-tpZL ......
CL
(SEE NOTE 1) I WAVEFORM 1
(See Note 3)
VT
-= -= .-tpZH-+-
WAVEFORM 2
(See Note 3) VT
Switching Waveforms
INPUTS. UO.
REGISTERED
FEEDBACK
eLK
REGISTERED
OUTPUTS
COMBINATORIAL
OUTPUTS
---------------------~
Schematic of Inputs and Outputs
Notes: 1. CL includes probe and jig capacitance.
2. When measuring tpLZ and tpZL' $r is tied to Vee. When measuryng
~ ••• -ZVCC tpHZ and tpZH ' S1 is tied tp ground. When measuring propagation
'--Cc['" •~q-'"~'
delay times of 3-state outputs, 81 is open, i.e., not connected to Vee
or ground.
3. Waveform 1 is for an output, with internal conditions such that the
output is Low except when disabled by the output control. 'Waveform
2 is for an output with internal conditions'such that the ,output is High
-= -= except when 'disabled by the output 'control.
OE
REGISTERED
OUTPUTS 1I~~rJj~rJj~~ __1TEST DATA
thp
'reload data must be held constant while the PRELOAD pin is low.
400 400
300 300
v-- ~
.,,/ r--
-
/' 1
u200
V .9 V I
~/
1..-........ ~ ..... '"
",'" /'"
o
o
'" 4 8 12 16
00 '" 8 12 16
(STANDBY) FREQUENCY-MHz ('MAX> (STANDBY) FREQUENCY-MHz ('MAX)
400
400 I
I I
I I
I I
I
300
~ 300
I
~ l.,.---~I
I
I
1, 200 / I
I I~ I
I
~ V
I
I I
I I
I
t/
... ~.,..----
....... I
////
I 100
100 I
I
",'" I
10-'" I I
I I
I
",'" I
I ~/ I
o
o '" 4 8 12 14 16
o
o 8 12 14 16
(STANDBY) FREQUENCY-MHz ('MAX)
(STANDBY) FREQUENCY-MHz ('MAX)
TA = 8S·C
TA = -40·C
_ _ = MAXIMUM VALUE
___ = Vee = 5V WITH 32 INPUTS MAX PER PRODUCT TERM
4-20 MonoIlthlcW.emorie.
ZHAL64R32
70 70
--1 I
=MAXIMUM VALUE
60 L 60
/
L 'so
r-- J
L
V
-
40 40
r--
~
30
o 16 32 48 64 16 32 48 64
NO. OF INPUTS/PRODUCT TERM
NO. OF INPUTS/PRODUCT TERM
70 70
~
60
/ .60
V
-V .
Ii'
J
so ",
L
40 ~
V
40
r-----
30
o 16 32 48 64 30
o 16 32 48 64
NO. OF INPUTS/PROOUCT TERM NO. OF INPUTS/PRODUCT TERM
~=wc ~=WC
How To Use The PAL/ZHAL64R32 is different from the logic sense of that output as defined by its
The following description and example demonstrate the func- equation, the output is inverted or active low polarity. If the
tionality of the PAL/ZHAL64R32, using PALASM 2 software. logic sense of a specific output in the pin list is the same as
Conventions for writing equations conform with the PAL De- the logic sense of that output as defined by its equation, the
sign Specification format. Features to be programmed into the output is active high polarity.
PAL device are completely specified by the equations and Product Term Sharing
automatically configured by PAL device assemblers. The basic configuration is sixteen product terms shared be-
Register Bypass tween two output cells. For a typical output pair, each product
Outputs within a bank must either be all registered or all term can be used by either output; but, since product term
combinatorial. Whether or not a bank of registers is bypassed sharing is exclusive, a product term can be used by only one
depends on how the outputs are defined in the equations. A output, not both. If equations call for both outputs to use the
colon followed by an equal sign [:=] specifies a registered same product term, two product terms are generated, one for
output with feedback which is updated after the low-to-high each output. This should be taken into account when writing
transition of the clock. An equal sign [ = ] defines a combina- equations. PAL device assemblers configure product terms
torial output which bypasses the register. Registers are by- automatically.
passed in banks of eight. Bypassing a bank of registers This example on the following page uses the 84-pin package.
eliminates the feedback lines for those outputs. Four output equations are shown to demonstrate functionality.
Pin names are arbitrary.
Output Polarity
Output polarity is defined by comparison of the pin list and the
equations. If the logic sense {)f a specifiq output in the, pin list
~
---c..... PATTERN
For evaluation of the ZHAL24A circuit, sample patterns are
available. See the description in this document for details. ZERO~]fl
POWER
HARD
ARRAY . ... • .
NUMBER
p.R.OCESSING
LOGIC STO = Standard
XXXX = Other
~~~:~7N~~TS .. PACKAGE
NS = Plastic DIP
OUTPUT TYPE NL .. Plastic Leaded
L - Active Low Chip Carrier
C ... COmplementary
R ... Registered L.._ _ _ _ _ TE~~E~~6~:~f5~~GE
X XOR Registered
;0:
4-24 MonoIlthlt:WMe",or/es
ZHAL24A Series
CUSTOMER
,---------1
I I
MONOLITHIC MEMORIES
I I
I I
~-----+~ I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
IL- _ _ _ _ _ I
-'-~...:...---J
ZHAL12L10A ZHAL14L8A
INPUT INPUT
AND ACTIVE ACTIVE
AND
LOW LOW
OR OR
LOGIC OUTPUT OUTPUT
LOGIC
CELLS CELLS
ARRAY ARRAY
ZHAL16L6A ZHAL18L4A
INPUT ACTIVE
INPUT LOW
ACTIVE AND
AND OUTPUT
LOW OR
OR CELLS
OUTPUT LOGIC
LOGIC
CELLS ARRAY
ARRAY
ZHAL20L2A ZHAL20C1A
ACTIVE COMPLE-
INPUT LOW INPUT
AND MENTARY
OUTPUT AND OUTPUT
OR CELLS OR
LOGIC CELLS
LOGIC
ARRAY ARRAY
ZHAL20L8A ZHAL20R8A
ZHAL20R6A ZHAL2OR4A
ZHAL20L10A ZHAL20X10A
INPUT
AND
OR OUTPUTREG
LOGIC CELLS
ARRAY
ZHAL20X8A ZHAL20X4A
MonoIlthlcWMemor/es 4-29
ZHAL24A Series
ZHAL20S10A ZHAL20RS10A
INPUT REG
AND OUTPUT
OR CELLS REG
LOGIC
REG
ARRAY
ZHAL20RSSA ZHAL20RS4A
4-30 MonoIithicWMemories
ZHAL24A Series 12L10A, 14L8A, 16L6A, 18L4A, 20L2A, 20C1A
Operating Conditions
INDUSTRIAL COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
Rl = 1Kn
tpD Input to output 13 256 13 256 ns
CL = 50pF
Notes: 1. These are absolute voltages with respect to the the ground pin on the device and includes all overshoots due to system and/ or tester noise.
Do not attempt to test the&6 values without suitable equipment.
2. JEDEe standard no. 7 for high-speed CMOS devices.
3. Applies to pins 14-23 for DIP (pins t7. 18.20-27 for PleC).
4. Disable output pins = V cc or GND.
5. Add 3mA per additional 1.0MHz of operation over 1MHz.
6. For outputs, with more than 12 inputs in a product term, tpD = 30n8.
Operating Conditions
INDUSTRIAL COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
Operating Conditions
INDUSTRIAL COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
Vee Supply Voltage 4.5 5 5.5 4.75 . 5 5.25 V
lw Width of clock 15 5 15 5 ns
20X10A,
Setup time from
t..u 20X8A, 25 1 15 251 15 ns
input or feedback to clock
20X4A
th Hold time 0 -10 0 -10 I1S.
TA Operating free-air temperature -40 25 85 0 25 75 0Q
f MAX
Maximum
20X8A,
20X4A
22.2 32
. 22.2 32 MHz
frequency
Notes.. 1.
'2.
-
For outp~ WIth more th", 12 Inputs In a product term, !lou 30ns and !Po 30no.-
These are absolute voltages with respect to the. ground pm on the device and include 'all overshoots due to system and/eil' tester noise.
Do not attempt to test these valueswilhout suitable equipment; .
3. Pin 10 (PRELOAD pin), pin 13PLCe (PRELOAI':f pin). Applies to registered devices-only.
4. JEDEC standlird 110. 710r high-speed eMOS devices: .' . . . •.. -
5. Applies to 'pins 14·23 lor DIP (pins 17, 18,20-27 lor PLee).
6. Disable output pins - Vcc or GND. . :.
7. Add 3mA per add"ional 1.0MHz of operation over 1MHz.
8. eL - 5pF.
4~33
ZHAL24A Series 20S10A, 20RS10A, 20RS8A, 20AS4A
Operating Conditions
INDUSTRIAL COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP MAX MIN TYP MAX
4·34 MonoilthicWMemorles
ZHAL24A Series
'CL'
TEST .. '. '.
1'."(SeE NOTE. 2)
- --=-
~
••• ~"·,.vee
Notes: 1. ct In<;l~ prooeand jig ~clti.~. . .
--I
INPUT.~'
• P P 2. wt:'en m~~ng fuand Ip~. 51' is\i9d,to Vee' When rneasuiing
tpHi andlpzH," SHe ,tiedU> ground: \pzx . is 'measured with
YN - '..
.•••
--I
.
N
. . . . . ' . .... OuTPUT
CL ~ SOpF,lpxz 1.rneasuredw~h CL·=·SpF,. . , '
of
When measuring Propagation delay .timeS three-state OUlpLlts. S1
to:
i~ 1JPlIn; i:e:. O'!t connected \(i5c:' or ~round.. . . ' .
-=- ~ 'lVl1vefOrm 1 IS: lot an pulpUt 'Wltliii!tGmaJ Conditio.,,~ such thai the
pulP"! 'is ,LOW ilxeept when JjisSbkldby 'the oulput control.
Wii.vef~ 2 is tOr anoiltpuf Witi1'.lhternal conditions.·such !hat' the
Output Register PRI;LOADt oul!>ut,is'I:tIGHexcept when disabled,bi1h" output control.
The,PRELOAD·function allows.tlTe register to be loaded·from
PIN 1 Q'JI....;.._...;..-,.---_ _...;.._ _ _ _ _ __
datil placed on thEl output pins. ThisfElature aids fqnctiOrial
testing' ofstatEl sElquElncElr. dElSigns by allowing dirElct sEltting. of
output statEls for improvEld test covElrl\Q9. ThEl procedure for
PRELOAD using DIP pin numbers, is as follOWs:
1. Raise Vee to 4.5V.
2. Disable output registers by setting, pin 13 to V1H . Se.t pin 1
toilV.
3~ Apply V1LIV 1H to all registered outputs.
4. F'ulse pin 10 to Vp.(l2V),.then back to OV.
5. Remove V1LIV1H frorn allregJstered outputs. .
6. ,Lower pin 13 to V1L'tO enable tl:le outPUt registers..
7. Verify for VollVOH at all registered outputs.
t Note; Only applies to partswilh oUlJlut registers.
, Typical isup - 50nS ' PIIII:10
, VIL.."..'-..--......- J
Iwp = lOOns
thp - 50ns
IIH = 30pA (Pin ·10)
ZHAL24A Evaluation #4
Function Table
OE CK 11 10 CI 07·00 07·00 OPERATION
H . ... . Z HI-Z'
L t L L X X L CLEAR
L t L H X X 0 HOLD
L t H L X D 0 LOAD
L t H H H X 0 HOLD
L t H H L X o plus 1 INCREMENT
·When DE is HIGH, the three·state outputs are disabled to the high-
impedance states; however, sequential operation of the counter is not
affected.
H = HIGH voltage level
L = LOW voltage level
X = Don't care
Z = High impedance (off) state
! = LOW-to-HIGH clock transition
4-36 MonoIlthleWMemor/es
ZHAL24A Evaluation #4
Logic Diagram
ZHAL20X8A
CK IO 00 01 02 03 04 0506 07 Il GNO
JOE /CO Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO /CI VCC
EQUATIONS
TWX: 910-338-2376
Monolithic ~T!n
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374 Memories Il1Jn.U
5-2
Configurable Logic Block Interconnect
The core of the Logic Cell Array is an 8 x 8 matrix of The Array's extraordinary flexibility is also the result of a two-
Configurable Logic Blocks. Each CLB provides four logic layer metal network of lines that run horizontally and vertically
inputs, a clock input, a combinatorial logic section, two logic between the logic and I/O blocks, and a variety of user-
outputs, and a programmable storage element. definable interconnection elements.
The inputs drive a combinatorial logic section that can perform Definable interconnection points connect the inputs and out-
any logic function from a simple gate to a three-out-of-four puts of logic and I/O blocks to nearby metal lines.
majority decoder. Crosspoint switches and interchanges are clustered at the
The combinatorial portion accepts and generates both posi- intersection of every row and column of logic blocks. They link
tive- and negative-true logic, eliminating the need for inverters horizontal and vertical paths and allow signals to be switched
or the routing of complementary signals. from one path to another.
The storage element can serve as aflip-flop (D-type) and can Finally, "long lines" run the length and breadth of the chip,
be programmed to have clock enable, synchronous set and bypassing interchanges but tying into logic blocks and other
reset, and various gated inputs. In addition, since all these lines and distributing clocks and other critical signals with a
options can be specified independently for each logic block, minimum ~f propagation delay.
designers can mix asynchronous and synchronous logic in any Interchanges and interconnection point assignments, as well
combination. as all routing are handled automatically by the XACT Develop-
ment System Software. In addition, special graphics-based
deSign tools are included to facilitate any necessary deSigner
interaction.
•• •• •• •• •• •
· ... .ii.
~.=-im=~
•• • • • • ._--
•• • • ---
•• • • • • • • •••
•• • • • • • • • • ••
• • • • • • • •• ••
•• •• •• •• •• •• •• •• •••
•• ••• •
•••••••••••••••••
• • ••
Configurable I/O Block
External Signals enter and leave the chip through general-
purpose, user-definable I/O blocks positioned around the
periphery of the array. Each block can be programmed inde-
pendently to be an input, output or bidirectional pin with a
tristate control on the output. When configured as an input,
the designer can select TIL or CMOS thresholds. In addition,
each I/O bloc contains an input register option whose clock
line is common to all the other I/O blocks along the same
edge of the die.
I/O blocks can also handle more than input and output
functions. For example, the Input registers of unused I/O
blocks can be used for read/write storage registers or as
stages of a shift register.
Figure 1
MonoIllhlcilD.emorles 5-3
Logic Cell ArrayTM
M2064
Features/Benefits less than 10% of equivalent TTL systems. The use ofinnova-
• CMOS programmable Logic Cell Array (LCATM) for tive 110 buffers providing either TTL or CMOS input switching
replacement of standard logic levels insures lOwest -possible power consumption in· totally
CMOS systems without any cOmpromise in performance.
• Completely reconfigurable by the user in the final system
'I
• High performance Ordering Information
• 20M Hz flip-flop toggle rate (-20 speed grade) M2064'- 20 C NL
• 33MHz flip-flop toggle rate (-33 speed grade)
• 50MHz flip-flop toggle rate (-50 speed grade)
PART
NUMBER
=r ..'
L e..,,,,m.
,~L:~: ~:~ ~~~ru;.~r~IP Carrier
SPEED GRADE _ N = 48 Pin Molded Dip
• User-configurable logic functions, interconnect and I/O for - 20 = 20MHz toggle rate
-33 ... 33MHz toggle rate TEMPERATURE RANGE
maximum flexibility - 50 = 50MHz toggl~ C = Commercial
• 64 user-Configurable Logic Blocks (CLBs) providing usable
gate equivalency of upto 1500 gates
PART NUMBER DESCRIPTION
• 58 individually-configurable I/O pins allowing any mix of
inputs, outputs or bidirectional signals (68-pin package) LCA-MDS21 XACT Development System
• User-selectable TTL or HCMOS input threshold levels LCA,MDS22 P-SILOS Simulation Package
• Multiple configuration modes for greatest flexibility and ease
LCA-MDS24 LCA In-Circuit Emulator
of use
• Verification feature allows user to check configuration data LCA-MDS25 In-Circuit Emulator Pod
• User-selectable security feature prevents read-back of LCA-MEK01 XACT Evaluation Kit
configuration data
• Read-back of internal register states for system del:)ug 0
vo
General Description
The M2064 is the first member of a family of configOrable
Logic Cell Arrays (LCAs) availabla from Monolithic Memori.es. vo
These general purpose CMOS integrated circuit devices allow
the user to rapidly implement complex digital logic functions
directly without the requirement for masking or other.vend.or
vo
performed programming steps. Unique configuration circuitry
allows complete reconfiguration within a user's. final system to
'10
allow system changes "on-tlw-fly." liD
Mono/ithicm1!n
Memories ·uurw
TWX, 910'338-2376
21.75 Mission College Blvd. Santa Clara, CA 95054-1592 Tel, (408)970-9700 TWX, 910-338.-2374
5-4
Logic Cell ArrayTM M2084
PinDescriptlbn -RCLK-IIO
1/0 Dual function output and 110. General purpose user-configura-
ble 110 pin during normal operation. During master mode
User-col)figur~lell)putlOutPlJt pins. configuration, a low level outputon-RClKindicates that the
-PWRDN ' " ..'
external memory device is 'beilig accesSed.
Input,forCEilsdeviceinto low. power (node; operaticm is sus- Do-DIN-I/O
pended,
Multi-functien input and 110. General purpose user-configUra-
~o--RT ' ble 110 pin during" normal" operation.. During master mode
Dual function input. During initial Power up; the state of MO configuration, this pin is bit l) of the8-bit parallel input data
and M 1 determines the configuration mode: After' corifigura~ bus.(Do). buring slave mode or peripheral mode'configuraticin,
tion'i.arising'. edgeon~T'il:ritia~es a. configuration read this. pin is the sEirial inpUt data pin (DIN). " ,
opera~n;
M1-"'flI) , '.,
Dt-~S-I/O .. " .,' ., '.
Multi-~l'I.ction input
aridllp. GenE!r!llp~.rpose u$er-configura-
DualfunCfloniriput/outPuLDurlrlg'lnitial power up; thEistate of ble I/O' pinauring norm.al .. oper~,jon, b~ring m~ster mode,
M1!1hd,t.1l) detEirmihe~ fh~ configuration mode. After boilfigu- configuration,this' pin is 'bft' 1 of'lha 8~bit parallel inplit data
ratjoil"jS'eolnpjete, ~p outputs,;eoofigtJr~tiOn data during ~ bus (D1). During peripheral mode configOration,'a lowriivel"on
c6nfigur'atidri' teadback operation'syrlC:ihrohously With' die "WS indicates that. a, wrlte.'Operatiomjs >being perkinned, by
toggling:'of the GCLK Inpljt. " ' the controlling processor;·,See note; .
-i!t~ET< ' D2~1I0. .'. . , '.
I~put. low level on this input after' configurafi~ncauses'~i1
A • MtiJtltfunction"iiiptit and I/O;'General purpose'user-eonfig&a-
regi:;ter elements internal to the LCA to be forced toO . .!f b1e.ii'Opin during normal. opei'il.tlori',1)uri'ng h18$termode
asserted prior to the start of configuration, causes the LCA to corifiguration;''ttiisPin is. bit 2 ofthe .$~bit' parallel input data
remain in the initialization+$te (configuration is not startEKt). If bus'(D2); pUring p$riJ)hefal mode' cORfiguratiori,a high 'level
asserted duringconfigurlllion t~e LCA returns to the initializa- on os .indicates that a writeoper'ati,0n is being pertormetiby
tion state. ' thEi tcintrollihg prQCEisSor:See note,' , ' ,
DONE-"-9G D3,.~£,o.:,,() ".. ,. ",i'
Dual function~()utputlinputDuring configurationthe,LCA pulls M~ti"funp#OIl irip\;Jt' aQcl119.'Gelleralpurpose user:collfigura~
DONE low and releases it when cORfig\lration,lsicompIElte til~ 1)0 pill dUring'normal'operatibn.;OUripg .master mode
(output isopElodrain). After configlJration iscompletEl. a falling' configurlltion" this. pih is bit 30t the 8-bit. parallel input data.
edge on ~G inltiatilSs,nLCA programming cycle (if enabled bus (OS). During peripheral mode configuration, a low level on
in thEt currerit configuration). This pin has an i!iternaluser" ...q:O ir:idic,8tes'thala writEl'op!lratiOn is being performed bY
enabled pull~uP'Tesi~tor. ' .' thecontrollirig proce~r,,~e note~
XTAL1.l/0 D4--CE1~lio, ' " , : ' " ,
Dualfuo9tiOil input~ndI/O; Tllis pin maybe configured liy the Multi·fun9ti~~iinput lind Ilo,Gell~raIPurposa usar-configura-
user"to bEl a Rorm!llJ/O pi.n;~quivalent te anyof.the general ble .\lOPil'l&udr1g ,)normal' ope~tlon. , During, master" mode
purpose,1/0 pins. Alterrtamly; this pin and XTAL2 my be
used to connect a crystal for use with the internal crystal
confiQIJration, this :pin is bit 4 Of th~ §-~itparaIJel;inpUt data
bus (04). OUringper:iphEiralmodeconfigur&tion,a lowlevel on
oscillator cpQfig~ration. . -CE1 indicates "that a writeoP"r4tion is being: performed Qy
~AL2-1I0 ., the contr.olling prqceSsor.· S!,!Ern.ofEi~ .1'
Dualfunptionoutput a~d VO. Tois pin may QeCOnfrgured by ,0.5-1/0, to D7.,.I/Q;\; ''i
the user to be a normal tlOpin eqllivale\1~!w,aoy Itf~tle Input and IIQ;G~ner§l pUtpe~. USE!I~on'.igu(!lb.le 110 pins
gemttal.purP()S8<\lQ pins: .A!~r:oativEtly, this pirjuldXT'Al.1 during normal op!ltation., Ouri~ .master. mode., configuration,
may'!~cu~to.,CQr\necl:apl'ys~lfo~ witll, uSe. ,he imQr,oa,t these pins are bit~,5through 7~f the ~bit.P8rajjelinput da.~
cryElta( ~ciIJatQt~nfiQuiaiiqj1:: . ", . . ,.,.. ,., .. '., .. bus (05-07). . " '.
~~,!',,~;~." '-<~,:":: ':<~;' <~>«,' '~'~,~~l~'
1\. "} '>"t> Ao-II0 .to. A15-liO
'QQnfigIJratiOJl,'.~·. depjendent!inpllt/Q\ltpIltCClKt .is . the .Output and 1/0; General purpose usef-qonfigurablElIIO pins
Ji\1a$ler QbrifiQ,ui'atiiln clockusetHo.•cotlfigur(i ,the, lCA; Insl~ during i'lorrual.ope~~on, DUrin9,: master. '.~.. ponfiguration
tnodeit is 81'\ input; In.-all oth~;mCldesit.isan OlItput designeQ these .pins are.:addressoutpU\ pins (Ab-A15) 'u!ied to address·
to:providetl,leinp\jt, c1~9gof,,;ltdditionaLsiave molledaisy the external storage elemen~,used.forconfigutation data.•
e;hain COllIi1~ .. :le~,dEll/ices:Al)Ilrir1g, a donfiguratiQnTEi~d ~otEt: .~!?~rtRrl!laperip~ei'at.~ode w,rite, :t~,!fOIl9wi~gI99icaf
~k operatiOIi'l.~LK.seJ:iteSaJLthe<;lock Input ,uSEid ,.to read
tbe;iitte~nalconjiUUration:.Csata:~',;<" ",(
eoml,)iitationis .n~"Elssal:Y:-WS.~;CE9·.cE'} ," '.' +, .r:
t:urictt~810is~riPtion" . i'., . ~,. ."
ooU,-r~I/O ...... .,ii ..,"'."
line Mt064il! ,.a. bigh1>ertOrn:lance CMqSLogiCJCeIi·'Ai'tllY
f)uel (uftCtion·~~tput ariql/O;; S~ralpurp0$6.~ser:configUra-:
•Provic\iOg" superiOl'systerrLperi0rmanceWith grelllast user,
bl&, IIPPil1 ~!fl,/iinQ'riorrn8! :o~ratio~,Durfng configuratiOrSthe
flexibility ",~rnpreteuSel:;;COllfigur8bUitY provtdes .an ;optimized
'serialdata sl(ea,mElupplied from the first LCAto .LC~ .(fown~ solution Ie logie. implementatiOn ,J)roblems. ;.;
thit'5erfal ttatlYthaih'is Qtitji,4t i>f\.OOUT. ;..' .
Tha'M2064 utltizes.a ),iniqueConfigurabte;L;ogiC Block.{CLB)
structlK8.:as'j1hEl,basic· f.unctionalbuilding 'black 'of ,the ,device;
Ea(lh ~;il!a combination,o#;./I pr()gl'l!lT)irl8ble .1O{jiC.funotiOn
and a storage element. The CLB has the capability of perform- either the A input to the CLB or from the F output of the
ing any function of its inputs with the option of the output of combinational logic module.
the storage element included in the input field. User-defined Clock for the storage element may be individually enabled or
logic is implemented in.a matrix of sixty-four CLBs which are disabled and can be driven by the clock input, K, to the CLB,
interconnected with user-configurable interconnect r\lsources. the C input to the CLB, or the G output of the combinational
Fifty-eight independently configurable I/O Blocks; each of logic module. Final outputs, X and Y, from the CLB can be
which can be a direct or latched input, a dir~ct or open drain selected to be either of the two outputs, F and G, of the
output, or a bidirectional I/O buffer; provide the interface to combinational logic module, or the a output from the storage
external circuits. Input voltage levels are user definable and element.
may be either standard n.L or CMOS for all I/O Blocks, 1/0 Elements
depending on the user's configuration choice. The M2064 contains fifty-eight user-configurable I/O -blocks
lJser-definable path selector or multiplexers are utilized to for connection to external circuits. Each block is a general
select configuration,options for the CLBs and I/O Blocks. purpose device containing a three-state output buffer, an input
These selectors are set in the desired state by the configura- buffer, and an input flip-flop as shown in Figure 2. The input
tion data loaded into the device upon power up. buffer always reflects the status of the I/O pin or the contents
Logic of the input flip-flop. If the flip-flop is selected, data present on
the I/O pin will be clocked to the input buffer by the I/O block
User logic is implemented in one or more CLBs which are
clock signal. All I/O blocks on a particular edge of the device
general purpose 4-input, 2-output elements. Figure 1 shows a
share it common I/O clock Signal. The output buffer may be
block diagram of a single CLB. Each element is composed of
enabled, disabled, or under the control of the three-state
a 4-input cOmbinational logic module with two outputs, a
connection. .
general purpose storage element, and routing selection logic.
The module can generate any combinational logic function of
the four inputs, or it can generate any two independent
functions of any three of the four inputs. If a function of four t - - - - - - TS
inputs is selected, that same fUnction will be .available on both
of the outputs of the combinational module. The inputs to the
combinational module are three of the four inputs to the CLB
(A, Band C) and either the 0 input to the CLB, or thea output r-<J---------O
of the storage element.
A----+_!
8-----1
x
y
D = USER DEFINABLE
PATH SEL£ClOR
-V.,..O-a.
....OCK-- •• ,.
COMB. ~~---4~~~
c---~-l LOGIC
D
Figure 2. Block Diagram of an 110 Element
K
Interconnect
5·6 MonoIlthlcmMemorieS
Logic Cell ArrayTM M2064
from the 1/0 blocks or ClBs. In addition to the programmable the alternate clock buffer can drive long lines in any column of
connections to adjacent interconnect resources, there are ClBs as well as local interconnect.
direct connection paths which do not utilize the general
interconnect resources. These paths allow selected connec-
LOGIC CEll
tion between some 1/0 blocks and ClBs and between adja- ARRAY
cent ClBs. For example, the outputs of a ClB in the interior of
the matrix of ClBs may be connected to adjacent ClBs =----,
XTAL2I-46
without using any interconnect resources. XTALI
43
Rl
I GLOBAL CLOCK BUFFER
~ L~ m eJm !!:1m eJeD!!!l!!llf.!"l
LJ U Ll LJ Ll LI Ll Ll
o LJ LI LJ LJ
LJ U o L} o (j LJ LJ Suggested component values:
R1 1- 4MQ
Ll Ll Ll o LJ Ll Ll R2 0 -1Kn
(may be required for low frequency, phase shift
andlor compensate level for crystal Q)
L1 U o LJ o (j U LJ C1, C2 5 - 20pF
Y1 1 - 10MHz AT cut
CJ Ll o [j o [} LJ CJ Figure 4. Crystal Oscillator
y
U
u
o
()
LJ
LJ ¥
o
f!lm!!!ll!!lf!!
LI LJ LJ
I!!Im
Ll Ll ()
em
ALTERNATE CLOCK
fl!l~l' ~
Each ClB has a special clock input (K) which can be selected
as the clock input of the storage element. Clock inputs to user
selected ClBs can be configured to be driven from either the
Global Clock Buffer, the oscillatorIbuffer or from other local
interconnect. Clocks to the 1/0 blocks can be configured from
either of the clock buffers or the local interconnect.
ClBa BUFFER
10lIo CRYSTAL OSClllAlOR
Programming
CIRCUIT Configuration of the device may be performed in anyone of
three modes. The desired configuration mode is set by the
state of the mode pins MO andM1 at power up (see Table 1).
Figure 3. Overview Functional Layout of the M2064 All configuration data relating to ClB function definition,
interconnect resource utilization, and 1/0 block programming
must be loaded into the device prior to use. In the peripheral
and slave modes the data is supplied in a serial stream in
Clock Generation and Buffering conjunction with the configuration clock Signal, CClK. In
The M2064 contains two special purpose clock buffers lor master· mode, the device automatically loads data from an
generating and driving clock signals to multiple ClBs or I/O external memory device by supplying addresses and reading
blocks with negligible skew. The Global Clock Buffer, is bytes of data. In all modes the data patterns required to
dedicated to driving a matrix of long lines which have con/igur- create a specific configuration are the same.
able connections to the K input of each ClB register. This
clock buffer may be driven from an internally generated
register source, or configured with a connection directly to an MODE SELECT PINS MO M1
1/0 block for driving it with an external· clock signal. The
Master lOW mode 0 0
output from the Global Clock Buffer may be configured to
directly drive an I/O block for driving clock Signals off the Master HIGH mode 0 1
device.
Peripheral mode 1 0
The alternate clock buffer can be configured either as a
simple buffer or as a buffer for the crystal oscillator. In the Slave mode 1 1
crystal oscillator mode, an externally connected crystal and Note: During configuration, Pin 27 on the 68-pin package or
optional passive components form a clock generator for use Pin 7 on the 48-pin package must be held HIGH.
on the chip or for driving other external circuits (see Figure 4).
When configured in the buffer mode, the alternate clock buffer Table 1. Modes
can have either one or both of its input and output configured
to directly drive, or be driven by, an 1/0 block. The output of
Dala patterns for a specific user-configuration are created with out, the-AD pin will return to its .inactivestate. The .configura-
the Monolithic Memories XACT LCA Development System and tion data maybe read.·at any· time with no effect on the
can be output to a standard EPROM programmer or saved on operation of the device. Once a configuration read-back has
disk for inclusion with other software. Users who are using the been initiated. all data must be read out of the device to insure
Monolithic Memories XACT debugging system can directly that subsequent read-back operations will begin at the start of
access the configuration data and load the device directly the configuration data.
during a debug session. Because of ·Ihe complexity of the data Master Reset
patterns and difficulty in generating. therh without a thorough After device configuration, the -AESETpin becomes a mas-
knowledge of the device, users are discouraged from attempt- ter reset for all CLB and lOB storage elements inJhe d.evice.
ing to generate data patterns on their own. Data pattern files Asserting this control signal. will asynchronously reSet . all of
for M2064 devices contain 1536 by1es. the internal storage registers regardless of the operating
Special Features condition of the circuit.
The M2064 contains several special features which enhance Development System
its capacity tor use in a wide variety of applications. Among The Monolithic Memories Design System is an integrated
these are the following: package of design tools for developing configuration data for
Data Security LCAs. All aspects of configuration are specified through inter-
The M2064 configuration data contains special controls bits active graphics software. Facilities to verify functionality and
which enable or disable configuration data security control. If timing of the designed configuration insure that designs oper-
enabled, the security control will prevent the read-back of ate as desired.
configuration data after the initial configuration. There are two XACT is a graphic deSign system used to specify LCA
possible modes of operation under security control. One mode designs. It contains several standard and several optional
allows a single read-back after configuration to allow verifica- software and hardware packages. The basic. package runs on
tion of the data. In the second mode, all access to the an IBM PC/XT or AT compatible computer with 640K memory,
configuration data is prevented. a color monitor and a mouse. The tools accessible from the
Reprogrammablllty executive, including the optional packages, are:
Configuration data changes are controlled by reprogramming • LCA Editor and Macros
control bits in the configuration data supplied to the device. If • Timing Analyzer
reprogramming is enabled, the user may supply new configu- • Simulator (P-Silos, optional)
ration data at any time by asserting. the correct control
sequence on the DONE--PGandMO and M1 mode control • Configuration-File Generator
pins. Alternatively, the user may elect to prevent reconfigura- • Configuration, File .Formatter
tion of the device. When operating in this mode, the only • XACTOR 2 In-circuil-emulator (optional).
method to remove the configuration is to remove all power XACTOR 2 consists of a software program plus a hardware
from the device. attachment that allows control of up to four LCAs. The
Inactive Power-down program contains commands lor:
In a system which is to remain in its current <;:onfiguration • Loading configuration data
through power . loss, the M2064 may be forced into a· .Iow • Activating the Master Reset input
power inactive state by using the -PWRDN pin. When held • Reconfiguring
low, the LCA will retain .all configuration data but will not
• Single stepping the device clock
operate. All clocks will be stopped and all outputs put into a
high-impedance state. Power is reduced to a very low level, • Reading back configuration data and state of all 122
allowing a simple external battery arrangement to supply the internal registers on .any clock cycle.
required configuration data saVing power (see electrical char- • Real time system debug.
acteristics). An evaluation kit is available which includes:
Configuration. Data Read-back • Complete documentation of the Development System
A mechanism is provided in the M2064 to provide verification • Asall)ple LCA design
of .stored. configuration data. The configuration read-back is • XACT software package.
initiated by toggling the "'AT pin and clocking the C<;:LK pin. Contact your local. Monolithic Memories Representative or
Each clock applied to CCLK will read out a configuration data Distributor founore information.
bit on the -AD pin. When all configuration data has bee.nread
Operating Conditions
SYMBOL PARAMETER MIN TYP MAX UNIT
VOH High level output voltage Vee = 4.75V IOH = -4,OmA 3.86 V
Val Low level output voltage Vee = 4.75V IOl = 4.0mA 0.32 V
CMOS
Quiescent Vee =5.0V 5 mA
inputs ,
Power on Timing VCC must rise from 2.0V to minimum specification level in
The M2064 contains on-chip reset timing logic for power-up 10ms or less. For other modes, initiatioh of configuration must
operation. To insure Proper master mode system operation, be delayed for 60ms after VCC reaches the minimum speci-
fied level.
OUT
(LOGIC ONLY)
OUT
(THROUGH LA1CIt)
INPUT (LOGIC)
1.b-.~;3-0kO-.
ASFFCLOCK
• ~IO·
OUT
(FROMFF)
--------------~~
(SETIR~ /
--"'10--+1_1
1+1--.
INSETIRESET)
(LOGIC TO - - fI ~
OUT 1foo· - - - - - -...LO----~ ,.__....,...-
(FROM8.E.)
~---------------
CLOCk
(AH'I SOLIRCE) .
5-11
Logic Cen ArrayTM M2064
PAD
THREE-STATE
iplD-H I
I
(DI:~____ (.;".-~-tl-P-I-""'\.- I
I
I
IPL \.w=1 I
I
L~
I
I
I
f.-tu-l I
I
INPUT ; - I
(LATCHED)
_----J
toP-+-!
I
I \'-----
~"'I~
OUTPUT __________________ -J~~________________________
MASTER
RESET
\1-_---
Notes: 1. Output (0) refers to the output connection on the lOB
2. Input (I) refers to the input connection on the lOB
3. Three-state (T) refers to the three-state control on the lOB
4. Pad or Pin (P) relers to the device pin connected to the lOB
5. Latch (l) refers to the input Flip-Flop clock connection
CCLK
Iocc
/
I- -I- -I
r-'cCH-1
'ceo
\ r
I--'ccL -I
-cEO(1)
DIN'IIIl~IIIII7I'JI- ~
VALID
/ \
-~~ -ws \~.-J/ \
CL_.-J/ \ /
CCLK(2) ... ~'------J/ L
DIN
~ VAUD
·po-D7
5-15
LogicCeUArrayTM M20:64
tMR
Mode control setup to Master
Reset
60 60 100 -- " ns '
'-t''uRwj
fCl Clock buffer input frequency' ,50 33 20 MHz
VCCVALID I--'VMR~ ,
:)_~d""'---
DONE/-PO ~ , /
!--'POW
CLOCKS
Test Conditions: The USE!!' inputs da~ via ,a graP~i~:oriellteq physiQ!l1 editing
Outputs loaded with rated DC current and 5~~,,~ capaci~a".ce environment. User functions are translated into CLB logic
to GND specifications and ,interconnections automatically. Standard
logic libraries, and,: other macro capabilities can be utilized for
Design Aids " rapiddijs1gn entry.
XACTTM provides complete,' design automation for users to '. ptiy~i;';(placement and hard connections are performed with
specify and implement designs utilizing Monolithic MePl'orieS" " the graphics placement and connection capabilities. Final
LCA products; Configuration of CLBs, internal routing, VO device' layout ,and rot,rting are visible and can be modified
block definitions and global routing are all 'handled in an without dil\tl,Irbing the logiCal arrangement. Logical connectivi-
integrated. easy-to-use system. ty and physical layout rules, checking are performed automati-
Placement and routing of' logic and I/O bloCkS is accom- cally.
, pUshed using interactive graphics. Final, programming bit pat- Full timing artalysis and functional simulation of user configu-
terns are automatically produced for debugging, transfer to rations allows device' performance and functional checking
other systems,' or downloading to standard,EPROM program-
without eldemal test hardware. In addition, point-to-point path
mers. Debugging with the XACTOR 2TM emulation liysten( timing calculatiort CipabilitY is provided to simplify gerteral
allows full device emulation and operation analysis in the 'timihg analysis aoo critical path determination.,
target system.
Logic Cell ArrayTM M2064
PART
VENDOR DESCRIPTION
NUMBER
g gg
@@®@®®®®@
DoNIH'G ~AUET @@@@@@@@@)@@ 110 ""'AT
I/O XTAL1-1IO @ ® ® @ 110' "'/tID
®®®®®®@@@
M2064
LOGIC CEll ARRAY
(48 PIN DIP)
il~!~~~il
~1~I~il~1
~ g g
e! sg g g g g 5g g g g g g g g
>.-
DONE--N M1· RO
.....,-1/0 110
VII
VII
VII
110
110
vee
VII
vo
_ON
5-1& MonoIlthlcW"nlOries
PALASM® 2 Software
TWX: 910-338-2376
Monolithic r!1!n
2175 Mission College Blvd. Santa Clara, CA 95054-1592 Tel: (408) 970-9700 TWX: 910-338-2374 Memories InJrW
6-2
PALASM 2 Software
Software Files
Following is a summary of all currently available programs. 1. .PDS User PALASM 2 PLD design
1. PDSCNVT PALASM 1 to PALASM 2 syntax conversion description
2. PALASM 2 PALASM 2 syntax parser 2. PALASM 2 .TRE PLO intermediate design
3. XPLOT PALASM 2 fuse map and JEDEC output description
4. SIM PALASM 2 simulator 3. .PDF PLD architecture description data
5.ZHAL ZHAL device fit 4. .XPT Contains PLD fuse map data
5. .JED Contains PLD fuse JEDEC data
Supplementary Software
6. .HST Contains full simulation history
1. MENU Simplified PALASM 2 user interface data
2. PC2 Programmer interface program 7. .TRF Contains user simulation trace
3. VTRACE Graph display simulator trace output data
8. .JDC Contains both PLD fuse JEDEC
data and JEDEC test vectors
<filename>. PAL
PALASM1 input design file
<filename>.POS
PALASM2 Input design file
PALASM2. TRE
<filenarne>.XPT <filename>.H5T
<filen.ame>.JEO <filename>. TRF
<filename>.JOC
Mono/ilhicWMemor;es 6-3
PALASM 2 Software
PDSCNVT ZHAL
PDSCNVT allows you to interactively convert PAL "device ZHAL makes sure that a PAL device description will fit into the
design specifications from the PALASM 1 format to PALASM ZHAL device architecture. ZHAL reads the description that
2 software. Input is a PALASM 1 formatted specification file, has been preprocessed by the PALASM 2 software program,
and output is the equivalent design in PALASM 2· software and a YES or NO answer is output. If the design fits, you must
syntax. send the PAL device De~ign Specification to Monolithic. Mem-
PALASM 2 ories for mask processing. Before a description is rejected, the
prograrn will attempt to minimize the input equations to make
PALASM 2 is the fitst program you will use in the PALASM 2
use of some sharing features in the ZHAL architecture. ZHAL
software suite. It reads and validates your input - a PAL
will also indicate what the error is before a no fit answer is
device design specification - for correct design syntax. If an
output.
error is detected, the program attempts to indicate where in
the input description the error has occurred. Recovery is
attempted after each error in order to catch as many errors as NOTE
possible on a single run. Only if no error is detected is an ZHAL currently accepts designs only for valid Monolithic
intermediate specification file generated. This file contains the Memories PAL devices.
input specification in a hierarchically structured form to enable
easy processing by follow-on programs. Further, it is guaran-
teed to be syntactically correct. This program recognizes input
MENU
deSCriptions for all current PAL devices. MENU is an interactive program designed to simplify user
interface to PALASM 2 software. MENU's multiple choice
XPLOT selection process offers you a number of options at each
XPLOT validates the architectural design of an input PAL stage. Once you have made a selection, your choice is
device description and produces fuse maps and JEDEC data automatically executed. MENU makes the modular design of
for a specified PAL device. Input is a set of Boolean equations the PALASM 2 software system invisible to you. All you need
that has been preprocessed by the PALASM 2 program. to know is what you want to do, not how-to. For example, if
XPLOT checks the equations for consistency among them- you select Simulation, the programs PALASM 2, XPLOT and
selves and with the specified PAL device. When an error is SIM automatically run in sequence, and your need to under-
detected, XPLOT attempts immediate recovery. In this way, stand the functions of the individual programs is greatly
XPLOT spots as many errors as possible on each run. Only if reduced.
no errors are detected will the output fuse maps and JEDEC
data be generated. The architectural information for each PAL
PC2
device is read in from a file containing a profile description for PC2 enables communication .between PLD programmers and
the specific PAL device. IBMTM PC machines (-PC, -XT, -AT, etc.). It is a menu-driven
multiple-choice program that guides you through various op-
tions for programming and checking PLD devices.
NOTE
XPLOT will check only valid Monolithic Memories PAL de-
VTRACE
vices. VTRACE reads the trace output of the PALASM 2 software
simulator. The text-formatted data of the trace file is converted
into graphic form. VTRACE output looks very much like timing
SIM diagrams of the simulation results.
SIM checks the functionality of a PAL device design. You will Software Customization
run this program after XPLOT. If the design is architecturally
For software development and user customization of PALASM
correct, however, you can run SIM directly after PALASM 2.
2 software, you will need a Pascal compiler/linker and a
SIM reads a special simulation syntax that has been prepro-
second disk drive. These are necessary to create .the execut-
cessed by PALASM 2. It will simulate thE! operation of thePAL
able version of the program. Monolithic Memories recom-
device you specify, calculating the output values based on
mends the Professional Pascal compiler (Microtek Inc.) which
input signals through the Boolean equations and any feed-
was used to develop and test the programs on the IBM-PC.
back. Output is a history file that traces the values of every pin
PALASM 2 software is written in nearly ISO Standard Pascal
through a simulation sequence. A trace file, which is. a subset
. to ease porting to many computer systems.
of the history file, traces only the pins you specify in the
simulation syntax. If XPLOT has been run. and a JEDEC fuse CAUTION
address file has been created, then SIM will add test vectors Porting PALASM 2 software to other computer sys-
to the JEDEC file that duplicate the simulation sequence when tems will require you to Install and modify the origi-
the device is tested on a programrner. All JEDEC checksums. nal. source code. Allow at least two to four weeks of
are recalculated. software engineering time to complete this task.
Monolithic Memories makes no guarantee of the
NOTE portability of PALASM 2 software, and does not
provide support for such efforts or other user modi-
SIM will test only valid Monolithic Memories PAL devices.
fication.
Table of Contents
lOCI DO Dl D2 D3 D4 D5 D6 D7 DS D9 GND
IOC2 Y9 YS Y7 Y6 Y5 Y4 Y3 Y2 Yl YO VCC
EQUATIONS
; DESCRIPTION
; THE 10-BIT OPEN COLLECTOR BUFFER WILL OUTPUT THE INPUT DATA (D). THE
;OUTPUTS (Y) WILL BE EITHER L OR HI-Z.
;CERTAIN OUTPUTS WILL BE HIGH-Z (Y=Z) IF EITHER OUTPUT CONTROL LINE
;IS HIGH (jOC=H) REGARDLESS OF OTHER INPUTS. NOTE THAT OC2 CONTROLS
;OUTPUTS Y9-Y5 AND OCl CONTROLS OUTPUTS Y4-YO. OC2 AND OCl CONTROL
; INDEPENDENTLY.
;OPERATIONS TABLE:
jOC2 JOCl D9-DO Y9-Y5 Y4-YO OPERATION
-----------------------------------------------------------
H X x Z x
HI-Z FOR UPPER 5 BITS
X H X X Z HI-Z FOR LOWER 5 BITS
L L D D D OUTPUT TRUE (L or HI-Z)
/OC1 00 01 02 03 04 OS 06 07 OS 09 GNO
/OC2 Y9 YS Y7 Y6 YS Y4 Y3 Y2 Y1 YO VCC
EQUATIONS
MonoI,"thic W Memories
10..Bit Open: Collector Inverting Buffer
; DESCRIPTION
;OPERATIONS TABLE:
Monolithic WMemories
10-Bit Addressable Register
i -----OUTPUTS-------
iCONTROL -----FUNCTIONS---- ---INPUTS-- Q Q Q Q Q Q Q Q Q Q
i/OC CLK /CLR /PR /E3 E2 E1 D C B A DIN 987 654 3 2 1 0 COMMENTS
j-------------------------------------------------------------------------------
L C L L X X X X X X X X L L L L L LL L L L /CLR OVRRD /PR
L C H L X X X X X X X X HHHHHHHHHH /PR OVRRD ENABLE
L C H H L H H L L L L L H H H H H H H H H L LOAD QO WITH DIN
L C H H L H H L L L H L H H H H H H H H L L LOAD Q1 WITH DIN
L C H H L H H L L H L L Hg H H H H H L L L LOAD Q2 WITH DIN
L C H H L H H L L H H L HHHHHHLLLL LOAD Q3 WITH DIN
L C H H L H H L H L L L HHHHHLLLLL LOAD Q4 WITH DIN
L C H H L H H L H L H L H H H H L L L L L L LOAD Q5 WITH DIN
L C H H L H H L H H L L H H H L L L L L L L LOAD Q6 WITH DIN
L C H H L H H L H H H L H H L L LL L L L L LOADQ7 WITH DIN
L C H H L H H H L L L L H L L L L L L L L L LOAD Q8 WITH DIN
L C H H L H H H L L H L LLLLLLLLLL LOAD·Q9 WITH DIN
L C H H L H H H L L H H H L L L L L L L L L LOAD Q9 WITH DIN
L C H H L H H H L L L H H H L L L L L L L L LOAD Q8 WITH DIN
L C H H L H H L H H H H HHHLLLLLLL LOAD Q7 WITH DIN
L C H H L H H L H H L H H H H H L L L L L L LOAD Q6 WITH DIN
L C H H L H H L H L H H HHHHHLLLLL LOAD Q5 WITH DIN
L C H H L H H L H L L H HHHHHHLLLL LOAD Q4 WITH DIN
L C H H L H H L L H H H H H H H H H H L L L LOAD Q3 WITH DIN
L C H H L H H L L H L H HHHHHHHHLL LOAD Q2 WITH DIN
L C H H L H H L L L H H HHHHHHHHHL LOAD Q1 WITH DIN
L C H H L H H L L L L H HHHHHHHHHH LOAD QO WITH DIN
L C H H L L L X X X X X H H H H H H H H H H HOLD STATE
L C H H L H H L L L L L H H H H HH H H H L LOAD QO WITH DIN
L C H H L L H X X X X X HH H H HH H H H L HOLD STATE
L C H H L H H L L H L L HHHHHHHLHL LOAD Q2 WITH DIN
L C H H L H L X X X X X H H H H HH H L H L HOLD STATE
L C H H L H H L H L L L HHHHHLHLHL LOAD 04 WITH DIN
L C H H H L L X X X X X H H H H H L H L H L HOLD STATE
L C H H L H H L H H L L HHHLHLHLHL LOAD Q6 WITH DIN
L C H H H L H X X X X X HHHLHLHLHL HOLD STATE
L C H H L H H H L L L L HLHLHLHLHL LOAD Q8 WITH DIN
L C H H H H H X X X X X HLHLHLHLHL HOLD STATE
H X X X X X X X X X X X Z Z Z Z Z Z Z ZZ Z TEST HI-Z
;~---------------.--------------------------------'--- --------------------------
; DESCRIPTION
;THESE FUNCTIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
;OPERATIONS TABLE:
D C B A DIN Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Ql QO
--------------------------------------------------------
L L L L DIN Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Ql DIN
LLLH DIN Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 DIN QO
L L H L DIN Q9 Q8 Q7 Q6 Q5 Q4 Q3 DIN Ql QO
LLHH DIN Q9 Q8 Q7 Q6 Q5 Q4 DIN Q2 Ql QO
LHLL DIN Q9 Q8 Q7 Q6 Q5 DIN Q3 Q2 Ql QO
L H LH DIN Q9 Q8 Q7 Q6 DIN Q4 Q3 Q2 Ql QO
LHHL DIN Q9 Q8 Q7 DIN Q5 Q4 Q3 Q2 Ql QO
LHHH DIN Q9 Q8 DIN Q6 Q5 Q4 Q3 Q2 Ql QO
H L L L DIN Q9 DIN Q7 Q6 Q5 Q4 Q3 Q2 Ql QO
HLLH DIN DIN Q8 Q7 Q6 Q5 Q4 Q3 Q2 Ql QO
HLHL DIN Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Ql QO
H L .HH DIN Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Ql QO
H H X X DIN Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2. Ql QO
_:..._--'--':""- ..... _---------------------------------------------
CHIPMC6800~MICROPROCESSOR_INTERFACE PAL20LlO
Al5 Al4 Al3 Al2 All NC /S /R PH2 VMA /ARGND
EN IN EN /IO /RAM4 /RAM3 /RAM2 /RAMl /PROM2 /PROMl /RSET VUA VCC
EQUATIONS
IF (VCC) PROMl Al510 Al410 Al3* Al2 * VMA10 PH21o/RSET ;PROM1, FOOO-FFFF
IF (VCC) PROM2 Al510 Al410 Al31o/A12 * VMA10 PH21o/RSET ;PROM2, EOOO-EFFF
IF(VCC) RAMl = /Al51o/Al41o/A131o/Al21o/All1o VMA10 PH21o/RSET ;RAMl, 0OOO-07FF
IF (VCC) RAM2 = /A151o/Al41o/A131o/A121o All10 VMA10 PH21o/RSET ;RAM2, 0800-0FFF
IF (VCC) RAM3 = /A151o/A141o/A131o A121o/All1o VMA10 PH21o/RSET ;RAM3, lOOO-17FF
IF(VCC) RAM4 = /Al51o/A141o/A131o A1210 All10 VMA10 PH21o/RSET ;RAM4, l800-1FFF
IF(VCC) IO Al510 A141o/A131o A1210 All10 VMA10 PH21o/RSET ;I/O, D800-DFFF
IF(VCC) /EN /PROM11o/PROM21o/RAM11o/RAM21o/RAM31o/RAM41o/I01o VMA1o/RSET ;EN=/VUA
IF (VCC) /VUA ENIN ; ASSERTIVE HIGH VUA SIGNAL (INVERT EN FEEDBACK)
IF (VCC) RSET S ;SET
+ /R * RSET ;RESET
+ /AR1o RSET ;AUTO RESET
; DESCRIPTION
;THIS PAL20L10 INTERFACES BETWEEN THE MOTOROLA MC6800 MICROPROCESSOR AND ITS
;SYSTEM COMPONENTS ON A SINGLE BOARD COMPUTER. THE FUNCTIONS IT PERFORMS,
;PREVIOUSLY DONE WITH RANDOM LOGIC ARE: ADDRESS DECODING, MEMORY AND I/O
; SELECT, RESET SIGNAL GENERATION, AND CONTROL OF THE BUFFER WHICH INTERFACES
;THE DATA BUS TO OTHER BOARDS IN THE SYSTEM.
MonoiithJcIRlFJl·Memor/es 1·11
MC6800 Microprocessor Interface
;B A lCO lCl· lC2 2CO 2Cl 2C2 3CO 3Cl 3C2 4CO 4Cl 4C2 lY 2Y 3Y 4Y
SEL ------INPUTS------ --OUTPUTS-- COMMENTS
lC 2C 3C 4C
B A 012 012 012 012 lY 2Y 3Y 4Y
;--------------------------------------------------~--
L L LHH HHH HHH HHH ---
L H H H lCO=O
L L HHH LHH HHH HHH H L H H 2CO=0
L L HHH HHH LHH HHH H H L H 3CO=0
L L HHH HHH HHH LHH H H H L 4CO=0
L L HLL LLL LLL LLL H L L L lCO=l
L L LLL HLL LLL LLL L H L L 2CO=1
L L LLL LLL HLL LLL L L H L 3CO=1
L L LLL LLL LLL HLL L L L H 4CO=1
L L HHH HHH HHH HHH H H H H TOGGLE LINES
L H HLH HHH HHH HHH L H H H lCl=O
L H HHH HLH HHH HHH H L H H 2Cl=0
L H HHH HHH HLH HHH H H L H 3Cl=0
L H HHH HHH HHH HLH H H H L 4Cl=0
L H LHL LLL LLL LLL H L L L lCl=l
L H LLL LHL LLL LLL L H L L 2Cl=1
L H LLL LLL LHL LLL L L H L 3Cl=1
L H LLL LLL LLL LHL L L L H 4Cl=1
L H HHH HHH HHH HHH H H H H TOGGLE LINES
H L HHL HHH HHH HHH L H H H lC2=0
H L HHH HHL HHH HHH H L H H 2C2=0
H L HHH HHH HHL HHH H H L H 3C2=0
H L HHH HHH HHH HHL H H H L 4C2=0
H L LLH LLL LLL LLL H L L L lC2=1
H L LLL LLH LLL LLL L H L L 2C2=1
H L LLL LLL LLH LLL L L H L 3C2=1
H L LLL LLL LLL LLH L L L H 4C2=1
H L HHH HHH HHH HHH H H H H TOGGLE LINES
H H LLL LLL LLL LLL H H H H SELECT = 4
HH HHH HHH HHH HHH H H H H TOGGLE LINES
;-------------------------------------------------------
; DESCRIPTION
; THIS IS AN EXAMPLE OF A QUAD 3-TO-l MULTIPLEXER USING A PAL18L4. SELECT
;LINES A,B ARE ENCODED IN BINARY, WITH A REPRESENTING THE LSB. THE OUTPUTS
; (Y) ARE ALL HIGH IF THE SELECT LINES ARE BOTH HIGH (B,A=H).
OPERATIONS TABLE:
INPUT OUTPUTS
SELECT
B A Y
----------------
L L CO
L H Cl
H L C2
H H H
---------------- TB00510M
7-12 Mono/iihicWMemorifl.
Quad 3: 1 Multiplexer
MonoIlthicWMemories 7-t3
4·Bit Counter With Register
I I
R I C I
C C R S C C R
L L L ELL E E D--D R--R C--C C
K R D L R D P T 3 0 3 0 3 0 0 COMMENTS
;-------------------------------------------~--------- ---------------
C L X X X X X X XXXX LLLL XXXX X CLEAR REGISTER
C H L L X X X X HHHH HHHH XXXX X LOAD REGISTER HI FROM DATA
C H H X H L X X XXXX HHHH HHHH X LOAD COUNTER FROM REGISTER
C H H X H H L H XXXX HHHH HHHH H ENABLE RCO AND HOLD COUNT
C H H X H H H H XXXX HHHH LLLL L COUNT AND ROLLOVER
C H H X H H H H XXXX HHHH LLLH L INCREMENT COUNTER
C H H X H H H H XXXX HHHH LLHL L "
C H H X H H H H XXXX HHHH LLHH L "
C H H X H H H H XXXX HHHH LHLL L "
C H H X H H H H XXXX HHHH LHLH L "
C H H X H H H H XXXX HHHH LHHL L "
CHHXHHHHXXXXHHHHLHHHL "
C H H X H H H H XXXX HHHH HLLL L "
C H H X H H H H XXXXHHHH HLLH L "
C H H X H H H H XXXX HHHH HLHL L "
C H H X H H H H XXXX HHHH HLHH L "
C H H X H H H H XXXX HHHH HHLL L "
C H H X H H H H XXXX HHHH HHLH L "
C H H X H H H H XXXX HHHH HHHL L "
C H L H H H H L XXXX HHHL HHHL L LOAD REGISTER FROM COUNTER
C H H X L X X X XXXX HHHLLLLL L HOLD REGISTER, CLEAR COUNTER
i-~--------------------------------------------------- ----------------
;DESCRIP'l'ION
;THIS PAL DESIGN SPECIFICATION DESCRIBES A 4-BIT SYNCHRONOUS COUNTER WITH
;4-BIT REGISTER. DATA CAN BE LOADED TO THE COUNTER FROM THE REGISTER. IT
; CAN ALSO BE SYNCHRONOUSLY CLEARED. THE REGISTER CAN BE LOADED FROM EITHER
;THE COUNTER OR THE DATA INPUTS UNDER CONTROL OF THE SEL INPUT. THE REGISTER
;CAN ALSO BE SYNCHRONOUSLY CLEARED. THE COUNTER AND REGISTER HAVE A COMMON
;CLOCK FOR SYNCHRONOUS OPERATION.
EQUATIONS
;F
;CLK 10C ILD D8 D7 D6 D5 D4 D3 D2 D1 DO IBO Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO
DATA IN DATA OUT
; CONTROL DDDDDDDDD QQQQQQQQQ
;CLK 10C ILD 876543210 IBO 876543210 COMMENT
C L L LLLLLLLLL L LLLLLLLLL LOAD (BORROW)
C L H xxxxxxxxx H HHHHHHHHH DECREMENT
C L L LLLLLLLLH H LLLLLLLLH LOAD
C L H xxxxxxxxx L LLLLLLLLL DECREMENT (BORROW)
C L L LLLLLLLHH H LLLLLLLHH LOAD
C L H xxxxxxxxx H LLLLLLLHL DECREMENT
C L L LLLLLLHHH H LLLLLLHHH LOAD
C L H xxxxxxxxx H LLLLLLHHL DECREMENT
C L L LLLLLHHHH H LLLLLHHHH LOAD
C L H xxxxxxxxx H LLLL.LHHHL DECREMENT
C L L LLLLHHHHH H LLLLHHHHH LOAD
C L H xxxxxxxxx H LLLLHHHHL DECREMENT
C L L LLLHHHHHH H LLLHHHHHH LOAD
C L H xxxxxxxxx H LLLHHHHHL DECREMENT
C L L LUIHHHHHH H LLHHHHHHH LOAD
C L H xxxxxxxxx H LLHHHHHHL DECREMENT
C L L LHHHHHHHH H LHHHHHHHH LOAD
C L H xxxxxxxxx H LHHHHHHHL DECREMENT
C L L HHHHHHHHH H HHHHHHHHH LOAD
C L H xxxxxxxxx H HHHHHHHHL DECREMENT
C L L HHHHHHHLL H HHHHHHHLL LOAD
C L H xxxxxxxxx H HHHHHHLHH DECREMENT
L L H xxxxxxxxx H HHHHHHLHH HOLD
C L H xxxxxxxxx H HHHHHHLHL DECREMENT
C L H xxxxxxxxx H HHHHHHLLH DECREMENT
C L H xxxxxxxxx H HHHHHHLLL DECREMENT
X H X xxxxxxxxx Z ZZZZZZZZZ TEST HI-Z
i ------------------'----------------------------------~ ------------
; DESCRIPTION
;THE 9-BIT SYNCHRONOUS COUNTER HAS PARALLEL LOAD, DECREMENT, AND HOLD
; CAPABILITIES. .DATA (D8-DO) IS LOADED INTO THE OUTPUT REGISTER (Q8-QO) WHE.N THE
;LOAD INPUT IS TRUE. (jLD=L) AND A .POSITIVE EDGE PULSE .IS RECEIVED ON THE CLOCK
;PIN (CLK). THE COUNTER WILL DECREMENT IF A CLOCK PULSE IS RECEIVED WITH THE
;LOAD INPUT BEING FALSE (jLD=H). THE OPERATION IS A HOLD IF NO CLOCK PULSE IS
;RECEIVED REGARDLESS OF ANY OTHER INPUTS.
;THE BORROW OUT PIN (jBO) SHOWS HOW TO IMPLEMEN.T A BORROW OUT USING A REGISTER
;BY ANTICIPATED ONE COUNT BEFORE THE TERMINAL COUNT IF COUNTING AND THE TERMINAL
;COUNT IF LOAPING.
;OPERATIONS TABLE:
H X x x Z HI-Z
L L X x IQ HOLD
L C L D D LOAD
L C H X Q MINUS 1 DECREMENT
------------------~---------------------------
1DESCRIPTION
1THE REF~S,H~LOCKGENlilRATOR .CAN. GENERATE REFRESH CLOCK (RFCK) FOR THE DYNAMIC.
1RAM CONTROLLERS. THE PERIOD OF RFCK DEPENDS ON F3-FO WHILE THE DURATION OF
1RFCK BEING LOW DEPENDS ON M3-MO.
,0000 12 0000 o
0001
0010
: 0011"
+,
28.
60
0001
0010
0011
4
8
12
0100 16 0100 16
0101 92 0101 20*
Olla .108 0110 24
0111 124 0111 28
1000 140 1000 32
1001 1!S6 1001 36*
1010 172 1010 '40*
1011 188 1011 .44*
1100 204 1100 48
1101 220 1101 !S2*
1110 236 1110 56
1111 252 1111 60
-----------------------
1*NOT ALLOWED DUE TO BAD WAVEFORMS
; DESCRIPTION
;THE a-BIT ADDRESSABLE REGISTER LOADS THE DATA (DIN) INTO THE APPROPRIATE
;ADDRESS LINE REGISTER (Q) ON THE RISING EDGE OF THE CLOCK (CLK).
;THE INPUT ADDRESSING PINS (C,B,A) CHANNEL THE D~A (DIN) INTO ITS CORRESPONDING
;OUTPUT REGIST,ER (Q) WHEN THE ENABLE PINS (jE2,El) ARE (LOW, HIGH) RESPECTIVELY;
;ANY OTHER COMBINATION OF INPUTS FOR THE ENABLE PINS HOLDS THE PREVIOUS STATE OF
;THE REGISTERS (Q).
; CLEAR OVERRIDES PRESET, PRESET OVERRIDES LOAD EN~BLE.
; THESE FUNCTIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
; OPERATIONS TABLE:
IOC CLK ICLR IPR El IE2 C BA DIN Q7-QO OPERATION
....
--~---~- ~:---'---------;"---~- ...------:",,-------;,;,,-----.-- ----
H X. X X X X X X Z HI-Z
L C L X X X X X L CLEAR
L C H L' X X 'x X H PRESET
L C H H H L C BA D D ENABLE
L ·C H H H H X. X Q HOLD
L .C : H. H L H X X Q HOLD
L C H H L L X X Q HOLD
--------------------------------------------------------
7·23
Octal Addressable Register With Demux/Enables
/QO := /PR* El* E2*/DIN*/C*/B*/A* MODE ;LOAD /QO WITH /DIN (MODE=H)
+ /PR* El* E2* /C*/B*/A*/MODE ;LOAD /QO WITH HIGH (MODE=L)
+ /PR* El* E2*/QO * A* MODE ;/QO IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/QO * B * MODE i/QO IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/QO * C * MODE ;/QO IS EITHER PREVIOUS STATE OR LOW
+ /PR* El*/E2*/QO ;HOLD IF NOT LOADING (El=H,/E2=H)
+ /PR*/El*/E2*/QO ;HOLD IF NOT LOADING (El=L,/E2=H)
+ /PR*/El* E2*/QO iHOLD IF NOT LOADING (El=L, /E2=L)
/Ql := /PR* El* E2*/DIN*/C*/B* A* MODE ;LOAD /Ql WITH /DIN (MODE=H)
+ /PR* El* E2* /C*/B* A*/MODE ;LOAD /Ql WITH HIGH (MODE=L)
+ /PR* El* E2*/Ql * /A* MODE ;/Ql IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/Ql * B * MODE ;/Ql IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/Ql * C * MODE ;/Ql IS EITHER PREVIOUS STATE OR LOW
+ /PR* El*/E2*/Ql ;HOLD IF NOT LOADING (El=H, /E2=H)
+ /PR*/El*/E2*/Ql ;HOLD IF NOT LOADING (El=L,/E2=H)
+ /PR*/El* E2*/Ql ;HOLD IF NOT LOADING (El=L,/E2=L)
/Q2 := /PR* El* E2*/DIN*/C* B*/A* MODE ;LOAD /Q2 WITH /DIN (MODE=H)
+ /PR* El* E2* /C* B*/A*/MODE ;LOAD /Q2 WITH HIGH (MODE=L)
+ /PR* El* E2*/Q2 * A* MODE ;/Q2 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/Q2 * /B * MODE ;/Q2 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/Q2 * C * MODE ;/Q2 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El*/E2*/Q2 ;HOLD IF NOT LOADING (El=H,/E2=H)
+ /PR*/El*/E2*/Q2 ;HOLD IF NOT LOADING (El=L,/E2=H)
+ /PR*/El* E2*/Q2 ;HOLD IF NOT LOADING (El=L,/E2=L)
/Q3 := /PR* El* E2*/DIN*/C* B* A* MODE ;LOAD /Q3 WITH /DIN (MODE=H)
+ /PR* El* E2* /C* B* A*/MODE ;LOAD /Q3 WITH HIGH (MODE=L)
+ /PR* El* E2*/Q3 * /A* MODE ;/Q3 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/Q3 * /B * MODE ;/Q3 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/Q3 * C * MODE ;/Q3 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El*/E2*/Q3 ;HOLD IF NOT LOADING (El=H,/E2=H)
+ /PR*/El*/E2*/Q3 ;HOLD IF NOT LOADING (El=L,/E2=H)
+ /PR*/El* E2*/Q3 ;HOLD IF NOT LOADING (El=L,/E2=L)
/Q4 := /PR* El* E2*/DIN* C*/B*/A* MODE ;LOAD /Q4 WITH /DIN (MODE=H)
+ /PR* El* E2* C* /B* /A* /MODE ;LOAD /Q4 WITH HIGH (MODE=L)
+ /PR* El* E2*/Q4 * A* MODE ;/Q4 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/Q4 * B * MODE ;/Q4 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/Q4 */C * MODE ;/Q4 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El*/E2*/Q4 ;HOLD IF NOT LOADING (El=H,/E2=H)
+ /PR*/El*/E2*/Q4 ;HOLD IF NOT LOADING (El=L,/E2=H)
+ /PR*/El* E2*/Q4 ;HOLD IF NOT LOADING (El=L,/E2=L)
/Q5 := /PR* El* E2*/DIN* C*/B* A* MODE ;LOAD /Q5 WITH /DIN (MODE=H)
+ /PR* El* E2* C*/B* A*/MODE ;LOAD /Q5 WITH HIGH (MODE=L)
+ /PR* El* E2*/Q5 * /A* MODE ;/Q5 IS EITHER PREVIOUS STATE OR'LOW
+ /PR* El* E2*/Q5 * B * MODE ;/Q5 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/Q5 */C * MODE ;/Q5 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El*/E2*/Q5 ;HOLD IF NOT LOADING (El=H,/E2 ...H)
+ /PR*/El*/E2*/Q5 ;HOLD IF NOT LOADING (El=L,/E2=H)
+ /PR*/El* E2*/Q5 ;HOLD IF NOT LOADING (El=L,/E2=L)
/Q6 := jPR* El* E2*/DIN* c* B*/A* MODE ; LOAD /Q6 WITH /DIN (MODE=H) .
+ /PR* El* E2* c* B*/A*/MODE ;LOAD IQ6 WITH HIGH (MODE=L)
+ /PR* El* E2*/Q6 * A* MODE ;/0.6 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/06 * IB * MODE , /Q6 IS EITHER PREVIOUS STATE OR LOW
+ /PR* El* E2*/06 */C. * MODE ; /Q6 IS EITHER PREVI.OUS STATE .OR LOW
+ /PR* El*/E2*/Q6 ;HOLD IF NOT LOADING (El=H,/E2=H)
+ /PR*/El*/E2*/Q6 ;HOLD IF NOT LOADING (El=L,/E2=H)
+ /PR*/El*E2*/Q6 ;HOLD IF NOT LOADING (El=L,jE2=L)
/Q7 := /PR* El* E2*/DIN* Col! B* A* MODE ; LOAD /Q7 WITH /DIN (MODE=H)
+ /PR* El* E2* C* B* A*/MODE ,LOAD /Q1 WITH HIGH (MODE=L)
+ /PR* El* E2*/Q7 * /A* MODE ;/07 IS EITHER PREVIOUS S~ATE OR LOW
+ /PR* El* E2*/07 * /B * MODE ;/Q7 IS EITHER, PREVIoqS STATE OR LOW
+ /PR* El* E2.*/Q7 */C '" MODE ;/Q7 IS EITHERPREVIOU'S STATE OR LOW
+ Im* El*/E2*/Q'7 ;HOLD IF NOT LOADING (El=a,/E2=H)
+ IPR*/El*/E2*/07, ;HOI:D IF NOT LOADING (El=L,/E2=H)
+jPR*/El* E2*/Q7 ;HOLD IF NOT LOADING (El=L,/E2=L)
1-25.
Octal Addressable Register With Demux/Enables
;FUNCTION TABLE
;jOC CLK MODE jPR jE2 El C B A DIN Q7 Q6 Q5 Q4 Q3 Q2 Ql QO
; DESCRIPTION
;THE 8-BIT ADDRESSABLE REGISTER AND DEMULTIPLEXER PERFORMS TWO FUNCTIONS ON ONE
;MSI PACKAGE. IF MODE=O THE PART PERFORMS A 3 TO 8 DE-MULTIPLEXER FUNCTION WITH
; PRESET, LOAD, AND HOLD; IF MODE=l IT IS AN 8-BIT ADRESSABLE REGISTER WITH
; PRESET , LOAD, AND HOLD.
;WHEN THE CONTROL PINS (/E2,El) ARE (LOW,HIGH) THE UNIT IS ENABLED AND THE INPUT
;ADDRESS PINS (C,B,A) EITHER CHANNEL THE INPUT DATA (DIN) TO ITS APPROPRIATE
;OUTPUT REGISTER (Q) WITH MODE=l, OR SELECT THE ADDRESSED OUTPUT REGISTER (Q)
;WITH MODE=O. ANY OTHER COMBINATION FOR THE INPUT CONTROL PINS HOLDS THE
;PREVIOUS STATE OF THE OUTPUTS.
; PRESET OVERRIDES ENABLE.
; THESE FUNCTIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
; OPERATIONS TABLE:
/OC CLK MODE /PR /E2 El C B A DIN Q7-QO OPERATION
-------------------------------------------------------------------
H X X X X X XXX X Z HI-Z
L C X L X X X X X X H PRESET
L C L H L H C B A X MUX ADDRESSED OUTPUT=LOW
L C H H L H C B A D REG ADDRESSED OUTPUT=D
L C X H H L X X X X Q HOLD
L C X H L L X X X X Q HOLD
L C X H H H X X X X Q HOLD
-------------------------------------------------------------------
749
Octal Addressable Register With Demux/Clear
; DESCRIPTION
;THE OCTAL ADDRESSABLE REGISTER AND DEMULTIPLEXER PERFORMS ONE OF TWO MSI
;FUNCTIONS ,DEPENDING ON THE STATE OF THE MODE SELECT PIN. IF MODE=HIGH THEN THE
;PART PERFORMS THE FUNCTION OF AN ADDRESSABLE REGISTER WITH 8 OUTPUTS (Q7-QO)
;AND ONE DATA INPUT (DIN). THE REGISTERED OUTPUT IS SELECTED BY THREE INPUT
;ADDRESS PINS (A,B,C). WITH MODE=LOWCONVERTS THIS CHIP INTO AN ACTIVE LOW
;3-TO-8 DEMULTIPLEXER, WHERE THE ADDRESSED OUTPUT IS LOW AND ALL OTHER OUTPUTS
;REMAIN HIGH. CLEAR (/CLR) AND PRESET (/PR) ARE ACTIVE LOW OUTPUTS WHICH SET
;ALL OUTPUTS TO LOW OR HIGH RESPECTIVELY. WHEN ENABLE (IE) IS HIGH, THE CHIP IS
;DISABLED AND THE OUTPUTS RETAIN THEIR PREVIOUS STATES.
; CLEAR OVERRIDES PRESET AND ENABLE, PRESET OVERRIDES ENABLE.
;THESE FUNCTIONS .ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE
;OPERATIONS TABLE:
C B A DIN Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO
-----------------------------------------------
L L L DIN Q7 Q6 Q5 Q4 Q3 Q2 Q1 DIN
LLH DIN Q7 Q6 Q5 Q4 Q3 Q2 DIN QO
LHL DIN Q7 Q6' Q5 Q4 Q3 DIN Q1 QO
LHH DIN Q7 Q6 Q5 Q4 DINQ2 Q1 QO
H L L DIN Q7 Q6 Q5 DIN Q3 Q2 Q1 QO
HLH DIN 07 Q6 DIN Q4 Q3 Q2 Q1 QO
H H L DIN Q7 DIN Q5 Q4 Q3 Q2 Q1 QO
H H H DIN DIN Q6 Q5 Q4 Q3 Q2 Q1 QO
000 001 002 003 004 005 006 007 008 GNO
009 010 011 012 TRU COM NC NC NC VCC
EQUATIONS
COM 012* 011
+ 011* 010
+ 011 *009
+ 011 * 008
+ 011 * 007
+ D11 * 006
+ 011 * 005
+ 011 * 004
+ 011 * 003
+ 011 * 002
+ 011 * 001
+ 011 * 000
;FUNCTION TABLE
;012 011 010 009 008 007 006 005 004 003 002 001 000 COM TRU
I
MonoIflhic W Memories
4·Bit Counter With Terminal Count Lock
7-32
4·Bit Counter With Terminal Count Lock
Ht.-Z
..
---.7>·-
L. ex XL L CLEAR.
L .C L L X.A A LoAD'
L C L H H . X Q HOLD
L C L H. t X ,'Q PLUS 1 INCREMENT
-----------------~-----------'-------~-~~~----'-------~~-~
Memory Mapped 1/0
; DESCRIPTION
THIS PAL PROVIDES A SINGLE CHIP DECODER FOR USE IN MEMORY MAPPED I/O OPERATIONS
REQUIRING FOUR ACTIVE LOW PORT ENABLES AND FULL 16-BIT DECODE WITH TWO TWO
STROBE LINES (lRD AND /WR). EQUATION TERMS CAN BE CHANGED TO ACCOMMODATE ANY
16-BIT ADDRESS.
THE PAL WILL MONITOR THE SYSTEM MEMORY ADDRESS BUS (A15-AO) AND DECODE THE
SPECIFIED MEMORY ADDRESS WORD (lF76,lF77,lF78,lF79) TO PRODUCE A PORT ENABLE
FOR READ, WRITE, A
1·35
745508 Memory Map Interface # 1
Title SNS4/74SS08 MEMORY MAP INTERFACE WITH THE INTEL 808S (DESIGN # 1)
Pattern P708S
Revision A
Author VINCENT COLI
Company MMI SUNNYVALE, CALIFORNIA
Date OS/lS/82
eLK ADO AD1 AD2 AD3 AD4 ADS AD6 AD7 GND
IOE IE1 ALE 12 I1 IO /GO E2 E3 VCC
EQUATIONS
7·36 MonoIlthicm.emories
748508 "emory Map Interface #1
;DESCRIPTION
;THIS PAL PROVIDES THE DECODE LOGIC FOR INTERFACING THE MMI SN54/74S508, 8";BIT
;SEQUENTIAL MULTIPLIER/DIVIDER, WITH THE INTEL 8085 MICROPROCESSOR. - THE PAL16R4
;MONITORS THE LOWER 8 BIT ADDRESS/DATA BUS (ADO-AD7), THE ADDRESS LATCHENAB~
; (ALE), AND THREE OF THE UPPER 8 BIT ADDRE.SS BUS (A8-A15) WHICH IS LABP;LED
;/E1,E2,M THE 8085 IN ORDP;R TO .
;DECODE AN ACTIVE LOW CHIP-ACTIVATION SIGNAL (/GO) FOR THE 74S508. THP;
;INSTRUCTION LINES AND CHIP-ACTIVATION SIGNAL ARE REGISTERED IN ORDER TO INSURE
;THAT INSTRUCTION INPUTS WILL NOT CHANGE WHEN THE CLOCK IS LOW (CLK=L). BY
;MONITORING THE MACHINE STATUS CYCLE, THE 74SS08 CAN BE ADDRESS . MAPPED BY THE
;8085 AS IF IT WERE AN I/O DEVICE, THUS NOT USING ANY MEMORY MAP ADDRESS SPACE.
;THE MACHINE CYC~ STATUS FROM THE 8085 IS AVAILABLE ON THE FALLING EDGE OF.ALE~
;FOR THIS PARTICULAR DESIGN, THE THREE INSTRUCTION INPUTS TO THE 74S508 (IO-I2)
;ARE ASSIGNED TO THE THREE LSB BITS OFADDRES.S BUS (A8:"A10) ,WHILE THE~INING'
;ADDRESS BITS (All-A15) ARE DECODED BY' THE ,PAL TO DETERMINE IF THE 74S508IS,
; SELECTED. ALSO, ADDRESS 100 TO 107 IS RESERVED FOR THE 74S508. THE ADDRESS
;SPACE CAN BE CHANGED BY SIMPLY EDITING THE LOGIC
748508 1II....ory Map Interface #2
Title SN54/74S508 I/O DEVICE INTERFACE WITH THE INTEL 8085 (DESIGN # 2)
Pattern P7086
Revision A .
Author' VINCENT COLI
Company 10(1' SUNNYVALE, CALIFORNIA"
Date 05/15/82
CHIP ~N54/7~S508-,I/Q_DEV;tCE~INTERF~CE_WITH_THE_INTEL_8085_tDESIGN_#_2) PAL16R4
CLK A15' A14A1~ A12 All A1C)A9A8 GNP
JOE 10M ALE' 12 11' 10 IGO $1 SQ. ,VCC
EQUATIONS
GO :=. /Al1*/A12*/A13* Al4*/A15 ;MQNITOR ADDRESS BUS (All-A15)
* 'tOJt*/Sl .. SO· ; MONITOR MACHINE CYCLE STATUS (I/O WRITE)
* /A~
., ~ '" ,
.' ; MONITOR ADDRESS/DATA CONTnOL (FALLING EDGE)
110 := IA8 ;REGISTER INS~RUCTIONINPUT 10
III :- /A9 ;REGISTER INSTRUCTION INPUT 11
112 :- /A10 ; REGISTER INSTRUCTION INPUT 12
;OPERATIONS TABLE
H X X Z HI-Z
L C IO =H 15 IO INTERRUPT (HIGHEST PRIORITY INPUT)
L C Il =H 14 Il INTERRUPT
L C Il =H 13 I2 INTEAAUPT
L C Il =H 12 I3 INTERRUPT
L C Il =H 11 14 INTERRUPT
L C Il =H 10 I5 INTERRUPT
L C Il =H 9 I6 INTERRUPT
L C Il =H 8 I7 INTERRUPT
L C Il =H 7 IS INTERRUPT
L C Il =H 6 I9 INTERRUPT
L C Il =H 5 IlO INTERRUPT
L C Il =H 4 III INTERRUPT
L C Il =H 3 Il2 INTERRUPT
L C Il =H 2 Il3 INTERRUPT
L C Il =H 1 Il4 INTERRUPT
L C Il =H 0 Il5 INTERRUPT (LOWEST PRIORITY INPUT)
-------------------------------------------------------------------
MonoIlthlc·I!!DMemorles
15 Input Registered Priority Encod.er
EQUATIONS
/QO := /10* II
+ /10*/11*/12* 13
+ /10*/Il*/12*/I3*/14* 15
+ /10*/11*/12*/13*/14*/15*/16* 17
+ /10*/11*/12*/13*/14*/15*/16*/17*/18* 19
+ /10*/11*/12*/13*/14*/15*/16*/17*/18*/19*/110* III
+ /10*/11*/12*/13*/14*/15*/16*/17*/18*/19*/110*/111*/112* 113
+ /IO*/I1*/I2*/I3*/I4*/I5*/I6*/17*/18*/19*/110*/Il1*/112*/I13*/Il4
/Q1 := /10*/11* I2
+ /IO*/11*/I2* 13
+ /10*/11*/I2*/13*/I4*/15* 16
+ /10*/11*/12*/13*/14*/15*/16* 17
+ /10*/11*/12*/I3*/14*/I5*/16*/17*/18*/19* 110
+ /IO*/11*/I2*/I3*/14*/15*/I6*/17*/18*/I9*/110* III
+ /IO*/Il*/12*/I3*/14*/15*/16*/17*/18*/19*/IlO*/Ill*/Il2*/Il3* Il4 .
+ /10*/11*/I2*/I3*/I4*/15*/16*/I7*/18*/19*/110*/Ill*/112*/I13*/Il4
/Q2 := /10*/11*/12*/13* 14
+ /10*/11*/12*/13*/14* 15
+ /10*/11*/12*/13*/14*/15* 16
+ /10*/Il*/I2*/I3*/14*/15*/16* 17
+ /10*/Il*/12*/13*/14*/15*/16*/17*/18*/19*/IlO*/I11* Il2
+ /IO*/11*/I2*/13*/I4*/15*/I6*/17*/I8*/19*/II0*/111*/I12* 113
+ /10*/I1*/I2*/13*/I4*/15*/16*/17*/18*/19*/II0*/111*/112*/113* 114
+ /10*/11*/12*/I3*/14*/15*/16*/17*/I8*/19*/II0*/111*/I12*/I13*/I14
/Q3 := /to*/Il*/12*/I3*/14*/15*/I6*/17* 18
+ /10*/11*/12*/13*/14*/15*/16*/17*/18* I9
+ /10*/11*/12*/13*/14*/15*/16*/17*/18*/19* 110
+ /10*/Il*/12*/I3*/14*/15*/16*/17*/18*/I9*/I10* III
+ /IO*/11*/12*/I3*/I4*/15*/I6*/17*/18*/19*/110*/111* 112
+ /10*/11*/12*/I3*/14*/15*/16*/17*/I8*/19*/110*/Il1*/I12* 113
+ /10*/11*/I2*/13*/I4*/15*/16*/17*/18*/19*/110*/111*/112*/113* 114
+ /10*/11*/12*/13*/14*/15*/16*/17*/18*/19*/110*/111*/112*/113*/114
/FLAG = /10*/I1*/I2*/I3*/14*/I5*/16*/17*/18*/19*/II0*/111*/I12*/113*/I14
; DESCRIPTION
;OPERATIONS TABLE
MonoIithicWMemorles 7-43
',8 Input Registered Priorltv Encoder
MonoIlthlc.IRMMentorles
8 Input Registered Priority Encoder
; DESCRIPTION
;THE 8 INPUT REGISTERED PRIORITY ENCODER ACCEPTS SIXTEEN ACTIVE.-LOW INPUTS
;(IO-I7) TO LOAD THE BINARY WEIGHTED CODE OF THE PRIORITY ORDER INTO THE OUTPUT
;REGISTER (Q2-QO) ON .THE RISING EDGE OF THE CLOCK (CLK) PROVIDING THE FOUR
;ENABLE INPUTS ARE TRUE (El=H,E2=H,/E3=L,/E4=L). A PRIORITY IS ASSIGNED TO EACH
;INPUT SO THAT WHEN TWO INPUTS ARE SIMULTANEOUSLY ACTIVE, THE INPUT WITH THE
;HIGHEST PRIORITY IS LOADED INTO THE OUTPUT REGISTER. THEREFORE THE HIGHEST
;PRIORITY INPUT (IO=H) PRODUCES HHH .IN THE OUTPUT REGISTER AND THE LOWEST
;PRIORITY INPUT (I7=H) PRODUCES LLL IN THE OUTPUT REGISTER.
;THE PRIORITY INTERRUPT ENCODER REGISTERS (Q3-QO) ARE UPDATED ON THE RISING EDGE
;OF THE CLOCK (CLK) PROVIDING THE FOUR ENABLE INPUTS ARE TRUE (El=H,E2=H,/E3=L,
; /E4=L). THE PREVIOUS DATA IS HELD IN THE PRIORITY .ENCODER REGISTERS IF ANY OF
;THE ENABLE INPUTS ARE FALSE (El=L,E2=L,/E3=H,/E4=H). REGARDLESS OF CLOCK
;TRANSITIONS. NOTE THAT THE POLARITY OF THE ENABLES CAN BE CHANGED BY MERELY
;EDITING THE LOGIC EQUATIONS.
;OUTPUT Q4 SERVES AS THE INTERRUPT FLAG AND IS TRUE (Q4=L) WHEN ANY OF THE 8
;INPUTS ARE. ACTIVE (I=H) ON THE RISING EDGE OF THE CLOCK (CLK) PROVIDING THE
;FOUR ENABLE INPUTS ARE TRUE (El=H,E2=H,/E3=L,/E4=L). THE INTERRUPT FLAG IS
;FALSE (Q4=H). WHEN ALL INPUTS ARE INACT:):VE (I=L) OR WHEN ANY ONE OF THE FOUR
;ENABLE INPUTS ARE FALSE (El=L,E2=L,/E3=H,/E4=H).
; OPERATIONS TABLE
;/OC eLK El E2 /E3 jE4 I7-IO Q4 Q3-QO OPERATION
i-------------------------------------------------------------------------
H X X X X X X Z Z HI-Z
L C L X X X X H Q NOT ENABLED (El=L)
L C X L X X X H Q NOT ENABLED (E2=L)
L C X X H X X H Q NOT ENABLED (lE3=H)
L C X x X H X H Q NOT ENABLED (lE4=H)
L e H H L L L H X .NO INTERRUPT FLAG
L C H H L L IO=H L 7 IO INTERRUPT (HIGHEST PRIORITY)
L e H H L L .Il=H L 6 t l INTERRUPT
L e H H L L I1=H L 5 12 INTERRUPT
L e H H L L I1=H L 4 13 INTERRUPT
L C H H L L Il=H L 3 14 INTERRUPT
L e H H ·L L Il=H L :2 15 INTERRUPT
L C H H L L Il=H L 1 16 INTERRUPT
L C H H L L Il=H L 0 17 INTERRUPT (LOWEST PRIORITY)
,._---------------------------------------------------------------------------
. .
;CLK IOC lENA SETA ROTA MODEA SW1A SW2A SW3A SW4A IENB SETB ROTB MODEB SW1B
;SW2B SW3B SW4B
; CHIP STEPPER MOTOR A SSSS STEPPER MOTOR B SSSS
; CONTROL wwww wwww
;CLK IOC lEN SET ROT MODE 1234 lEN SET ROT MODE 1234 COMMENTS
; -------------,----,----------------------'------------ ------------------------~~
C L L H X X HLHL L H X X HLHL SET A AND B Tb STEP 1
C L L L. H H HLLL L L L H LLHL FULL STEP A CW, B CCW
C ·L L L H H HLLH L L L H LHHL FULL STEP A CW, B CCW
C L H L It H HLLH H L L H LHHL HOLD MOTOR POSITION
C L L L H H LLLH L L L H LHLL FULL STEP A CW, B CCW
C L L L H H LHLH L L L H LHLH FULL STEP A CW, B CCW
C L L L H H LHLL L L L H LLLH FULL.STEP A CW, B CCW
C L L L H H LHHL L L L H HLLH FULL STEP A CW, B CCW
C L L L H H LLHL L L L H HLLL FULL STEP A CW, B CCW
C L L L H H HLHL L L L H HLHL FULL STEP A CW, B CCW
C L H L L L HLHL H L H L HLHL HOLD MOTOR POSITION
C L L L L L LHHL L L H L HLLH HALF STEP A CCW, B CW
C L L L L L LHLH L L H L LHLH HALF STEP A CCW, B CW
C L L L L L HLLH L L H L LHHL HALF STEP A CCW, B CW
C L L L L L HLHL L L H L HLHL HALF STEP A CCW, B CW
X H X X X X ZZZZ x x x x ZZZZ TEST HI-Z
;----------------------------------------------------------------------------
; DESCRIPTION
;CLK IOC lEN SET ROT MODE SW1...,SW4 COMMENTS
i -----~--------,--,---------~~_----------------'------- ----------------,-----------
;X H x X x x Z HI-Z
;C L H X X X HOLD HOLD MOTOR POSITION
;C L L H X X 1 SET MOTOR POSITION Tb STEP 1
;C L L L H H SW PLUS 1 HALF-STEP MOTOR CLOCKWISE
;C L L L H L SW PLUS 2 FULL-STEP MOTOR CLOCKWISE
;C L L L L H SW MINUS 1 HALF-STEP MOTOR COUNTERCLOCKWISE
;C L L L L L SW MINUS 2 FULL-STEP MOTOR.COUNTERCLOCKWISE
i~--------~--------------------------~---------------- ------------------------
r600950M
G NC DO D1 D2 D3 D4 D5 D6 D7 NC GND
/OC NC Q7 Q6 Q5 Q4 Q3 Q2 Q1 QO NC VCC
EQUATIONS
Monolithic m
Memories 7-49
C'eanOctal Latch
; DESCRIPTION
;THIS PAL16L8 IMPLEMENTS AN 8-BIT LATCH FUNCTION WITH THREE-STATE. OUTPUTS. THE
;LATCH PASSES EIGHT BITS OF DATA (D7-DO) TO THE EIGHT OUTPUTS (Q7-QO) WHEN LATCH
;ENABLE IS TRUE (G=HIGH). THE DATA IS LATCHED WHEN LATCH ENABLE IS FALSE
; (G=LOW). THE OUTPUTS WILL BE DISABLED (HI-Z) WHEN OUTPUT ENABLE IS TRUE
;(jOC=TRUE) REGARDLESS OF ANY OTHER INPUTS.
;G
1- 00 01 11 10
1----1----1----1----1
O! 01 11 1! 01
!-------------------!
1! 0 1 1! 1 1 1.1
I----!----I--~-I~---I
7-50 MonoIlthlcWMemories
Shaft Encoder # 1
MonoIllhlcWMemorles 7-51
Shaft Encoder # 1
7-52 MonoilthlcWMemorles
Shaft Encoder # 1
; DESCRIPTION:
;THIS PAL16R4 IMPLEMENTS A TWO CHANNEL SHAFT ENCODER OF THE TYPE USED IN SPEED
;CONTROLLERS AND OPTICAL DEVICES.
;BOTH THE "UP" AND "DOWN" OUTPUTS OF THE PAL ARE NORMALLY HIGH.
;WHEN THE SIGNAL AT THE "PHIO" INPUT LEADS THE SIGNAL AT THE "PHI90" INPUT, THE
;"DOWN" OUTPUT ALTERNATES BETWEEN HIGH AND LOW LEVELS AT HALF THE "CLK"
;FREQUENCY RATE. ALSO, WHEN THE SIGNAL AT THE "PHIO" INPUT LAGS THE SIGNAL AT
;THE "PHI90" INPUT, THE "UP" OUTPUT ALTERNATES BETWEEN HIGH AND LOW LEVELS AT
;HALF THE "CLK" FREQUENCY RATE.
;THE SHAFT ENCODER FEATURES THE CONFIGURATION AND OUTPUT POLARITY TO DRIVE AN
;74S193 TYPE UP/DOWN COUNTER.
THIS DESIGN WITH GLITCHFREE OUTPUTS WILL BE EXTREMELY USEFUL IN ELECTRICALLY
NOISY ENVIRONMENTS. THE PINNING IS GIVEN AS A FIRST PROPOSAL AND CAN BE
CHANGED ACCORDING TO THE PC-BOARD LAYOUT.
MonoIlthicWMemor/e. 7-55
Shaft Encoder #2
C L H H L H HLLL H L
C L H H L H HLLH L L
C L H L L H LLLH H L
C L H L L H LHLH L L
C L H L H H LHHH H L
C L H L H H LHHL L L
C L H H H H .HHHL H L
C L H H H H HLHL L L
x H. X X X X zzzz Z Z TEST HI-Z
;------------~----------------------~-~--------------- ------------------------
; DESCRIPTION
;THIS PAL16R8 IMPLEMENTS A TWO CHANNEL SHAFT ENCODER OF THE TYPE USED IN SPEED
;CONTROLLERS AND OPTICAL DEVICES.
;THE "COUNT" OUTPUT OF THE PAL IS NORMALLY HIGH. DURING SHAFT ENCODING THIS
;OUTPUT ALTERNATES BETWEEN HIGH AND LOW.
;INPUT "X4" SELECTS BETWEEN HALF (X4=H) OR QUARTER (X4=L) CLK FREQUENCY OF THE
;"COUNTER" OUTPUT.
;OUTPUT "UD" DETERMINES WHETHER SIGNAL PHIO LEADS (UD=H) OR LAGS (UD=L) SIGNAL
;PHI90.
;THE SHAFT ENCODER FEATURES THE CONFIGURATION AND OUTPUT POLARITY TO DRIVE AN
;74S697 TYPE UP/DOWN COUNTER.
THIS DESIGN WITH GLITCHFREE OUTPUTS WILL BE EXTREMELY USEFUL IN ELECTRICALLY
NOISY ENVIRONMENTS. THE PINNING IS GIVEN AS A FIRST PROPOSAL AND CAN BE
CHANGED ACCORDING TO THE PC-BOARD LAYOUT.
IDOWN := Sl* S2* S3*/S4* PHIO* PHI90* X4 PHIO LEADS PHI90 - COUNT=FREQ/2
+ /Sl*/S2*/S3* S4*/PHIO*/PHI90* X4 PHIO LEADS PHI90 - COUNT=FREQ/2
:+: Sl*/S2*/S3*/S4* PHIO*/PHI90 PHIO LEADS PHI90 - COUNT=FREQ/4
IUP
+ /Sl* S2* S3* S4*/PHIO* PHI90
:= /Sl*/S2* S3*/S4*/PHIO* PHI90
PHIO
PHI90
LEADS
LEADS
PHI90
PHIO
-
-
COUNT=FREQ/4
COUNT=FREQ/4
&
+ Sl* S2*/S3* S4* PHIO*/PHI90 PHI90 LEADS PHIO - COUNT=FREQ/4
:+: Sl*/S2* S3* S4* PHIO* PHI90* X4 PHI90 LEADS PHIO - COUNT=FR.EQ/2
+ /Sl*S2*/S3*/S4*/PHIO*/PHI90* X4 PHI90 LEADS PHIO - COUNT=FREQ/2
MonoIithlcWMemories 7-59
Four-to-Sixteen Decoder
Logic Symbol
as
SIMUlATION
TOTAL FUSES BLOWNt 101
TRACE ON A9 AS 1\,7 A6 AS 11,4 11.3 AEN jCSMONOCHRMl-O
- jCSGAMEIOAO ICSCQLORAD jCSPRINTERAD /CSSFLOPPYAD
jCSRS232AD ICSNMfMKRG jCSDMAPGRG ICSPPICHIP
ICSTIMERCHIP jCSINTCCHIP ICSOMACCHIP
Logic Symbol
SETF AEN
SETF lAg 111.8 111.7 IA6 lAS jM 111.3 IAEN
SETF A5
SETF A6
SETF jA5 A7 VCC
SETF AS
SETF A4 jA6
SETF A9 All- A7 A6 AS 11.4 ;'.3- CSDMACCHIP
SETF /A3
SETF 111.5
$ETF IA4 jA6 111.7 JAS CSINTCCHIP
SETF 11.9 A8 A7 /M AS 11,4
CSTIMERCHIP
CSPPiCHiP
CSDMAPG.RG
CSNMIMKRG
CSRS232AD
CS5FlOPPYAD
CSPRINTERAD
CSGAMEIOAD
Monolithic WMemories
Octal Comparator
SIMULATION
SETF 1.7 /1.6 /1.5 /1.4 /1.3 /1.2 /1.1 /1.0 ;A7=H, B7=L
/87 /86 /85 /84 /83 /82 /81 /80
SETF /1.7 1.6 ;A6=H, B6-L
SETF
SETF
/1.6 AS
/1.5 1.4
;AS=H,
;A4=H,
B5-L
B4-L
Logic Symbol
SETF /1.4 1.3 ;A3-H, B3-L
SETF /1.3 1.2 ,A2=H, B2-L 16C1
SETF /1.2 1.1 ,A1=H, B1-L
SETF /1.1 1.0 ,AO=H, BO=L A7 vee
SETF /1.7 /1.6 /1.5 /1.4 /1.3 /1.2 /1.1 /AO ;A7-L, B7=H
B7
SETF /B7 86 ;A6=L, B6=H AO B7
SETF /B6 B5 ;A5=L, BS-L
SETF /B5 84 ;A4-L, 84=H BO B6
SETF /B4 83 ;A3-L, B3-H
SETF /83 B2 ;A2"'L, B2-H
;Al.... L, 81-H A1 A6
SETF /B2 B1
SETF /B1 BO ;AO-L, BO-H
SETF /80 ;Test all Lts B1 NE
SETF 1.7 1.6 AS 1.4 1.3 1.2 1.1 AO ;Test all H's
87 B6 85 B4 83 B2 B1 BO A2 EQ
SETF /1.7 1.6 /1.5 1.4 /1.3 1.2 /1.1 1.0 ; Test even ones
/B7 B6 /85 84 /83 82 /B1 BO B2
: Test· odd ones B5
SETF 1.7 /1.6 AS /1.4 1.3 /1.2 1.1 /1.0
B7 /B6 B5 /84 B3 /B2 B1 /BO
A3 AS
B3 B4
;Function Table' for PALASMl
GND A4
7·62 MonoilthlcWMenior/es
Three-to-Eight Demultiplexer
CLK /CLR /PR A B C /LD POL TOG 'GNo : Function Table tor PAIASMl
10C 07 06 05 04 03 02 01 00 VCC
:10C CLK JCLR IPR ILD POL TOG C B A 07 06 05 04 03 02 01 00
EQUATIONS
; Control Functions Polarity Input Output
: JOC CLK ICLR IPR jLD POL TOG CBA 07----00 Comments
100:= CLR
+ /PR. W./POL./C./S./A
:Clear 00
:oecode 000 : --------.,..---~--------
L C L L L
.. -----
H
..------------------------------
L XXX LLLLLLLL Clear
+ /PR. W. POL. A :Load true
+ /PR. LD* POL* B :Load true L C H L L H L XXX HHHHHHHH PRESET
+ IPR. Lo* POL* C ;Load true L C H H L H X LLL LLLLLLLH Load a
+ /PR*/LO*/TOG·/QO ;Hold L C H H L H X LLI! LLLLLLHL Load 1
+ /PR*/LD* TOG. QO :Togqle polarity L C H H L H X IJIL LLLLIJILL Load 2
L C H H L H X lJIH LLLLHLLL Load 3
101:- CLR ;Clear 01 L C H H L H X HLL LLLHLLLL Load 4
+ /PR* Lo./POL*/C./S. A :Decode 001 L C H H L H X HLI! LLHt.LLLL Load 5
+ /PR. LO. POL. II. ;Load true L C H H L H X HHL LHLLLLLL Load 6
+ /PR* Lo. POL. 8 ;Load tru,e L C H H L H X HHH HLLLLLLL Load 7
L C H H H X L XXX HLLLLLLL Hold 7
+ /PR* LO* POL* C ;Load true
XXX IHHHHHHH Hold
+ /PR*/LD·/TOG*/01 ;Hold L C H H H X H
+ /PR./LD* TOG* 01 ;Togqle polarity L C H H H X H XXX HLLLLLLL Hold
L C H H L L X LLL HHHHHHHL Load 0
;Clear 02 L C H H L L X LLH HHHHHHLH Load 1
102 :- CLR
IJIL HHHHHLHH Load 2
+ /PR. LO*/POL.jC. S*/A ;Decode 010 L C H H L L X
+ /PR. LO. POL. A ;Load true L C H H L L X lJIH HHHHLHHH Load 3
+ /PR. LO. POL. /8 :Load true L C H H L L X HLL HHlILHHHH Load 4
;Load true L C H H L L X HLI! HHLHHHHH Load 5
+ /PR* LO* POL* C L C H H L L X HHL HLHHHHHH Load 6
+ /PR·jLD*/TOG*/02 ;Hold Load 7
:Toggle polarlty L C H H L L X HHH LHHHHHHH
+ /PR*/LD. TOG* 02 L C H H H X L XXX LHHHHHHH Hold 7
L C H H H X H XXX HLLLLLLL Hold
103 :- CLR ;Clear Q3 LHHHHHHH Hold
;Decode 011 L C H H H X H XXX
+ /PR* LO*/POL*/C* 8* A H X X X X X X XXX ZZZZZZZZ Test HI-Z
+ IPR* _Lo* POL* jA ;Load true
; --------,-----------------------------------------------~--
+ jPR* LO* :POL* /S ;Load true
+ /PR* LD* .POL. C ;Load true
+ /PR*/LD*/TOG·/Q3 ;Hold
+ /PR*/LD* TOG. Q3 ;Toggle polarity
SIMULATION
"""'Ithlc WMemor/es
Basic Flip Flops
JKT :- J*/JKT*/CLB.
+ /X* JKT*/CLR
;JK Flio-Flop
; (3XC - IQ)
Simulation Results
+ PR :Preset Q q eqcqcqcqcgcg cqcqcg egcg-cge
JOC LLLLLLLLLL LLLLLLLLLL LLLLLLLLLL LLLLLLLLLL
JXC :- p* X */PR ; JK Fl ip- Flop PR LLLLLLLLLL LLLLLLLLLL LIJIHHLLLLL LLLLLLLLLL
+ 13*PKT*/PR ; (JX = IQ) eLR HHHHLLLLLL LLLLLLLLLL LLLLLLLLLL LHHHLLLLLL
+ K* JKT*/PR J XXXXLLLLLL HHHHHHLLLL LLLLLHHHHH HHHHHHHHHH
+ CLR ;Clear /0 K XXXXL!..LHHH HHHLLL~LH HHHHHHHHLL LLLLLl,LLLL
JKT XXXLLLLLLL LLHHHHHHHH HLLLHHHLLL HHHLLLHHHH
TT :- T*/TT*/CLR ;T Flip-Flop T XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXLLLHHH
+ IT* TT* leLR ,(TT = Q) TT XXXLLLXXXX XXXXXXXXXX XXXXHHHXXX XXXLLLLLLH
+ PR ;Preset Q o XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX
DT XXXLLLXXXX XXXXXXXXXX XXXXHHHXXX XXXLLLXXXX
TC := IT*/TT*/CLR :T Flip-Flop S XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX
+ T* TT*/PR ,(TC - IQ) R XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX
+ CLR ;Clear /0. SRT XXXLLLXXXX XXXXXXXXXX XXXXHHHXXX XXXLLLXXXX
SIMULATION
:IOC CLK 09 08 07 06 05 04 03 02 01 DO
,09 08 07 Q6 Q5 Q4 Q3 Q2 Q1 QO
EQUATIONS
;LOad 09 02 02
/09 := /D9
03 03
SIMULATION
SETF /OC
CLOCKF eLK ;Test HI-Z
; JOC eLK 09 08 07 06 D5 04 03 02 01 DO
'Q9 Q8 Q7 Q6 05 Q4 Q3 Q2 Q~ QO
QS : .. /53 */52 *
/51 * /50 * 05 No shift
07 06 05 04 03 02 01 DO /PLl IPSl GND eLKl + /83 * /52 *
/Sl * SO * 06 Shift 1 space
IOCl 00 NC 01 NC 02 NC Q3 HC Q4 HC Qs NC Q" + /53 * /52 * Sl * ISO * 01 Shift 2 spaces
Ne Q7 He jOC2 CLK2 vee IPS2 /PL2 He He Ne + /53 */S2 * Sl * SO * 08 Shift 3 spaces
Ne He 80 81 82 83 NC Ne NC NC Ne NC Ne + /53 * 52 * /51 .. /50 * 09 Shift 4 space.
/PL3 IPS) GNO CLIO /OCl He Q8 He 09 NC 010 + /53 * 52 * /51 * 80 * 010 Shift 5 spaces
NC 011 Ne 012 Ne 013 NC 014 NC QIS /OC4 + /53 * 52 * 51 * /50 * 011 Shift 6 spaces
eLK4 vec /PS4 /PL4 DIS 014 OIl 012 011 010
09 08
/53 * 5;2 * 51 * SO * 012 Shift 7 spaces
83 * /52 * /Sl * ISO * 013 Shift 8 spaces
53 * /52 * /51 * SO * 014 Shift 9 spaces
EQUATION5 53 .. /52 * 51 * ISO * 015 Shift 10 spaces
s3 * /82" Sl" SO * DO 8hift 11 spaces
00 := /53 * /52. /SI * ISO .'00 NO shift S3 * 52 * /81 * /50 * 01 Shift 12 spaces
+ /83. /82 • /Sl * SO. 01 8hi ft 1 space 83 * 82 * /51 * SO * 02 8hift 13 spaces
+ /83. /52. 51 * /50 • 02 Shift 2 spaces 83 * 52 * 51 * ISO * 03 Shift 14 spaces
+ /83. /82. 81 * SO * 03 Shi ft 3 spaces 53" S2" 51 * SO * 04 Shift 15 spaces
+ /53. 82 * /51 * /80 * 04 8hift 4. spaces
/83. 52 * /51 * SO * OS Shi ft 5 spaces 06 : = /S3 .. /52 * /51 * ISO * 06 No shift
/83 * 52 * 51 * /50 • 06 Shift 6 spaces T /S3" /52 * /51" 80 * 07 Shift 1 space
+ 183. 82 * 81 * SO * D7 Shift 7 spaces T /53" /52" 81 * /50 * 08 Shift 2 spaces
83 * /82 * /81 * /50 * 08 Shift 8 spaces T /S3 * /52 * Sl * SO * 09 Shift 3 spaces
53 * /82 * /81 * 50 * 09 Shift 9 spaces T /53 * 52 * /Sl * /50 010 Shift 4 spaces
83 • /82 * 81 * /50 * D10 Shift 10 spaces + /S3 * 52 * /Sl * SO Dl1 Shift 5 spaces
S3 * /52. 51 * 80 * Dll Shif~ 11 spaces T /S3 * $2" 51" /50 * 012 5hi ft 6 spaces
53 * 52. 151 * /80 • 012 Shift 12 spaces T /S3" 52 * 81" 80 * 013 5hi ft 7 spaces
53 * 52 * /Sl * 80 * 013 8hift 13 spaces 53 .. /52 .. /51 * ISO * 014 Shift 8 spaces
53 * 52 * 81 * ISO * D14 Shift 14 spaces 53 • /52 .. /Sl * SO * 015 Shift 9 spaces
53 * 52 * 51 * SO * D15 8hift 15 space:s 53 * /52 * Sl * /50 * 00 Shift 10 spaces
53 * /52. 51 * SO * tn Shift 11 spaces
01 :- /53 * /82 * /Sl * /50 * Dl No shift 53 * 52 * /Sl * /50 * D2 Shift 12 sPaces
+ /$3 * /52 * /81 * 50 * D2 Shift 1 space 53" 52 * /51 * SO * 03 Shift 13 spaces
+ /S3 * /82 * 51 * /50 * D3 8hift 2 spaces 53 * 52 * 51 * /50 * 04 Shift 14 spaces
+ /S3 * /82 * 81 * SO * 04 Shift 3 spaces + 53 * 52 * 51 * SO * 05 Shift 15 spaces
+ /53 * 82 * /81 * /50 * 05 Shift 4 spaces
+ /53 * 82 * /51 * SO * 06 Shift 5 spaces Q7 : ... /83 * /92 * /Sl * /50 * 07 No shift
+ /53. S2 * 51 * /50 * 07 Shi it 6 spaces + /53 * /52 * /51 * SO * D8 Shift 1 space
+ /S3 * 82 * 81 * SO * oa 8hift 7 spaces + /83" /52. S I . /50 * 09 Shift 2 spaces
+ 53 * /S2 * /51 * /50 * 09 5hift 8 spaces + /53 * /52 * 81 * 80 * 010 Shift 3 spaces
83 * /S2 * /81 * SO * 010 Shift 9 spaces + /S3 * S2" /81 * ISO * 011 Shi ft 4 spaces
53 * /52 * 81 * /50 * 011 8hift 10 spaces ... /53 * 82 * /Sl * 80" 012; Shift 5 spaces
83 * /52 * 81 * SO * 012 Shift 11 spaces + /53 * 52" Sl * /50 * 013 Shift 6 spaces
+ 83 * 52 * /51 * /80 * 013 Shift 12 spaces + /S3 * S2 * 51 * SO * 014 Shift 7 spaces
+ 53 * S2 * /S1 * SO * 014 shift 13 spaces + 53" /82 * /51 * /50 * DIS Shift 8 spaces
53 * 52 * 81 * /50 * 015 Shift 14 spaces 83 .. /52 * /81 * SO * DO 5hi ft 9 spaces
53 * S2 * 51 * SO * 00 Shift 15, spao.es + 53. • /82 * 51 * ISO * 01 Shift 10 spaces
* * * * 02 + 53 * /S2 * 51 * SO * 02; Shift 11 spaces
02 : - /83
+ /83 *
/82
*
/SI
*
/80
*
No shift + 83" 82 * /51 * /50 * 03 Shift 12 spaces
/52 /51 SO D3 Shift 1 space 83 * S2. /Sl * SO * 1)4 Shift '13 _paces
+ /83 * /82 * 81 *·/SO * 04 Shift 2 spaces 53 * S2 * 51 * /50 * 05 Shift 14 spaces
+ /53 * /82 * 51 * 80 * 05 Shift 3 spaces 53 * 52 * 51 * SO * 06 Shift 15 spaces
+ /S3 * 52 * /81 * /50 * 06 Shift 4 spaces
+ /83 * 82 * /81, * SO * 07 Shift 5 spaces 08 : - /53 *
/52 * /Sl * ISO * 08 No shift
+ /83 * S2 * 81 * ISO * 08 Shift 6 spaces
+ /5'3 * /82 /51 * * SO * D9 Shift 1 space
+ /83 * 52 * 51 * SO * 09 Shift 7 spaces
+ /53 * /52 51 * * /80 * 010 Shift 2 space~
53 * /82 * /81 * /8Q * 010 Shift 8 spaces
/53 * /82 51 * * SO * 011 Shift 3 spaces
+ 83 * /52 * /51 * SO * 011 Shift 9 spaces
/S3 * 52 * /Sl * /50 * 012 Shi ft 4 spaces
+ 83 * /82 * 51· * /80 * 012 5hi ft 10 spaces
+ /S3 *' 82 * /51 * SO * 013 Shift 5 spaces
83 * /52 * 81 * 80 * 013 5hift 11 apaces
+ /83 *82 * 51 * ISO * 014 Shift 6 spacas
+ 53 * S2 * /Sl • /80 * 014 Shift 12 spaces
+ /S3 * * * * Shift 7 spaces
+ 83 * S2 * /51 * SO * 015 Shift 13 spaces
+ *
S2 51
/52 * /81 *
SO
*
Ol5
Shift 8 spaces
+ 53 * 52 * 51 *180 *' 00 Shift 14 spaces
+
53
83 * /52 .. /51 *
/50
*
00
83 * 82 * 81 * SO * 01 Shift 15 spaces
+ 53 * /82 *
51 *
SO
/50 *
01
D2
Shift 9 spaces
Shift 10 spaces
Q3 :- /53 * /S2 * /81 * ISO * 03 No shift + 93 * /52 91"* SO * 03 Shift 11 spaces
+ /53 * /52 * /81 * 50 *.1)4 Shift 1 space + 53 * 82 *
/S1 * /50 * 04 Shift 1-2 spaces
+ /53 * /82 * 51 * ISO * 05 Shift 2 spaces 53 * 52 *
/51 * SO * 05 $hift 13 spaces
+ /53 * /82 * 51 * SO *
06 Shift 3 space. 53 *52 *
81 * /50 * 06 Shi ft 14 spaces
+ /83 * 82 * /51 * ISO *
01 Shift ,4 spaces 53 * 52 Sl * * SO * 07 Shift 15 spaces
+ /S3 * S2 * /81 * 80. 08 Shift 5 spaces
Q9 : - /S3 * * * * No shift
+ /53 * 52 * 51 * /80 * 09 Shift 6 spaces
+ /53 *
/82
*
/Sl
*
ISO
*
09
Shift 1 space
+ /53 * 82 * 51 * SO *
010 Shift 7 spaces
+ /53 *
/52
/52 *
/51
51
SO
* ISO * 011
010
8hift 2 spac••
53 * /52 * /51 * ISO *
011 Shift 8 spaces
+ /53 * 182 * Sl * SO * 012 Shift 3 spac••
S3 * /52 * /S1 * SO *
012 Shift 9 spaces
+ /53 * * * * Shift 4. spac••
+ 53 * /52 * 51 * ISO * 013 Shift 10 spaces
+ /53.
52
82 *
/51
/51 *
/50
SO *
013
014 Shift 5 space.
+ S3 * /82 * 51.. SO * 014 Shift 11 spaces
... /S3 * S2 * 51 * ISO * DIS Shift 6 spaces
·
* 182 * Sl * 80 * Dl0 "
83 S2" 81 180 .• 07 Shift. 14 .p~c.s
+ 83::." S2 *
~l * so. 1)8 S~ift ,l!;ii s-paces
+
83
S3
S2 * /Sl * I~O * Dl1
• S2 * /81 * 80 • D12
Shift· 1.2, ,'.pac.s .
Shif1; 1~ .•paces
010 '-/U • /S2 '0 181 * ISO * 'Olq ; No shi(t + S3 * 82 •. 81 • ISO * 013 "hi~t, '14 apace.
+ /83, * /82 ~ 181 * 80 * ,011 ; Shift 1. sPac. S3 * ','S2' * 81 * J~o * Dl' Shl~~ 15 !.pac.~_
+ /S3 * 182 * 81 * ISO *012 t ~bift 2 space.
+ /93' * 182'. 'Sl * SO'])13 Sbit.t 3, spac•• SIIIULATION
+ IS3 '. 82' /81* ISO. D14 Shift 4 spa.,..
+ IS3 * S2 */81 *
+ /S3' * S2" 81 *
80 * 015
/SQ, .. DO
Shift -5 spaa.;.
Shift ,6 apaces TRACE_ON;~\~~;L;~~/~1 ~i~~ ~!~;'
+ ISl'·. ,S2 ,* 'Sl ,ff SO" bl 8hift 7 spaces 92 81 50 00 ,01 02 D3' D4' D5 D6 07 DB'
+ s:r· ." /82 iii! /Sl • D9 010 Oll 012 013 01' 015 01 02 QO
+
+
93' * /82 .. /81 *
-83'" /82 *. ~l * ISO *
ISO .. "02'
80' 03
D4
Shift 8, spao.s
,Shift 9.spaces
Shift 10 Sl?aqes
gi.~~~~5 06 08 Q9 010 Oll 012 013
Q7
* *., '*
+
+.
+
83 /82 81
83. S2 * lS,l • ISO
SO.
012 : .)S) * /S2 .. lSl * ISO * 'D12' No shift SETF IS3 52 S.l ISO ';shitt 6
+ IS3 *
IS2 *
ISl * SO D13 * Sh:ift ,1 space CLDcn CIJ(l C;LR2 CIJ(3 CIJ('
+ IS)' /S2" Sl * ISO * D,14 I Shift 2, spac •• ,Shift 7
+ IS3 *-/82 * Sl * .so * D15
+ /S3 * S2 * /81 * ISO * DO
Shift 3 space.•
~p.itt4" spac~ ~~~K~~~~ ~k~OCIJ(1 CIJ(4
+ 183* S2*/81* 80*01 Shift 5 spaces
;Shift 8
+ /S3 * $2" 91 * ISO * D2 Shift 6 apac._ SETF 53' /S2 /51 ISO
+ /S3*- 82*_81* 80*03 Shift 7. ,space. CLDClC~ CIJ(l CIJ(2 CLK3 CLK4
+ 83 *'
/S2 .. /Sl * ISO D4 * Shift 8 .pac••
+ $) * 182 * /81 * SO * .05 Shift ,9 spac•• ;The 16-bit barrel 8h1fter will ,shift U bita of data
+ S3 *
IS2,~ 81 /80 • 1)6* Shift 10 apaces ; (015-00) a nWllber of locations into the output pins, es
+ 8,3 * /82 * 81 * SO * ~7 ~hif,t 11 ~c;:es ,specifiacLby the binary encoded·input. A compact~
+ $3* S2*/Sl*/SO*08 .: Shift 12 spac•• ;equation :can be u.~ to specify· this desiqn. It ,can ba
+ 83, * 82 * /Sl -* SO * D9
+ 83 *, S2 * Sl * ISO • 010
+ 8) *" S2 *, Sl * SO * 011
shift 13 spac••
Shift 14 spac_.
~hi~t '15 sp.ces
,
,apacUied ali followinq' '
;0[J-o-".15] ,- . , '
Q13 '-/S3 '*. /S2 * /Sl .* ISO' * D13 No shift ; eR[I~..o •• lS.] tD[(J+lC)-( (J+it)/16)'U]*IIIN[K,I=3 •• 0]S(I) )
+ IS3 * /82 * 181 * SO * 014 Shift 1. spade'
; Inputs ara iilhewn: by o. sf are Iohiftaloount input" arid
+ 183 * '/S2
+ 183 • 182
+ 183 * 82
+ 183 '" S2
+ IS3 '. S2
·* 81 * 180 * 01.5
81 * SO"; DO
.. /Sl * ISO *. 01
* /Sl * SO • D2
81*/80*03
Shift 2, space.
; ,Sl1ift 3 .pac~ •
Shift " .pa~s
'Shift, s: spa<;es
8hift 6 apace.
'OJ acre ,output•• 16 product terms ill each output pair
;are 4i,rected to one output, thua only 16 out of' 32
loutput 'pl.na a-re ulled. '
,*
*
81*/80*07
* 81 * 80 * D8
/Sl .,. /80 * D9
ISl • ·SO * 010
; Shift? space"
; I!hUt io apac.• s
; Shift ~l space.
.' Shitt 12 space.
Shift'13 .pac••
·
+ 83 * S2 * Sl * ISO • Oll : Shift 14 spaces
+ S3 * 82 Sl * SO * D12 Shift 15 ~pac~s
7-68
i6-Bit Addressable Register
07
.
+
:- lAO
/A2
A3*Q6
lAO. AI. A2./A3*CATA
*00
*07
;hold
;hold
;load
;hold
CLOCKF CLKl CLJ(2
XPLOT Output
9 ...._ ............ ----X- ------... ----...--... __.......... _...................- -_ ........- -X---
PA1ASII XPLO'l', V2. 0' .. BlTA RELEASE
(C) .. COPYRIGII"l' KOJILI'1'HIC IIEIIOllIES IRC.; 198' .7 -----............. - -..X............- - --...- ..--- ---...---...... - ...- ...- ...- .---...............--:..
.8 ..X----- ..---......X- ... - ......... - .........................------ ---..........;..........~-- ...-- ----...
9, ""'-"X--'" "'---"'-X'" --...- - - -----....................- ... - ...... - ...- ......----...-- .....---
;!:~:rn : ~i,~·~l. h91.ur 100 X......... X-... X---"'-"'- --..- ..- .......... --_..................- - ...----:...... -:------- X-...-JC
aevi.loa I A 101 XXXXXXXX xxxxxxxx xxxxxxxx XXXXXXXX XXXXXXXX XXXXXXXX XXXUXXX XXXXX
Author : John Birkner 102 XXXXXXXX XXXXXXXX xxxxxxxx XXXXXXXX xxxxxxxx: XXXXXXXX UXXXXXX XXXXX
Coapany I Nonal1thic"x.orl. . me 103 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XlCXXXXXX XXXXXXXX XXXXX
Date : 2/.1,1/15 104 :xxxxxxxx XXXXXXXX XXXXXXXX XXXXXXXX XXlOOOOCX XXXXXXD ·XXXXXXXX XXXXX
105 XXXXXXD XXXXXXXX XXXXXXXX.XXXXXXXX XXXXXXXX XXXXXXXX xxxXXXXX XXXXX
10. XXXXXXD XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX
......,.
'ALU1U'
107
108
10'
X..--...X..-
.......-X..- ..
-X----..-
~10 --.................
X---............. --......- ...- ......----- - ........- ...- .................-- .....................
--X"-"'-'" ---...--...- ......- ...- - - ...-_ ..................- ......'" ....,............-
...-X.. --........ --............- --..... _-... ,......................- ...- ....-- - ..- ..--...-
- ...x.. _-...... ---...---..............--~ '..- .......-...- -.........----. -..................
-X-"X
....---
---.. -
---.. -
111111 11112222 22222233 3333333.3 oUt ... "", 44555555 55556
01234567 "012345 57110123 45678.0-1 23.56789 01234567 '90123'5 "890 111 ---......- ...- - ... X...---- -----...-- --............... -----..............- ...- ...- -.-........... - ... X---..
o -------- .......................... ----- -------- -------- -------- -------- -x--- 112 .............. X................-- - ..------ - - -......- - ...------ ----...- ..... ----.....- -X"'-'"
1 ---............ -------- -------- ----_____ ------.- ""'------- ..............-- ____ _ 113 ------X- ------- --...-..--- ----- -----...-... -...---....- ...----...-- ........-X
2 X------- ..........---- ------.-- -------- -------- ----.. --- . .------- -----
3 ----x. . . . ------- ------- -------- . _------ -------- -------- -----
114
115
-X"'---X'"
"'-"'-X"'X'"
.......--...-- ----..... - ..............- ...-
.....---...- ......- .............'" - ..- ..----
- ............--- -----...- ............ "'--
--............- ......------ --------
..-_....
--.. _-
116 X..- ......X...... X..........- ...... --..- ....................-.... --.. - ......- ......------' ......- ............. X.........
.. -x---x-- x........._-- -------- -------- -------- ----...-.........-... ---- X--"'X
117 XXXXXXXX XXxxxx:xx nxxxx:xX XXXXDXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX
5 XXXXXXXX XXXXXXXX xxxxxxxx XXXXXXXX XXXXXXXX xxxxxXu: XXXXXXXX XXXXX
, XXXXXXXX Xxxxxxxx XXXXXXXX XXXXlClQCX XXDXXXX xxxxxxxx XXXXXXXX XXXXX 111 XXXXXXXX XXXXXXXX ~ xxx:x:x:xxx xxxxxxx:x XXXXXXXX XXXX:XXXX XXXXX
7 XXXXXXXX xxXXXXXX xxxxxxxx XXXxxxxx XXXXXXXX XXXXXXXX XX)CXXXXX XXXXX 119 XXXXXXXX XXXDXXX X:lJCOPD(X x:xxxxxxx XXXXXXXX XXXXXXD XXXXXXXX XXXXX
8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXDXX XXDXXXX XXXXXXXX XXXXX 120 XXXXXXXX DXXXXXX XXXXXXXx XXXXXXXX XXXXXXXX XXXXXXXX XXXXDXX XXXXX
9 XXXXXXXX XXXXXDX XXXXXXXX XXXXXXXX XXXXXXXX xxkxxxxX XXXXXXXX XXXXX 121 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX
10 XXXXXXXX XXXXXXXX XXXXXlCXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX 122 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX
-"'--X--- X------- -------- -..--..--- '..... -----.. ------.. . . ----..:--- -X--I 123 X-..- ... X-- X-......--.........-~ ......- ....................... ---.....................--..- - - .....- ...- ... -X-"-
11 -X---X"'-
12
X------- -------- --.. . . . - -----..
-------- ------- -.. . -.......--- --------
-................................. -------:... -------- --X--
-~------ '--x--
124
125
-"X-X"'-- ... __..---......- ...--...-- -----...- ........ ---.............--...... -- ..- ..- .... - ... -----
-XX--"'-- ....-.. ---- -.. ---.. . . . -.. . --_..- -------.........--.. . -- ----.. . -.. ----x -----
13
14 -------- -----.. _- - .. - ...... _- -------- ------- --.------ -------- --x-- 12' --X----- -------- --.....---- ------... - -..------ -------- ----.....-...
15 -------- --......... -- ...... ----- -----__ ------- ----__ ,...'- ~------- x-x-- 127 --X-"'--" - - - -......- - ..- - - -... - .. --.........- ...----...-- ... ---... - .........---......... - X----
16 ---..................------
17 -------- --------
18 X........- ..-- ---..----
~-------
--------
- - - -..... -
--------, -------- .. --... -~-- -----... x-
-------- ----..--- ...-----...-, ~,- ..
-------- ..-------. - ...------ ------x-
---X- -X---
---"X
----- OUTPUT PIKS: 111222223334
1........-X--- -----..--
20 ...X.........X.... X-----......
21 XXXXXXXX XXXXXXXX
------...-
----...- ...-
XXXXXXXX
---...- ..-- .....---...- .. -----...-- - ...----X-
--...........-- - ..... --'~ ...... --.... - .................----
XXXXXXXlC XXXXXXXX XXXXXXXX XXXXXXXX
x----
-----
xxxxx
1234,,,012347810
POlARITY' roSE; ....--......--......- ...--...-
22 xxxxxxxx xxxxxxxx xxxxxxxx XXXXXXXX XXXXXXXX XXXXXXXX"XXXXXXXX XXXXX
23 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXDXX xxxxxxxx XXXXX
24 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX xxxxxxxx XXXXX OUTPUT IAHlCr 4-40 17-24
25 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX rWSH :roSE I X X
26 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX xxxxxxxx xxxxxxxx. XXXXXXXX XXXXX
27 -X......-X-... X.... ----- ----.....-- --.....---- - ..... --.................- .... -- -------- -X--- TOTAL roSES 8L011D1: 5008
2. ----X---
X-.. ----......... -.. -.. ---- -----...........--.. . .--- . . .---.. . .- -----..
-----............................................................... - -:...X-----
-----.........-X----- -----
-----
--X----- ----x
29
30 ............---- ......--.............-----...- ---...--..- -------- ----...---
31 .....................----..-- -----...- ----......- ... ------...- --------
--X----- X----
32 ..- ..... - ........ ----...--- - ...--....-- -----.....- --..- .. --- ------X- -..----.. - -x---
33 ---... ---- -------- .........----... -------- -------- - .. --...... X- --...---...- -----
34 ... X--..-....... -.. ----- . . . .---- -.. ------ ---.. ---- ------X..... --.. . . .-- -----
~- QO
35 - ... -;.-X...... ---......--- - .........---- ...-----...... ---~ ... - ...-----X- ..::----...-- -----
36 X---X"-- X----...-- --............... - - .........---- ...---...--- -------- _ .....---...- X---X
37 XXXXXXXX XXXXXXXX :xxxxxxxx XXXXXXXX xxxxxxxx XXXXXXXX xxxxxxxx XXXXX
3'
==
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXltXXXXX xxxxx
01
!~
41
::= ::= =~: ~=~~ ~~:r:rx~~ ~~~
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX.XXXX xxxxx 02
42 XXXXXXXX XXlCXXXXX ZXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX
43 X---X--- X------- -------........----...... ----~-..... -------- ...--...---- -X--X
44 - ...---X.....
-X---. . -.. -.. ---.---.................
. --.. - . .---.. --- --- .--..
.----...........
---.. - -.--.. --.. ---- --X""---
. --- ..... X----- .-----.
.-------
. -- -----
-----
03
- ... ---.......... ----......-- ......------ --.....---- .....- .........-- ...-X----- 00:----..... - -----
45
---.. - ......... - ..........................- .. - - - -------- ---....... -- ...... X----- .:.-.. ----- X----
46
47
41 ...--.. - ......- -----.. - ... --... - ......- ...- ..----- ------X- -...--.. --- ----........- -X---
4' -------- -------- ----...--... - ............--- .......- ...-X- - ..- ..... - ...... -------- ----X NC
!l0
51
-X---. . . . . -------.. -.. . ----- --.. ----- ---.. --x- ..------- .....--...... -- ----...
- ... ---X-......- ... - ...--- - .....----................. -- - - -......X- -_...- ..- .... - .. ---......- --.....-
!l2 X---X"'-" X...---......... --...- ......- -------- ......--..... -- --......---- ------..... X---- NC
!l3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX xxxxxXxx XXXXXXXX XXXXXlPCX XXUX
54 XXXXXXXX XXXXXDX XXXXXXXX XXXXXXlQC XXXXXlCXX XXXXXXXX 'XXXXXXXX xxxxx
55 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX
56
57
51
5'
XXXXIXXX
XXXXXXXX
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X---x.........
XXXXXXXX
xxxxxxxx
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X...--...---
XXXDXXX
xxxxxxxx
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XXXXXXXX
xxxxxxxx: XXXXXXXZ
............---- ... _--..- ......
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XXXlCXXlCC XXXXXXXX
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---......--- .........--...-
--- --X----- --.
XXXXXXXX
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----........-
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XXXIX
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-X-"'- A1
..
II:
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---X............
. . . ---.
--..-.. ....-. -.---.
. . . .. .-..--............. ---.. ....-....-.. .--..-- -.-.----..
.. ----.
-..----. -----
W
60
61 X------
..
.. . -- --.....................
.2 .._-..--- -------......---.. -- . . -.. -.. -.. - --X-"--
X---..... ----- i!: AND-OR II:
.----.
.----....- ..--.. -.--.. ----X II:
63 .........----- ..... ----......... ---- - ...- ........- -X----- . -- X---- CO ARRAV ~
." ------......---......-- ------..- ------X'" ..- -...---'.'...... _-.......... - ......---..... ~X.. --
':i 8K
FUSES
!§
65 .. -----.........---........- ---.................- ..- ..X~· .:....--....- .. - ... - ..- ....:- - ...;......--.. .;,;....- ..
t
•• X......- ....... ------...- - -......- ...- ... --..
10 XXXXDXX XXXUXXX
XXXXXXXX
XXXXXXXX:
DXXXXXX
XUXXXXX
--x- -....--........ -.. -----.. -....---.....-.. --
.7 --"'-"X- ------...- ---...........- ................X.....- - - -........ - -...... -- -_..- .....-- - ...- ...-
.....X..-X...... X .........---......----........ -----....... - ........- ... - - - - - -... - ...- -..-- X"'--X
. . XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX
XXXXXXXX XXXXXXXX XXXXXXXX XXXXX
i
71 XXXXIXXX XXXXXXXX XXXXXXXX; XXXXXXO:XXXXXXXX XXXXXXXX XXXUXXX XXXXX
72 XXXXXXXX XXXXXXxx XXXXXXXX XXXXXXXXXXXXltXXX XXXXXXXX XXXXXXXX XXXXX
73 XXXDXXX XXXXXXXX xxxxxxxx 'XXXXXXQXXXXXXXX XXXXXXXX XXXXXXXX 'XXXXX
74 XXXXXXXX XXXXXXXX XXXXXXD XXXlQCXXX xxxxxxxx
-xxXXXXXX xxxxxxxx XXUX
75 ... X.....I---
7 ......---X-... --_........ - --...- - - - -x---.. . . . . -,----, ----.. . -.. . . ;.----...----
X---~ .. -- ......- ...--...- ...- - - -...- ......---...:-.........- ..---' .............. _-... -X--X
77 X...-_...... -----...- .............- ......-" ...-X...:"''''_- ...-----.. "',..-... ---.. -.;.....--- -----
7' -------- ------.. -, ---....._.. -X"':---- -.....-.. -.. - .............-..... --_ .........- -~---
79 ......------ ---............ ---... ~ ...-- ...-X...- ..-- ..----'.. - ... -_..... ;.--......------- x...---
80 ......- ..---..... ---...--- -----X...... . .-.. _. . . -:--- . . . ----: -.. . . . . .-- ~~---
~- ~
81 ...... _ .... __ ...--...--.... - ......--... X... -..,.....,........_ ':"'---":'--.....- .........--.. -""......... ---
....o--X
82 X. . . ----......-.. . . . --- ------X- ...........- . .---.. . .-- ---...........- .......----- .-"._-
-~
13 ........ --X...- ................-- .....- .....-X- ;....;.,.......... - --':' ... ~-.. - -----.....- ..--.....---
-----
14 "'X--X--- X...--..- ..... , ---_ ..........~..-~,..-.:. ----:---- ---.............. -------- X----
85 XXXXXXXX XXXXXXXX xx.xxxxxx XXXXXX;XX XXXXXXXX XXXXXXXlI; XXXXXXXX XXXXX
86 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX xxxxxxxx: XlCQCXXXX XXXXXXXX XXXXX
87 XXXXXXXX XXXXXXXX XXXXDXX lQCXXXXXX Xxxxx:xxx. XXlCClXXX XJOQOCXXX xuxx
II XXXXXXXX XXXXXXXX XXXXXJCXX xxxxxxxx ~x nxxxxxx XXXXXXXX XUXX
89 XXXXXXXX X~ xxxxxxxx: lPC[XXXXX XXXXXQX xxxxxxxx XXXXXXXX XXXXX
90 XXXXXXXX XXXXXXXX xxxxxxxx ~ mxxxxx XXXXXXXX XXXX~xxx XXXXX
'1 "'X--X-"''' X..... _ ................---........ ------- - ....---..-- ,.........:....- ...- ---...- ...-- -X---
92
93
---X"'- .------.
X---- .----........
... -X-........................................- ...--;...-...... - ... - ...---...
--X-;'-"'- ----~......- - -...---- - .. -~- ...... - - -.........-
--.. --
.....---
94 - ...- -..-- ----..- ...- .... X................- - -...-- - -...---- - -...---......-----.... "'--X
,5 ' .....- ...--- --.....................X-..- ... --....---......---......-- - ...... - ...--- --_...--- X----
lBO''''''
Traffic Signal Controller
sw ~w a:~
a: >- CI
lliJ=
o
o
REDI
YEll
10001 I
GRNI
SEN2
r.l.,
I I
I I
I I
I I
l_J
r-----,
I to- SENI
~---- ....
SENI REDI
SEN2 RED2
INIT TRAFFIC YEll
SIGNAL
CONTROLLER YEl2
GRNI
GRN2
ClK
Figure 2
STATE
so = BIIH4] (Rl,Yl,Gl,Y2,G2)
Sl - BIN(4J(Rl,Yl,Gl,Y2,G2)
52 - BIN[4](Rl,Yl,Gl,Y2,G2)
53 ... BIN(S](Rl,Yl,Gl,Y2,G2)
54 ... BIN[17) (Rl,Yl,Gl,Y2,G2)
85 - BIN!.l?] (Rl,Yl,Gl,Y2,G2)
86 ... BIN[17](Rl,Yl,Gl,Y2~,G2)
57 - B,IN(18] (Rl,Yl,Gl,Y2 I G2)
EQUATIONS
SETF OE INIT
CLOCKF
CLO<;KF
CHECK IRl /Yl Gl IY2 /G2
CLOCKF
CHEcK Rl G2
CLOCKF
CHECK Rl IYl· /Gl Y2 /G2
CLOCKF
CHECK /Rl /Yl Gl /Y2 IG2
CLOCKF
CLO<;KF
CLO<;lU'
CLO<;lU'
7·72 MonoIlthloDHlAmorleS·,
Memory Handshake Logic
State Machine Design Example write complete. the request line is lowered. hence completing
A typical control logic problem is the memory-to-processor the cycle. Table 1 shows the state assignments and the
handshake 011 memory transfer used in many computer archi- appropriate outputs. The state diagram is shown in Figure 1.
tectures. The processor makes a transfer request by activat- Also the handshaking operation is illustrated in the timing
ing a request line (REO) and specifies a read or write diagram of Figure 2.
operation on a Read/Writeline. (R/W). The memory-board logic to implement this function may· be
Duling a:. read. operation. the. processor waits for a Data designed with gates and edge-triggered flip-flops as· shown Tn
Available sign~f at which time the data bus is sampled and the Figure 3. This particular deSign would require about five 5511
request line lowered. thus completing the cycle. During a write M51 packages. but the same deSign can be implemented by a
operation. the processor places data on the bus .and waits for single PAL16RPS. The PAL design specification using state
a Write Complete signal after the write cycle is finished. Upon equations is. shown on the next page.
STATE DOUT DA WE WC CO C1
WAIT· 0 0 0 0
-0 O.
READ.1 1 0 0 0 0 0
READ2 1 1 0 0 0 0
READ3 .. 0 0 0 0: 0 0
COUNT1 0 0 1 0 1 0
COUNT2 0 0 1 0 0 1
COUNT3 0 0 1 0 1 1
WRITE1 0 0 1 0 0 0
WRITE2 0 0 1 1 0 0
WRITE3 0 0 0 1 .0 0
REQoRWoADDIl
1-73
_emory Handshake .Loglc
CK DATA
OUT
ENABLE
OATA,
!lAILABLE
Wiiiii
COMPLETE
7·74
Memory Handshake Logic
STRING II t REQ*RW*ADORl*ADDR2*ADDR3*ADDR4*/INIT I
STRING 12 I REQ*/RW*ADDR1*ADDR2*ADDR3*ADDR4*/INIT'
STRING I3 ' (/REQ+/ADDRl+/ADDR2+/ADDR3+/ADDR4) • /INIT '
STRING 14 ' (/REQ+/RW+/ADDRl+/ADDR2+/ADDR3+/ADDR4) • /INIT '
STRING IS I INtT I
STATE
WAIT - BIN[Ol(DOUT,OA,WE,WC,CO,Cl)
READl - BIN(32] (DOUT,DA,WE,WC,CO,Cl)
READ2 - BIN(4S) (DOUT,OA,WE,WC,CO,Cl)
READ3 - BIN(O] (DOUT,DA,WE,WC,CO,Cl)
WRlTEl - BIN[S) (DOUT,DA,WE,WC,CO,Cl)
COUNTl • BIN[lO) (DOUT,DA,WE,WC,CO,Cl)
COUNT2 - BIN[9] (OOUT,OA,WE,WC,CO,Cl)
COUNT3 ... BINell) (DOUT,OA,WE,WC,CO,Cl)
WRITE2 ... BIN(12) (DOUT,DA,WE,NC,CO,Cl)
WRITE3 ... BIN[4] (DOUT,DA,WE,WC,CO,Cl')
EQUATIONS
READ3
+ 15*WAIT
:- Il*READ3 + 14*WAIT
Logic Symbol
+ I5*WAIT
WRITEl := I4*COUNTl + 13*COUN'l'1 + I2*COUNTl "+ Il*COUNTl
+ 15*WAIT
COUNTl :- 14*COUNT2 + 13*COUNT2 + 12_COUNT2 + Il*COUN'l'2
+ 15*WAIT
COUNT2 :- I4*COUNT3 + I3*COUNT3 + 12 *COUNT3 + Il*COUNT3
+ 15*WAIT
COUNT3 := I4*WRIT!:2 + 13*WRITE2 + I'2*WRITE2 + Il*WR1TE2
+ 15*WAIT
WRITE2 :- I4-WRITE3 + I3*WRITE3 + 12*WRITE3 T Il*WRITE3
+ 15*WAIT
WRITE3 :- 1l*WRITEl + 14*WAIT
+ 15*WAIT
SIMULATION
SETF /REQ
CLOCKF
CHECK /DOUT /DA
SETF /REQ
CLOCKF
CLOCKF
CLOCKF
MonoIlthlcWMemorles 7-75
4·Bit Counter
SIMULATION 01 C
;The 4-bit counter counts up or clown and has the clear and
;load capability. The clear operation overrides count and.
ilead. The counter counts up when CLR-low, LOAD-low, and
;OP-high. It counts down whenever CLR.. low, LOAD-low, and
EQUATIONS
S£TF'OC SET 05 05
CLOClCF CLK
CHECK 07 06 05 04 Q3' 02 01 '00 iAll outputs high
SETF JSET UP eIN 'JID ;Counting l,lP 06
FQR 1:"1 TO 9 DO 07
BEGIN
CLOCKF eLK
IF 1-8 THEN )Checkinq' after 8 SET
BEGIN :clock pulses
CHECK /07 /06 /a5 /04 /03, 02 01 00 OC
END
END
MonolithicWMemories 7-77
9·Bit Counter
/eo
;The 9-bit synchronous counter has parallel load, increment,
land hold capabilities. The carry out pin (fCO) shows how to ,
;CLK /OC /LO 08 07 06 05 04 03 02 01 DO
08 07 R6 OS 04 Q3 02 01 90
; implement a carry out using a register by anticipated one
;count before the terminal count if counting and the terminal Data In oat. 'Out
:count if loading. ; Control oODDDoDOD QQQQQQQQQ
leO
;operations Table
:CLK /OC ILO 876543210
: ---------------------
C L L LLLLLLLLL
--------------
H
---------- -------
876543210
LLLLLLLLL Lo••
":'
eom:ment
,, e
joe leo Q8 Q7 Q6 Q5 04 Q3 Q2 Ql 00 vee , C L L LLLHHHHHH H
L H XXXXXXXXX H LIJILLLI.LL Increment
EQUATIONS e L L LIJlHHHHHH H LLHHHHHHH Lo••
, e L H XXXXXXXXX H UlLLLLLLL Increment
UlHHHHHHH Lo••
/00:" /LO*jQO
... LO·/DO
;Hold 00
;Load 00 (LSS) ,, Ce L
L
L
H
LHHHHHHHH
XXXXXXXXX
H
H HLLLLLLLL Increment
:+: ILD ;Count , e L L HHHHHHHHH L HlDIHlDIHlDI Load (Carry out)
, C L H XXXXXXXXX H LLLLLLLLL Increment (Rollover)
/01:'"
...
ILO.jOl
LO·/OI
;Hold 01
:Load 01 ,e
, C L
L
L
H
HHHHHHHLL
XXXXXXXXX
H
H
H
HHHHHHHLL
IIHlIHHlDIIJI
IIHlIHHlDIIJI
Lo••
Increment
Hold
:'1": fLO. QO ,Count
, L
C
L
L
H
H
XXXXXXXXX
XXXXXXXXX H HHlIHHJlHHL Increment
/Q2 :- ILo./a2
-+ LD*jD2
;Hold ,02
jLoad 02 ,e
, C L
L
H
H
XXXXXXXXX
XXXXXXXXX
L
H
HHHHHHHHH
LLLLLLLLL
Increment(Carry out)
Increment{Roll over)
Test HI-Z
------------------------ ---- ------- ------------------------
;C,ount , X H X XXXXXXXXX Z ZZZZZZZZZ
:+: ILO· QO* 01
:
/03 :- ILD*/03 ;Hold 03
+ LO*/03 ~,;Load 03
:+: ILO* QO* 01* 02 ; Count
Simulation Results
104 :'" ILO*/04 IKold Q4-
... LD*/04 ;Load 04 Page: 1
:+: ILD* 00* 01* Q2* 03 ; Count 9 cgcgcqc gcqogcqj::9,? q090q c
IOC LLLLLLLLLL LLLLLLLLLL LLLLLLL
/05 :., /LO* 105 ;Hold OS fLO LLLLHHLLHH LLHHLLHHLL HHLLHHH
+ LO*/05 ;Load 05 08 LLLLLLLLLL LLLLLLLLLL LLLLLLL
:+: ILO* 00* 01* 02*,03* 04 ; Count D7 LLLLLLLLLL LLLLLLLLLL LLHHHHH
06 LLLLLLLLLL LLLLLLLLLL LLHHHHH
106 : .. ILD*/Q6 ;Hold Q6 05 LLLLLLLLLL LLLLLLLLLL LLHHHHH
+ LD*/06 ;Load 06 04 LLLLLLLLLL LLLLLLLLHH HHHHHHH
: ... : /LO* 00* 01* 02* 03* 04* QS ';Count 03 LLLLLLLLLL LLLLHHHHHH HHHHHHH
02 LLLLLLLLLL HHHHHRHHHH HHHHHHH
107 :.. ILO* 107 ;Hold Q7 01 LLLLLLLLLL HHHHHHHHHH HHHHHHH
+ LO*/07 ;Load 07 DO LLLLLLHHHH HHHHHHHHHH H8HHHHH
:+: ILO* QO* 01* 02* 03* Q4* QS,," 06 ;Count ICO XXXHHHHHHH HHHHHHHHHH HHHHHHH
08 XXXLLLLLLL LLLLLLLLLL LLLLLHH
108 :.. lLO*/08 :Hold Q8 07 XXXLLLLLLL LLLLLLLLLL LLLHHLL
+ LO*/08 ;Load 08 (MSB) Q6 XXXLLLLLLL LLLLLLLLLL LLLHHLL
:+: /LO* QO* Q1* 02* 03* 04* 05.- 06~ Q7 ; Count 05 XXXLLLLLLL LLLLLLLLLL LHHKHLL
Q4 XXXLLLLLLL LLLLLLLHHH HLLHHLL
CO :- ILO*/OO* 01* 02* O~* 04* 05* 06* Q7* 08 :Carry out (Anticipate Q3 XXXLLLLLLL LLLHHHHLLH HLLHHLL
+ LO* 00* 01* 02* 03* 04* 05* D6* 07* ,08 ;Carry out (Anticipate Q2 XXXLLLLLLL LHHLLHHLLH HLLHHLL
Ql XXXLLLLLLH HHHLLHHLLH HLLHHLL
SIMULATION QO XXXLLHHHHL UlHLLHHLLH HLLHHLL
7-78 MonoilthlcmMemorles
10-Bit Counter
Block Diagram'
:j
02 COUNTER
01
QO
OUTPUT '
-IV
MS.
GPL 2P4
vccJJ
0423 104
V~~
MR
, MAsTER
RESET
LOAD COUNT,"{ 3 D3 03 22
2
03 NC~I
NC~ NC
OR LOAD
02~ 3 02
ROLLOVER
DATA '
""1..f1..fLn..
LS8
4 D2
5 Dl
'DO
PAL
2ORA10
(ROLL 01)
7 CLK COUNTER :18
01 19 5:
4 PAL,"
1601 HIT 18
(ROLL02) R
,',
6 R4 COMPARATOR NC.,1!-}
NC 8NC R3 17 7 R3 NC~ "
LOAD COUNT 9 LD
R2 16 8 R2 NC~,NC
'mlD 10 LR Rl 15 9 Rl'NC~
11 iiif
i5ifl
ROLLOVER RO 14
,.....E GND ~ GND ROf1L
.". .".
7-80 MoneI/thlDm~.
5·Bit Up Counter
SIIIULATION
TRACE_ON PL OE ex 00 01 02 03 Q4
7-81
5·81t Up.Counter
FUNCTION TABLE NOTE: THIS PAL DESIGN SPEC WAS ASSEHBLoO ON PALABM V1.7.
Q4 Q3 Q2 Q1 QO R4 R3 R2 R1 RO IMR IRST
I
; I R
,QQQQQ RRRRR M S
;43210 43210 R T
7-82
7·Bit 1/0 Port with Handshake Logic
Functional Description Input data is stored in the register when DCLK signal is
This application is for a seven-bit register with handshake applied, and at the same time, the event is signified by
logic. The chip can be used for interfacing between a micro- asserting DRDY signal. The DRDY signal indicates that the
processor and its peripheral 1/0. The on-chip flag flip-flop data is available in the register. By monitoring the DRDY
provides the handshaking capability required in typical de- signal when it is high, the stored input data can be transferred
mand-response-based data transfer. Both the register and the to Q output port by asserting 10E tt"lree'state control signal.
flag flip-flops are asynchronously cleared by CLR signal. After moving the data, DACK signal should be applied to clear
the flag flip-flop.
Block Diagram Handshake Operation
CE---==:~)- ____________-,
00,01,06
CLR----.,--!------l
DCLK---+~-----,
I----------------,DRDY
DACK
Slm"latlon Reeults
page ,,1
>q q qq qq q
CLK HHHHLL/.LLL I,
00 XZZLLLLI.LL L
al ,XZZLLLHIIHH H
g~'~m~~
CHIP IOPOR1' PAL20RAIO a4 XZZLLLLLLL L
as XZZLLLHHIIH H
PI. DO Dl D2 D3 D4 D5 D6 CE DCU, CUl'GlID ""' a6 XZZLLLLLLL L
OE DACK DRDY IIC a6 a5 a4 a3 a2 al ao VCC DCLK LLLLLIIHLLL L
DRDY XLZZLIIHHHL L
EQUA1'IOIIS DACK LLLLLI¥-HH L
ao l- DO IIBB of '-bit req8
go.CLICP - DCLK tE¢.l:nal clock
ao.sET!' - CUt ;Clear register
QO.1'RS1' -CE :Tristate control
al .- D1 IData 1
al.CLICP - DCLK :!xternal clock
al.SB"rF , ela.r register
- CUt
al.1'RS1' -"CE ;Tristate control
a2 .- D2 ;Data 2
a2.CLICP - DCLK ,External clock
a2.SET!' -cta ,Clear reqlster
a2.1'RSl' - CE' 'T!,i~tat. ~control
a3' .- D3 ;Data 3·
a3.CLICP - DCLK ; External clock
a3 .. SETF - CUt ;Clear register
a3.1'RST -CE :Tristate control
a4 :- Dot ;Data 4
Q4.CLICP - DCLK ;External clock
Q4.SETF - CLK ;Clear register
a4.1'RSl' -CE ;Tristate control
PL vee
as .- D5 ;Data 5
a5.CLICP - DCLK ;External clock DO QO
a5.SETF - CUt : Clear reqister
as.1'RSl' - CE ;Tristate control
01 Q1
a6 .- D6 ;Data ,
a6.CLICP - DCLK ;EXternal clock
a6.SETF -CLK 02 Q2
I Clear req,ister
a6.1'RS1' -CE :Tristate . control
D3 Q3
DRDY, .- GlID ;Hanelshake logic
DRDY.CLICP - DACK ;Cleared by DACK
DRDY.IISTF ; Clear D4 Q4
- DCLK
DRDY.SB"rF -CLK ; A•••rted by DCLK
DRDY.1'RS1' • vee I (External clock) 05 Q5
SIIIULAl'IOII 06 as
TRACE_Oil CUt aO al a2 a3 a4 as as DCLK DRDY DACK
CE NC
SETF PL ICE IDE 100 Dl ID2 D3 104 DS 106 CLK IDCLK lDACK
;Set input values
;Tristate outputs OCLl( DROY
sliTI' CE OE CUt :Remove the tri- ClR OACK
; states on the
;outputs and clear
; registers GNO OE
SETF CUt
SETF CUt
/'
SETr lCUt .Clock the data ,
SETF DCLK ; ••t DllDY reqiater
SETr DCLK
SETF'/DCLK
SETF DACK
SET!' DACK
SETF lDACK
SETF llIACK
NI4
Serial Data Link Controller
Before
SVSRESET
A2 ,r--------------------------------------------T~
·A1
AI
+5Y
(CSO)
D 0
'i----------'----------------DIR DIY
R °t---r-~~~-------------------BLOCK
A5
A4 RiC.
A3
AUXDECOD
t----t-~~----------------'------HDS~KE
AD r----+------~---------------------------~
+5Y 1r=~t===========================================RXD
,-------------------,
TXD
CK
E
RIW I I
om TXD I I
DO RXCLK
D1
I I
D2 TXCLK I I
D3
D4 D4 I I
D5 D5 8850 L __________________ I
~
DB DB
D7 D7 NOTE: A1yncilronOUl Divider
Figure 6.
After
TEST ~ j!YCC
SVSRESET T~
A2 ~ I::
DIRDIV
A1 ~ E: BLOCKREC.
~ ~
~
CK PAL ~NC
AUXDECOD
A3
..
~ 2ORA10
~NC
~NC
A4 'iii.
AS ".. ..
GND [i) Ilil/OE
AO
E: -
+5Y
~
CSO
-C CS1
~~
RTS HDSHAK~
C§2
E
CTS
iR:I5
f----J DC6
RIW Rfii RXD RXD
iiiQ IRO TXD TXD
DO 00 RXCLK
01 D1
D2 D2 TXCLK ~
D3 03
D4 D4
D5 05 8850
D6 06
D7 D7
Figure 7.
/DIV4. CLKF
/DIV4.SETF
+ /DIV2*/DIV4
+ /DIV1*/OIV4
+ DIV1*OIV2*OIV3*DIV4
- CK
• /DIRDIV
:divider MSB
; eLK by eK (external)
;CLR by speed option
TEST VCC
EI
;Load speed choice SYSRESET
SPEEDSEL :- /Al
SPEEDSEL. CUF • eso : eLK WI ADOR. decode
A2 DIRDIV
SPEEDSEL. SETF - /HDSIIAKE ;CLR by CTS/RTS line
A1 BLOCREC
SIIIULATION
TRACE ON Al,A2,A3,A4,A5,A6,E, ;Siqnals to be HDSHAKE CSO
- AtJXDECOO,SYSRESET,/TPH,HDSHAKE, ; observed
eso, SPEEDSEL, DlROIV, CK,
OIV1, DIV2, DIV3, DIV4 CK DIV1
SETF SYSRESET,jHDSHAKE ;Reset all regs
E DIV2
CHECK /SPEEDSEL, /DIRDIV, TPH
SETP /SYSRESET,Al,A2,A3,A4,AS,/A6,HDSHAlCE, ;set decode
E,AUXDECOD :condition AUXDECOD DIV3
Functional Description drivers and receivers) eight MSI, SSIIC, (7400, 740;1 and
One of the more widely used computer families is the Digital 7474s) along with some transistors and discrete parts. This
Equipment Corp.'s PDP-11 series. This family of computers parts count can be considerably reduced by using
uses the DEC unibus to communicate between cards. A PAL20RA10 and PAL20L10 devices.
specific protocol is required to interface a card to the unibus. Figure 1 shows how the circuit with the PAL devices would
This protocol is described in the available DEC literature. look. The two PAL devices allow almost all of the 7400, 7402
Since the unibus il! an asynchronous bus, much of the and 7474 packages to be removed. (Almost a 4-1 saving in
interface circuitry consists of combinational logic.to generate chip count.) In addition the preload pin (PRLD) on the 20RA10
specific $ignals and flip-flops which are set and reset as flags. allows the flip-flops to be easily set to a known state on power
This tends to use, a lot of SSI a!1d MSI logic packages. Using up, or when re-initializing. So the PAL devices reduce the logic
Monolithic Memories' PAL devices, much of this logic can be package count from eight chips to three.
condensed into a few packages. Figure 2 is the schematic This shows that by using PAL devices substantial space and
diagram for an interrupt Controller to be used on the unibus. circuit ,savings can be realized when interfacing to the unibus.
(p.6 - 30 of the 1976 DEC PDP-11 Peripherals Handbook.) In the schematic shown, there are three VLSI devices, three
Many cards communicate over the bus by taking control of the MSls and two SSls. Using a PAL20RA10 logic circuit, it is
unibus with an interrupt request, and then do whatever they possible to replace three MSls and one SSI device, thereby
require before releasing control. As can be seen, this interrupt reducing the chip count by a factor of two. The ICs inside the
controller takes six special interface ICs, (380 and 8881 bus enclosed loop were replaced.
:fN~B~~~~~~~BH~----_,
INTRAH .1 PRELOAD 24 VCC
FF1 8881
INTRAHEN 2 23
22 ENINTRA AINTR FF2 BUSBBSYL
MCLEARAH 3 22
INTRBH 4
NFF2
INTRBHEN NC 21
ABGIN BUSSACKL
MCCLEARBH FF1RESET
21 FF1RESET
20 NBGINBH FF4
BGINBH
SSYN 20
PAL 19 SSYN
PAL
20L 10 EN8881 2ORA10 NFF4
18
19
BGINAH -+---;"'" 17 ......-++-t-INTRDDNE AH 18
FF3
16 INTRDONE BH BINTR
15 ......_-r-t--rE-"N7IN'-T~R=B_-t-t-' NC BUSBRAL
BUSSSYNL~~-~~ 14 ......_++-t-'-F'-F3=R~E=S=E~T_++-_F~F~3'-R=E~SE'-T~
BBGIN 10
BUSBRBL
BUSBBSYL--4-~~
10 NC 11
12 13
MASTERAL
STARTINTRAL-----t---;
MASTERBL
VCC
STARTINTRBL--~_----- __-
BUS DOSL
BUS 007 L
BUS 006 L
BUS D05 L
Figure 1.
PAL Design Specification
PAL20LIO DESCR:t:PTION
INTRPOI
INTERRUPT LOGIC COMBINATORIAL LOGIC FOR PAL20RAIO INTERRUPT _CONTROLLER
MONOLITHIC MEMORIES INC., SANTA CLARA, CA (1ST 'PART OF THE TWO PALS SOLUTION: PAL20L19 & PAL20RA10)
INTRAa INTRAHEN MCLEARAH INTRBH INTRBHEN MCLEARBH BGINBH MONOLITHIC MEMORIES INC'., SANTA CLAM, CA
BGINAH BUSSSYNL BUSBBSYL STARTINTRAL GND DAN KINSELLA 7/19/84
STARTIHTRBL FF3RESET ENINTRB INTRDONEBH, I~RDONEAH ENeSSI
SSYN NBGINSH FFIRESET ENINTRA NBGINAH vee NOTE: THIS PAL DESIGN SPEC WAS ASSEMBLED oN PALASM VI. 7 •
EQUATIONS
MonoiithlcDJlMemorles
Interrupt Controller
INTRAH
BUSBRAL
INTRENBAH
BUS SACK L
BUSBBSYL
MASTERAL
MASTER
CLEARAH
BGDUTAH
GND~------~~---------=-=-=-===~===
INTRB H r-----.,..-, i
INSIDE PAL20L10
IBINTR 7400 BUS BRBL
I' ,
INTR ENB B,H I 7400
I
I
I
I
'1
I MASTER B L
I
I
MASTER I
CLEAR BH
BGDUTBH
L---:__~--_--_-_-_--_-_-_-_-'-'_-_-_-_-_-_-_-_i~l~.~~.~:..~~N~.: .:.:..,~_;...;'::,::~.,-~..
I~
:,::.,::,.:::.,::,.:::=.;::::,:.,:.:..::.:•.::... ::,:." •.•
I
:~ INSIDE PAL20L 10
BUSSSYNL
INTR DONE B H I
INTRDONEAH
START INTR A L
START INTR B L
VECTOR BIT 2 7400 I
~---------------~
BUS 006 L
BUS 007 L
BUS 008 L
Figure 2.
Table of Contents
1. Boolean Algebra Now let's look at the operator 'OR'. Suppose A is true if B or
C.is true. This equation can be written:
1.1 The Language of Logic
A=B+C
Although you may not be aware of it, you are already an
expert at forming, simplifying and comprehending Boolean Do not confuse the + with the addition sign of arithmetic; in
equations and expressions. Boolean algebra, in its most Boolean algebra, it is shorthand notation for the word 'OR'. A
common application, is concerned with the truth or falsity of truth table for. this equation would be:
statements. Anytime you describe what circumstances would
make something true or false, you have made a Boolean B C A
equation.
For example, suppose A is true only if Band C are true. These 0 0 0
three letters may represent anything you like - A may be 0 1 1
whether or not you may become president, B mily be whether
or not you are elected, and C may be whether or not you are a 1 0 1
citizen of the U.S.A. You may become president only if you are 1 1 1
elected and you are a citizen of the United States. If we wrote
that statement in equation form, it might look like this: Figure 1-2. The OR Operator
A = B*C
where.the * is ·a' shorthand notation for the word 'AND'. A, B This table expresses a different relationship between the
and C are all Boolean variables, since they represent some variables than AND does; AND requires that both of its
value. which may be either true or false. You either are a operands be true for the expression to be true. OR only
citizen of the United States, or you are,not.- there is no in requires that one of its operands be true for the expression to
between. Examining the relationship .between these three be true. From the table above, WEI can see that:
variables, we find that: .
1) if both Band C are false, then A is false:
1) if you are elected and you are citizen then you may
2) if B is false, and C is true, then A is true:
become president;
3) if B is true and C is false, then A is true and:
2) if you are elected but you are not a citizen then you cannot
become president; 4) if both B andC are true, then A is true.
3) if you are not elected, but you are a citizen, you still can't Finally, let's look at the operator 'NOT'.. If A equals NOT B,
become president, and; then the value of Ais the inverse of B.This equation would
be: . •
4) if you are neither elected nor a citizen, then you definitely
cannot become president. A = IB
This same relationship, which may be expressed in terms of Again, the'/' should not be mistaken for the division sign of
an English sentence, may also be represented by a table of all arithmetic. It is a shorthand notation for the Boolean operator,
the possibilities, called a truth table. If we let "1' stand for 'NOT'. The truth table for this.equation is:
true, and "0' stand for false, we can make the following table:
B C A ·EEEE····B
o.... .· ....·1A.•...
0 0 0 1 . 0
0 1 0
Figure '1-3. The NOT Operator.
1 0 0
1 1 1 which is to say that:
1) if B is false, then A. is .true and:
Figure I-I. The AND Operator
2) il B. is true then A islalse.
The elementary operators are summarized in Figure 1-4.
The table above is a standard way of expressing logical
relationships. Our truth table lists the possibilities one-by-one.
If Band C are false, then A will be false. If B is true and C is OPERATOR SYMBOL
false, then A will still be false. If B is false, and C is true then .'
AND i'
A will again be false. However, if Band C are both true, then *
A will be true. OR +
1.2 AND, OR and NOT NOT I
rhe fact is that every time you have an equation of the form:
" '.
A = B*C Figure 1-4. Elementary Boolean Operatora
(OU will have a truth table in the forni of Figure I-I because
:he table and the word 'AND' are just two ways of expressing
:he same relationship between two Boolean variables.
1.5.2 Using Truth Tables obtained by replacing alil's with O's, all O's with l's, all ANDs
Finally, theorems may be demonstrated with truth tables. A with DRs, and all DRs with ANDs.
theorem always holds true if it holds true for all cases. Since In fact, the easiest way in which to obtain the complement of
two variables can only have two values each, there are only a function is by taking the dual of the function and comple-
four possible cases, so it is reasonable to look at a theorem menting each individual variable (called a literal). For example,
on a case-by-case basis. For example, we can prove Theorem the complement of:
5a with the following truth table: F = (x + ly)*[W*(x + z)]
can be found by
x V I(x + V) (lx.IV) 1) taking the dual:
FD = (x'ly) + [W + (x'z)]
F F T T
2) complementing each literal:
F T F F
IF = (/x·y) + [IW + (/x'/z)]
T F F F 1.6 Algebraic Simplification
T T F F A literal. is a complemented (Ix) or uncomplernented (x)
variable. A term is asubexpression, often enclosed in paren~
Figure 1·6 theses. The equa,ion:
F = (x + IY)'/x
It can be seen from Figure 1-6 that, in every case, I(x + y) is has three literals and two terms. Simplifying a Boolean equa.
equal to (/x*ly). tion is an attempt to minimize the number of literals or the
1.5.3 Complement ota Boolean Function number of terms in an equation. Unfortunately, in many
situations, one can only be minimized at the expense·of the
A Boolean expression is some mixture of Boolean variables
other, so it is important to decide from the outset whether you
and operators that has a value. For example:
are minimizing literals or terms. Literals can be minimized by
x + y*zo/a repeated applications of. the postulat!'ls and. theorems of
is a Boolean expression. A Boolean function is a statement in Boolean algebra (Table 1-6), but there is no algorithm; it is a
which two expressions are equated. For.example: trial and error process, and the result may not be unique. For
a= b-c example, the equation:
I(c*d) = Ic + Id F = (x*/z) + f(x+ y)*/:;:]
are. Boolean functions. The difference is the presence of an may be simplified ttlrough the foll()wing steps:
equal sign. It is. worth noting that 'eqllals',or equival(;lnce, IS
also a Boolean function,since two expressions either are or F = (x-/z) + [(x + y)*/z]
are not equal. However, in this book we will aHemPt to present = (/z'x) + [/z'(x + y)] Postulate 3b
only true equations, so the Boolean value of an equal sign = Iz*[x + (x + y)] Postulate 4a
may be ignored in functions. = Iz'[(x + x) + y] Theorem 4a
.So far, wel1ave talked. about aBoolean expression's value as = Iz-(x + y) Theorem la
True or False. More frequently; these vafuesare written as 1 The equation is now simplified because there are no postu-
and 0, with 1 standing for True, and 0 standing for. False. From lates or theorems which, when .applled,will serve to reduce
hereon, we will also adopt this standard; the number of items further.
The complement of an expression· may be written easily by 1.6.1 Sum-of-Products and Product·otoSums
placing the NOT operator in front of the enclosed expression: When an equation is in the form:
lex + yl.zo/a), F=(a*b).+ (c'/a) + d
but it is also possible to complement a function. The comple- for example, it is sai.d to be in sum .of products Jorm. This is
mentofa function is ()btained by complementing both sides of because the equation is composed of a number of pro(:fuct
an equation. For· example, given the. equation: terms (AND) .that are summed (ORed) together. The subex"
/a =b*c + 1 pre.ssion resulting from two operands being ANDed.together is
the complement would be: referred t() as a product because of the resemblance of the
AND. operator to the multiplication operat()r of arithmetic; the
1(/a) = I(boc +1)
result of OR is referred to· as. a sum because of the resemc
which Could be simplified: blanceof the OR operator to. the addition operator of arithme-
a = /(b*c + 1) by Theorem 3 tic.
a = l(b*c)'/l bYTheorem5a When an equation is in the form:
a = Jlb-cl*O def; of c()mplement F = (a + b)'(a + Ic)
a""O by Theorem 2b for example, it is said to be in product of sums form, because
Note the differences between obtaining the complement of a it is composed of a number of sum 'terms (OR) that are
lunction, and obtaining the dual ofa function. The comple- ANDedtogether; Both sum ofpr6ducts arid product of sums
nent is obtained by complementing the entire expression on forms are called standard forms.
)oth sides of the equation, and manipulating it from there with
:he given postulates and theorems. The dual of a function is
MonoIlthlcWMemories
Logic, Tutorial
8-6 ~lthlcmMemOl"l_
Logic Tutorial
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
The Equivalence (XNOR) operators, symbols, and truth table
are shown in Figure 1·9. It is true only when both conditions 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
are the same. Thus XNOR is the complement of XOR 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Here x :*: y is equivalent to x*y + Ix*/y.
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A B A :*: B 0
- x Y :+: + :-: IV IX 1
Example 2.8 This technique can also be done by visual inspection. Start
with the least significant. digit of the number and visually scan
a) 1010.11 -1000.01 =?
to the left. Leave all digits unchanged until the first '1' is
1010.11 encountered. Then invert all the remaining digits to the left of
+0111.10 +- l's complement of 1000.01 this first '1'. Note that the binary point has no effect on this
overflow 1 0010,01 procedure.
+ 1 +- add overflow carry 2.2.4 Subtraction with 2's Complement
0010.10 ....
answer The steps for subtracting two binary numbers X and Y, (X-V),
areas follows:
b) 1001.10 -1100.11 =?
1. Add X.to the 2's complement of Y.
1001.10 2. Check result for overflow carry:
+ 0011.00 +- l's complement of 1100.11 a. If there' is an overflow carry, then throw it out. The
no overflow 11.00.10 .... -0011.01 .... answer result now represents (X-Y).
2.2.3 2's Complement b. If there is no overflow carry,the number is negative.
The most widely used numbering manipulation technique in Take the 2's complement of the result and place a
current digital computers is the 2's complement method. This negative sign in front of it.
method is easily implemented with any decent computer Example 2.10
instruction set. Using the same hardware for addition and
subtraction in 2'scomplement makes system design simpler a) 1110.11 -1011.10 =?
and can lead to savings in cost. 1110.11
Finding the 2' s complement of a binary number requires the +0100 ..10 +- 2's complement of 1011.10
overflow carry.
following:
throw out 1 0011.01 -+ + 0011.01 -+ answer
1. Take the logical complement by inverting each digit 01 the
binary number. b) 0001.11 -1000.10 =?
2. Add 1 to the least significant digit. 0001.11
Example 2.9 + 0111.10 +- 2's complement of 1000.10
no overflow
The 2' s complement of 001100.01 is carry 1001.01 -+ -0110.11 -+ answer
step (1) 110011.10 +- logical complement of 001100.01 Note that in computing systems which need. to represent
step (2) + ___-'- negative numbers, the MSBserves asa sign bit. When it is
110011.11 -+ answer '1', the number is negative.
~
I
I
I
MonoIithicW.emor/e. 8-9
Logic Tutorial
3. Karnaugh Maps a mirror image of the first-half with the MSB equal to a '1'.
This can be seen above when comparing the three-variable
3.1 Karnaugh Map Technique list to the two-variable list.
There exists a technique that ..allows the logic designer to
3.1.3 Karnaugh Map Examples
minimize Sum of Product terms by utilizingK~m~ugh maps.
The Karnaugh map (sometimes referred to as K-map) graphi- Examples of three- and four-variable K-maps are shown
cally displays the implicants (IT!interms) of .any sum-of-prod- below. The corresponding truth tables for the examples are
ucts expression in a matrix. It is derived directly from the truth also shown to illustrate the derivation of the K-maps.
table of this expression. K-m~s are very useful for minimizing Example 3.1
three, four, five and even six variable functions, but it gets too Three-Variable K-map:
complicated beyond six. For expressions with. more than six
variables, the numerical manipulation should be done on a B,C
A B C F
computer that uses a. method such as the Quine-McCluskey It. DO 01
0 0 0 0 1 GO 1 1 1 1]
the number of product terms is reduced. On the other hand,
by maximizing the number of cells in each grouping, the 0 0 0 1 1 01 1 1 0 0
number of literals in each product term is reduced.
0 0 1 0 1 11 1 1 0 0
For any product term, the variables which are included in the
term are those whose values in the labels of the grouped cells 0 0 1 1 1 10 0
are constant. The constant values give the polarity of the .L ...! 1
0 1 0 0 1 1
variables. "}
0 1 0 1 1 3
In example 3.1, product term 1 has cells with labels ABC =
010 and 110. Band C are constant here; B is 1 and C is 0, 0 1 1 0 0 Karnaugh Map
giving the product term B·/C.
0 1 1 1 0
3.1.2 Karnaugh Map Matrix Labels
In labeling the K-m~ matrix, the following rule should be 1 0 0 0 1
followed: 1 0 0 1 1
Top to bottom or left to right:
1 0 1 0 1
Two-variable Three-variable Four-variable
Add a '0' MSB and use the 1 0 1 1 0
00 000
01 001 three-variable chart for the first 1 1 0 0 1
11 011 half. For the second half, add a
10 010 '1' MSB and repeat the same 1 1 0 1 1
product term 1 = IC
110 chart in reverse order. 1 1 1 0 0 product term 2 - IA./B
111 product term 3 = IB.C./D
101 1 1 1 1 0 F - IC + I A./B + IB.C./D
100 Truth Table
Notice that the number of variables shown above is referring
to one axis only (X or V). However, this technique may be
used for any number of variables that may be desired on each
axis. For any axis greater than one variable, the second-half is
8-10 MonoIllhlcWMemorle.
Logic Tutorial
11 X X X xJ 11 X X X X
10 1 1 X X 10 1 o Irx x
d
c = ty + x + Z d = /x./z + /x.y + y./z + x.ty.z
00-..0 0 0
..2.. 00 1 0 0 0
01 0 0 0 1 01 1 1 0'1
=orming a truth table from Figure 4-1 is dorie by writing all '1 0' .
)ossible inputs down, then determining which segments
11 X X X X 11 ..!. x x X
10 1 1 X X
MonoIlthlcWMemorhia
Logic· Tutorial
a = ~m (0, 2, 3, 5, 7, B, 9,10,11,12,13,15)
ROW A B C MINTERMS MAXTERMS
b = ~m (0,1,2,3,4,7, B, 9,10,11,12,15)
0 0 0 0 IA-/S-IC = mO A+S+C=MO c =~m (0, 1, 3, 4, 5, 6, 7, B, 9,11,12,13,14.15)
1 ... d = ~ m (0, 2,3, 5, 6, B, 10,11, 13)
1 0 0 IA-/S-C = ml A + S + IC = Ml
e = ~ m(O, 2, 6, B, 10, 14)
2 0 1 0 IA-S-IC = m2 A + IS + C = M2
f = ~ m (0, 4, 5, 6; B, 9, 10, 11, 12,13,14, 15)
3 0 1 1 IA-S-C = m3 A + IS + IC = M3 g =' ~m(2, 3, 4, 5, 6,B, 9,10,11,12,13,14,15)
4 1 0 0 A-/S-IC= m4 "/A+S+C=M4 Example 4.3
5 1 0 1 A-/S-C =mS IA +S + IC = M5 We can easily rework the first two K-mapsfrom Example. 4•.1
to get a maxterm solution.
6 1 1 0 A-S-/e = m6 IA + IS + C = M6
7 1 1 1 A-S-C = m7 IA+ IB + IC = M7 ~
W,X DO 01 11 10 ~
w,x. DO 01 11 10
00 1
0 1 1 00 1 1 1 1
Figure ....3 Mlnterm and Maxterm Expansions for 3 Variablea
01 01 1 1
lro 01 1 .
;rol lrol
1
10
X
1
:I!J
1
x
X
I~
X
products expression· may also be written wi~h minterms.
Each maxterm is a sum of variables. It is derived by solving a
K-map for the O-terms instead of the 1-terms. Maxterms are I. = X./Z + IW_/X./V.Z Ib = X./V + X_/Z
used in a product-of-sums solution. • =(IX + Z).(W+ X + V + 17:) =
b (IX +Y)-(lX + Z)
a = 1TM (1, 4, 6, 12, 14) b =lI'M (5, 6, 13, 14)
Example 4.2
Given either camonical form, it is a simple matter of convert-
Rewriting the Sum of Products equations from example 4.1 in
ing to the other form, or the inverse of either form.
minterm form can be done by inspecting the truth table or K-
map.
..
DESIRED FORM
GIVEN FORM Minterm expansion Maxterm expansion Inverted Mlnterm Inverted Maxterm
of F. of F expansion of F expansion of F
Mlntern
expansion of F
- Maxterm numbers
are those numbers
List minterms not
present in F
Maxterm numbers
are the same as
not on the minterm minterm numbers
tist for F of F
Maxterm Minterm numbers - Minterm numbers List maxterms not
expansion of F are those numbers are the same as presem in F
not on the. maxterm maxterm numbers
list for F of F
8-12 /IIfono/ithlt:WMemorJes
Logic Tutorial
Example 4.4
From the K·map in Figure 4-6, we can find equations for an
AND-OR, NAND-NAND, OR-NAND and NOR-OR networks.
CD
~ 00 01 11 10
00 1 0 1 0
01 1 0 1 0
11 1 1 1 1
10 0 0 0 0
4.4 Multiplexers
F = A-B + IA-/C-/D + IA*C*D AND-OR Multiplexers are circuits which select one of 2" input lines
= I[/(A-B + IA-/C-/D + IA-C-D)] using n selector lines. For example, an eight-input multiplexer
= I[/(A-B)-/(/A-/C-/D) + I(/A-C-D)) NAND·NAND (often called a 'MUX') selects one of 2 3 input lines using three
= 1[/ A + IB)-(A + C + D)-(A + IC + 10)) OR·NAND select lines.
= I(/A + IB) + I(A + C + D) + I(A + IC + 10) NOR·OR Example 4.6
Design an 8:1 multiplexer in SOP form by using a truth table.
In order to get a network of NOR gates we must start with the
minimum product-of-sums form of F. SELECT MULTIPLEXER INPUTS OUTPUT
Example 4.5 A B C DO 01 02 03 04 05 06 07 Y
From the same K-map. we can also find equations for OR-
AND, NOR-NOR, AND-NOR and NAND-AND networks. 0 0 0 0 X X X X X X X 0
F = (/A + B)-(A + C + ID)-(A + IC + D) OR·AND 0 0 0 1 X X X X X X X 1
= I[/(IA + B) + I(A + C + /0) + I(A + IC + D)] NOR·NOR
= I(A-/8 + IA-/C-D + IA-C-/D) AND'NOR 0 0 1 X 0 X X X X X X 0
= I(A*/B)*/(/A-/C*D)*/(/A*C*/D) NAND·AND 0 0 1 X 1 X X X X X X 1
NAND-NAND and NOR-NOR networks are very common in 0 1 0 X X 0 X X X X X 0
industry because both the NAND and NOR gates are universal
gates: Thus, these gates are made in great quantities, making 0 1 0 X X 1 X X X X X 1
them more available for deSigners. 0 1 1 X X X 0 X X X X 0
A NAND-NAND network is made from a Sum of Products
0 1 1 X X X 1 X X X X 1
(SOP) solution. The AND and OR gates of the SOP solution
are replaced by NAND gates with all the interconnections 1 0 0 X X X X 0 X X X 0
staying the same. Variables that are input directly to the
1 0 0 X X X X 1 X X X 1
output gate must be inverted. L
A NOR-NOR network is made from a Product of Sums 1 0 1 X X X X X 0 X X 0
solution. The OR and AND gates are replaced by NOR gates 1 0 1 X X X X X 1 X X 1
with all interconnections staying the same. Any variables that
are input directly to the output NOR gates must be inverted. 1 1 0 X X X X X X 0 X 0
I-- 1--
An easy way of/orming either a NAND network from a Sum of 1 1 0 X X X X X X 1 X 1
Products solution or a NOR network from a Product of Sums 1 1 1 X X X X X X X 0 0
solution is to place two inversion bubbles in series between
the two levels as demonstrated in Figure 4-7. 1 1 1 X X X X X X X 1 1
MoneIilhlcWMemorles 8-13
Logic Tutorial
06
0 1 1 13 =0 0 13
OUT y
14
}-- 1 0 0 14 = 1 15
07 0 16
'- 1 0 1 15 =1 0 17
so Sl S2
.... 1 1 0 16 =0
A
:: 1 1 1 17 = 10 ABC
8
C
::-... Figure 4-11
8-14 MonoIlthlcWMeniorles
Logic Tutorial
Logic Diagram
PAL20L2
IJ I 2 l 4 $ 6 1 8 91011 1213141!! Hi 11181~ ZQ211213 24252627 28293031 32333435 363138~
I
I I
DO
, ""'--
01 .... " 04
02 3
" 05
03 !..-- " 06
B • r
. <,
"
42
"
44
"" ""
./ VA
C 1
r
41
.. 11
NC
"'"
OAO
, ... I~
DA4
DA2 10
" DAS
II 13
OA3 .... OA7
82,81,80
8
9 3 TO 8 OECODER
000 0 Ir1 rrn 1 1 1m 1 1
h f
001 1 1 1 1 1 1
0 0
A 9
It
C 011 0 0 0 0 1 1 1 1
8
C
k
j
010 0 om 0 'I 11 1 1
~
I
110 0 0 0 0 0 0 0
m
111 0 0 0 0 0 0 0 0
m 101 0 0 0 0 1 1 0 0
(a) (b)
100 0 0 0 0 1
rl '1 0
Figure 4-13. (a) Logic Diagram for 3-to-8 Decoder B> A = IA2.82
(b) Block Diagram for 3-to-8 Decoder
+ IA2./A1.Bl
+ IA2./A1>/AO.BO
+ IA2./AO·B1>80
+ IA1.82.81
4.6 Magnitude Comparator + I AO.82.81080
A magnitude comparator is combinatorial circuit that compares + IAh/AO.82.80
two numbers, and puts out one of three signals: A > B, A = B Of course, A = B only if (lot A < B and not A >B
or A < B.
(A = B) = /(B <: A)'/(B > A)
Example 4.9
We can design a 3-bit mag~itude comparator in a PAL device. Figure 4-14 (Continued)
82,81,80
A2, Al,AO 000 001 011 010 110~ 111 101 100
The six-variable K-maps are used to produce Sum of Product
equations for A > Band B ,< A. These equations are then
000 0 0 0 0 0 0 0 0
used to form the two-level logic diagram of the 3-bit magni-
tude comparator and the equation for A = B, as shown in
001
" 0 0 0 0 0 0 0
Figure 4-15.
~ ~
011 1 0 0 0 0 0
010 1 t 0 0' ,0 0 0 0
110lnl 1 1 1 0
o 1fT
,...-
111 mJ)[ 1 1 1l[1 ! [ill 0 il.!..: ru.. A>.
101 1 1 1 0 0 0
lJ L.!.. AI
100 1 1 1 1 0 0 0 0 AI
AIJ
A> 8 = A2./B2 A:oB
+ Al./B2./B1
+ AO·/B2./B1>/BO
+,AhAO./B2·/80
+ A2.A,./Bl
.,
82
80
+ A2.A hAO./80
+ A2.AO./B1·/BO
.>A
Figure 4-14
Figure 4-15
8·16
Logic Tutorial
that 5 outputs· remain, which can be used for some other 10 0 0 0 1 0 1 1[1] 1
functions if needed.
4.7 Adder Y =A./B./C,N + IA./S.C,N
A binary adder takes two binary inputs, adds them, and + A*B*CiN +./A*Bfr/C1N
generates the binary sum. A full adder is the basic building (a,
block of any adding network. A full adder is a l-bit adder with
A--~------------,
a carry-in and a carry-out. The truth table is shown in Figure 4-
16. The logic design and block diagram appear in Figure 4-17.
A B CaN y COUT y
0 0 0 0 0 CI:=;:::====i=*=1Q::f:;:=L)
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1 COUT
1 0 0 1 ··0
1 0 1 0 1 (b)
1 .1 0 0 1
1 1 1 1 1
CIN
The truth table is used. to form K-maps for the outputs Y and
Cin, These simple K-maps are solved to obtain equations for Y
andCin ·
:=$-' COUT
(e)
Figure 4-17. (a) Karnaugh Maps for .the Full Adder, (b) Logic
Diagram, (c) Block Diagram
Logic Diagram
PAL16P8
AO I
'1123 4567 "'011 12'131415 16171119 20212223 24~2Ul, 28293031
D
,
1....
1
3
•• 19
"~L>
A>B
6
1
2
A1
-
••
10
11
12
13 " ~U
J....
18
B>A
3
""
..
18
1....
11
19
20 11
"" ~U
A=B
23
24
-
""
21
28
,.
29
31
./ ~L>
1.... 16
-5
32
1....
33
34
"3631 15
38 ./ ~U
6
"
BO
40
J....
41
.....
42
43
14
41 " ~U
7
B1
..
"
50
"""
Sol
16
,
~U
1... 13
8
B2
50
9
"
50
SI
eo
11
12
13 ~U J 12
II
0123
MonoIlthIcW.emorl••
Logic Tutorial
Logic Diagram
PAL16L8
1
A3
0111 .. $ , I • '1011 1111''''$ ,,111'1' 1021222) 242U621 212130]1
,,•
·
· ••,
rJ 19
C03
A2
, ... ...
' ..
I
••
""
..""
)-J 18
Y3
, " ...,
A1 . Ii
! . ..
i
-
.."
~
II
F.
" C02
"""
4
" I
AO ...:JI;
~
I
""
""
21
""
"
rJ 16
Y2
I
...,
..
I
83 ~
i
",.
~
II
"" IS
C01
""
, "
82
..
...."" ~ 14
Y1
..
"
81. ~
. .... ,
~r---
.
". r-J " COO
~
..
53
80 ~ .. .
,
..
..." ~ 12
YO
.
""
9 .. ..., 11
CIN '-----I... D1 2 1 .. S , 1 • t IOlt 12 111415 '61111'1 lGll2l2'J Z4U1521 2U93O)1
NC
Logic'Tutorial
4.8 Hazards CD
Even though a digital network is designed correctly, it still may ~oo 01 11 10
have erroneous outputs at times due to hazards. Hazards 00 <D 0 1 0
exist because physical circuits do not behave ideally. For
example, a D-type flip-flop has two outputs; 0 and 10, which 01 0 <D 0 0
should always be complements of each other. In the real
world 0 may be switching from 1 to 0 and 10 from 0 to 1.
11 0 0 0 <D
Unless both 0 and 10 switch at exaCtly the same time, 0 will 10 0 o.1f 1 0
equal /0 for some finite amount of time. In some cases this
could cause the network to malfunction. The change in the
flip-flop output may. not· cause the steady-state output of the Figure 4-21. Kamaugh Map with Function Hazards
network to change, but the transient OUtput may have had a
spurious change due to the non'ideal flip-flop. If, for instance,
the network's output was. the $et line of a latch, the latch
A function static 1 hazard is present when the input variables
would set due to the hazard.
A, B, C and D go from <0000> to <0101 >. If both Band D
There are two types of hazards, static and dynamic. Static changed simultaneously no temporary erroneous pulse would
hazards occur when the steady-state output ofanetwork is' appear on the output; however in the real world either B or D
not supposed to change due to an input change, but a would change first. The transient output would have gone to 0
momentary change does occur as the inputs change. This is asaresultofbeing momentarily in state <0100> or <0001>.
often referred to ass "glitch." Static hazards are qualified Looking at the K-map, it is easy to see function static hazards
further as either static 1 hazards or static 0 hazards .. Static 1 and funCtion dynamic hazards.
hazards exist when the steady,state output is 1, stalicO
The easiest way to avoid function hazards is by restricting
hazards exist when the steady-state output is O.
input changes to one variable at a time. This method is not
always possible though, since the inputs may not be prediCt-
able.
Logic hazards exist because of the way a function is realized.
<al (b) Logic hazards can exist even if input changes are restricted to
Figure 4-19. <a) Static 0 Hazard,(b) Static 1 Hazard
one variable at a time.
A K-map is a very good way of locating logic hazards. When
trying to locate the static 0 and statiC 1 logic hazards on a K-
Dynamic hazards occur 'when the steady-state output is sup- map it is only necessary to map the 1-sets orlhe O-sets.
posed to change due to an input change. The hazard occurs A I-set is a product expression derived from a grouping of 1's
when the transient output changes several times before on the l<-map. If there are two adjacent input states that
settling down. produce a 1 onthe output. but are not covered by the same 1-
term, a static logic hazard exists. Logic hazards may be
eliminated by redesigning the circuit so adjacent input states
that produce ones are covered by the same 1-term.
y z
~z
~ 00 01 11 10 w,X 00 01 11 10
Figure 4-20. Dynamic Hazard
00 00
if1l r,-
There are two classifications of hazards: function hazards and
011rl 01
Irl
11111 1 1
logic hazards. 11l!.J '['l!J
Function hazards can be present when more than one input
variable changes. It is easy to see from the K-map in
10
lQ: = 1
TBOO16Oh1
10 1
;>;0;; ~
Figure 4-21 why function hazards exist.
(8) (b)
8-20 MonoilthICWMemorle8
Logic Tutorial
Figure 5·1 •. $oR Latch (a) Lllgic Circuit. (b) Slate Table. (c)
S-R latch, we should remember that SET = RESET = 1 is CharacteristIC Equatilln (6) Waveforms
forbidden.
The S-R latch circuit, state table, characteristic equation and
waveforms are shown in figure 5.~1.
Sl~
Latches can have more than two inputs. In Figure 5-2, we 81 82 R °t+1
~..
examine a .latch circuit that has two SET terms instead of one.
The logic diagram and the tranSition table are shown.
In some applications using latches; it is del?/rable for the input .• ..•. :.'
0
1
0
X
0
0
°t
1
data to be effective only when another signal - usually
R .' '.. Q X 1. 0 1
referred to as a control signal - is active. For these applica.
tions, the S-R latch could be modified as shown in Figure 503. 0 0 1 0
U
It is apparent from Figure 5'3 that tITe values of SET .and X 1 t X
RESET are effective only when the control signal (C) is active.
When C = 0, changes in the SET and. RESET inputs do not 1 X 1 X
have any effect on the outPUt.
Of courSe in the input of the latch dbesnot affect the output (a) (b)
immediately; there is a short delay for this change to appear at
Figure 5·2. $oR Latch with twll SET inputs (a) Lllgic diagram (b)
the .output. ThiS delay, shown in figure 5-3(b), is cauSed Slate Table
because of the propagation delays of the gales between
inpulsand .OUtputs.
MonoIlthlc,W.Memories
Logic Tutorial
s.:..'--- Dt C at + 1
Q
0 1 0
c 1 1 1
0 0 at
R --lJ---o"-"'" 1 0 at
(8) (b)
(8)
R ______ ~r_l~____~
C
·· ··
L
Q
c
(e)
Q~ u Figure 5-4. D-type Latch with Gate (a) Logic Circuit (b) State
Table (c) Wave'orms
(b)
5.2.3 J-K Latch
Figure .5-3. 8-R Latch wlth Control (a) Logic Diagram Another useful latch is the J-K latch which is shown in Figure
(b) Waveforms
5-5. This latch consists of an S-R latch with two ANO gates in
front of the inputs. This is most useful be.cause J-K latches act
like S-R latches, and it is permissible to apply '1' to both
5.2.2 D-type Latch inputs simultaneously. The state table and characteristic equa-
Other kinds of latches are used in sequential circuits. One of tion for a J-K latch are also shown in Figure 5-5.
the most popular latches is cal,led ,a delay latch, orO-type
'~,,=::[t
latch. An S-R latch is modified to a O~type latch by inserting
an inverter between Sand R, and calling the input "0"
instead of "S". The Ootype latch will take the value of its input
and transfer it to the output. The advantage of the Ootype K R Q '-""""OM
latch over the S-R latch is that in the former only one input is
needed and there is no forbidden state. The only disadvan-
tage of the Ootype latch is that it does not have a "no (8)
change" condition. This condition can be provided by inserting
a control signal, C, as an input to the latch (Figure 5-4). $t At at at + 1
This configuration is probably the most widely used one, with
0 0 0 0
the control input commonly called the "Gate". Oevices with
active high gates and with active low gates are both commer- .0 0 1 1
cially available.
0 1 0 0
0 1 1 0
1 0 0 1
1 a 1 1
1 1 0 1 Q.+l =J.fQ + IK.Q
1 1 1 0
(b)
Figure 5-5. J-K Latch (a) Logic Diagram (b) State Table and
Characteristic Equation
MonoIllhlcWMemor/es
Logic Tutorial
T~
Qt+l = T + Qt T-type flip,flop
Qt+l = D D-type flip-flop
DJ
L
INPUT I
L ,L
P
o o
GI-----I G
I I OUTPUTS
C C C
, ''''''''''"
,,
~------Ir-
Figure 5-8. Sequential ,Circuit Block Diagram
outputs are generated through the output combinatorial circuit. before, the circuit can have four states: AB = 00. 01, 11 and
The outputs do. not change .until the next clock edge. 10. At this point, we try to cover transitions for one input state.
Figure 5-9,shows an example of a sequential circuit. Suppose the circu.it is in the 00 state. If an X = 0 input is
applied, the next slate will be 00. If an X = 1 is applied, the
CLOCK-------------, next state will be 11. The output for both. cases is Z = O.
z
PRESENT NEXT STATE PRESENT
STATE At+1 8 t+1 OUTPUT
AS x=o X=1 Z
00 00 11 0
01 11 00 0
11 01 10 1
x-........--IJ.~
10 00 10 1
Figure 5-9. Example of a Sequential Circuit Figure 5-10. State Transition Table for Figure 5·9.
This circuit consists of two J-K flip-flops, an inverter, an AND 5.4.2 State Tables and State Diagrams
gate and an XOR gate. It has an external input, X, and an
We can assign names to the four possible states: So = 00, SI
external output, Z.
= 01, S2 = 11 and S3= 10. Using these assignments the
5.4.1 State Transition Tables state transition table can be modified to the state table shown .
The stat~s of a sequential circuit are determined by its inputs, in Figure 5-11.
the outputs and states of the flip-flops. In order to examine
these states, we should determine the input equations to the
flip-flops. From Figure 5.-9. we have: PRESENT NEXT STATE PRESENT '.'
STATE OUTPUT Z
JA=X:+:B Ja=X*/A Z=A X=O X=1
KA=/X Ks=X
SO SO S2 0
The characteristic equation for a J-K flip-flop gives:
S1 S2 SO 0
At+l = JA'/Q + IKA'O
= (X :+: B)'/A + X'A S2 S1 S3 1
= (X'/B + IX-B)·/A + X'A S3 SO S3 1
= IA'/B'X +/A*.B./X + A'X
Bt+l = Js*/Q + IKs·Q Figure 5·11. St.ate Table for Figure 5-9.
= IA*/B*X + B'/X
These are called the state equations. The corresponding K- A state diagram can be derived using the state table. A state
maps are: diagram shows transitions between states. Each state is
x represented by a circle, and the transitions between states are
A,B 0 1 shown by arrows.
00 0 CD The condition under which a transition occurs. is represented
by X/Z. Applying an input, X, a tra.nsition from one state to the
01 1 0 other takes place, and an output Z will be produced. The state
11 1 0
diagram for the state table in Figure 5-11 is shown in Figure 5·
12.
10 0 0
At.l 11,+1
Using these maps, the state transition tables for Figure 5-9
can be derived. There.are only four different combinations that 0/1
A and B can have. The next state values are derived using
these four possible combinations.
The. present state is the state of the flip·flop before the clock
DFOOO;!lM
pulse; the next state is the state of flip.f1op after the clock
pulse has been applied. The present output; Z, is. the output of
the sequential circuit after the clock pulse... As mentioned' Figure 5-12. State Diagram for Figure 5-9
8-24 MonoIlthlcW.emories
Logic Tutorial
0 ....
0 .... 0
....
1
0
1
x
X
0/0 1
1 ....
0
1
X
X
1
0
(8)
ex
0'00"""
A,B 00 01 11 10
(8) 00 0 1 1 0
01 0 0 1 1
PRESENT NEXT STATE PRESENT OUTPUT
STATE 11 X X X X
x=o X=1 X=O X = 1
10 1 1 1 0
50
51
51
52
54
54
0
0
0
0
"""" .
52 52 53 0 0 ex ex
53 55 54 1 0 ~ 00 01 11 10 A,B 00 01 11 10
00 0 1 1 0 00 X X X X
54 55 54 0 0
55 56 54 1 0 01 0 0
rl
'1" 01 X X X X
~W
56 52 53 0 0 11 X X 11 X X X X
(b)
10 x Irx "7 x 10 0 0 0 1
JA =/B.X + B.e
(b)
ex
A,B 00 01 11 10
00 0 0 0 1
0/0
01 1 1 0 0
11 X X X X
(e) 10 0 0 0 1
50 51 54 0 0 00 0 0 0 1 00 X X X X
51 52 54 0 0 01 X X X X 01 0 0 1 1
52 52 53 0 0 11 X X X X 11 X X X X
53 55 54 1 0
10 0 0 0 1 10 X X X X
54 55 54 0 0
55 52 54 1 0 J a =e./x Ka=e
(d) (e)
cx X~r1~-r-----------------,
A,B 00 01 11 10
00 1 0 0 0
01 0 1 0 1
11 X X X X
z
10 1 0 0 0
'cx ex
~oo 01 11 10 ~ 00 01 11 10
ooW 0 x X 00 X X 1 1J
01 0 1xl x 01 X X 1 0
11 x I~ xW 11 X X X X
loB 0 x x 10 X X 1
~
1
cx
~ 00 01 11 10
Example 5.2
00 0 0 0 0
We will derive the state diagram,state transition table, and'
01 0 0 0 '1 state equations of a sequential circuit which adds five to a
binary number in the range of 0000 to 1010 (decimal 0 to 10).
11 X X x Ox The inputs and outputs will be serial with the least significant
~
bit arriving first. This design Y{ill, be realized with J-K flip-flops.
10 0 0 0 1
Solution:
In Figure 5-17a, all the possible combinations for the input and
Z = A.C./X + B.e./X
the output are shown. The sequence will start from state A. At
(e) time 10 (when the first input is received), if X = 0, then we look
at the map for all possible combinations and notice that at to
Figure 5-15 (Continued)
whenever X ,= 0, the output is a 1. Thus, if the present state is
o
A, under X = the output is, Z = 1. On the other hand, if X = 1
the map shows that t will be a O. At time t 1, if X .;. 0 and the
The state equations are derived from the K-maps. Using the sequence of the inputs has been 00 then the output would be
state equations, the logic diagram in Figure 5-16 is obtained. a 01. So in this transition Z = O. Likewise, the remaining states
The state equations are summarized as follows. of the state diagram can be derived by inspection of the table
J A = IB'X + 'B*C J B = C*/X Jc = B-X + IB-/C-/X in Figure 5-17a, The state diagram is then completed as in
Figure 5-17b. Note that the states have been labeled arbi-
KA=/C*;X Ks=C KC,=/B+X trarily and that we have not yet determined how the states will
be implemented.
The state table is determined from the state diagram. Inspect-
ing the state table shows that some of the states are
equivalent. States K, J, I, and H have the same next state
under X = 0 and X = 1, and produce the same outputs;
therefore K = J = I = H, and they can be replaced by the H
state. This allows us to reduce the state table to the table
shown in Figure 5-18b. There are now a total of nine states
used, so four state variables will be needed. The state
variables are called A, B, C and D. A complete state transition
table is shown in Figure 5-18c.
The K-maps are drawn from the state table. The state
equations are derived using the K-maps.
MonoIlthlcW Memories
Logic Tutorial
INPUT
J, .. ','
OUTPUT
C F ..,.. 1 -
X Z ·0 G H 1 1
" E I J 1 0
t3 t2 t1 I:, to ' 13 t2 ·t1 to
F " K L 0 0
0 0 0 ,,0 .',," 0 1 ;0 1, G A A 0 0
0 0 0 1 0 1 1 : ,0 H A A 1 1
0 0 1 "'0'" 0 + ; 1" 1 'I A A 1 1
0 0 1 ,1 ; l' "0.. 0 0 J A A, t 1
0 1 0 ., 0 1 0' 0 1 ,
A 1, 1
, K A
0 1 0 1 , .. 1 6 1 0 L A '- 1 -
0 1 1 0 1 0 1 1 (8)
0 1 1 1 1. 1 .. 0 0
1 0 0 0 1 1 0 1 NEXT STATE Z
PRESENT STATE
1 0 0 1 1 1 1 0 X.= 0 X=1 X=O X=1
1 0 1 ,0 1, 1 1 1
, , , ,~,
A B C 1 0
B 0 E 0 1
C F ~
1 -
0 G H 1 1
E H H 1 0
F H L 0 0
G A A 0 0
H , ',A A 1 1
L A - 1 -
(b)
0000 ,
0001 0010 1 0
0001 0011 0100 0 1
0010 0101 - 1 -
0011 0110 0111 1 1
0100 0111 0111 1 0
0101 0111 1000 0 0
0110 0000 0000 0 0
0111 0000 0000 1 1
1000 0000 - 1 -
(e)
Figure 5-18. Exaniple 5.2 (a) State Tranaltlon Table (b) Reduced
Stete Table (e) Reduced Transition Table
8-28
Logic Tutorial
10
XVx
Yx
X/
Yx
x/x
/X
almost all equipment containing digital logic. The sequence of
states followed determines the different types of counters
x x/ X (SCD, binary, etc).
The binary counter is. one of the simplest counters. An n-bit
binary counter is a register with n flip-flops and associated
combinatorial logic that follows the sequence from 0 to 2n-l.
X =011 X =0/1
Example 5.3
~
A,S · 0 0 01 11 10 ~
A,S 00 01 11 10 We will look at the design of a 3-bit up/down binary counter.
There are three outputs from the binary counter: DA, DB and
00 Va°VI0 1 VX 00
Yx x x X DC. The input to the counter is X; the counter will increment if
01
lYx1/"
X x
x X x
x
01
Yo x '/'XVV
0
/1
1 1 X = 1, and decrement if X '" O. We will use D flip-flops for this
design.
11
lXVXV VX 11
Yx V X /X
X
Solution:
10
lYx ~~~
x 10
Yx x x xX This circuit will have eight different states, because the 3-bit
counter cycles through 23 states. The states are called qO, q1,
'''''''''''' q2, q3, q4, q5, q6 and q7. If X = 1 each state will have a
dB = C + O.X KS =C + O.X transition to its next higher state. For example, qO will go to
qt, q1 will go to q2, and so on. If X = 0 then each state wil.1
change to its previous state. For example, q7 will go toqS, q5
to q4, and so on.
The state diagram of this design is shown in Figure 5-22a.
State transition tables, derived from the state diagram, are
shown .in Figure 5-22b. The .K-maps and the state variables
are shown in Figure 5-22c. The state equations are derived
from the K-maps. The equations are summarized as follows:
DA: '" /Ao/S·IC·/X + IA-S-C'X + MS./e + A-/S-X + A*C-/X
TOO0250M DB: = IS'/C-/X + IS-C' X + So/C·X + S-C-/x
J c = B.IX + .D./X + O.X Kc =.B + 10 Dc: '" Ie
A,
MonoIlthIcW.e;"orie. 8·29
L09ic Tutorial
11 0 1 0 1 11 1 1 0 0
UP Qn BORROW OUT NEW Qn
10 1 0 1 0 10 1 1 0 0
L L L L
L L H H
De: =IB./C./X + IB.C.X DC: = IC
L H .. L H
+ B.C./X
(e)
L H H L
Figure 5-20. 3-Blt Up/Down Counter (a) State Diagram (b)
State Transition Tables (e) Karnaugh Maps Figure 5-22. Borrow-out Table
Logic Diagram
PAL16R4
CLK' ....
.....
Olll 4~" '91011 111l1.1~ 1,,111'19 l021Ull lUUUI 21111031
XL~
illilll,I~lllp~:;1""'llt-~----"" HC
~---H
:ll···~l
" ~~~____________~18 HC
."
"
I I I
HC~'"
::IIR"_IF
I! I I I! I' i I I
!1'1111111~")-----b[Jl0" ~DB
::It I, ,I I I ...
HC.!.........j..
"III'
~
"
IIR~iI'ml'~i1~!'1111~:::>--1~): ~DC
, II ...
HC!......t..
.
HC~'"
HcL;o..
HC L....tr
MonoIlthlcWMemorlea 8-31
Logic ,Tutorial
RE· Q'
LO HOLD UP 0 OPERA:rION
SET
H X X X X .X SefaliLOW
;
L L X X 0 0 {.9ad 0
L H H X X 0 Hold Q
L H L L X ci plus 1 ' 'InCrement
L H L H X Q minus 1 Decrement .
Table of Contents
L~.ndard
PREFIX 8
• Reduces Ie iniieiito/ies and simplifies ttiEiir control
PLE ~ Programmable
• Expedites and simplifies prototypirig and board layout logic Elament 1. xxxx = Other
• Saves space with O.3-inch SKINNYDIP@ packages (except
~NUMBER OF INPUTS PACKAGE TYPE
PLE12P8) N - Plastic DIP
OUTPUT TYPE _ _ _--' NS - Plastic SKINNYDIP
• Programmed on standard PROM programmers
P = Non. Registered J = Ceramic DIP
• Test and simulatibn made simple with PLEASMTM software A" -' Registered JS - Ceramic SKINNYDIP
RA - Registered F -. Ceramic Solder Seal
• Low-current PNP inputs Asynchronous Flat Pack
• Thre~·state outputs Enable L .. Leadless Chip Carrier
RS ,.; Registered NL - Plastic Leaded Ollp
• Reliable TiW fuses guarantee >98% programming yeld Synchronous Corrier
Enable W ... Cerpack
PLE11P8 11 8 2048 35
PLE12P4 12. 4 4096 35
PLE12P8 12 8 4096 35
PLE9R8 9 8 512 8 15
8~
~
PLE10R8 10 1024 8 15
PLE11RA8 11 8 2048 8 15
PLE11RS8 11 8 2048 8 15
·Clock to output time for registered outputs.
Note: COmmercial limits specHied.
"INPUTS
INPUTS
13 12 11 10
, 7 ' 7~ 7 ~ 7
'OR" ARRAY
13
7
12
7 ~
11
7 ~
10
7 "OR" ARRAY
V V ~. V
(PROGAAMMAIILE)
.. V V V ~ --_. (FIXED)
=< "1=\
=< F=<
=<
F<
F=<
I=<
F< F=<
~ F<
F< F<
F< F<
~ F=<
~ F<
~ F<
~ F=<
~ F=<
~ F<
I=<
L-I
I=<
L-,.f
"AND" ARRAY
FIXED WQ9
03 02 01 00
"AND" ARRAY
(PROGRAMMABLE) 'VVVy
03 02 01 00
Logic Symbols
PLESP8lA PLESP16
....
"",
Programmable Logic Element PLE™ Circuit Family
Logic Symbols
PLE10Pl PLE11P4 PLE11P8 PLE12P4
9-8 wb.o,lthit;Wi"emorieS
Programmable Logic Element PLET.. Circuit Family
Logic Symbols
PLE11RA8 PLE11RSS
COOl$31'" COOt141M
Absolute Maximum Ratings
Operating Programming
~~2~1:t~:~~::::::::::::~~r::::::::::::::::':':~~:;:::~::::::::::::::~::~;::::::'::::::::~~J~~.;~::::::::::::::::::::::::::::::::~E
"i;!f .......................,.. ,...................:.........
Storage temperature ................. :.-,65 to +J50 C
Operating Conditions "
~ ·,'f : ' i
~",. , . " , .'
't'f>j,,", '".' "i ",
y' MILITARY
iitARAM~TER •.-1' ...' COMMERCIAL
SYMBOL UNIT
j,
!.. ~ .
.. ~MIN NOM MAX MIN NOM MAX
Vee Supply Voltage;. ,; ::,:,,' ",.. '; 4.75 ,.5 5.?S' 4.5 5 5.5 V
TA Operating free-air,te,mperafu~ , '::' :0 25 75' -55 25 125 ·C
",.: ' .,
""'"
Electrical CharacterlstlC8':'~~Oper8!!nIlCondltlOll.
, .. ' .'
r,·
SYMBOL PARAM~R .. ,.. TEST CONDlllQNS ", MIN TYpt MAX UNIT
VIL Low-level input vpJlagEi ,: Gllarant~ logical lowvol~ge for all Inputs O.S V
V IH High-level input vo~ge Guarant8ed logical higl:l. voltage, for' all inputs 2 V
VIC Input clamp volt8g'e' . Vee - '-1IN I; --~8rnA -1.5 V
IlL Low-level input curr!ilnt Vee - MAX VI ~ 0.4V -0.25 mA
IIH High-level input current Vee - MAX VI - Vee 40 jJA
VOL Low-level output voltage Vee - MIN IOl - 16111A I Com 0.45
V
I Mil 0.5
Com IOH - -3.2mA 2.4 V
VOH High-level output voltage Vee - MIN
. Mil IOH - -2mA
IOZl Vo = 0.4V -40
jJA
Off-state .output current Vee - MAX
IOZH Vo - 2.4V 40
los Output short-circuit. current· Vee -.5V Vo - OV -20 -90 mA
5PS 90 125
5PSA 90 125
5P16 140 1S0
6P16 150 190
SP4 SO 130
SPS 90 140
9P4 SO 130
'Ii -MAX
AlNnputs 9PS 104 155
grounded;
10P4 95 140
all outputs open
lee Supply current 10PS 92 160 mA
11P4 110 150
11PS 135 1S5
12P4 130 175
12PS 150 190
9RS 130 1S0
Vee - MAX 10RS 130 180
.All inputs TTL;
all outputs open 11RAS 140 1S5
11RSS 140 1S5
t TypIcaIa at 5.OV vee and 25"<: TA.
• Not more than one output should be shorted at a time and duration of the short ~ should not exceed one second.
Programmable Logic Element PLE™ Circuit Famll,
5P8AC 15 20
5P8C 25 20
.'
5P16C 18 15
6P16C 20 ". 15
8P4C 30 .. '
20
8peC 28 25
9P4C 35 20 ....
9P8C . . 30 25
..
10P4C 35 25
10P8C 30
. 25 i
.c
llP4C 35 25
llP8C '. '.' '. 35 25 c
12P4C 35 25
·c· ". ..
12P8C 35 30
5P8M 35 30
8P4M 40 30
8P8M 40 30
9P4M 45 30
9P8M 40 30
10P4M 50 30
10P8M 45 30
llP4M 50 30
11P8M 50 30
12P4M 50 30
12P8M 40 35
~11
PLE9R8
Operating Conditions
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYP' MAX MIN TYP' MAX
Switching Characteristics Over Operatllllll Conditions and ueilllll Standard Test Load
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYp. MAX MIN TYp. MAX
Definition of Waveforms
I....... -----)rt·~---
_---"--'H \\ ~~7- -
E_ _ _ ·h7S.~!1_~I .. __f
I
CLK
o
'VOL +0.5 V
Mono/lthlc.WMemor/es 9-13
PLE 1 OR8,11 RA8, 11 RS8
Operating Conditions
MILITARY COMMERCIAL
SYMBOL , '
PARAMETEA UNIT
MIN TYp. MAX MIN TYP· MAX
Switching Characteristics Over Operallng Conditions and using Standard Test Load
,
MILITARY COMMERCIAL
SYMBOL PARAMETER UNIT
MIN TYp· MAX MIN TYp· MAX
Definition of Waveforms
-______________~i-~_-ti-~-i:l------.--------
i
/·!-=--I~t~1
-----J.--t..... .,Of +=1
130
1 I ...
I I
I
Ir--+-\!--..Jr--tl---.I
CLK
i--'Pxz-l I+-tpzx-!
~~~___-+rf;nr------~------"r-~--"~~OH-O$V
o _______-Jl'--_ _-JUJr.uv u..l-_ _ _ _ _ _Ij\-_ _ _ -VOL +UV --I~
.ouTPiJT
Definition of Waveforms·
:rI
.
a.* . ": "
",...
R2
R1
MUsT iE STEADY WILL BE STEADY
........
NOTES: Apply to eleclrlcaland switching characteristics. Typic81at S.OY Vee and 25·CTA- Measimi~~iaaiiSOl~ ~~ r~'~~igraur1!l~'
pin on the device and includes all overshoots due to system and/or tester noise. In.alIPLE.deVIceillmused.lftPUIS must be tied·to iIth8r ground or
Vee. the sedIIl! re.tstor ...q.,iI1Icifor unused Inpule. on standard TTL is NOT required kW PLE deviqes. thus using'leas parts. "N<it more then O!!6
output should be ,shOrted at a time and duration of the short-circuit should not ~ one: second. For commerclalopSrating range R, .,. 200'1 Rz •
3900. For.m1ll1i11yoP8ratlngranga R, - 3l100.R2 - .6090. '.. . ' .. ' .,.; " ,.... ..... .
1. Input pulse al1iPfib,lda ov to a.av; i
2. Input ....anci!iitj.I!m8ll 2-5n8 from 0.810 2.0V.
3; Input ac;cass ·rriessured at th$ 1.5V layel.
4. Data delBy Is tested WI1h swltch8';<:io8ed. CL • 3OpF.an<! massured al1.5Voutpul le\IlIl.· , . . .
5. Ir>zx .is measured at th8 1.5V output I8v8I WI1h CL • 3OpF.• 8, is open for hig~-impedanCelo "I" teat and cloSed for hig/1-I~ce 10 "0" tesL'1px2"
Is~ured C~.,:,.~pF. 8, is open for "I" to hlgh-Impedan~ teat. maa~at VOH :; O.!>¥ qUIp,,! level; 8" is closed for "O"'Io~Igh-imj:lell!lnce teal
,inea8Ured at VOl + O.SV output 18v81, ' . .,1 'd' •
;' , , "
Block Diagrams
PLEIPIIA
11
A7
1•
••1 AI
17
. ,au.,.
PIIOGItAIIIIULI AI PROGRAIIMAIILE
AllR4Y A1
2 ARRAY
AD
111 5
A4
4
A,3
AI
1 2 3 4 I
01 02 01 04 01 •
01
7
07
I
01
........
II
PI.EIN
101'.
!lOW
~
101'32 32114
ROW PIIOGIIAMIIA8LE .
DlCODER ARRAY
101'.1
COLuMN
DECODIR
A,34
Al7 101'1'
A1' :=
AD'
1-18
PLE 1 OR8, 11 RA8, 11 RS8
Block Diagrams
1.8 ,. AI 22
1.7 ,. AI 23
",17 I4XI4 1 1 OF 14 , • • 14
PROGRAMMABLE 1.7 ROW PIIOGIIAIIIIMLE
AS ,. 2
DECODER
1.1 2
NtfIAy
'"
AS
3
4
AFIIIAY
1.0 A4
5
1.3
1.4 5
1.3 4 1.2
1.1
• 7
1.2 3
08
.....,...
PLE1C1P4 PLE11N
1 OF 14 I4XI4 1 OF . . I4X1.
ROW PROGRAMMABLE ROW PROGRAMM'IIILE
DECODER NtfIAy DECOOER ARRAY
1.10 ~8'--r_--..,
1.3 4
1OF1. 1 OF 32
c:ou.N 1.27 COLUMN
DECODER DlCOD£R
1.1 •
1.0_5......._ _ _'"
Ii 10
14 13 12 11
01 02 03 04
Block Diagrams
PLE11P8 PLE12P4
A10 21 A11 17
At 22 A10 18
At 23 128l!128 '
At 19 1 OF 128 128 X 128
A7 PROGRAMMAllLE 48 1 ROW PROGRAMMAllLE
'ARRAY A7 2 DECODER ARRAY
At
A6 :
M
AS
M
At
A2
A1
AD
ii
E2
E3
PLE12P8
A11 19
A1021
A9 22 1 OF 128 128.251
23 ROW PROGRAMMAI\LE
48 1 DECODER ARRAY
A7
48 2
M 3
L..--_...J
A4..!4Lr---,
A3 5
A2
A1
AD
9·18 MonoIlthlcWMemor/es
PLE 1 OR8, 11 RA8, 11 RS8
Block Diagrams
PLE11RA8
A10 21
A8 22
AI 23 1 OF 121 12k121
AI 23
A7 1 ROW PROO~
A7 1 1OF32 32X 121 A6 2 DECODER ARRAY
A8 2 DE~R PROGRAMMAIIU!
ARRAY
AS
A4
3
4
AS 3
A4 4
0iS 20
A3 .J5Lr---,
A3
A2 6 10F1. A2
7 COLUMN Al
• DECODER AI
CLK --':--;;~--~
E 18
01
PLE11Rsa
PLE10R8
1.10 21
AI 22
AI 23 1 OF 121 126 X126
At 22
:: !3
AS
ROW
DECODER
PROGRAMMABLE
ARRAY
AI 23 A4 4
64X 121
1.7
PROGRAMMAIIU!
A8 2
ARRAY
AS 4
A4
-is 20
9 10 11 13 14 15 ,. 17
01 02 Q3 Q4 os Q6 07 Q8
Monolithic W Memories
PLE10R8, 11RA8, '11RS8
9-20 MoneI/thlem.emor/e.
PLE Circuit Applications
Table of Contents
Random Logic Replacement Although it seems that XOR functions may be replaced by
PROMs, as logic elements, have been providing solutions as 551s, in most applications, the XOR functions.will. not be alone
replacements of random logic. This is the concept of PROM by themselves, PLE. circuits can provide ~he flexibility of
as a Programmable Logic Element (PLE) device. adding in additional functions without using additional pack-
ages. .
The usages of PLE devices include simple multiplexer/demul-
tiplexer / encoder/decoder, control signal generators, data In the data path, a PLE device can be used to implement
communications support like CRC, and arithmetic elements complex functions such as a Pseudo Random Number (PRN)
like ALUs, multipliers, sine and inverse look-up tables, and Generator. Random number sequences are useful in encoding
applications in signal processing. and decoding of information in signal processing and commu-
nications systems. They are used for data encryption, image
The advantages of PLE devices over 551/M51 logic devices
quantization, waveform synchronization, and white noise gen-
are the lIexibility of design and the fast turnaround time which
eration, etc.
non-programmable devices cannot offer. For example, if a
decoder is used to select between memory pages and I/O There are many techniques for generating PRN sequences.
ports, once a design is done, it will be fixed - it is not easy to The most common technique, however, is to use'n' stages of
find a part to be put just in the same place without modifica- linear shift registers with feedback through a logic function.
tion of PC board layout in case the designer wants to expand The function f is an arbitrary function chosen for a specific
the memory or to increase the I/O. For a PLE device, what is application. A most general linear function is an 'm' input XOR
needed is to program another PLE device and place it in the (m ';;;n).
same socket where the old part was placed. In addition, it can
allow designers to define their logic functions in a component.
The ANO-OR planar structure of the PLE circuit array lends
itself naturally to being viewed as a two-level logic circuit. The
fixed AND plane contains all possible combinations of the
literals of its inputs. Each combination (product term) is fuse-
connected to each output in the programmable OR plane.
A common PLE device application in the control path is to
customize logic functions. An n input exclusive OR function is
There are a number of examples in the following session
quite commonly required in comparator and adder circuits. It
which shows how a PLE device can be used to replace 551/
contains 2" - 1 product terms, which becomes quite large for
M51 logic devices using PLEA5M softwarE!. "
large values of n. Tl)erefore, it is very convenient to implement
'arge XOR functions in PLE devices.
fhe PLE logic circuit implementation of a 4-input XOR is
9hown below.
cd
ab 00 01 11 10
00 0 1 0 1
01 1 0 1 0
11 0 1 0 1
10 1 0 1 0
10~3
Random Logic
04 = 10 + II + 12 + 13 + 14 OR GATE ~~"
~. . 04
14
FUNCTION TABLE
10 11 12 13 14 01 02 03 04 05 06 07 08
DESCRIPTION
NOTE ALSO THAT THREE-STATE OUTPUTS ARE PROVIDED WITH ONE ACTIVE LOW
OUTPUT ENABLE CONTROL (/E).
PLEASM SOFTWARE GENERATES THE PROM TRUTH TABLE FROM THE LOGIC
EQUATIONS AND SIMULATES THE FUNCTION TABLE IN THE LOGIC EQUATIONS.
BASIC
GATES
PLE5P8
MonoIlthicWMemor/es
Random Logic
FUNCTION TABLE
All A12 A13 A14 A15 /MREQ /CE1 /CE2 /CE3 /CE4 /CE5 /CE6 /CE7 /CE8
ADD LINES
11111 CHIP ENABLES
12345 /MREQ 12345678 COMMENTS
-----------------------------------------------------------------------
LLLLL L LHHHHHHH SELIOC:T ADDRESS RANGE 0-2K
HLLLL L HLHHHHHH SELECT ADDRESS RANGE 2K-4K
LHLLL L HHLHHHHH SELIOC:T ADDRESS RANGE 4K-6K
HHLLL L HHHLHHHH SELIOC:T ADDRESS RANGE 6K-8K
LLHLL L HHHHLHHH SELIOC:T ADDRESS RANGE 8K-10K
HLHLL L HHHHHLHH SELIOC:T ADDRESS RANGE 10K-12K
LHHLL L HHHHHHLH SELIOC:T ADDRESS RANGE 12K-14K
HHHLL L HHHHHHHL SELIOC:T ADDRESS RANGE 14K-16K
XXXXX H HHHHHHHH NO MEMORY SELIOC:T (/MREQ=H)
-----------------------------------------------------------------------
EIGHT
ACTIVE
LOW
CHIP
ENABLES
DESCRIPTION
THIS PLE8P8 PROVIDES A SINGLE CHIP ADDRESS DOCODER FOR USE WITH MANY POPULAR
8-BIT MICROPROCESSORS SUCH AS '!HE Z80 AND 8080. THE FIVE MSB ADDRESS LINES
(All-A15) AND '!HE MEMORY REQUEST LINE (/MREQ) FROM THE Z80 MICROPROCESSOR ARE
DOCODED TO PRODUCE EIGHT ACTIVE LOW CHIP ENABLES (/CE1-/CE8) TO SEr.ECT A RANGE
OF 2K BYTES FROM A BANK OF EIGHT 2Kx8 STATIC RAMS. THIS BANK OF STATIC RAMS
WILL OCCUPY THE LOWEST 16K BYTES OF ADDRESS SPACE LEAVING THE UPPER 48K BYTE
SPACE AVAILABLE. FOR OTHER MEMORIFS AND I/O. THE PLE8P8 HAS THREE ADDITIONAL
INPUTS WHICH CAN BE RFSERVED FOR FUTURE SYSTEM EXPANSION.
MEMORY ADDRESS
DECODER
PLE8P8
VCC
OK
CH UNUSED
2K
m 4K UNUSED
CE3
6K i.iiiE'Q
CE4
8K
CE5
10K
E2
CE6
12K
CE7
14K
CE8
16K
CHIP ENABLE
ADDRESS
MAP
GND
MICRO-
PROCESSOR
DRAM = /AS * Al2 * Al3 * /Al4 * A1S SELECTS ADDRESS RANGE OOOO-BEPF
+ /A9* Al2* A13*/Al4* A1S
+ /AlO* A12* A13*/Al4* A1S
+ /All * A12 * Al3 * /Al4 * AlS
+ /A12* /Al4
+ /Al3*/Al4
+ /AlS
10 AB* A9* A10* All* A12* A13*/A14* A15 SELECTS ADDRESS RANGE BFOO-BFFF
FUNCTION TABLE
A8 A9 A10 All A12 Al3 A14 A15 /DRAM IIO ISRAM IPROM
ADDRESS LINEs
11 111.1
8901 2345 IDRAM /IO' ISRAM IPROM COMMENTS
------------------------------~----------------------- ----------------------
LLLL LLLL L H H H OOXX HEX SELECTS DRAMS
LLLL HHLH L H H H BOXX HEX SELECTS DRAMS
HHHH HHLH H L H H BFXX HEX SELECTS I/O PORTS
LLLL LLHH H H L H COXX HEX SELECTS SRAM
LLLL HLHH H H L H DOXX HEX SELECTS SRAM
LLLL LHHH H H H L EOXX HEX SELECTS PROM
HHHH HHHH H H H L FFXX HEX SELECTS PROM
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _ _ _ _ _ _0_ _ _ _ _ _ - - - - _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
DESCRIPTION
THIS PLE8P4 PROVIDES A SINGLE CaIP ADDRESS DECODER FOR USE WITH MANY POPULAR
8-BIT MICROPROCESSORS SUCH AS 'l'HE MOTOROLA 6809. THIS PLE DEVICE DECODES THE
EIGHT MSB ADDRESS LINES (AB-Al5) FROM THE MICROPROCESSOR TO PROVIDE FOUR ACTIVE
LOW CHIP ENABLES (/DRAM, 110, /SRAM, AND /PROM).
THE 64K MEMORY MAP OF THE SYSTEM IS DIVIDED UP INTO FOUR SECTIONS: DRAM, IO
PORTS, SRAM, AND PROM. EACH OF THESE FOUR SECTIONS CAN CONTAIN ONE OR K:>RE
BLOCKS OF MEMORY. EACH OF THESE BLOCKS CAN START AND STOP ON ANY 256 BIT
BOUNDARY
Block Diagram
16
~:~~ --'""'I"--~'----""ADDRESS
8 H--t:>-- i5iWi
ADDRESS r-1-,._- iO CHIP
DECOOER t--II-I.~- SRAM ENABLES
System Diagram
Memory Map
~-----,64K
PROM
....---..,--t 56K
--,,~==SR=A=M=:::::t :~4K
I/O PORTS
DRAM
L..-_ _ _ _--' 0
MenoIIth/c.m·Memorles 10-9
Random Logic
FUNCTION TABLE
11 12 01 02 03 04 05 06 Yl Y2 Y3 Y4 Y5 Y6
TRUE/COMPLEMENT
D 6 AND CLEAR/SET 1-7L-H>-;"'-y
LOGIC FUNCTIONS
tt
11 12
SELECT 1 :4
FUNCTIONS
10-10
Random \ Logic
DESCRIPTION
THE PLE8P8 ALSO FEATURES THREE-STATE OUTPUTS WITH TWO ACTIVE LOW OUTPUT ENABLE
CONTR:>LS (/El AND /E2).
6-BIT TRUE/COMPLEMENT
ZERO/ONE LOGIC FUNCTIONS
PLESP8
Y4 po.
DI • S2 • /S1 • ISO ACTIVE HIGH, SELECT 4
+ /po • DI ACTIVE LOW, DI INACTIVE
+/po • /S2 ACTIVE LOW, SELECT 0-3
+/PO • S1 ACTIVE LOW, SELECT 2,3,6,7
+/po • SO ACTIVE LOW, SELECT 1,3,5,7
Y5 po.
DI • S2 • /S1 • SO ACTIVE HIGH, SELECT 5
+ /po • DI ACTIVE LOW, DI INACTIVE
+/po • /S2 ACTIVE LOW, SELECT 0-3
+/po • S1 ACTIVE LOW, SELECT 2,3,6,7
+ /po • ISO ACTIVE LOW, SELECT 0,2,4,6
Y6 po.
DI • S2 • S1 • ISO ACTIVE HIGH, SELECT 6
+ /po • DI ACTIVE LOW, DI INACTIVE
+/po • /S2 ACTIVE LOW, SELECT 0-3
+/PO • /S1 ACTIVE LOW, SELECT 0,1,4,5
+ /po • SO ACTIVE LOW, SELECT 1,3,5,7
Y7 po.
DI • S2 • S1 • SO ACTIVE HIGH, SELECT 7
+ /PO • DI ACTIVE LOW, DI INACTIVE
+/po • /S2 ACTIVE LOW, SELECT 0-3
+/po • /S1 ACTIVE LOW, SELECT 0,1,4,5
+ /po • ISO ACTIVE LOW, SELECT 0,2,4,6
10-12 MonO/ithicWMemories
Random Logic
FUNCTION TABLE
PO DI S2 S1 SO Y7 Y6 Y5 Y4 Y3 Y2 Yl YO
SSS yyyyyyyy
1PO DI 210 76543210 COMMENTS
------------------------------------------ EXPANDABLE
H L XXX LLLLLLLL DATA INPUT = 0 3-TO-8 DEMULTIPLEXER
H H LLL LLLLLLLH SELECT OUTPUT 0
PLE5P8
H H LLH LLLLLLHL SELECT OUTPUT 1
H H LHL LLLLLHLL SELECT OUTPUT 2
H H LHH LLLLHLLL SELECT 'OUTPUT 3
H H HLL LLLHLLLL SELECT OUTPUT 4
H H HLH LLHLLLLL SELECT OUTPUT 5
H H HHL LHLLLLLL SELECT OUTPUT 6
H H HHH HLLLLLLL SELECT OUTPUT 7
L H XXX HHHHHHHH DATA INPUT = 0
L L LLL HHHHHHHL SELECT OUTPUT 0
L L LLH HHHHHHLH SELECT OUTPUT 1
L L LHL HHHHHLHH SELECT OUTPUT 2
L L LHH HHHHLHHH SELECT OUTPUT 3
L L HLL HHHLHHHH SELECT OUTPUT 4
L L HLH HHLHHHHH SELECT OUTPUT 5
L L HHL HLHHHHHH SELECT OUTPUT 6
L L HHH LHHHHHHH SELECT OUTPUT 7
------------------------------------------
DESCRIPTION
PIN ASSIGNMENTS:
OPERATIONS TABLE:
L H X H OUTPUTS HIGH
H H S DEMUX DEMUX ACTIVE HIGH PO
L L S /DEMUX DEMUX ACTIVE LOW DI
H L X L OUTPUTS·LOW
y
TB01160M
L L Al A2 X X C1 C2 X X Al C1 A2 C2 SELPX::T A, C
L H Al A2 X X X X D1 D2 Al D1 A2 D2 SELPX::T A, D
H L X x B1 B2 C1 C2 X X B1B2 C1 C2 SELPX::T B, C
H H X x x x
B1 B2 D1 D2 B1 01 B2 D2 SELPX::TB, .0
------------------------------------------------------------------------------
DtJAL2:1
MULTIPLEXER
PLE1OP4
EIGHT { : X} FOUR
DATA c DATA
INPUTS D y OUTPUTS
SY
TWO
S.ELECT
LINES
FUNCTION TABLE
MonoIlthlCW'.emor/e. 10·15
Random Logic
DESCRIPTION
THE PLE10P4 ALSO FEATURES THREE-STATE OUTPUTS WITH TWO ACTIVE LOW ENABLE PINS
<lEI AND /E2). THE FUNCTION IS SUMMARIZED BELOW:
L H A X A
L L A X /A
H H X B B
H L X B /B
-------------------------------
EIGHT { A FOUR
DATA Y } DATA
INPUTS B OUTPUTS
SEL POL
TWO
CONTROL
LINES
10-16 MonoIilhlcWMemorles
Random Logic
OA = B* /D 1 SEGMENT A
+ B* C
+ /A* /C*/D
+ A* C*/D
+ /A* D
+ /B*/C* D
+ LT IF LT=H MAKE BLANK TEST ON SEGMENT A
OB /C*/D SEGMENT B
+ A* B* /0
+ /A*/B* /D
+ A*/B* D
+ /A* /C
+ LT IF LT=H MAKE BLANK TESTON SEGMENT B
oe /C*'D SEGMENT C
+ A*/B
+ C*/D
+ A* /D
+ /B* /D
+ LT IF LT=H MAKE BLANK TEST ON SEGMENT C
OD = /A*/B*/C SEGMENT D
+ /B* D
+ A*/B* C
+ A* B*/C
+ /A* B* C
+ /A* B* /D
+ LT IF LT=H MAKE BLANK TEST ON SEGMENT D
OE = /A* /C SEGMENT E
+ C* D
+ /A* B
+ A* B* D
+ LT IF LT=H MAKe BLANK TEST ON SEGMENT E
OF = /A*/B SEGMENT F
+ /B*C*/D
+ /C* D
+ B* D
+ /A* B* C
+ LT IF LT=H MAKE BLANK TEST ON SEGMENT F
DESCRIPTION
HEXADECIMAL TO
SEVEN-SEGMENT DECODER
PLE5P8
10-18 MonoIlthlcWMemorles
Random Logic
+5V
2700 3.3K
OUTPUT ENABLE
LAMP TEST
INPUT 0
INPUTC
INPUTB
INPUT A
PLESP8
5·BIT {
BINARY
B1} TWO
BCD
CODE BO DIGITS
FUNCTION 'D\BLE
BI4 B13 BI2 BIl BIO B13 B12 B11 B10 B03 B02 B01 BOO
~ADDRESS ----DATA----
; BINARY BCD 1 BCD 0 DESCRIPTION
~ 43 210 3210 3210 (DECIMAL VALUE)
-----------------------------------------------
LL LLL LLLL LLLL 0
LL LLH LLLL LLLH 1
LL IBH LLLL LLHH 3
LL IBL LLLL LLHL 2
LL HHL LLLL LHHL 6
LL HHH LLLL LHHH 7
LL HLH LLLL LHLH 5
LL HLL LLLL LHLL 4
THREE-STATE OUTPUTS ARE ALSO PROVIDED WITH ONE ACTIVE LOW ENABLE PIN (jE).
MonoIlthiclFJllMemor/es 10-21
Random Logic
G1 .. 81 :+: B2 CONVER'l' Gl
G2 .. B2 :+: B3 J CONVERT G2
G3 .. 83 CONVER'!' G3 (MBB)
DESClUPTION
THIS PLBSPS WILL CONVERT A 4-BIT BCD INPUT (B3-BO) INTO A 4-BIT
GRAY CODE REPRESENTATION (G3-G0) lOR. OUTPUT.
vee
E
UNUSED
83.
B2
.).. ~.Blt .
. GRAY·
eDDE
1c)'22
Random Logic
B2 = G2 :+: G3 CONVERT B2
B3 = G3 CONVERT B3 (MSB)
DESCRIPTION
'MIS PLE5P8 WILL CONVERT A 4-BIT GRAY CODE INPUT (G3-GO) INro A 4-BIT
BINARY REPRESENTATION (B3-BO) FOR OUTPUT.
4-BIT { 4 4-BIT
GRAY G B } BCD
CQDE
Sl = 17 1 17'-10 = 1XXXXXXX
+ 16 17-10 .. X1XXXXXX
+ /15*/14* 13 17-10 = XX001XXX
+ /15*/14* 12 17-10 .. XXOOX1XX
FUNCTION TABLE
17 16 15 14 13 12 11 10 EN S2 S1 .SO
-j
10
11 3·BIT
S1 PRIORITY
12 CODE
~ "
. 8-BIT·
52
8 ",',;"
INPUT PRIORITY
LINES 14 ENCODER
EN
15
16
17
ElE2
11).24
Random Logic
DESCRIPTION
'l'BIS a-BI'f PRIORI'l'f ENOODBR SCANS FOR THB FIRST HIGH INPU'l' LINB (17-10) FROM I7
(WHICH BAS '!'HB HIGHEST PRIORI'l'f) TO 10 (WHICH HAS '!'HB LOWBST PRIORI'l'f). IT
WILL GENBRATB A BINARY BNCODBD OU'J.'PO'll (S2-S0) WHICH WILL POINT TO 'l'BB HIGHEST
PRIORI'l'f INPUT WHICH IS AT A HIGH STATB.
IF NO INPUT LIRBS ARB HIGH (I7-IO-LOW), 'l'BBN 'l'BB BINARY BNCODBD OUTPUTS WILL DB
ZJR) (S2-S0-LOW) AND 'l'BB BNULB OUTPUT WILL BB HIGH (BN-HIGH) INDICATING A
CARRY OUT TO 'l'BB NBXT PRIORITY BNcoDBR. 'l'BB OUTPUT BRULB WILL BIl. LOW (BN-LOW)
IF ANY OF. '!'HB INPUT LINBS ARB HIGH.
'!'HB PLBSP4 ALSO HAS TllRBB--STATB OUTPUTs WI'l'iI '!'NO AC'l'I:vB-LOW OUTPUT 'BNABLB
CONTROL PINS (/81 AND /B2). .
a·BIT PRIORITY
,ENCODER
Random Logic
GT" A3 */B3 A3 GT B3
+ A3:*:B3 * A2 */B2 A2 GT B2
+ A3:*:B3 * A2:*:B2 * Al */81 Al GT B1
+ A3:*:B3 * A2:*:B2 * Al:*:B1 * AD */BO AD GT BO
OESeR! PTION
THIS PLEBP4 COMPARES TWO 4-BIT NUMBERS (A3-AOAND B3-BO) TO ESTABLISH IF THEY
ARE EQUAL (A .. B THEN BQ=H), NOT EQUAL (A NOT .. B THEN NE-H), LESS THAN (A
LT B THEN LTcH), OR GREATER THAN (A GT B THEN GT=H) AND REPORTS THE
COMPARISON STATUS ON THE OUTPUTS (EQ, NE, LT, GT) AS ILLUSTRATED IN THE
t:lPERATIONS TABLE BELOW.
THE PLEBP4 ALSO FEATURES THREE-STATE OUTPUTS WITH TWO ACTIVE-LOW OUTPUT ENABLE
CONTROL PINS (/E1 AND /E2).
A B H L L ·L COMPARE A EQUAL TO B
ANOT=B L H X X COMPARE A NOT EQUAL TO B
A LT B L H H L COMPARE A LESS THAN B
A GT B L H L H COMPARE A GREATER THAN B
4-BIT MAGNITUDE
COMPARATOR
PLE8P4
1ti;.B ,
Random Logic
EQ= A3:*:B3* POL * A2:*:B2* POL * Al: * :Bl * POL * AO:*:BO* POL A EQ B
+ A3:+:B3*/poL * A2:+:B2*/POL * Al:+:Bl*/POL * AO:+:BO*/POL A /EQ B
NE" A3:+:B3* POL + A2:+:B2* POL + Al:+:Bl* POL + AO :+:BO* POL A NEB
+ A3:*:B3*/poL + A2:*:B2*/POL + Al:*:B1*/POL + AO: * :BO* /POL A /NEB
DESCRIPTION
THIS PLE9P4 OOMPARES TWO 4-BIT NUMBERS (A3-AO AND B3-BO) TO ESTABLISH IF THEY
ARE EQUAL (A EQ B), NOT EQUAL (A NE B), LESS THAN (A LT B), OR GREATER THAN
(A GT B) • THE OOMPARISON STATUS IS REPORTED WITH ACTIVE-HIGH POLARITY (EQ,
NE, LT, GT) WHEN 'mE POLARITY CONTROL INPUT 'IS TRUE (POL=H) AND WITH ACTIVE-LOW
POLARITY (/EQ, /NE, /LT, /GT) WHEN THE POLARITY CONTROL INPUT IS FALSE (POL=L).
THE PLEap4 ALSO FEATURES THREE-STATE OUTPUTS WITH ONE ACTIVE-LOW OUTPUT ENABLE
CONTROL PIN (/E).
OPERATIONS TABLE:
Block Diagram
EQ
-r~
4-BlT
MAGNITUDE NE
4-B1T COMPARATOR COMPARiSON
INPUT WITH STATUS
NUMBERS POLARITY LT
CONTROL
GT
POL i
,-
10;.29
Random Logic
DESCRIPTION
THE 8-BIT BARREL SHIFTER, IMPLEMENTED IN A PLEllP8, ROTATES EIGHT BITS OF DATA
(D7-DO) A NUMBER OF LOCATIONS INro THE OUTPUTS (07-00) AS SPECIFIED BY THE
3-BIT BINARY ENCODED SHIFT CONTROL LINE (S2-S0). THE THREE-STATE OUTPUTS ARE
IN A HIGH-Z STATE WHEN ANY ONE OF THE 'lW0 OUTPUT ENABLE PINS (fEl OR /El) ARE
HIGH.
PlE11P8
00-----...---"---00
01~ 01
8 BIT 02: 8-BIT 02 8-BIT
I~~~ D3' :~I~~ g! O~
05
06__ 08
07 _ _......,..-,-...,.....-_07
t it
so 5152
-........-,
3-SIT5HIFT
CONTROLUNE
MonoIlthlcWMemorle$ 10-31
Random Logic
52 51 SO D7 D6 D5 04 D3 D2 D1 DO 0706 05 04 03 02 01 00
~5HIFT INPUT DATA OUTPUT DATA
~ 55S DDDDDDDD oooooooo
~ 210 76543210 76543210 COMMENTS
----------------------------------------------------------------------
LLL HLLLLLLL HLLLLLLL BARREL SHIFT ONE HIGH 0 PLACES
LLH HLLLLLLL LHLLLLLL BARREL SHIFT ONE HIGH 1 PLACES
LHL HLLLLLLL LLHLLLLL BARREL SHIFT ONE HIGH 2 PLACES
LHH HLLLLLLL LLLHLLLL BARREL SHIFT ONE HIGH 3 PLACES
HLL HLLLLLLL LLLLHLLL BARREL SHIFT ONE HIGH 4 PLACES
HLH HLLLLLLL LLLLLHLL BARREL SHIFT ONE HIGH 5 PLACES
HHL HLLLLLLL LLLLLLHL BARREL SHIFT ONE HIGH 6 PLACES
HHH HLLLLLLL LLLLLLLH BARREL SHIFT ONE HIGH 7 PLACES
LLL LHHHHHHH LHHHHHHH BARREL SHIFT ONE LOW o PLACES
LLH LHHHHHHH HLHHHHHH BARREL SHIFT ONE LOW 1 PLACES
LHL LHHHHHHH HHLHHHHH BARREL SHIFT ONE LOW 2 PLACES
LHH LHHHHHHH HHHLHHHH BARREL SHIFT ONE LOW 3 PLACES
HLL LHHHHHHH HHHHLHHH BARREL SHIFT ONE LOW 4 PLACES
HLH LHHHHHHH HHHHHLHH BARREL SHIFT ONE LOW 5 PLACES
HHL LHHHHHHH HHHHHHLH BARREL SHIFT ONE LOW 6 PLACES
HHH LHHHHHHH HHHHHHHL BARREL SHIFT ONE LOW 7 PLACES
----------------------------------------------------------------------
T80._
10;.33
Random Logic
FONC'l'ION TABLE
1-coNTROL-
11 I - INPUT DATA- OUTPUTS
1E S S N DDDDDDD 0000
1N 1 0 V 6543210 3 2 1 0 COMMENTS
--------------~----~-------------------~---------~-~~--------~--~--~--~~-.
H X X X xxxx x x X LL L L "TEST ENABLE, OUTPUTS GO· LOW '
L L L L L L LHHHH H H H H SHIFT COUNT '" 0, TRUE' POLARI~
L L H L L LLHHHH L H H·H =
SHIFT COUNT .'. 1, TRUE POLARITY:
L HL L L LLHHHH LLHH SHIFT.COUNT = 2, TRUE POLARITY.'
L H H L L LLHHHH LLLH =
SHIFT Cot1NT .. 3, TRUE' POLARIT!'
,.
L L L H LLLHHHH L L L L S.HIFT COUNT .. 0, COMPPOLARI~
L LH H L L.r. H H H H H L L L SHIFT COUNT ... 1, COMPPOLARI~ ,
L H L H L. L LHHHH H H L L SHIFT COUNT =
2, COMP POLARITY
=
--
L HH H LLLHHHH H H H L SHIFT'COUNT 3, COMP POLARI~ .
... ... ...
------------------------------------------~~ ----~.,..'":'"' ~------- 7"":------.--,-~'~-
"
11),.34
Random Logic
DESCRIPTION
THE OUTPUT DATA IS NONINVERTED (O"D) WHEN INV=L AND INVERTED (O=/X» WHEN
INV=H. THE OUTPUTS ARE FORCED LOW (O=L) WHEN /EN=H RFGARDLESS OF OTHER
INPUTS. THE PLE1;LP4 ALSO FEATURES THREE-STATE OUTPUTS WITH ONE ACTIVE LOW
OUTPUT ENABLE (IE).
OPERATIONS TABLE:
I
SEVEN
~__:.-:;,
02..,..--+ SHIFTER
00)
01 FOUR
DATA 03__ WITH DATA
INPUTS 04 _ _ PROGRAMMABLE H-D-02 OUTPUTS
05__ OUTPUT
06__ POLARITY 03
i iso i
--
S1
SHIFT
CONtROL
UNE
INV
10·35
Random Logic
FUNCTION TABLE
D7 D6 DS D4 D3 D2 D1 DO Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO ,DECIMAL
------------------------------------------------------------
L L L L L L L L L L L L L L L L 0
L L L L L L L 8 8 H 8 8 8 8 8 8 1
L L L L L L 8 8 8 8 H 8 8 8 L 8 3
L L L L 8 8 H
L 8 8 8 8 8 L L 8 7
L L L 8 8 8 H
L 8 H H H L L L H 15.
L L L H H H H '8 H 8 8 L L L L 8 31
L L H H H H H H H L
H L L L L H 63
L H H H H H H H H L
L L L L L H 127
H H H H H H H H L L L L L L L L 255
H H H H H H H L L L L L L L H L 254
H H H H H H L L L L L L L H L L 252
H H H H H L L L L L L L 8 L L L 248
H H H H L L L L L L L H L L L L 240
H B H L L L L L L L H L L L L L 224
H H L L L L L L L B L L L L L L 192
B L L L L L L L H L L L L L L L 128
------------------------------------------------------------
8-BIT { TWO'S
BINARY Y } COMPLEMENT
NUMBER REPRESENTATION
10-36
Random Logic
DESCRIPTION
THIS PLE8P8 CONVERTS AN 8-BIT BINARY NUMBER (07-00) IN'l'O TWO'S COMPLI!'.MEN'l'
REPRESENTATION (Y7-YO) WHERE 07 AND Y7 ARE THE MSB AND DO AND YO ARE THE LSB.
TWO'S COMPLEMENT REPRESENTATION IS USED IN SIGNED ARITBME'l'IC SYSTEMS.
NA2 • A2
:+: AO* Al
r TIMING 'WAVEFORMS
10.38
Random Logic
PUNC'l'ION TABLE
NNNNN
,AAAAA
,43210
AAAAA
43210
TIMING WAVEFORMS
TIALR TVCC TO , II , COMMENTS
---------------------------------------------------------------------
LLLLL LLLLH H L L 01 1 ASSERT TIALR
LLLLH LLLHL H L L 02
LLLHL LLLHH H L L 03
LLLHH LLHLL H L L 04
LLHLL LLHLH H H L 05 ASSERT TVCC
LLHLH LLHHL H H H 06 ASSERT TO
LLHHL LLHHH H H H 07
LLHHH LHLLL H H H 08 1
LHLLL LHLLH H H H 09
LHLLH LHLHL H H L 10 CLEAR TO
LHLHL LHLHH L L L 11 CLEAR TIALR , TVCC
LHLHH LHHLL L L L 12
LHHLL LHHLH L L L 13
LHHLH LHHHL L L L 14
LHHHL LHHHH L L L 15
LHHHH
HLLLL
HLLLL
HLLLH
L
L
L
L
L
L .
I
16
17
HLLLH HLLHL L L L 18
HLLHL HLLHH L L L 19
HLLHH HLHLL L L L 20
HLHLL HLHLH L L L 21
HLHLH HLHHL L L L 22
HLHHL HLHHH L L L 23 ;
HLHHH HHLLL L L L 24
HHLLL HHLLH L L L 25
HHLLH HHLHL L L t 1,26
HHLHL HHLHH L L L 27
HHLHH HHHLL L L L 28
HHHLL HHHLH L L L 29
HHHLH HHHHL L L L 30
HHHHL
HHHHH
HHHHH
LLLLL
L
L
L
L
L
L
31
32
',.
---------------------------------------------------------------------
DESCRIPTION
THE PLE CONTAINS BOTH S-BIT NEXT ADDRESS AND 3-BIT WAVEFORMS. TIALR
OUTPUT IS A TIMING WAVEFORM FOR I, A, AND L/R SIGNALS, AND TVCC AND
TO OUTPUTS ARE USED FOR VCC AND 0 SIGNALS, RESPECTIVELY.
TIALR. TYCC
TO
PLESP8
BECAUSE THE TIMING PATTERNS ARE S'roRED IN THE PK>M, WE CAN EASILY
CALIBRATE THE RELATIONS AND THE PERIOD AMONG THOSE SIGNALS 'ro MAKE
AN OPTIMUM CONDITION.
A PORTION OF A
TIMING GENERATOR FOR
PAL LOGIC CIRCUIT ARRAY PROGRAMMING
PLE5P8
TB01410M
PUNC'l'ION TABLE
NNNNN
JAAAAA AAAAA TIMING WAVEFORMS
743210 43210 'l'VCCP TPOI TP11 7 It J COMMEN'l'S
--------------------------------------------------------------------------
LLLLL LLLLH H L L 01 ASSERT 'l'VCC, START HERE
LLLLB LLLBL H H L 02 ASSERTTPOI
LLLBL LLLBB H H L 03
LLLBB LLBLL H H L 1 04
LLBLL LLBLH H H L 05
LLBLH LLBHL R H L 06
LLBHL LLBBB R R L 07
LLBBB LBLLL R H L 1 08
LBLLL LBLLB H H L 09 CLEAR TPOI
LBLLR LBLBL H L L 10 ASSERT TP11
LBLBL LBLBB B L H 11
LBLBB LBHLL H L H 12
LBBLL LBBLH H L R 13
LBBLH LBBBL H L H 14
LBBRL LHRHH R L H 15
LBBRH RLLLL H L R 16
BLLLL HLLLH H L H 17
BLLLH HLLBL R L H 18
BLLHL RLLBH R L L 19 CLEAR TPll
BLLHB HLBLL L L L 20 CLEAR 'l'VCC
RLBLL RLHLH L L L 21
RLBLB HLBLH L L L 22 LOOP HERE UNTIL RESET
--------------------------------------------------------------------------
DFSCRIPTION
THE PLE LOGIC CIRCUIT CONTAINS '1WO FUNCTIONS IN THE SINGLE CHIP. THE FIRST
FUNCTION IS A UNIQUE COUNTER USED FOR NEXT ADDRESS GENERATION. THi COUNTER
INCREMENTS UP. TO COUNT-21 AND THEN LOCKS .. UP THE INCREMENTAL OPERATION AT
COUNT-22. THE SECOND FUNCTION IS A TIMING GENERATOR USED FOR DEFINING
TIMING RELATIONSHIP AMOUNG VCC, POI, AND PH SIGNALS.
A(O:4)
PLESP8
APPLYING 200 KHz CLOCK SIGNAL TO THE CLK INPUT OF THE REGISTER, THE
FOLLOWING TIMINGS ARE GENERATED:
1. VCCWIDTH 95 usee
2. TPP 40 usee
3. to 5 usee
.MonoIIthicWMemor/es 10-43
Fast· Arithmetic Look-up
Fast Arithmetic Look-up sin (X) + sin (XO) + cos (XO) (X - XO)
In performing arithmetic operations like trigonometric func- Since X - XO is represented by only the bits after the more
tions, multiplications and division, in order to reduce the delay, significant n-bits, and co~ (XO) = sin ('1T12 ~ XO), the implemen-
look-up tables are often used. tation will be very simple.
Sine Look-up Division
For trigonometric functions like sine function, it is very time- Division will normally be much slower than multiplication.
consuming to generate the function using the polynomial There are several ways to perform division. Bit-by-bit division
which represents the function. PLE devices can provide avery restoring and nonrestoring algorithms are generally very slow.
good alternative for sine look-up. An example is to use a 2Kx8 Another way is to use several bits at a time division which is
PLE device to do a sine look-up of ant1-bit input to 8-bit sine faster than the previous methods. A third way is to multiply the
outputs. dividend by the inverse of the divisor. The inverse of the
Since sine function has the following property: sin (x) = sin divisor can be found by getting an approximation followed by
(11' - x) = -sin (11' + x) = -sin (211' - x) = sin (211' + x), what is iterations.
needed is just the sine function for 0 < x < 11'/2; the rest can The approximation is again given by the Taylor series:
be easily calculated using the above relations. In order to fully f (X) = f (XO) + f' (XO) (X - XO) + 1/2f" (XO) (X - XO)2 + ...
utilize the dynamic range, the inputs of the sine look-up PLE and f(XO) = 1/XO
device should be normalized to (1I'/2)/(2n) = 1I'[2n + 1] where f' (XO) = -1/X02
n is the number of address lines to the device. f" (XO) = 2/X03
Since n is fixed for the PLE device chosen, and 11' is a Say XO is 8-bits long and the first approximation of the inverse
constant, for the look-up table 1I'/[2n + 1]is a constant. is found using a 256x8 PLE device. The first approximation
Therefore, if the sine function of a given x is to be found, x will can be obtained by subtracting (X - XO)/(X02). Since the first
first be multiplied by the constant [2n + 1]/11' and sent to the approximation is limi.ted by an error of approximately (X -
address of the PLE device to get the final result. XO)2/X02, and if XO at least 1, the error is limited by approxi-
Cos (x) is related to sine function as sin (11'/2 - x). Thus the mately (X - XO)2. Since XO has an S-bit resolution, X - XO is
cosine function can also be found in the same manner by represented by the rest of the bits. The resolution of the
using 11'12 - x instead of just x. Other functions like tangent, second approximation Will be about 1f) bits. The thirdapproxi-
secant etc., can also be found as a function of sine. mation is similarly dedUCed and has a resolution of about 32
To increase the dynamic range of outputs, we can just use bits, and the fourth has a resolution of about 64 bits.
another PLE device to generate the less-significant bits of the The in'!:;'s'? ~n:.::; 0btained is then multiplied by the dividend to
sine function. give the quotiem. .
If a larger dynamic range is needed for the inputs, the result Scaling
may be approximated using the Taylor series:
In arithmetic operations, scaling is sometimes needed. Scaling
f (X) = f (XO) + f' (XO) (X - XO) + 1/2f" (XO) (X - XO)2 + ... normally involves multiplication or division by a constant. Ilthis
Where f' and f" are the first and second derivations of f. Since constant can be expressed in 2n where n is an integer, then
XO by itself represents a resolution of 2- n, and X is XO scaling is simply shifting. Scaling with other constants may
concatenated with the rest of the bits, X - XO must lie need a multiplier. A multiplier is more expensive and has a
between 0 and 112- n• For f (X) = sin (X), higher pin count than using a PLE device because the
f (XO) = sin (XO) constant that the operand is to be scaled by is not required as
f' (XO) = cos (XO) an input as in the case of a multiplier. This will tremendously
, reduce the overhead for data scaling.
and f" (XO) = -sin (XO)
So f" (XO) is between -1 and 0 for XO lies between 0 and 11'/2 Other Applications
and X - XO < 2- n. Therefore, the last term will be between Arithmetic look-up are also very useful for arithmetic opera-
'1/2n and 0, and as long as we do not want to expand the tions where conventional binary integral arithmetic is not
dynamic range of X beyond 2n-bits, it should be sufficient to applicable - like residue arithmetic, and distributed arithmetic.
approximate sin (X) in the first two terms:
FUNCTION TABLE
X3 X2 Xl XO Y3 Y2 Y1 YO S7 S6 S5 S4 S3 S2 Sl SO
,-oPERANDS- PRODUCTS
,XXXX yyyy SSSSSSSS COMMENTS
:3210 3210 76543210
------------------------------------------
LLLL LLLL LLLLLLLL o * 0 .. 0
LLLH HHHH LLLLHHHH 1 * 15 .. 15
BHHH LLLH LLLLHRRR IS * 1 .. 15
HHHH HHHH HHHLLLLH 15 * 15 .. 225
DESCRIPTION
S7 S6 S5 S4 53 S2 81 SO
~
. J
x y
FUNCTION TABLE
'mIS APPLICATION ILLUSTRATES THE CALCULATION OF THE ARC TANGENT FUNCTION USING
A PLE5P8 AS A LOOK-UP TABLE. OTHER TRIGONOMETRIC FUNCTIONS (SUCH AS SINE,
COSINE, COTANGENT, SECANT, COSECANT AND THEIR ARC INVERSE EQUIVALENT FUNCTIONS)
OR HYPERBOLIC FUNCTIONS CAN ALSO BE CONSTRUCTED USING PLE DEVICES AS LOOK-UP TABLES.
~ ------------~t------------
ARCTANGENT
LOOK-UP TABLE
PLE5P8
-..it.
2
V =ARCTAN X
ANGLE {
IN A--cr.-.-... F } ARC TANGENT
RADIANS 5 OFA
FUNCTION TABLE
HYPOTENUSE OF A RIGHT
TRIANGLE LOOK-UP TABLE
PLE5P8
DESCRIPTION
7---RADIUS---- -------PERIMETER-------
INTOOER MSB INTEGER LSB PERIMETER OF A CIRCLE
R4 R3 R2 R1 RO P7 p6 P5 P4 P3 P2 Pl PO 7RADIUS LOOK-UP CALCULATED
------------------------------------------------------------------------------
L L L L L L L L L L L L L 0 0 0.0
L L L L H L L L L L H H L 1 6 6.3
L L L H L L L L L H H L H 2 13 12.6
L L L H H L L L H L L H H 3 19 16.6
L L H L L L L L H H L L H 4 25 25.1
L H L L L L L H H L L H L 6 50 50.3
H L L L L L H H L L H L H 16 101 100.5
H H H H H H H L L L L H H 31 195 194.6
------------------------------------------------------------------------------
PERIMETER OF A CIRCLE
LOOK-UP TABLE
PLE5P8
DESCRIPTION
THIS EXAMPLE ILLUSTRATES HOW TO IMPLEMENT A LOOK-UP TABLE IN A PLE5P8 FOR THE
PERIMETER OF A CIRCLE AS A FUNCTION OF THE RADIUS. THE INPUT PINS (R4-RO),
WHICH REPRESENT THE RADIUS OF A CIRCLE, ARE MULTIPLIED BY 2 TIMES PI IN ORDER
TO CALCULATE THE PERIMETER OF A CIRCLE (P7-PO). THIS LOOK-UP TABLE IS VALID
FOR RADII BETWEEN 0 AND 31. A PLE8P8 SHOULD BE USED INSTEAD IF A LARGER
RADIUS RANGE (BE'lWEEN 0 AND 81) IS REQUIRED.
C), ..."
PERIMETER.
P }
OF THE
CIRCLE
T7= L3* L2* L1* LO COMPUTE DIGIT FOR 2EXP2 (4) (MSB)
+ L4
FUNCTION TABLE
PLE5P8
DESCRIPTION
THIS PLESP8 IS USED TO IMPLEMENT A LOOK-UP TABLE FOR '!'HE PERIOD OF OSCILLATION
OF A MATHEMATICAL PENDULUM. '!'HE PERIOD OF OSCILLATION FOR MATHEMATICAL
PENDULUM ('1') IS DEPENDENT UPON ITS AMPLITUDE OF SWING (L) AND THE ACCELERATION
DUE TO GRAVITY (G). THE PERIOD OF OSCILLATION IS CALCULATED USING THE
FOLLOWING EQUATION:
THIS EXAMPLE DEMONSTRATES HOW EASY IT IS'TO CONSTRUCT LOOK-UP TABLES FOR
COMPLEX ARI'l'HME'l'IC FUNCTIONS USING PLE DEVICES
PERIOD'OF }
LENGTH { ~ OSCILLATION FOR A ...!.L.- PERIOD OF
OSCILLATION
OF PENDULUM L MATHEMATICAL'PENDULUM' - T
LOOK-UP TABLE IN SECONDS
I.************************************************
J* THIS DESIGN IS ~T YET SUPpORTED BY PLEASM *
I.************************************************
V C:+: C3 ; OVERFLOW
Z = /C3*/C2*/C1*/CO ; ZERO
DESCRIPTION
THIS ALU CAN PERPORM 8 FUNCTIONS ON TWO 4-BIT OPERANDS A (A3-AO) AND
B (B3-BO) WITH CARRYIN (cm) AND GIVES A 4-BIT RESULT C (C3-C0) WITH
CARRYOUT (C). IT WILL ALSO GIVE STATUS AS OVERFLOW (V) AND ZERO (Z).
THE FUNCTION IS DETERMINED BY A3-BIT FUNCTION SELECT CODE (S2-S0):
ARITHMETIC LOGIC UNIT
MOOE S2 S1 SO FUNCTION PLE12P8
---------------------------------- vcc
0 0 0 0 CLEAR
1 0 0 1 B - A - 1 +cm
2 0 1 0 A - B - 1 + CIN
3 0 1 1 A + B + cm 82
4 1 0 0 A XOR B
S 1 0 1 A+B
6 1 1 0 A* B ii
AO
7 1 1 1 PRESET
---------------------------------- AND
OR
CIN
GATE
A2 ARRAY E1
NC
C2
GND co
a7 a6 a5 a4 a3 a2 a1 aO =A
b7 b6 b5 b4 b3 b2 b1 bO =B
c7 c6 c5 .c4 c3 c2 c1 cO =C
d7 d6 d5 d4 d3 d2 d1 dO =D
+) e7 e6 e5 e4 e3 e2 e1 eO =E
81 and 80 are just h11 and h10' 810-82 can be obtained It needs four PLE10P4 devices, two 748381 ALUs and one
through addition of other bits. The hardware implementation is 748182. An alternative is using ten 748381 ALUs and four
as follows: 748182 Carry Lookahead Generators.
4
G2
4
G3
4
G4
.1008-06 _.1-00
B000070M
FUNCTION TABLE
ABC D E F G p2 Pl PO
PPP COMMENTS
;A BCD E F G 210 A+ B+ C + D+ E + F + G =P
L L L L L L L LLL 0+0 + 0 + 0 + 0 + 0 + 0 =0
L H L H L H L LHH 0+1 + 0 + 1 + 0 + 1 + 0 3
H L H L H "L H HLL 1 + 0 + 1 + 0 + 1 + 0 + 1 =
4
H H H H H H H HHH 1 + 1 + 1 + 1 + 1 + 1 +1 =7
DESCRIPTION
A
B
C SEVEN
D l-BIT
E INTEGERS
F
+ G
---
SEVEN 1-BIT INTEGER ROW
P2 PI PO PARTIAL PRODUCTS ADDER
3-BIT PLE8P4
RESULT
10-60 MonolithicW"Memories
Wallace Tree Compression
P3,P2,P1,PO = A1,AO .+. B1,BO .+. C1,CO .+. D1,DO .+. E1,EO P -A+B+C+D+E
FUNCTION TABLE
A1 AO B1 BO C1 CO D1 DO E1 EOP3 P2 P1 PO
;M BB CC DD EE PPPP COMMENTS
;10 10 10 10 10 3210 A+B+C+D +E - P
-----------------------------------------------------------
LL
LH
HL
LL LL
LH
HL
LH
HL
LL LL
LH
HL
LLLL
LH
HL
0 + 0 + 0 + 0 +0
LHLH
HLHL
0
1 + 1 + 1+ 1 + 1 .. 5
2 + 2 +2 + 2 + 2 .. 10
HH HH HH HH HH HHHH 3 + 3 + 3 + 3 +3 15
DESCRIPTION
Al AO}
Bl:B° FIVE.
C1 CO 2·BIT
Dl DO INTEG.ERS
+ E1 EO . .
FIVE2-BIT INTEGER ROW
P3P2 PI PO PARTIAL PRODUCTS ADDER
'-.-'
4-BIT PLE10P4
RESULT
"',.....
10-61
Wallac•. Tr•• Compr•••ion
FUNCTION TABLE
A2 Al AO B2 Bl BO C2 Cl CO D2 Dl DO P4 P3 P2 PI PO
DESCRIPTION
5-81T
RESULT
10-62 MonoIlthlC.mMemorllltl
Wallace Tree Compression
FUNCTION TABLE
A3 A2Al AD B3 B2 B1 BO C3 C2 C1CO P5 P4 P3 P2 P1 PO
=12
3
6
DESCRIPTION
P5 P4 P3P2 P1 PO
.... .rII
6-81T
RESULT
10-63
Residue Arithmetic using PLE Devices
MoIIoIithlcm.Metnortes 10-65
Residue Arithmetic Using PLE Circuits
Figure 1. Architecture of an RNS This method of expansion is not effective with bigger integers.
If the integer is N-bit and the PLE address space available is
M-bit. then 2N_M sets of PLE devices will be needed. BeSides.
as the dynamic range increases. the width of the outputs will
also increase about proportionally. An alternative method is to flow. It is sometimes necessary to add some other moduli to
use two or more levels of PlE devices to generate the boost up the dynamic range for the intermediate calculations.
residues. The first level generates the remainders from the Arithmetic Operations In RNS
more significant bits of the integer and the products of some
The arithmetic operations of the RNS is different from regular
of the moduli. These remainders are in turns concatenated
arithmetic in that even simple addition must be performed in
with the rest of the bits to become the inputs to the second
modulo arithmetic. Simple AlU may not be able to handle this
level PlE devices.
arithmetic. Again, PlE devices are proven to be most useful. A
For example, for a 16-bit integer 43689, and let us use (2, 11, PlE8P4 device can perform addition, subtraction, or multipli-
13, 15, 23) as the set of moduli. We may choose 23, 30 and cation on two 4-bit residue numbers and give a 4-bit modulo
143 as the moduli for the first level. The first level consists of result.
PlE12P4s and PlE12P8s which generate the remainders of
the most significant 12 bits of 43689 which is 2730. We know
that 12730123 will be at most 22 and can therefore be repre- -c
sented by a 5-bit number; 127301,5 will be at most 14 and can
be represented by another 4-bit number; and 12730h 43 will be
at most 142 and can be represented by a 6-bit number. The 5~
bit number represented by 12730123 will be concatenated with Figure 5. Calculating C =A + B, A - B, B - A x BUsing
the least significant 4 bits of the integer and gives a 9-bit PLE8P4
number which can perform another division by 23 to give the
final 143689~3; the 4-bit number represented by 12730h 5 will be
concatenated with the least significant 4 bits of the integer If the modulus is large, say greater than 64, the combined
and gives an 8-bit number which can perform another division number of bits for two residues will be greater than the
by 15 to give the final 1436891,5; the 6-bit number represented number of address bits for the largest of the commercially
by 127301,43 will be concatenated with the least significant 4 available PlE device. Of course, more than one device can be
bits of the integer and gives a to-bit number which can used to deepen the effective address space. In this case, for
perform another division by 11 and 13 to give the final every additional bit of a modulus, two more bits of address will
1436891" andf43689ha. As .in the first example, 14368912 is just be needed - one for each operand. In other words, for each
the least significant bit of the integer. additional bit of a modulus the address space of operation will
be quadrupled. It is not very effective when the modulus
1_ FIRST
LEVEL
_I I-.!iECON~1
LEVEL
grows too large. Fortunately, for both addition and multiplica-
tion, there are more efficient procedures.
1-+-",->"-1 PLESP4 r--IX115
12 4 PLE12P4.
Large Modulus Addition
or 1-+4-"7''--1 PLEIP8 rlXI23 Table 5 shows the contents required for the addition opera-
2PLE12P8s 4 tions. in modulus 11. There is a lot ·of redundancy in the table
10
I
L-_ _ _S--;':........I>-:;,.<-;~I PLE10P8
LIXI,1'
! I X I, 3 which can be compressed by reducing what should be eight
bits of inputs to five bits. What we need is just another level of
'----~4'-----4---_r_----IXI2
mapping. There are a total of 121 combinations for a number
of modulus 11 operating on another operand of the same
modulus. In reality, only numbers ranging from 0 to 10 can be
Figure 4. Mapping a 16-Blt Integer X to Residues In Modulo 2, represented in modulus 11. The sum ranges from 0 to 20 (not
11, 13, 15, and 23 Using Two-Level Mapping. The First in modulus 11). This range can be represented by a new set
Level Gives Remainders from the More Significant of submoduli(3, 7) which is five bits wide. In fact, any new set
Twelve Bits, While the Second Level Finds the Final of submoduli .which has a dynamic range of at least twenty-
Residues one can be used. The operands in modulus 11 will be
converted to their representations in submoduli 3 and 7. The
addition is done in the submoduli and the result is reconverted
In some circumstances, although an N-bit integer only has a back to modulus 11 RNS (see Table 6).
dynamic range of 2N, the intermediate calculations may over-
.. 0 1 ,,2 ·3 4 5 6 7 ,8 9 10
0 0 1 2 3 4 5 6 7 8 9 10
1 1 .2 ,3 A 5 6 7 8 9 10 0
2 2 3 4 5 6 7 8 .9 10 0 1
3 3 4 5 6 7 8 9 10 0 1 ~
4 4 5 6 7 8 9 10 0 1 2 3
5 5 6 7 8 9 10 0 i 2 3 4
6 6 7 8 9 10 0 1 2 .3. 4 5
7 7 8 9, 10 0 ' 1 ~ 3 4 5 6
8 8 9 10 0 1 2 3, 4 5 6 7
9 9 10 0 1 2 3 4 5 6 7 8
10 10 0 1 2 3, 4 5 6 7 8 9
,
x+y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
\x+ y!11' 0 1 2 '3 4 5: 6 ., 8 9 10 0 1 ' 2 3 4 5 6 7 8
20
9
Ix + yj7 0 1 2 3 4. 5 6 0 1 2 3 4 5 6 0 1 2 3 '4 5 6
Ix + YI3 0 1 2 0 1 2 0" 1' 2 0 1 2 0 1 2 0 1 2 0 1 2
; "
Table 8. Conversion Table Batw. .n Modulo 11 ArHh"etlc and ModulO 3 and 7, Arithmetic
FIgure 8. CelCulBtlng AddItIon of TWo Numbers InModll1o 11, U.lng Subrilodull Opilratlona
Large Modulus' Multiplication sentedas the residue of the two smaller integers'instead of.
The solution to this problem in multiplication is similar. For using them as submOduli. .
example, if two RNS digits in modulus 91' is to be multiplied,
(7, 13) may be chosen as a set of submoduli. Therepresenta-
tion of an RNS digit in modulus 91' needs 7-bits. These 7-bits
are first mapped to two RNS digits - in mOdulo 7 which
needs 3-bits; and in modulo 13 which needs 4-bits. The
representations Of the two operands in the two moduli can
then be multiplied and give the result in modulo 7 and modulo
13. The result Is then converted back to modulo 91. Unfortu-
.nately, this scheme can be used 'only when th~,modulus can
Figure 7. calculating Multiplication of Two Number. Iii Modulo
be expressed as a product to two Integers which are relatively 91 Ullng Sublilodull Operatlona
prime. But, In this Case, the RNS digit may simply be rep~
10-68
Residue Arithmetic UsingPLE Circuits
Suppose another modulus 101 is used. 101 is a prime number 3. Find X = 1><111 + ~t2 + ... + xn - 1In - 11 M
and fiNS in modulus 101 ranges from 0 to 100. The real In hardware implementation, ti's are all known beforehand.
dynamic range of the product of two numbers in modulus 101 We can map xi's to get the xiti's.Then we may perform
is 0 to 10000, which is already too large for a PLE address Wallace Tree Compression (see the session on this subject in
space. For this modulus, we may use three 4K-deep PLE this handbook for more information) on the xiti's to give two-
devices to deepen the address space. For a modulus like level operands which add to the final sum and divide it by M to
1001, it may not be too efficient to use this scheme. Instead, get X. Again, PLE devices provide the best solution for
since: Wallace Tree Compression.
xy = [(x + y)2 - (x - y)2]/4
or = [x + y)2]/4 - [(x - y)2]/4.
we may do x + y and x - y first and then do the squaring of
the sum and the difference scaled by a factor of 4. Since the
final product of two integers must be an integer, the squaring
and scaling may be performed in one operation with the
fractional part discarded. The way to obtain x + y and x - y is Figure 9a. Reverse Mapping to Get XI~
the same as what was discussed earlier in the "Large Modulo
Addition" session.
In any event, operations on residues of large moduli are xx •• xxxx.xxxxxx
slower and involve more hardware and are not recommended.
xxxxxxxxxx.xxxx
wwwwwwwwwwwwwwwwww
wwwwwwwwwwwwwwww
Conclusion
The Reverse Conversion Memory elements provide excellent solutions to mapping
The reverse mapping from RNS to integer is not as straight- functions - for control purposes, for arithmetic operations
forward as the other way. For an RNS system which has a and general logic replacements. This paper investigates the
total of twelve bits for all the residues, we can still use 12- possibility of using PLE devices as arithmetic units. In fact, for
input PLE devices to convert. We may also use several sets of logic like residue number arithmetic, there is no better solution
12-input PLE devices to reverse map the RNS if the integer is than to use these devices.
not much longer. But for very long integers, we may need to Acknowledgement
use the general algorithm for the reverse map: Portions of this article were extracted from "Integer Arithmetic
1. Find M = ml x m2 x ... xmn _ 1 (where n is the number Using PROMs" by Dr. G.A. Jullien of the University of
of moduli) Windsor, Canada.
2. Find ti = Mimi
MonoIlthlcWMemor/ea 10-69
Disttibut... Arithmetic Using PLE~Devices
Distributecl Arithmetic Using PLE Devices address lines if we want to use only PLE mapping. Since' 20
bits of address 'translate to 1M words, and there is no
In digital Sign&! proCessirig;sum:ef~prOducttypEiOf operations
available 1M-deep PLE device on the market, it is not realistic
are
"
often
.,.."
neCeSsary;
-", ,
These'
.. . ,
operations
.'." " ..
take" the form
.
of:., '
'~' to use PLE mapping. Instead, H (j) can be partitioned as
follows:
'Y'" ,,1:, ¥r where 8;'s are some constants,
20
L..,O
H (j) :E 8;X; (j) forM .. 20
If real multiplications are to be p8Hormed on every prOduct i .. 1
term, it will need a total of M ,multiplications and M-1 additions. 10 20
Multiplicationoplwmions nOrmal,lf. taks"mliCh longer than sim- = 1: 8;X; (j) + E II;xt (j)
ple addition. An alternative ,to, calculate equations of the above 1= 1 i'" 11
form is by using distrib~ arithmetic.
the20-bit address can be Separated to two 10-bit addresses
Suppose there is an N-bit, int~e.. X· given by: and each of them is individually mapped. The two outputs will
x = [x(N - 11, x(N-2), .."x(1),x(0)] then be added together to give H (J). An Implementation of
or equivalently:' ,:;'jA, ~.'" ,:,,' : this mapping Is shown in figure 2.
N-1
x'" Z X(j)2J".
j ... 0 XtJ) '0
where x(N - 1) is ,the most significant bit The equation: X,OcJ) H(J)
M " " Xl1 (J) '0
Y- 1: 8jXj
i- 0
~J)
can be expressed as:
y= j ~ ·.·~·(~=i:~0>2j)'
1
Figure 2. Mapping the ~ Bit of Each of lIj'. to an L-blt Reeu"
~1 (.~,
When There Are T~ Many x'. (20 In Thl. Ceae)
N 2i 8;X1(j))
j =0 1=,1
Now, let: There is another alternative for impl!tme~l)g asum:ef-prOduct
operation: by using a multiplier accumulator (MAC). '
M
The main, constraint on distributed arithmetic is that one set of
H(j) ... 1: 8jXi(j)
the multiplicands musttle fixed, i.e: ai's in this eSse, for the
i-1 sum.of-prOduct mapping whiie, a MAC will allow flexibility. '
Since H (j) is independent of ia~d siocJ al's are all constants,
There are normally SOme constraints on the width for the data
we precompute for every x(j) = [x,(j). x20>"':' xM(j)l the values
bus from which the operands are loaded. If all the operands
[x,(j). x2(j) ..... ~(j)] the values of H 0); Then x6rca" be used
are new. it will OEIed M cycles to load in the operands anyway,
as the address of.PLE:devJces·whose'outputs ar.ethe precom- dis,tributed arithmetic .offers no advantages over MAC, since
puted result H(j). ;:
distributed arithmetic needs to wait for all the operands to be
loaded in before any operation can start while' MAC can
X,(J), •.. , l I u ( J ) 4 ~NG ~ L-IIITRESULT perform a multiplication and an addition every cycle. M cycles
will be needed anyway for the complete operation using a
MAC while distributed arithmetic may take even longer.
On the other hand, for operations like convolutions where one
r
Figure 1. Mapping the h Bit from Each of the lIj'. to An L-blt set of operands are fixed and only one new variable operand
Reau" is needed for every result, distributed arithmetic will be a
better solution since it can give a result in every clock-cycle
while a MAC will need M-cycles (because recalculations of ' all
If th,ere are M bits of data and the result is L-bit wide. and if M the prOduct terms are necessary). An implementation for
is very large, say 20, and L' is 8, Jhen we need 20 bits of convolution is shown in Figure 3.
1(10.70
Distributed Arithmetic Using PLE™ Devices
Note that the second term of the last equation means that the
INPUT previous result (Yi _ 1) is shifted right one-bit; the last bit of
Yi - 1 is truncated.
The implementation of such a system is shown in Figure 3.
The system consists of a shift register, a mapper (PLE circuits,
or PLE circuits with adders), an accumulator, and an ALU.
M
MAPPER
Registered PLE Devices in Pipelined The introduction of the registers for the pipeline increases the
operation time of every block due to the addition of the setup
Arithmetic times and the clock to output delays. The result is as follows:
PLE devices are useful as logic elements, and registered
1) Overall delay. The architecture in Figure 2 will need at
PLEs are excellent media for pipelined arithmetic. Monolithic
least an additional 2 setup time and 2 clock to output
Memories supplies a number of registered PLE devices which
delays of a register. In real, it will be more, because the
provide effective solutions to pipelined systems. •
minimum clock period will be determined by the sum of (i)
A data processing system may have fall-through architecture. the maximum of the operation times of individual blocks,
Since many of these operations may take a long. time, it and (ii) the setup time of the pipelined registers aria (iii) the
happens that the devices are not often tied up in operations. clock to output delay of the pipelined registers. Symboli-
For example, in a system as in .figure I, the operations can be cally, the. overall delays for the architectures in Figures 1
divided into three functional blocks; When the operands are and 2 are:
loaded in, block 1 will operate first, followed by block 2 <lnd
tpd (Fig.l) = tpd(blk 1) + tpd(blk 2) + tpd(blk 3)
then by block 3. When the data is in block 2; block lis not
doing anything. We cannot at this time put in the next set of tpd(Fig.2) = 2x( max[tpd(blk 1), tpd(blk 2), tpd(blk 3)]
operands because changes in operands may disturb the + tsu + telk } + tpd(blk 3) ".".
operation in block 2. Where tpd(Fig.l) and tpd (Fig. 2) are the propagation "delays of
the architectures in figure 1 and figure 2 respectively; tpd(blk
.,-------, --r- 1) tpd(blk 2), tpd(blk 3) are the propagation delays of block I,
BLOCK 1
...------1
BLOCK 2
-+-
tpd(blk 1)
Ipd(blk 2)
block 2,and block 3 respectively; and tsu and telk are the
setup time and clock-to-outputdelay of the registers respec-
tively.
1-----1+ 2) Throughputs ot clockr.l!te. The architecture in figure 1 has
BLOCK 3 Ipd(blk 3)
a throughput period of (tpd(blk 1) + tpd(blk 2) + tpd(blk 3) +
1..-.---,..--' ~""" tsu + telk), assuming that the operands are coming from
and the result is going to some registers; the architecture
Figure 1. An Example of the Fall-Through Approach to in Figure 2 has a throughput period of (max[tpd(blk 1),
Arithmetic Operation tpd(blk 2), tpd(blk 3)] + tsu + t elk) which is faster.
PLEdevices are useful as ~ogic elements, and registered PLE
devices are excellent media for pipelined' arithmetic; Monolith-
A solution to this is by registering the operands and signal ic Memories supplies a number of registered PLE devices
paths when the operations is switched to block 2; and by which provide effective solutions to pipelined systems.
registering the operands and signal paths again when the Applications for pipelinearithrTielicinclude" array and digital
operations is carried out in block 3. The result is stated in signal processing.
figure 2. This architecture is called the pipelined structure. It
makes the loading of the second set of operands possible
even before the first result is out, thus increasing the through-
put.
BLOCK 1
REGISTER
BLOCK 2
REGISTER
BLOCK 3
10-72 MonoIlthlcWMemories
General Applications
Table of Contents
Article Reprints
Table of Contents for Section 11 ........................................................ 11-2
Testing Your PAL Devices .............................................•................•• 11-3
PAL20RA10 Design for Testability .................•.....•............•................. 11-8
PAL Design Function and Test Vectors .............................................. 11-10
Metastability .•.••••.•..•••....•.••....••• ,. . •.• .••• •• •• . •• • •• . •••• •. . .• . •• . .. .. •.. . ... .. •• .. 11-13
High-Speed Bipolar PROMs F;i!)d New Applications as
Programmable Logic Elements .................................................... 11-17
. . ABEL™a
.. TM Corriplete . . . To.01 for Programmable Logic .....•.•.....•...•... 11-25
.. .... Design
CUPL the Universal Compiler for Programmable Logic ..•.•............••.... 11-29
:tHIlI~
software'. a Fortran IVptogram whlch-,assembles anO-8im.
ulates PAL circuits design sPec:iflcatlo~. I~ generates pAL cir-
cuit fuse patterns In formats compatible with PAL cir«;uits or
PROM programmers. '
Besides generating I?AL circuit fuse pattern i~ different pro- fig.... 2. I.oglc DIagram and It'a PAL Circuit IrnpIemIntatIon
Testi",g Your PAL Devices
Ideally the output should always be high if both inputs are high.
ABCDEFG The circuit is not glitch-free, the output might momentarily
(vector-2)
0000000 drop to low if we change the state orx, due to propagation
delay between X and x:
As it can be seen that both of the product terms are low, if the The problem will be solved by including a redundant (AB) term
observed output is high, one can conclude that either product to (eq-2).
terms or outputs are Stuck-at-one. The equation will look like this.
Fault simulation grading is used by Monolithic Memories to
evaluate candidates design for transfering from a PAL circuit to F=XA+XB+AB (eq-2)
a HAL circuit.
In designing with PAL circuits, four different cases should be The output is glitch-free, but untestable!
considered.
1. A purely combinational circuit where output is function
of input.
2. A purely combinational circuit where output is function
of input and feedback from output.
3. A purely sequential logic where output is function of
input and feedback from output.
4. A combinational-sequential logic where output is func- Figure 5. A Glltch·free CIrCuit
tion of input, feedback from combinational output and
feedback from sequential output. Node (2) is not Observable for (SAO). One can not force node
In cases 1 and 2. we can define a structured way of writing (2) to one and keep node (1) and (3) in the low state. So the
function table. Cases 3 and 4,on the other hand, because of redundant product term is untestable.
dependency of the device on the previous state of the device,
This circuit can be made testable by the addition of control
impose a relatively. more sophisticated scheme of testing
Signal (V) as follows:
strategy.
In the following examples the various techniques which might
be helpful in testability of PAls, will be discussed.
X~ A
B
.... l
.. 2
F
.......... .
iii
B
0
~1
(~1
0 f1\
\fj
0
0
Example 2: Unte.table Logic - A Simple
Example
- The logic F := Fis untestable
A A A
11-4
Testing Your PAL~"ices
The initial state of the oscillator is unknown; this system can be Example 4: Design "Pitfall" Caee Two
made testable as follows: COnsider the implementation of the following equation:
00 =A*01*QO + A*01*00 + 00
-~
~~
SET .'
DQ
C
Illegal Statee
Upon power-up the initial state of output registers are unknown; .
this might force the device into one of the "illegal states". Figure 12. Implementation olQO = A'*Q1*QO + A*Q1*QO + QO
The design engineer should be worried about the illegal state at
design time. For example let's look at modulo-6 state machine If O"D goes to one it will stay there forever, the logic needs a
control ~gnal ,~o clear it's output.
O
··'~fD Hard Array Logic (HAL) Devices
The HAL device is the Hard Array version of a,PAL device.
52?
HAL logic circuits are the best choice. for d$$lgns that are firm
4 3 and volumes are large enough to justify ttie initial cost. Besides
having Boolean equation in PAt. ,DESIGN SPECIFICATION
figura 9. State TranIItIon DIagram for. Modulo-6'Counter forinat the User should proyidetl1e follOWing:
3.
the illegal states into one of the known states. .2. The FUNCTION TABLS.sh~J be constru'cted s~,ch that the
devicemaY:be initillzecHo altnOWf! state within a specified
number of steps (or clockst.:,'
6
o 1
...•......
5 . 2
,'The HAL CIRGUIT SPECjF,'ICATION Isthe!np.,.t file used with
PALASM software for the HAL's. The input format as shown in
4 3 . example 5 is as follow:
~Lin~ 1 HAL cil'Cl,lit: part number "
figura 10. A MOduIoS Counter wl1h No Illegal State. • Line 2 'use~lllla~ nUIn~i)Oli(jwed .byorigi~ator's name
and the date "
Example 3: Design "pitfall" Caee One • Une 3 deVice application name
COnsider the implementation of the following example
• Line 4 user'.s company name. city, stata
01 := 11 • 01
• Line 5 pin list which is a sequence of symbolic names
. ''.• ~ !.• . ,
separated by one or mOf"Ejspaces. AI.I pins including VCC
and .GND must Pe~ed(
11~_~'·'··'.·.
metal masks from ,th&provided equations·,'
- -; ' -...
- . - - - - 0 .
10 "II+/J+/K 1
I 'D!Rl!Z PRDlCl'TEl'Hl: '1
N1IND.GM'E (l1X2 -4)
(II) , t2VJ), t3(/K)
PDNCrICN 'D\BtE
ABCDEPGSIJ1'I:LMNOPQR
II!SCMPl'ICN
'mE MI\IN PURPCSE OF 'mIS El!l\MPIE IS '.to !2IMILIARIZE
'mE USER w:rm
l'IIAT WI!;' MElIN. BY "PDNCrICN 'D\BtE",
PRDlCl' T!3t(P1') CXl!lERi\GE, S'lUCK-A'l'-O (SAO) AND
sm:K-AT-CNE (SAl) 'l'ESTS.
EXAMPLE 5
• Line N the function table which begins with the key word The allowabl.e states are H (HIGH LEVEL), L (LOW LEVEL),
"FUNCTION TABLE:' It's followed by a pin list which may X (IRRELEVENT), C (TRANSITION FROM HIGH TO LOW
be in a different order and polarity from the pin list in line 5. OR CLOCK PULSE) and Z (HIGH IMPEDENCE). After
VCC and GND cannot be listed. The pin list is followed by preparing the PAL DESIGN SPECIFICATION in the,above
dashed line; e.g.; ____ which in turn is fOllowed by a list format, PALASM software can be used to simulate and
of vectors, one vector per line. One state must be specified perform fault testing.
for each pin name and optionally separated by spaces. A
vector is a sequence of states listed in the same order as the
pin list and followed by an optional comment.
11-6
Testing Your PAL Devices
BllSIC GPmS
1 XXXXXXXXXlCccocl
2 XXXXXXXXXXXlCIX
3 llXXXXXXXXXXXXX
4 OOXXXXXXXXXXXXXX
5 XXlOXXXXXXXXXXXIIXX
6: XXOlXXXXXXXXXXXBXX
7 XXOOXXXXXXXXXXXLXXX
8 XXXXXXXXOXl.lBX
9 XXXXXXXXlXOllIXXXXXXl
10 XXXXXXXXlXlOllXXXXXXl
11 XXXXXXXXlXllLXX
12 XXXXOOXXXXXXXXllXXXXl
13
14
XXXXllXXXXXXXXL
XXXXXXlOXXXXXllXXXXXl 1:=1 O=--~--,
P=*
PASS SDIlIATIQI
PHDlCl': 1 OF EOOATIQI. 6: tlN'mSTED(SAl)FAllLT
~ I R=P.Q+P.O EO-6
PlOXlCl':
PlOXlCl':
2 OF EOOATIQI.
2 OF EClJATIQI.
6: tlN'JES'lm)(SAl)FAllLT }'
6: mm;sTED(SAO)mtlLT
.....----1
.
P*O
.. 85'
FAULT-TESTING
11-7
PAL®20RA10 Design for Testability
Edwin Young
This article is written to help customers of the PAL20RA1 The latch problem described is not unique to the 20RA10 but is
recognize some fundamental design-for-testability issues which clearly applicable to any PAL with asynchronous outputs with
may arise due to the part's unique architecture. Customers feedback (e.g., 16R4). The designer should realize, however,
should understand that these issues represent design criteria thatfalse latching may occur on a 20RA10 even if all outputs are
which Monolithic Memories will use to accept PAL20RA10 registered. Consider the equation setO:= C and D.CLKF = A'B
patterns for test generation/fault grading and for estimating the for a simple registered 20RA10 output. The resulting waveforms
resource cost to test engineering if accepted. This article does would look similar to those of the previous. asynchronous
not address the BUSINESS REQUIREMENTS such as the need example. The important distinction here is that a 20RA10 has
for acceptable test vectors and the acceptability of a particular programmable asynchronous clocks rather than a Single 'master
pattern for processing as a HAL@ device. clock' pin which can cause difficulties in testing.
The designer who wishes to use a 20RA10 in his/her design must
bear in mind that although the part has preloadability, certain
designs could diminish the effectiveness of this feature. The
Allow Data to Setup Prior to C,ocking
following rules are presented to help establish Test Engineering The previous two pitfalls were examples of flaky latching due to
acceptance standards for the 20RA10. Additional general guide- glitches during testing. Consider the equation set C := Band
lines applicable are available in the PAL Handbook article reprint C.CLKF = A for a registered output. The following example
"Testing Your PAL Devices" by M. Vafai. shows a definite positive latching ...but of flaky (skewed) data.
Introduction
This article was written to help customers understand the pur- The following simple example demonstrates how exercising
pose of seed vectors and provide some general guidelines as to seed vectors might be derived from a deSigner's state diagram:
what elements are important in developing them. It is assumed
that the reader has read the "PALASM'" Manual" and the "PAL@
Handbook" article reprint Testing Your PAL Devices. E9
In general, PAL@/HAL@ devices are required to provide a func-
tion table or "Seed Vectors" to Monolithic Memories in order to
ensure that parts shipped have a high degree of reliability for the
application intended. Ideally, these vectors should accomplish
three objectives: ,
1) Initialize the PAL device preferably in the same way as in
the actual system; E4
2) Exercise the customer's functions thoroughly, emulating
actual system operation as closely as possible;
3) Provide a high degree of fault coverage.
Initialization Assume the following state and edge definitions accompany the
Seed vectors which initialize the PAL logic circuit consist of one diagram:
'or more vectors placed at the very beginning which will bring
STATE 0 = LL EDGE 0 = LL
both combinatorial and registered outputs to a stable and known
STATE 1 = LH EDGE 1 = LH
logic state (1 orO). This is necessary in the system also so that its
STATE 2 = HL EDGE 2 = LL
operation upon power-up is predictable. Furthermore, care
(ILLEGAL) STATE 3 = HH EDGE 3 = LH
should be taken to ensure that the initialization state is a legal
EDGE 4 = LL
state of the state machine for which the PAL device is intended.
EDGES= HH
(INITIALIZING) EDGE 6 = HL
(INITIALIZING) EDGE 7 = HL
Exercise Functions (INITIALIZING) EDGE 8 = HL
(INITIALIZING) EDGE 9 = HL
The essential functions for which the PAL device was originally
designed must be exercised fully. This will assure thatthe tested
parts work the way they were intended to. In addition to essential From the above information, it is possible to create the truth
"designed-for" functions, it is prudent to include general test table for the diagram and then the function table representation:
exercises such as verifying that outputs don't change in the
absence of clock pulses and checking to see that inputs in the
"don't care" (X) state don't produce adverse responses. General
test exercises help to reinforce the validity of a deSign and can EDGE PRESENT STATE NEXT STATE
uncover overlooked design errors. After a set of exercises, has
AB CD CD
been decided upon, the next step is to write them in a format
suitable for simulation purposes. HL XX LL
The designer may have originally defined the functions in terms HH LL HL
of equations, state diagrams, truth tables, etc. Truth tables are
readily reformatted to PALASM1 syntax "Function Tables" and LL HL HL
exercises with the simulation option (code=S). State diagrams LH HL LH
can be converted by expressing each state and input edge in
binary vector format and sequencing them according to the LH LH LL
diagram's flow. The customer should become thoroughly LL LL LH
fam iliar with the syntax ofthe function table description (see the
PALASM Manual for a detailed treatment of syntax) before LL LH HL
attempting to translate truth tables, etc.
As can be seentrom the aboveel«lmple, given the same seed can improve the coverage significantly. For theabOlie example,
vectors, PALASM1 softWarewQuld shov" 100% coverage whereas the reader can verify that the following slight modification ofthe
"TGEN" would show"31% coVerage. Notice'that'the pOor seed vectors would yield 100% coverage for all calculation
coverage by "TGEN" is due to none of the input nodes being methods:
a
tested for stuck-at-f. ·In most histances, better set of test vectors
A B C D E F G H I
VECTOR 1 H H H L L L L L L
VECTQR,2 L L L H H H i:. L L
VECTOR 3 L. L. L L L L H H H
VECT9R4 L H H L H H L H H
VECTOR 5 H L H H L H H L H
VECTOR 6 H H L H H L H H L
11-12
METASTABILITY
A Study of the anomalous behavior of synchronizer circuits
Danesh M, Tavana
SYNCHRONIZERS
The design of a synchronous digital system is based on the assumption
that the maximum propagation delay ot a flip-flop and any other gates
are known. A digital system is free of hazardous race conditions and
timing anomalies if the maximum propagation delay in the system
does not exceed the clock's period. In systems where an asynchronous
input is intertaced with a clocked device suCh as a tlip-flop, the
maximum specified propagation delay of this device may no longer
be valid if certain electricat parameters are violated. Computer
peripherals, an operator's keyboard, or two independently clocked
subsystems are instances where there is a possibility oj inteliacing an
asynchrono1.)S input which will violate the synChronizer's electrical
parameters.
A populardevioe typically used in synchronized sysletrlS is the
edge-triggered register shown in figure I. The edge" triggered register
will properly synchronize the incoming data to the system's clock as
long as its Operating condHions are satisfied. Table I summarizes these
specilications torMonolithic Memories Inc:s(MMI) 74LS374 register II is
difficult to guaranteesetup and hold time requirements whE!n the data
is asynchronously inteliaced to a register. The ViOlation Of setup or hold
time in a register has a probabtiity of initiating a misbehavior termed
"Metastability:'
CLOCK
WHY THE SYNCHRONIZER FAILS
Belore attempting to explain how the synchronizer's Internal circuity
fails.!et's take a look at an interesting problem.
, CLEAR PROBLEM: In the SR type latch shown in figure 4 what happens if the
set (S) and the resel (R) inputs are simultan\30usly raised Irom a LOW
Figure I voltage level to a HIGH level?
TWX: ,8l0-aall-2378·
Montlllthlclltl.n
2175 Mission College BOUlevard, Santa Cla~a, CA 85050 Tel: (408) 870~9700 TWX,: 810-338-2374 MemorIes LnJrW
11-13
Metastability
ANSWER: The outputs will be in a stable state of HIGH prior to the RS METASTABLE DETECl'OR
transition and will quickly oscillate to a final steady state of either HIGH This section will show how to characterize the behavior of an edge
or LOW (see figure 3a).1b demonstrate·this result the reader is triggered flip-flop with an asynchronous data interiace. If the setup and
encouraged to do this excercise either mentally or to actually build the hold times of the Dip-flop are satisfied the output behaves properly
circult and view the output on the oscilloscope. (figure 60). One of the four possible events below can take place if the
Dip-flop goes metastable:
I) The output staris to make a transition but snaps back to its original
(SNS/DIv.IV/DIV) State (figUre 6b). '. ,
r-"\
\ 2) The outputm:ixkes a ccmplefe'transition but ihemaxlrnum propaga-
:tion del<lY ()/the device is exceeded (figure Qc). '
"\.
(a) CROSS-TIED NANDGATES (b) REGISTER WITII NORMAL BEHAVIOR 3) The outpU\stdrfs oscillating and retains its present state (figure 6d),
4) The output oscillates to a ne,,! state (ligO.fl16e).
(SNS/DIv.IV/DIV)
I J
'#fff"'"
AI
~
(b)
R----r-"""I
(c)
s-----L._..J (d)
Figure 4
(e)
Figure 6
10' fCLOCK=4MIIz
MAX loATA=IMHz
10'
~
~ 10'
~ 10' FAIRCHILD
~ 74F374 .
I'" 10'
10'
10"
10 15 35 40 45 50
CD JITTER BAND SlMULATESAN ASYNCHRONOUS DEIf:A.VlOR
CD METASTABLE OUTPUT Figure8a
CD PROPER OUTPUT WAVEFORM
(Dl>.CI.OCX SAMPLES THE OUTPtrr (Q)AFTERA DELAY!::.
10' fct.ocx=4MHz
MAX
loATA=IMHz
Figure 7
10'
G
fj!
I
If the output of the device goes into metastability it will be detected by 10'
the comparator pair (U2) and (U3). The comparators will have comple-
mentary outputs if the output (Q) of DUT is anywhere between VIH and
10'
VIL. The outputs of the comparators are latched by a delayed version of
the clock (l>Qock). The EXCLUSNE-NOR gate followed by the register ~
~
signal the event of metastability to an external counter.
The variable delay (l» between the two clocks will sample the output 10'
al various locations on the time axis. As this delay is varied the event of
metastability is sampled and counted at these locations by our circuit.
~
Therefore the output of our Circuit measures the rate of metastability 10'
versus time delay The reat behavior of a metaslable output can thus be
effectively characterized with this scheme. that is. we can determine the 10'
length of time a metastable condition will persist and the density 10
distribution of the melastable event.
Three 74374 devices and four PAL devices are used in this experiment.
The plots of metastable failure versus time are shown in figures 8a.b. The Flgure8b
next section will discuss in detail the characteristics of these plots.
Let·s take a closer look at one 01 the graphs to examine the behavior In the above equation the MAX value is representative of the
01 the devioe. The PALI6R4A-4 device exhibits one count per second H the maximum metastability failure rate in our device. This MAX vatue
delay (<1) ts 60 nanoseconds. As the delay (<1) is decreased. the rate is closely related to the frequency at which a metastable condition
Increases exponenUally untU the delay Squats 32 ns at which point the may occur in our device. The frequency at which metastability OCcurs
rate fiaUens out and remains fixed. The 32 ns fonns the knee of our is simply a constant multiple of the product of CLOCK and DATA
graph and will be referred to as <10. The rate will remain oonstant Uthe frequency
delay (<1) is decreased past the knee of our graph. FUrther reduction in
the delay will place the sampling clock's rising edge prior to data MAX = Kl • fCLOCK' fDATA
tronsItions and thus the error rate vanishes to zero. The t1me at which the
rate goes to zero is marked with an (X) on the graphs. By using this l1me
(X). and another location on the graph such as the l1me where orily one SubstituUng this in our ortgtnat equation we get:
error per second occurs. we can associate an approximate range of
a • In FAILURE = a' In(KI'fcLOC!{"fDATA) - b('" - "'0)
metastability for diUerent devices. This range of metastability is referred
to as the "mean l1me to snaP out of metastability". Prom tlie graph it is In FAILURE = In(KI'!cLOCK ·fDATA) - b/aC'" - l>o)
evident that the mean l1me to snap out of metastability lor the PALI6R4A-
410gtc cJrcuit is the diUerenoe between 60 ns and 25 ns which is 35 ns FAILURE = (KI'!CLOCK'fDATA)e- k2C l>-AO)
PALl6R4 EXAMPLE
For the hardware implementation in figure 10 determine the maxi-
mum clock frequency to give a typical error rate of one failure per year.
We must choose the minimum period to give an error rate of less than
PALI6R4A
--
CLOCK-.J~==~---_--.J
CLK-OUT= 15ns
Figure 10
-.-
Tee = SOns
-.-
setup=25ns
one fatlure per year From this result we can determine the maximum
clock frequency The time 6 in the equation below will determine the
distance between clock edges. We must determine 6 from the equation
by numerical extrapolation. The system clock's period can be repre-
sented as (6 + Tcc + setup). or plugging in the numbers it is 6 + 75.
FAILURE = (Kl' fCLOCK' fDATA) e- K2(£> - £>0)
PALI6R4A·4
and plugging in the appropriate values we have:
3.2EE - B = [(lEE -7) (l/(6+75ns» (9600)Je-[(43)(£>-37)1
PALI6R4A·2
CONCLUSION
Synchronization of two independent pulse trains is possible through
the use of edge triggered registers. The electrical characteristics of the
flip-flop are affected when the setup and hold times of the device are
violated. This misbehavior is termed "metastability" and its probability
of occurrence can be derived for a given system. The faclors which
affect this probability and the length of time which a metastable
condition persists are influenced by the technology of the device as well
as by the circuit design techniques.
An imporiant fact which needs to be stressed is that even if a register's
output goes metastable, the system may not necessarily fail if the
Figure 9 (2v/DlV, Sns/DIV) regtster snaps out in time to satisfy the system's worst case timing
requirement. The following design praclices are suggested when using
synchronizers:
Table 2 gives the three important parameters which can be used by Try to minimize the number of locations where asynchronous signals
system designers to fully characterize the metastable behavior of the enter your system.
mentioned devices. These parameters Can be obtained for different ClOCking the aSynchronous inputs through tWo pipelined registers can
devices by duplicating this experiment. An example is given below to greatly reduce the error rate.
show how the information on table 2 may help the designer in the Use a single clock within your local system environment. For multiple
design of asynchronous systems. system clocks, derive ail the clock signals from a single source to assure
synchronization between different devices within the system.
When anaiyzing the worst case timing of your system. add the time to
snap out of metastability to any register in an asynchronous data path.
MANUFACl1JRER DEVICE Kl(SeC) Kz(ns- Z) 60 (ns) A single PAL' with registers can be your best choice for state machine
I x 10-' analysis of asynchronous events, As the registers have virtually identical
PALI6R4 4:3 37
setup times, the simultaneous observation of a metastable event by
PAL I 6R4A I x 10-' 4.3 34.5 different regtster staies are likely to be the same. Contrasted to a
MMI PAL I 6R4A-2 1 x 10-' .64 25 distributed system of observjngregtster states with different setup times,
the PAL system of regtster states with identical setup times is a superior
PAL I 6R4A-4 I x 10-' 5 31 synchronizer.
7l!LS374 2x 10-' 1.8 27.5 Avcid edge sensitive devices on the output paths of the registers
which have asynchronous inputs. The glitch crealed when the synchro-
AMD 74LS374 2x 10-' 2.0 34.5-
nizer goes metastable is enough to trigger the edge sensitive deVice,
FAIRCHILD 74F374 2x 10-' 11.5 17.5 The use of level sensitive devices is generally a better design practice.
PAL devices can be effective synchronizers where various regtstering
1tIble 2 schemes are easily implemented.
Classic applications for bipolar PROMs include instruction numbers of applications as Programmable Logic Element
storage for microprogram control store and software for micro- (or PLE) devices. This paper will cover the architecture. applica-
processor programs. However. due to a new design methodolQgy tions, and software support for PLE devices.
and state-of-the-art performance, PROMs are finding increasing
* This paper is a slightly modified version of the 'paper by the same name which appeared in the Conference Proceedings of the 9th West Coast Computer Faire,
pages 40-47; April 1984.
Classic applications for bipolar PROMs include instruction where '*' represents the Boolean AND operator and '/' repres-
storage for microprogram control store and software for micro- ents the Boolean NOT or inverter operator. The fuses in the
processor programs. However, due to a new design meth- OR-array are programmed to select the desired AND
odology and state-of-the-:art performance, PROMs are finding combinations.
increasing numbers of applications as Programmable Logic
Element (or PLE) devices. This paper will cover the architecture,
@
applications, and software support for PLE devices.
PROGRAMMABLE FIXED AND ARRAY
LOGIC ELEMENT PROGRAMMABLE OR ARRAY
PLE.
Fuse-Programmable Logic Families PROGRAMMABLE
PLA BOTH ARRAYS
LOGIC ARRAY PROGRAMMABLE
A typical combinatorial Boolean equation can be written in
PROGRAMMABLE PAL PROGRAMMABLE AND ARRAY
sum-of-product form, which consists of several AND gates ARRAY LOGIC FIXED OR ARRAY
summed at an ORgste: In gener~I, a set of combinatorial
Boolean equations with n inputs (10,11, ... , In-1) and m outputs
(00,01, ... , Om,--l) can~e generated through one levelef Figure 2•. Structural Difference Between PLE (PROM), PLA
AND gates followed by one level ()f OR gates. Custom logic· and PAL Devices. Note thaUhe PAL and PLE Logic
functions can be defined using programmable logic. Circuits Complement Each Other. The PAL Device
has Many Input Terms While the PLE Device Is Rich
in Product Terms
INPUTS OUTPUTS
Due to this special characteristic of abundant product terms, Despite the existence of dedicated. encoders and decoders,
PROMs are also often used as logic devices. In this paper, many of these functions are application dependent. A standard
PROMs are referred to as PLE (Programmable Logic Element) 3-to-8 decoder/demultiplexer (748138) can be used in decoding
devices. applications. But the decoding scheme may require several
3-to-8 decoder/ demultiplexers and additional SSI OR-gates. On
Advantages of PLE Devices the other hand, a PLE device can be customized to perform the
PLE devices provide a cost-effective solution for many applica- required decoding function with no .additional gates. Simple
tions. Here are just some, of the advantages of PLE devices: decoders, such as those used for decoding memory chip selects
from address lines, can be implemented in a PLE device with five
1) Customizable Logic - The designeer is limited to standard
to ten inputs. More complex decoding may require eight to
functions if SSI/MSI devices are used. The deSigner can create
twelve inputs.
his own logic chips using PLE devices.
2) Design i=lexibility - Modification of design is possible even
without redesigning the PC board. For example, the address
space of a microprocessor-based system can .be reconfigured
by merely programming a new device if the decoding is
implemented in a PLE device. This feature comes in handy if you
Nant to upgrade a system which originally used 64-K Dynamic DATA BUS
RAMs to now use state-of-the-art 256-K Dynamic RAMs.
ADDRESS BUS
3) Reduce Errors - Errors are sometimes unavoidable and
)ftentimes quite expensive. Programmable devices make it
~asier and less expensive to correct errors.
~
PLE devices also offer a very flexible solution for code conversion
applications. Translations of codeS such as from ASCII to
EBCIDIC. Binary to BCD (Binary Coded Decimal). or BCD to
Gray code can be implemented in PLEs. The 74S184 Binary-to-
BCD Converter is actually a 32x8 PROM.
I. -. I 1,1./
o· 6" ~ ~ ~~.~ '6 <:>
C~Ic~_ ~~ . .
AO
A1
01
02
~LE Applications
•
An-1 On
'-~~l
mcoders, code converters, custom ALUs, error detection and AO
:orrection, look-up tables (both trigonometric and arithmetic), A1
A2
lata scaling, compression arithmetic like Wallace Tree adders, A3
listributed arithmetic, and residue arithmetic. A4 OUTPUT CODE
AS
leverallevelsof random logic chips can be replaced byone PLE
A6
ogic circuit. As discussed earlier, PLE devices can implement A7
ogic in sumot products form. 1:4 CODE {
AS
A9
/"":4 1 SELECT
( .....
.. r '~1
'l ~
11-19
High-Speed Bipolar PROMs Find New Applications as PLE Devices
AO~
F : iD--F
Figure 6. Block Diagram for a 4·Blt ALU which can be Imple- A3
mentedln a PLE Device (a)
Ao.Al
Data scaling is another PLE device application. A dedicated F= A o ®Al®A2®A3
A:c A3 00 01 11 10
multiplier is not required if the scaling factor is a constant; the
prescaled result can be stored in a PLE device. Fixed-bit multi- 00 0 (i) 0 (i) AO At A2 A3 + AD Al A2A3
pliers are typically implemented in PLE devices.
9
10
11
12
13
14
15
11-20 I/IonoIHhio m
lIIIemo,.les
High.Speed Bipolar PROMs Find New Applications as PLE Devices
INPUT
INTEGER
OUTPUT
BOOLEAN OPERATORS
Figure 11. This Truth Table Graphically Illustrates the Possible / Complement, prefix to a pin name
Glitch (HIGH to LOW to HIGH Hazard) for the • AND (product)
Function f = a* b* c* d Implemented In a 32x8 PROM. + OR (sum)
Address OF and 1F ContaIn a 1 while All Other : +: XOR (exclusive or)
Locations Contain a 0 for Output f.lf Address Input e : .: XNOR (exclusive nor)
Should Change, the PROM Decoders Could Mo-
mentarily Selct a Location Containing a 0 ARITHMETIC OPERATORS
11-22 MonoIHhlcWMemories
High-Speed Bipolar.PROMs Find New Applications as PLE Devices
03 • IO . . · ·
Il 12 13 I4
I INVERTER
; AND GATE
1
2
3
001
002
003
D9
,.
DA
O' • IO + 11 + 12 + 13 + I4 ; OR GATE •
5
00.
005
DA
19
05 == /10 + In + /12 + /13 + /14 ; NAND GATE
•
7
00.
007
lA
D'
06
07 •
<2 IIQ
IO
1> III
Il
1> /12
I2
*/13
I3
1> /14
14
NOR GATE
EXCLUSIVE OR GATE
8
•
10
008
00'
OOA
,.
DA
lA
08 = 10 : "': 11 :*: I2 :*: 13 :*: 14 EXCLUSIVE NOR GATE 11 008 D9
12 ooe lA
FUNCTION TABLE ,.
13 000
OOE
D'
,.
DA
10 11 12 13 ·'14 01 02 03 04 05 06 07 08 ,.
15 OOF
010
,.
DA
- - 1NV
;~~\~~! 8UF
OUTPUTS FROM BASIC GATES
AND OR NAND NOR XOR XNOR COMMENTS
17
18
on
012 lA
------------------------,---------------------------------------------
LLLLL
HHHHH
ALL ZEROS
ALL ONES
"
20
21
013
01'
015
D'
lA
D'
BLHtH
,.
ODD CHECKERBOARD
LHLHL EVEN CHECKERBOARD
22 01' DA
------------------------------------------------------------- -------- 23
2.
017
018 lA
25 01. D'
DESCRIPTION 26
27
OlA
01. ,.
DA
THIS EXAMPLE ILLUSTRATES THE USE OF PLEs TO IMPLEMENT THE BASIC, GATES:
BUFFER, INVERTER"AND GATE, OR GATE, NAND GATE, NOR GATE', EXCLUSIVE OR
GATE, AND E:ttCLUSIVE NOR_ GATE.
2.
2.
30
Ole
OlD
OlE
,.
DA
lA
NOTE ALSO THAT THREE..,STATE OUTPUTS ARE PROVIDED WITH ONE ACTIVE LOW 31 01' CD
OUTPUT ENA'BLE CONTROL (IE) •
PLEASM GENERATES THE PROM TRUTH, TABLE FROM THE LOGIC EQUATIONS" AND
HEX CROCK SUM '"' OOF3C
SIMULATES THE FUNCT'ION TABLE IN THE LOGiC EQUATIONS.
OOF3C
ADD AO Al A'2 A) 'A4 010203,04 05 06 07'68
--------------------------------,---------------
0 L L L L L L
• L L
•" L L
••
1 H L L L L H L L H H L H
2
,
3
L
H
•
H
L
L
L
L
L
L
H
L
L H
L H
H
H
L
L L
H
L Figure 12d. ASCII Hex Programming Fonnat. PLEASMSoft-
L L H L L L H L H H L H. H
5 H L H L L H L L H H L L L ware Generates this· ASCII Hex. Programming
6
7
L
H
H H L L L H L ·H L L L Fonnat with Hex Check Sum. Control Characters
H L H H H
•9 L
L
" L
L
L
H
H
L
L
H
L
H
L
H L H
L
L H H are Included so that the Information can be Down-
..
L L L H L L L
Loaded Directly to a PROM Programmer
10
11
L
H
H
H
L
L •
H
L
L
L
H "
L
L H
L
••
H L
L
L L
H
12
13
L
H L
L R
H
H
H
L
L
L
•
L
L H
L H
H
H
L
L
L
H
L
H
14 L H H H L H L H H L H H
H
16
H
L
H
L
•
L
H
L
L
• L
L
H
L H
L H
H
H
L
L
L
•
L
H
17
18
H
L
L
H
L
L
L
L
H
•
H
L
L
H
L
L H
•• H
L
L
L
L
L
L
.l000000032D9DAUDAl9lAD9DAl9lAD91AD9DAl940
19
20
ft
L
H
L
L
H
L
L
H
H
H
L
L
H
L
L H
• • H
L
L
•
L
H
L .,OOOlOOODAl9lAD9lAD9DAl9lAD9DAl9DAl9lA(D54
21 H L H L H H L L H H L H H : oOOOOOOlFF
22 L H H L H L H L .H H L H H
23
2'
•
L
H
L
••
L
L H
H •
L
L
H
L
L H
H
•
H
L
L
L
L
L
L
2S
26
H
L
L
H
L
L
H
H
H
H
H
L
L
H
•
L H
L H
H
H
L
L
H
H H
27 H H L H H H L
••
L
•• •• L L. L Figure 12e. Intel Hex. Programming Format. PLEASM Soft-
28
2.
30 • • " • ••
L
L
L
L H
H
H
H
•
H
L
H
L
H
L
L
L
U ..
H
•H
L
L
L
L
L
L
L
ware Generates .thls Intel H.ex Programming
Fonnat with a Hex Check Sum Following Every
31 H H H H H H L
" H 'H
------'"----------------..;---------'"---------------
L L H
16 Bytes of Data
HEX CffECIC SUM' -,., OOF,)C
PLE5P8 5 8 32 25
PLE5P8A 5 8 32 15
PLE8P4 8 4 256 30
PLE8P8 8 8 256 28
PLE9P4 9 4 512 35
PLE9P8 9 8 512 30
PLE10P4 10 4 1024 35
PLE10P8 10 8 1024 35t
PLE11P4 11 4 2048 35
PLE11P8 11 8 2048 35
PLE12P4 12 4 4096 35
PLE12P8 12 8 4096 40
PLE9R8 9 8 512 8 15
PLE10R8 10 8 1024 8 15
PLE11RA8 11 8 2048 8 15
.
PLE11RS8 11 8 2048 8 15
*Clock to output time for registered outputs
PLE1OP4
t Preliminary data.
NOTE: Commercial limits specified.
PLE5P8/A
Acknowledgements
Several ofthe designs discussed in this paper were proposed by
our good friend and colleague Ulrik Mueller, who is now stUdy-
ing Computer Science in his native country,. Denmark, and our
Monolithic Memories Pal Zahir Ebrahim. Special thanks also go
to Ranjit Padmanabhan for writing the PLEASM simulator.
Summary
There are many interesting applications for high-speed PROMs
PLE12P4
used as PLE devices. A software package called "PLEASM"
PLE11P4
software is available as a development tool.
References
1. "PAL Programmable Array Logic Handbook", 3rd edition,
J. Birkner, V. Coli, Monolithic Memories, Inc.
2. "Systems Design Handbook", Monolithic Memories, Inc;
3. "BlPolar LSI 1984 Databook", .5th edition, Monolithic Memo-
ries, Inc. .
4. "PROMs and PLEs: An Application Perspective", Z. Ebrahim,
Monolithic Memories Application Note AN-126.
5. "An Introduction to Arithmetic for Digital Designers",
S. Waser, M.J. Flynn, Holt, Rinehart & Winston, N.Y., 1982. Figure 13. Four Sample PLE LogiC Symbols
11-24
lIIIonoIlthk: mMemories
ABELTM, A Complete Design Tool
For Programmable Logic
Michael J. Holley
DATA I/O
10525 Willows Rd. N.E.
Redmond, WA 98073-9746
As the use of PAL@ and PLE devices (PROMs) increases. the 6809 MEMORY ADDRESS DECODER
need for high-level design tools becomes necessary. Designers Address decoding is a typical application of programmable
need easier, faster, and more efficient ways to design with such logic devices, and the following describes the ABELTM
programmable devices. With the more complex devices currently implementation of such a design.
being introduced to the market, this need is even greater.
Additionally, a designer should be able to specify logic designs A15
in a way that makes sense in engineering terms; he or she should ROM 1
not have to learn a new way of thinking about designs. A14
ROM2
A13
ABEL'·, a complete logic design tool for PAL devices, PLE 10
devices and FPLA devices meets these requirements. ABEL'· A12
incorporates a high-level design language and a set of software DRAM
programs that process logic designs to give correct and efficient Al1
designs.
A10
m. ·.
IBEL'· is a trademark 01 DATA liD.
module m6809a
title '6809 memory decode
Jean Designer Data liD Corp Redmond WA 24 Feb 1984'
H,L,X 1,0,.X.;
Address [A15, A14, A13, A12, All, Al0, X, X, X, X, X, X, X, X, X, X];
equations
!DRAM (Address (= "hDFFF);
Monolithic W.emorle.
ABELTM, A Complete Design Tool For Programmable Logic
Seven·Segment Display Decoder and OFF are declared so that the design can be described
This display decoder decodes a four-bit binary number to in terms of turning a segment on or off. To turn a segment
6n, the appropriate line must be driven low, thus ON is
display the decimal equivalent on a seven-segment LED
display. The design incorporates the ABELTM truth table declared as 0 and OFF as 1.
format and is implemented on a RA5PS PLE. The design is described in two sections: an equations
section and a truth table section. The decoding function is
ena described with a truth table that specifies the outputs
required for each combination of inputs. The first line of the
truth table (the truth table header) names the Inputs and
outputs. In this example, the inputs are contained in the set
a named bed and the outputs are in led. The body of the truth
table defines the input-to-output function. Because the
b design decodes a number to a seven-segment display,
00
e values for bed are expressed as decimal numbers, and
01 values for led are expressed with the constants ON and OFF
d that were defined in the declarations section of the source
02 file. This makes the truth table easy to read and understand;
e the incoming value is a number and the outputs are on and
03 off Signals to the LED.
The input and output values could have just as easily been
9 described in another form. Take for example the line in the
truth table:
a
5 ->[ON,OFF,ON,ON,OFF,ON,ON)
This could have been written in the equivalent form:
9
[0,1,0,1)- > 36
In this second form, 5 was expressed as a set containing
d binary values, and the LED set was converted to decimal.
(Remember that ONwas defined as 0 and OFF was defined
as 1.) Either of the two forms is valid, but the first is more
Figure 4. Block Diagram: Seven-Segment Display Decoder
appropriate for this design. The first form can be read as,
"the number five turns on the first segment, turns off the
I)eslgn Specification second, ... " whereas the second form cannot be so easily
Figure 4 shows a block diagram for the decoder design and translated into terms meaningful for this design.
:I drawing of the display with each of the seven segments
abeled to correspond to the decoder outputs. To light up Test Vectors
iny one of the segments, the corresponding line must be The test vectors for this design test the decoder outputs
friven low. Four Input lines DO-03 are decoded to drive the for the, ten valid combinations of input bits_ The enable is
:orrect output lines. The outputs are named a, b, e, d, e, also tested.by setting ena high for the different
" and g corresponding to the display segments. All outputs combinations. All outputs should be at high impedance
ire active low. An enable, ena, Is provided. When ena is low, whenever ena is high. If they are not, an error has occurred.
he decoder is enabled; when ena is high, all outputs are
friven to high impedance.
ena Summary
Two designs described with the ABEL" design language have
been shown. The first design shows how Boolean equations with
logical and relational operators are used to describe an address
bed led decoder. The Second design shows how a truth table describes a
seven~segment display decoder deSign for a PLE logiC circuit. In
both designs,test vectors were written to testthefunction ofthe
design using ABEL"'s simulator. In addition to 'the Boolean
Figure 5. Simplified Block Diagram: Seven-8egment Display equations and truth table shown in these examples, ABEL"
Decoder features a state diagram structure. The state diagram allows the
designer to fUllY describe state machines in terms of their states
)eslgn Method and state transitions.
=igures 5 and 6 show the simplified block diagram and the
lource file for the ABELTM Implementation of the display Regardless of the method used to describe logic, ABELTM's
lecoder. The FLAG statement is used to make sure that the automatic logic reduction and simulation ensure that the
)rogrammer load file Is in the Motorola Exorciser format. design uses as few terms as possible and that it operates
-he binary inputs and the decoded outputs are grouped into as the designer intended. The end results are savings in
he sets bed and led to simplify notation. The constants ON time, devices, board space, and money.
II :
....
U6 device 'RASPS';
bcd [D3,D2,Dl,DO];
led [a, b,c, d, e, f, g] ;
CUPL is the first software CAD tool designed especially for the support
of all programmable logic devices (PLDs), including PALs and PROMs. It
was developed specifically for YOU, the Hardware Design Engineer. Each
feature of the CUPL language has been chosen to make using programmable
logic easier and faster than conventional TTL logic design.
MAJQR FEATURES Qf ~
1. UNIVERSAL
a. PRODUCT SUPPORT: CUPL supports products from every
manufacturer of programmable logic. With CUPL you are free to
use not only PALS, but also other programmable logic devices.
b. PALASM CONVERSIONS: CUPL has a PALASM to CUPL language
translator which al10ws for an easy tQnversion from your
previous PALASM designs to CUPL.
c. LOGIC PROGRAMMER COMPATIBILITY: CUPL produces a standard JEDEC
download file and is compatible with any logic programmer that
uses JEDEC files.
2. HIGH LEVEL LANGUAGE
High Level Language means that the software has features that allow you
to work in terms that are more 1 ike the way you think than 1 ike the
final PLD programming pattern. Examples of these are:
a. FLEXIBLE INPUT: CUPL gives the engineer complete freedom in
entering logic descriptions for their design:
- EQUATIONS
- TRUTH TABLES
- STATE MACHINE SYNTAX
b. EXPRESSION SUBSTITUTION: This allows you to pick a name for an
equation and then, rather than write the equation each time it
is used, you need only use the name. CUPL will properly
substitute the equation during the compile process.
- THE DISTRIBUTIVEPROPERTY:
From Boolean Algebra, where A. & (B i C)
is replaced by A & B i A & C
- DeMORGAN'S THEOREM:
From Boolean Algebra, where .! (A & B)
is replaced by !A i !B
3. SELF DOCUMENTING
CUPL provides a template file which provides a standard "fill-in-the-
blanks" documentation system that is uniform among all CUPL users. Also,
CUPL allows for free form comments through out your work so there can be
detailed explanations included in each part of the project.
4. ERROR CHECKING
CUPL includes a comprehensive error checking capability with detailed
error messages designed to lead you to the source of the problem.
5. LOGIC REDUCTION
CUPL contains the fastest and most powerful minimizer offered for
Programmable Logic equation reduction. The minimizer allows the choice
of various levelS of minimization ranging from just fitting into the
target device to the absolute minimum.
6. SIMULATION
With CSIM, the CUPL Simulator, you can simulate your logic prior to
programming an actual device. Not only can this save devices but it can
help in debugging a system level problem.
2. DESIGN METHOD
First, all device pins are assigned in the logic description file (see
figure 1) using CUPL's pin declaration statements. Note the use of
indexed variables for the address bus allows a simple assignment for
pins 1 thru S. The active polarity for input and output pins are made
in these declarations, so the designer need only be concerned with the
logic instead of vol tage levels.
The address bus is assigned a name using the FIELD statement. This lets
the designer then describe the desired address range with the single
equation:
range = ioadr: £300 •• 31F] ;
instead of the difficult to understand
range = a9 & as & !a7 & !a6 & !as ;
This (ange expression is then used in the output equation for IO_DECODE
and ENABLE. Since ENABLE may be asserted whenever lOR or lOW are true,
the int~rmediate variable IOREQ is created to define this condition.
The resultant CUPL equation for ENABLE is simply
enable = range & ioreq ;
Finally, the READ signal is created using the active lOR and the
inactive AEN signals .as follows:
read = ior & !aen ;
Note that for a device such as the PAL16LS which has a fixed inverting
buffer on all of its output pins, CUPL will automatically convert the
logic equations when ~n output is desired to be active-level HI, as with
the READ output above.
3• CUPL OUTPUT FIL·ES
CUPL will create a standard JEDEC output file which is compatible with
most 199ic programmers. A simple serial download link is all that is
usually required to transfer the fuse information to the programmer. In
addition, CUPL generates an extensive documentation file which assists
the d~signer in analyzing his/her design. Figure 2 shows a small
section of this file, illustrating such features as pin and variable
names, product term utilization, and other information.
PARTNO P90001234
NAME peIO ;
DATE 02114/95 ;
REV 01 ;
DESIGNER Kahl/Osann ;
COMPANY Assisted Technology
ASSEMBLY PC Proto Board ;
LOCATION U2 ;
1********************************************************************1
1* This device provides a cIne-chip 110 interface fc.r an eQ~tivaley,t *1
1* of the IBM-PC proto board. This logic description may be placed *1
1* in either a PROM or PAL without alteration. *1
1********************************************************************1
1* Allowable Target Device Types: PAL--) PAL16L8, PAL16P8 *1
1* PROM-) PLE12P4 *1
1********************************************************************1
1** Inputs **1
PIN [1. • 8J [a2 •• 9J 1* CPU Address bits 0 thrll 9 *1
PIN 9 ael... 1* DMA Address Enable *1
PIN 1_7 ! iot' 1* I/O Read Strobe (act ive La> *1
PIN 18 ! iClw 1* lID Write Strobe (active La> *1
1** Oll-t puts **1
PIN 12: t'ead 1* Direction Control For Bus BufTer *1
PIN 13 ! er,able I-II- Enable For Bus BufTer *1
PIN 1A ! i CI dece.de
- 1* Dece.ded lID Strobe for Dr, B.::oard Use *1
Figure 1.
CUPL 2.02a
Device p1blB DL1B-c-18-5
Partr.o P90001234
Name PC10
Revision 01
Date 02/14/B5
Designer Kah 1/Osartrt
Company Assisted Technology
Assembly PC Pt'oto Board
L.::.cat i c'r. U2
====================================================================
Symb.;:.l Tab 1 e
====================================================================
a2 1 V
a3 2 V
a4 3 V
a5 4 V
ab 5 V
a7 b V
aB 7 V
a9 B V
aen 9 V
.enable 13 V 2 7
io - decc.de 14 V 1 7
ioadr 0 F
ior 17 V
ioreq 0 I 2
iow 1B V
rar.ge 0 I 1
read 12 V 2 7
enable oe 13 D 1
.ioc...decode c·e 14 D 1
ior Cte 17 D 1 1
ic.w oe 1B D 1 1
read c·e 12 D 1 1
Flgur&2.
COPL-G'l'S
DRAW LOGIC SCBEMATICS FOR PAL DESIGNS!
5 •.
Where ,thiS C;ombinat~()n plaq~s an. unnecessary <burdenon.the
designer, analternative.is now available. .
CUPL-GTS i~"a powerfUl"combination of hardware. and software which
turns an I.BM-PC type computer into a programmable logic
workstationwl}ichallo.\is.the u~ertodraw logic. schematics for
thefunctiQI10f a~~L •.. A basic.premise. in creating.CUPL-GTSwas
toproviqea friendlyenv:ironm~nt wh~re. tl}~ user is isolated from
thetradi tional . keyb<'><l:rdasm4cch as possible. To this end,
virtually all functions can be actuated wi th one button. by way of
the>moQse and a series of pop-upI'\lenus which ease the user's
tas.k.;An.area is provided at the top of the CUP!.,...GTSscre~1) .for.
pr6I11ptingth,~ us.erregardingtl}en~l{toperati.onin a.C;OIJlmanq
sequence. Highlighting ·of .variouselements on the SCreen is
coordinated 'with tl.'l~se,.prompts to enhance their effectiveness.
For,tl}emost;part,tlleuser n~edonly utpize the conventional
keyboardford.~finingsYIJlbolicnaIlles for wires, pins,.objects,
and files. .
An on-screen HELP faCility is providecl to aidthe user\..d.thCuPL-
GTS.commands •.. In addition to the basic. set of object types which
can be easily picked. from a pop-upmenu,theabil i ty to call.up
macro-objects is also provided. Th.ese macro-objects have been
previously drawn uSing CtJPL-GTS and stored away on the disk. unde.r
their own' symbolic name.
CUPLl~ Universal COl'l'lpiler>for Programmable Logic
After a logic schematic has been ~ntered, the user may quickly
check to see if.thedesign>fits in a specific PAL. This is done
by selecting the "Translate to PLD" command from the main menu
which automatically invokes the GTS translation programs. These
programs run in an on-screen window which overlays the graphical
information) providing feedback in the form of error messages
dUpl'ay,ed in . this window. Following the automatic execution. of
these programs, the cursor is r,eturnedto the user who can then
cdntinueto work in the graphics environment without ever having
fully left. In this way many errors can be quickly determined
and remedied without ever having to let go of the mouse.
When the user wishes a hard copy version of a design, the print
command fr.om the main menu may be selected. This causes the GTS
print program to execute in an em-screen window according to the
printer configuration file (PRINTCAP) which is stored on the
disk. The PRINTCAP file allows the user to bonfigure the GTS
print function for any dot.matrix printer they might hav.e.
Often a logic description not fit ina particular PAL due to a
logic capacity (product-term) limitation. Wh~n this occurs, the
universal capability of CUPL-GTS will easily allow the user to
try placing this same lOgic in a different PAL of similar
architecture.
Since CUPL-GTS incorporates CUPL the high lev.el language in its
internal ope.ration, i t alsobenefi ts from CUPL's powerful "Quine
Procedure" logic minimizer •. This is especially advantageous for
CUPL-GTS as logic descriptions showing many lev.els of gates can
be ·verydecepti ve in their ability to consume the logic
capacity of a PAL. The presence of the logid minimizerGan
el iminate unnecessary. and redundant logical functions, and
maximizes the probabil ity that a design Wi 11 fit in a target PAL.
Also included with CUPL-GTS lathe CUPLsiinulator, CSIM, which
allows the user to simulate a logic design pt'lot to physically
creating a programmedPAL. Not only can thissavedevlces,but
it can help significant.ly in debugging a system level 'problem.
CUP:L--GTSis desingedfdrgtowthandeJ{pandabi,l ity.As . new
programmabl~ logic devic~sare introduced users willbekept
current with updated device librariesandproductenhancements~
Most of us first use PAL devices to replaceTTL'iil order to
shrink a design and/o~add functionality.. The following example·
shows how thesiniple I/O deCOder design previously discussed
would appear on the CUPL-GTS screen prior to translation toa
PAL16!,S, PAL16P8 or PLE12P4.
11-36 Mono'''hlcW""emo('',es'
CUPLTM Universal Compiler for Programmable Logic
Change Scale
Set Center
Add Wire
Change Object
Name/Rename
Mcwe
Delete
Query
Find
Translate To PLD
A8
Load From Disk
8 A9 Save On Disk
Quit
More ..•
Monolithic m Memories
Notes
Monolithic W';""or/ea
•
12-2
Definition of Terms and Waveforms
12-3
Package Drawings
Package Drawings
1&1 Ceramic DIP
(5116"x3/4")
-11--.en8 ±.004
I -:m±.1Di
MII-M-38510,
Appendix C, 0-2
.311
7.8l1li
~MAX
1.524
.788 ± .G2O .273 + .D32
.:!1!MIN
.381
.040±.010
~
3.883 ± .50/1 .011 ± .om
.279 ±.D76
t ..
I-
~. .
.~±~
~ AE~. (2)
Notes:
1. Specified body dimensions allow for differences b_een 551, M51 and L51 packages.
• ~. Lead material tolerances are for tin plate finish only. Solder dip finish adds 2 - 10 mils thickness to all lead tip dimensions.
Package Drawings
18J Ceramic DIP
(5/16"x3/4")
MII-M-38510,
Appendix C, 0-6
..,ru..j
~.~ .~±~
7.899
---"'- =t::~1.016
""-'-""-l~.· J~\.t'·.z.;EF.:~
.219 ± .075
~
9.525 ±.635
Notes:
1. Specified body dimensions allow for differences between 551, MSI and LSI packages.
2.,Lead material tol'erances are for tin plate finish only. Solder dip finish adds 2 - 10 mils-,thickness to aU lead tip dimensions.
Package Drawings
,~.- I'
..:!!!!.MAX
4.064
-r---
. 0 2 5 1
.330 ±
~~:'! "1.""- 5. 715 MAX
E 3
~';·1
R,1\''
I-
I
611
TT
8.3B2±.1135 .158±.016 '
Package Drawings
035+.003
~
2 REF
t ~MIN . r-u........ r-~--......-'T"'l
t
v v-V'J.
:l~/'::'
I ""T"_....;;;.38,,;;,,1;...,.._ ( _
=1
.330
[
[
~
I ~
t
5.0B0
BSC
I
6.350
REF
~
!
C ,.....t1
~ . ~-
I
BOTTOM VIEW
~f~ll~F~X~~~O~~~~~~~~~ f:::
.014 %.008
-.f :3ii±.2ii3
8.38
MAX
1
_ .450 + .008
-I
so_
--'~6
REF
x45'(3)
11.430 ± .203
TYP
TOP VIEW
BOTTOM VIEW
Notes:
1. Solder fillets on lid edges not shown.
Package Drawings
'lJNI Cerpack
MIl M 38510,
AppendIx C, F-9
.G12+.CI03
_ -.004
PIN.,
IDENTIFY [U43
.045 MAX
i :f 1
+.tnII
• -;1011
I
I
1
L 30
.017 +.aozr
A32 +.061
1
.G17
.513 ~ 018
13.0311 ~ 457
A32
L
10 11 .j J
l:!!!!
.127
MIN
.oos +_ .002
.0CI1 .271:t.ooa 1 ,.. B.883 ± .229 I .078 + ,018
[~ ~ ~_---L
.1138 ± .178 .300 MAX
7.820
(GLASS FLOW)
24WCerpeck PlNU
a.M-38510.
Appetdx C, F-6
+.CI03
.012 -.004 IDENTIFY
PIG
[.-+:f:
t
1 24
-r
.1-.-
i.OO2·r,·i .017
.613 ~
±.OS1 .018
.432
15.670 ~ 457
','
~
12 13
=1l.
-l.
.127 ..
.oos + .001
. -.002
r---.'0.G6:t.+.o2oaW4.
~.. '
.412 ',.
.o?!£.G15
.127.~= b .:.::::::.:.:.jl
. ~.~~~~~~I=====:Jrt:M5:t.v1
. . . LlI33± .007 , . . .,
13-6
Package Drawings
Package Drawings
16N Molded DIP
(1/4"x3/4")
PIN NO.1
IDENTIFIER
PIN NO.1
IDENTIFIER
..Ir-~ 7.772±.2S4
~_"""'.1+, __.258__ ±_.0_'_2
,..\ -... 5.553 ±._
r \ 1'00TYP
t
.011 ±.002
.279±.051
-IU-.~:.. .
5' -12'
~
(2)
, . 9.144 ±.635
- --~
.457±.102
""",.,.
18N MoICIecI DIP
(1/4"x7/8")
PIN No. 1
IDENTIFIER
00::..pt~
(EJECTOR
OPTIONAL
~::::::~I PIN NO.1 .
IDENTIFIER'
'l!!!!!!Q!'!!
.130
3.302 ~--~r-~
7.772 ±.2B4
~---o.K-- 6.:'~.:s
10' TYP
~-+IU
.279:t.051 -.
~EF,(2) .. 5' - 12'
.380±.025
9.144±.635
Notes:
1. Lead material tolerances are for tin plate finish only. Solder dip finish adds 2 -,to.dlils-thickness to alnead tip dimensions.
2. Both Version 1 and Version 2 configurations are manufactur<ld interchangeably. •
3. Ejector pin marks on Version 1 are. optional.
MoRoIlthic W Memories ..
Package Drawings
Package Drawings
16WCerpack
MII-M-38510, PIN #1
AppendIx C. F-5
.012 -.004
+ .003
'
+.0111 1
[ IDENTIFY
fl.DISMAl
.040
(
•3l1li - .102
~1
,~-+=~
16
t r
.387 ...018
.017 ....0 0 2 J
9.830 ± .457
.432'" .051
~BSCJ
8 9 -L !
1.270 j-t.a:7~·:1-I .127
[.:!!!!!MIN
~
005 + .001 ,..·- - - - ,..... It-;::.~ .on ± .012
[1.i54±.ii5
.127:::: t-:!=----~I;;;:;;;:;;;:~I====~t*
l::::.: t~-J (GLASS FLOW)
18WCerpack
- ~.-:
.D05 1,. I :-,093 :.~ .075 ± .015
r~
.127:::: ~.:======~1~~~~31======tr
(.G33±.D07 I " I
'-±.1111 1--~MAl(--I
9.779
(GLASS FLOW)
UNLESS cm.RWI8IIPICIFIED:
'ALL DIMENSIONS MIN.·MAlLIN INCHEa
ALL DIIII!NSIONS .,N..MAX. IN IIILUIiIEnRS
ALL TOLI!RANCES ARE ± .007 INCHES
Package Drawings
PIN NO. 1
-
IDENTIFIER
-~=:-/~:::::::::I 1."
PlNlIO.1
t77i
IDeN\'lFlER
1.02l"'.lI15
.":1:.311
•
1.188:1:.ot5
,3tl.311:1:.381
~~.R_,(2l
...... .•
.-~~~'.~ .380:I:.~
.&1IH:I: • •
u~ OTItERWI8E.,.CFIED:
AU.. . . .MiN.~IIAX.ININCttE8
AI.!. DIIIENSIQItIS 1IfN,-Mf.1I, .INIIIUIMETElI$
AU. TOLEIIANcaAREUI_1NeHE8
Notee:,
.t. Laadmaterial toleranceii are lot 'fin plaia finish oniV. Solder .di~ finish 1!dds2 -
10 mils thickness to all lead tip dimensions.
2. Both VerSion 1 and Vllralo~ 2 con/igurationsara manufactured interchangeably. '
3, E)8ctor. pin marks on Vetsion 1 'are optiQriaI.
1M
Package Drawings
Package Drawings
24N Molded DIP
(1/16"x1-1/4")
.000
iii DIA (2)
(EJECTOR PIN)
OPTIONAL
Notes:
1. Lead material tolerances are for tin plate finish only. Solder dip finish adds 2 - 10 mils thickness to all lead tip dimensions.
2. Both Version 1 and Version 2 configurations are manufactured interchangeably.
3. Ejector pin marks on Version 1 are optional.
Package Drawings
20NL Molded Chip carrier
(.351"11.351")
.3111 ±.G05
...". ±.1Z7
i SIt
.MI
l - - r....... ..:!Z!!..
1.m
.100 ±.G05
1t5fO±.1Z7
13-11
Package Drawings
Package Drawings
28NL Molded Chip
(.451 "x.451 ")
.453 ± .003
11.506 ± .076
so
1~
J
.490 ±.005
12.446 ±.127
so
1
~
.172
~:.:
-++-,.776
4.369
.100 +.oos
2.S4O±.127
.i~DIA
.028 ± .003 TYP
Ji1±.07i L (EJECTOR PIN)
13-12 MonoIlth/r;F!lJMemGrIes
Package Drawings
Package Drawings
16F~5 Flat Pack
(1/4"x3/B")
PIN.'
IDENTIFY
r'-
.017 ±.OO2J
:m±.1Bf ~
a017
t
.396:t. .015
i~L (LID). 10.058 :t..381
+
.015±.009
I" aBllO±.m
·350 -l
+ .009
.381±.m
.045 MAX
1.143
1-;~7MAX-1
li~ I
.121±._ ~
sn
---'.M,..IoiI
.005±.001 } - - - . - · '80 N ~j4I~..::..,.=:I~I..~·' ' ' ' ' .~' ' MIN' '=J++
.,_
. =-.....
.'
[.078:t..OO7
1.9111 ±.178
.025 .. ,015
'.635 :1'.381
Io':t;;.;~
~+=~;[.:~.r'•.·"J'·~.8.· ·~·rilifl1
~±~
L 910 :~
~~ro
f
.~ 144 + .254
~r
1.270 I~
esc --+j
I 7.544:r..229
·[.t.··~~I'~"·'··"·
. . . . . . ..
1--
::;:! .'
.(il(LlD)
-.27-5-:r..-.0.1-o""......
.. . i ... '
~
I"'·.~. =.::!!·"'.:rI~·.I_~·.
'.1
"---·~L ~
'·"".030""==M=IN='J. :.::
:;..
6.985 ± . 2 5 4 · ..• 7112 .• 1.905;t.203
.025 :l015
~
UNLESS DTHEFlWISESPECIFIED:
ALLDIM.ENSIONS MIN.,MAX.ININCHES
ALL DIMENSIONS MIN.-MA.X. IN MILLIMETERS
ALL TOLERANCES ARE ± .OO7JNCHES
Package ·Drawlngs
211F-3 Flat. Pack
(1/4"x3/r)
PIN. 1
IIIEN1W'Y
, .
. .017
(UD)
1011
+
13-14
Representatives and· DistributorS .IC;.,
Monolithic Memories Area and Regional Sales Managers
. '.
14-6 lIIIonollt"';lm . .mortes
Monolithic Memories Franchised Distributors
MoneIllhlcW.emories
Monolithic Memories Overseas Representatives and Distributors
Monolithic W.emorles
Notes
MonoIllhloW • •morl••