1.

Features
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• Internal Organization
– 64 x 16
• Three-wire Serial Interface
• 2 MHz Clock Rate (5V) Compatibility
• Self-timed Write Cycle (5 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles Three-wire
– Data Retention: 100 Years
• 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages Serial EEPROM
• Lead-free/Halogen-free Devices
1K (64 x 16)

2. Description
The AT93C46E provides 1024 bits of serial electrically-erasable programmable read- AT93C46E
only memory (EEPROM) organized as 64 words of 16 bits each. The device is opti-
mized for use in many industrial and commercial applications where low-power and
low-voltage operation are essential. The AT93C46E is available in space-saving 8-
lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages.
The AT93C46E is enabled through the Chip Select pin (CS) and accessed via a three-
wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a Read instruction at DI, the address is decoded and the data is
clocked out serially on the data output DO pin. The write cycle is completely self-timed
and no separate erase cycle is required before write. The write cycle is only enabled
when the part is in the erase/write enable state. When CS is brought high following the
initiation of a write cycle, the DO pin outputs the ready/busy status of the part.
The AT93C46E is available in 1.8V (1.8V to 5.5V) version.
8-lead PDIP
Table 2-1. Pin Configuration
CS 1 8 VCC
Pin Name Function SK 2 7 NC
CS Chip Select DI 3 6 NC
DO 4 5 GND
SK Serial Data Clock
DI Serial Data Input
8-lead SOIC
DO Serial Data Output
GND Ground CS 1 8 VCC
SK 2 7 NC
VCC Power Supply DI 3 6 NC
NC No Connect DO 4 5 GND

8-lead TSSOP
CS 1 8 VCC
SK 2 7 NC
DI 3 6 NC
DO 4 5 GND Rev. 5207D–SEEPR–1/08
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature .........................................−65°C to +150°C age to the device. This is a stress rating only, and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground ........................................ −1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage .......................................... 6.25V conditions for extended periods may affect
device reliability.
DC Output Current........................................................ 5.0 mA

Figure 2-1. Block Diagram

MEMORY ARRAY ADDRESS

64 X 16 DECODER

DATA
REGISTER

OUTPUT
BUFFER
MODE
DECODE
LOGIC

CLOCK
GENERATOR

Table 2-2. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (DO) 5 pF VOUT = 0V
CIN Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
Note: This parameter is characterized and is not 100% tested.

2 AT93C46E
5207D–SEEPR–1/08
 AT93C46E

Table 2-3. DC Characteristics

Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V, (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
Read at 1.0 MHz 0.5 2.0 mA
ICC Supply Current VCC = 5.0V
Write at 1.0 MHz 0.5 2.0 mA
ISB1 Standby Current VCC = 1.8V CS = 0V 0.4 1.0 µA
ISB2 Standby Current VCC = 2.7V CS = 0V 6.0 10.0 µA
ISB3 Standby Current VCC = 5.0V CS = 0V 10.0 15.0 µA
IIL Input Leakage VIN = 0V to VCC 0.1 1.0 µA
IOL Output Leakage VIN = 0V to VCC 0.1 1.0 µA
VIL1 (1)
Input Low Voltage −0.6 0.8
2.7V ≤ VCC ≤ 5.5V V
VIH1(1) Input High Voltage 2.0 VCC + 1
VIL2(1) Input Low Voltage −0.6 VCC x 0.3
1.8V ≤ VCC ≤ 2.7V V
VIH2(1) Input High Voltage VCC x 0.7 VCC + 1

VOL1 Output Low Voltage IOL = 2.1 mA 0.4 V

2.7V ≤ VCC ≤ 5.5V
VOH1 Output High Voltage IOH = −0.4 mA 2.4 V

VOL2 Output Low Voltage IOL = 0.15 mA 0.2 V

1.8V ≤ VCC ≤ 2.7V
VOH2 Output High Voltage IOH = −100 µA VCC − 0.2 V
Note: 1. VIL min and VIH max are reference only and are not tested.

3
5207D–SEEPR–1/08
Table 2-4. AC Characteristics
Applicable over recommended operating range from TA = −40°C to + 85°C, VCC = +2.7V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units

4.5V ≤ VCC ≤ 5.5V 0 2

fSK SK Clock Frequency 2.7V ≤ VCC ≤ 5.5V 0 1 MHz
1.8V ≤ VCC ≤ 5.5V 0 0.25

4.5V ≤ VCC ≤ 5.5V 250

tSKH SK High Time 2.7V ≤ VCC ≤ 5.5V 250 ns
1.8V ≤ VCC ≤ 5.5V 1000

4.5V ≤ VCC ≤ 5.5V 250

tSKL SK Low Time 2.7V ≤ VCC ≤ 5.5V 250 ns
1.8V ≤ VCC ≤ 5.5V 1000

4.5V ≤ VCC ≤ 5.5V 250

tCS Minimum CS Low Time 2.7V ≤ VCC ≤ 5.5V 250 ns
1.8V ≤ VCC ≤ 5.5V 1000

4.5V ≤ VCC ≤ 5.5V 50

tCSS CS Setup Time Relative to SK 2.7V ≤ VCC ≤ 5.5V 50 ns
1.8V ≤ VCC ≤ 5.5V 200

4.5V ≤ VCC ≤ 5.5V 100

tDIS DI Setup Time Relative to SK 2.7V ≤ VCC ≤ 5.5V 100 ns
1.8V ≤ VCC ≤ 5.5V 400

tCSH CS Hold Time Relative to SK 0 ns

4.5V ≤ VCC ≤ 5.5V 100

tDIH DI Hold Time Relative to SK 2.7V ≤ VCC ≤ 5.5V 100 ns
1.8V ≤ VCC ≤ 5.5V 400

4.5V ≤ VCC ≤ 5.5V 250

tPD1 Output Delay to “1” AC Test 2.7V ≤ VCC ≤ 5.5V 250 ns
1.8V ≤ VCC ≤ 5.5V 1000

4.5V ≤ VCC ≤ 5.5V 250

tPD0 Output Delay to “0” AC Test 2.7V ≤ VCC ≤ 5.5V 250 ns
1.8V ≤ VCC ≤ 5.5V 1000

4.5V ≤ VCC ≤ 5.5V 250

tSV CS to Status Valid AC Test 2.7V ≤ VCC ≤ 5.5V 250 ns
1.8V ≤ VCC ≤ 5.5V 1000

4.5V ≤ VCC ≤ 5.5V 100

CS to DO in High AC Test
tDF 2.7V ≤ VCC ≤ 5.5V 150 ns
Impedance CS = VIL
1.8V ≤ VCC ≤ 5.5V 400

tWP Write Cycle Time 0.1 3 5 ms

(1)
Endurance 5.0V, 25°C 1M Write Cycle
Note: 1. This parameter is ensured by characterization.

3. Functional Description
The AT93C46E is accessed via a simple and versatile three-wire serial communication inter-
face. Device operation is controlled by seven instructions issued by the host processor. A valid
instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the
appropriate op code and the desired memory address location.

4 AT93C46E
5207D–SEEPR–1/08
 AT93C46E

Table 3-1. Instruction Set for the AT93C46E

Address
Instruction SB Op Code x 16 Comments
READ 1 10 A5 − A0 Reads data stored in memory, at specified address
EWEN 1 00 11XXXX Write enable must precede all programming modes
ERASE 1 11 A5 − A0 Erase memory location An − A0
WRITE 1 01 A5 − A0 Writes memory location An − A0
ERAL 1 00 10XXXX Erases all memory locations. Valid only at VCC = 4.5V to 5.5V
WRAL 1 00 01XXXX Writes all memory locations. Valid only at VCC = 4.5V to 5.5V
EWDS 1 00 00XXXX Disables all programming instructions

READ (READ): The Read (READ) instruction contains the address code for the memory loca-
tion to be read. After the instruction and address are decoded, data from the selected memory
location is available at the serial output pin DO. Output data changes are synchronized with the
rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 16-
bit data output string.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN)
instruction must be executed first before any programming instructions can be carried out.
Please note that once in the EWEN state, programming remains enabled until an EWDS instruc-
tion is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory
location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and
address are decoded. The DO pin outputs the ready/busy status of the part if CS is brought high
after being kept low for a minimum of 250 ns (tCS ). A logic “1” at pin DO indicates that the
selected memory location has been erased and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 16 bits of data to be written into
the specified memory location. The self-timed programming cycle, tWP, starts after the last bit of
data is received at serial data input pin DI. The DO pin outputs the ready/busy status of the part
if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO indi-
cates that programming is still in progress. A logic “1” indicates that the memory location at the
specified address has been written with the data pattern contained in the instruction and the part
is ready for further instructions. A ready/busy status cannot be obtained if the CS is brought
high after the end of the self-timed programming cycle, tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array
to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the
ready/busy status of the part if CS is brought high after being kept low for a minimum of 250 ns
(tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the
data patterns specified in the instruction. The DO pin outputs the ready/busy status of the part if
CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is
valid only at VCC = 5.0V ± 10%.

5
5207D–SEEPR–1/08
 ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write
Disable (EWDS) instruction disables all programming modes and should be executed after all
programming operations. The operation of the Read instruction is independent of both the
EWEN and EWDS instructions and can be executed at any time.

6 AT93C46E
5207D–SEEPR–1/08
 AT93C46E

4. Timing Diagrams
Figure 4-1. Synchronous Data Timing

μs (1)

Note: 1. This is the minimum SK period.

Table 4-1. Organization Key for Timing Diagrams

AT93C46E
I/O x 16
AN A5
DN D15

Figure 4-2. READ Timing

tCS

High Impedance

7
5207D–SEEPR–1/08
Figure 4-3. EWEN Timing(1)

tCS
CS

SK

DI 1 0 0 1 1 ...

Note: 1. Requires a minimum of nine clock cycles.

Figure 4-4. EWDS Timing(1)

tCS
CS

SK

DI 1 0 0 0 0 ...

Note: 1. Requires a minimum of nine clock cycles.

Figure 4-5. WRITE Timing

tCS
CS

SK

DI 1 0 1 AN ... A0 DN ... D0

HIGH IMPEDANCE
DO BUSY READY

tWP

8 AT93C46E
5207D–SEEPR–1/08
 AT93C46E

Figure 4-6. WRAL Timing((1)),( (2))

tCS
CS

SK

DI 1 0 0 0 1 ... DN ... D0

BUSY
HIGH IMPEDANCE
DO READY

tWP

Notes: 1. Valid only at VCC = 4.5V to 5.5V.

2. Requires a minimum of nine clock cycles.

Figure 4-7. ERASE Timing

tCS

CS CHECK STANDBY
STATUS

SK

DI 1 1 1 AN AN-1 AN-2 ... A0

tSV tDF

HIGH IMPEDANCE BUSY HIGH IMPEDANCE

DO
READY

tWP

Figure 4-8. ERAL Timing(1)

tCS

CS CHECK STANDBY
STATUS

SK

DI 1 0 0 1 0

tSV tDF
HIGH IMPEDANCE BUSY HIGH IMPEDANCE
DO
READY
tWP

Note: 1. Valid only at VCC = 4.5V to 5.5V.

9
5207D–SEEPR–1/08
AT93C46E Ordering Information
Ordering Code Package Operation Range
AT93C46E-PU (Bulk Form only) 8P3
AT93C46EN-SH-B(1) (NiPdAu Lead Finish) 8S1 Lead-free/Halogen-free/
AT93C46EN-SH-T(2) (NiPdAu Lead Finish) 8S1 Industrial Temperature
AT93C46E-TH-B(1) (NiPdAu Lead Finish) 8A2 (−40°C to 85°C)
(2)
AT93C46E-TH-T (NiPdAu Lead Finish) 8A2
Notes: 1. “B” denotes bulk.
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP = 5K per reel.

Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Small Outline Package (TSSOP)
Options
−1.8 Low Voltage (1.8V to 5.5V)

10 AT93C46E
5207D–SEEPR–1/08
 AT93C46E

Part marking scheme:

AT93C46E 8-PDIP

TOP MARK Seal Year Y = SEAL YEAR WW = SEAL WEEK

| Seal Week 6: 2006 0: 2010 02 = Week 2
| | | 7: 2007 1: 2011 04 = Week 4
|---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: :
A T M L U Y W W 9: 2009 3: 2013 :: : :::: ::
|---|---|---|---|---|---|---|---| 50 = Week 50
4 6 E 1 52 = Week 52
|---|---|---|---|---|---|---|---|
* Lot Number Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
| BOTTOM MARK
Pin 1 Indicator (Dot) No Bottom Mark

AT93C46E 8-SOIC

TOP MARK Seal Year Y = SEAL YEAR WW = SEAL WEEK

| Seal Week 6: 2006 0: 2010 02 = Week 2
| | | 7: 2007 1: 2011 04 = Week 4
|---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: :
A T M L H Y W W 9: 2009 3: 2013 :: : :::: ::
|---|---|---|---|---|---|---|---| 50 = Week 50
4 6 E 1 52 = Week 52
|---|---|---|---|---|---|---|---|
* Lot Number Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---|
| BOTTOM MARK
Pin 1 Indicator (Dot) No Bottom Mark

11
5207D–SEEPR–1/08
 AT93C46E 8-TSSOP

TOP MARK
Pin 1 Indicator (Dot) Y = SEAL YEAR WW = SEAL WEEK
| 6: 2006 0: 2010 02 = Week 2
|---|---|---|---| 7: 2007 1: 2011 04 = Week 4
* H Y W W 8: 2008 2: 2012 :: : :::: :
|---|---|---|---|---| 9: 2009 3: 2013 :: : :::: ::
4 6 E 1 50 = Week 50
|---|---|---|---|---| 52 = Week 52
BOTTOM MARK
|---|---|---|---|---|---|---|
C 0 0
|---|---|---|---|---|---|---|
A A A A A A A
|---|---|---|---|---|---|---|
<- Pin 1 Indicator

12 AT93C46E
5207D–SEEPR–1/08
 AT93C46E

5. Packaging Information

8P3 – PDIP

1
E

E1

Top View c
eA

End View

COMMON DIMENSIONS
D (Unit of Measure = inches)
e
D1 SYMBOL MIN NOM MAX NOTE
A2 A
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
b2 L D1 0.005 3
b3 E 0.300 0.310 0.325 4
4 PLCS b E1 0.240 0.250 0.280 3
e 0.100 BSC
Side View
eA 0.300 BSC 4
L 0.115 0.130 0.150 2

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE DRAWING NO. REV.
2325 Orchard Parkway 8P3, 8-lead, 0.300" Wide Body, Plastic Dual
8P3 B
R San Jose, CA 95131 In-line Package (PDIP)

13
5207D–SEEPR–1/08
8S1 – JEDEC SOIC

E E1

N L

Ø
TOP VIEW
END VIEW
e b
A COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1
A 1.35 – 1.75
A1 0.10 – 0.25
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
D
E1 3.81 – 3.99
E 5.79 – 6.20
SIDE VIEW e 1.27 BSC
L 0.40 – 1.27
θ 0˚ – 8˚

Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

3/17/05
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Colorado Springs, CO 80906 Small Outline (JEDEC SOIC) 8S1 C
R

14 AT93C46E
5207D–SEEPR–1/08
 AT93C46E

8A2 - TSSOP

3 2 1

Pin 1 indicator
this corner

E1 E

L1

N
L
Top View End View
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A D 2.90 3.00 3.10 2, 5

b E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20

e A2 A2 0.80 1.00 1.05

b 0.19 – 0.30 4
D
e 0.65 BSC
Side View L 0.45 0.60 0.75
L1 1.00 RE3

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
10/29/08
TITLE GPC DRAWING NO. REV.
Package Drawing Contact: 8A2, 8-lead, 4.4mm Body, Plastic Thin
[email protected] Shrink Small Outline Package (TSSOP) TNR 8A2 C

15
5207D–SEEPR–1/08
Revision History

Doc. Rev. Date Comments

5207D 1/2008 Removed ‘preliminary’ status
5207C 11/2007 Modified ‘max’ value on AC Characteristics table
5207B 8/2007 Modified Part Marking Scheme Tables
5207A 1/2007 Initial document release

16 AT93C46E
5207D–SEEPR–1/08
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5207D–SEEPR–1/08