S93A46A SeikoInstruments
S93A46A SeikoInstruments
S93A46A SeikoInstruments
com
Rev.2.1_00
Features
• Low current consumption Standby: 3.0 µA Max. (VCC = 5.5 V)
Operating: 1.0 mA Max. (VCC = 5.5 V)
0.6 mA Max. (VCC = 2.7 V)
• Wide operating voltage range Read: 2.7 to 5.5 V
Write: 2.7 to 5.5 V
• Sequential read capable
• Write disable function when power supply voltage is low
• Function to protect against write due to erroneous instruction recognition
• CMOS schmitt input (CS, SK)
• Endurance: 106 cycles/word* (at +85°C)
1.5 × 105 cycles/word* (at +125°C)
* For each address (Word: 16 bits)
• Data retention: 15 years (after rewriting 1.5 × 105 cycles/word at +125°C)
• High-temperature operation: +125°C Max.
• Lead-free products
Packages
Package name Drawing code
Package Tape Reel
8-Pin SOP (JEDEC) FJ008-A FJ008-D FJ008-D
Caution Before using the product in medical equipment or automobile equipment including car audios,
keyless entries and engine control units, contact to SII is indispensable.
Pin Assignment
8-Pin SOP (JEDEC) Table 1
Top view
Pin No. Pin name Pin description
CS 1 8VCC 1 CS Chip select input
2 7 2 SK Serial clock input
SK NC
3 DI Serial data input
DI 3 6 TEST 4 DO Serial data output
DO 4 5 GND 5 GND Ground
*1
6 TEST Test
7 NC No connection
Figure 1 8 VCC Power supply
*1. Connect to GND or VCC.
S-93A46AD0A-J8T2GB (Dynamic burn-in) Even if this pin is not connected, performance is not affected
S-93A56AD0A-J8T2GB (Dynamic burn-in) so long as the absolute maximum rating is not exceeded.
S-93A66AD0A-J8T2GB (Dynamic burn-in)
Remark Refer to the “Package drawings” for the details.
S-93A46AD0A-J8T2GD (Wafer burn-in)
S-93A56AD0A-J8T2GD (Wafer burn-in)
S-93A66AD0A-J8T2GD (Wafer burn-in)
Block Diagram
VCC
Memory array Address
decoder GND
CS
Clock pulse
Voltage detector
monitoring circuit
SK Clock generator
Figure 2
Instruction Sets
1. S-93A46A
Table 2
2. S-93A56A
Table 3
3. S-93A66A
Table 4
Pin Capacitance
Table 7
(Ta = 25°C, f = 1.0 MHz, VCC = 5.0 V)
Item Symbol Condition Min. Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 8 pF
Output Capacitance COUT VOUT = 0 V 10 pF
Endurance
Table 8
Operating
Item Symbol Min. Typ. Max. Unit
temperature
Endurance NW −40 to +125°C 1.5 × 105 cycles/word*1
*1. For each address (Word: 16 bits)
DC Electrical Characteristics
Table 9
Item Symbol Condition VCC = 4.5 to 5.5 V VCC = 2.7 to 4.5 V Unit
Min. Typ. Max. Min. Typ. Max.
Current consumption
ICC1 DO no load 1.0 0.6 mA
(READ)
Table 10
Item Symbol Condition VCC = 4.5 to 5.5 V VCC = 2.7 to 4.5 V Unit
Min. Typ. Max. Min. Typ. Max.
Current consumption
ICC2 DO no load 2.0 1.5 mA
(WRITE)
Table 11
Item Symbol Condition VCC = 4.5 to 5.5 V VCC = 2.7 to 4.5 V Unit
Min. Typ. Max. Min. Typ. Max.
Standby current CS = GND, DO = Open,
ISB 3.0 3.0 µA
consumption Other inputs to VCC or GND
Input leakage
ILI VIN = GND to VCC 0.1 2.0 0.1 2.0 µA
current
Output leakage
ILO VOUT = GND to VCC 0.1 2.0 0.1 2.0 µA
current
AC Electrical Characteristics
Table 12 Test Conditions
Input pulse voltage 0.1 × VCC to 0.9 × VCC
Output reference voltage 0.5 × VCC
Output load 100 pF
Table 13
Table 14
Parameter Symbol VCC = 2.7 to 5.5 V Unit
Min. Typ. Max.
Write time tPR 4.0 8.0 ms
tCSS *2
1/fSK tCDS
CS
tSKH tSKL tCSH
SK
tDS tDH tDS tDH
tPD tPD
*1
Hi-Z Hi-Z
DO
tSV
(READ) tHZ1
tHZ2
Hi-Z Hi-Z
DO
(VERIFY)
Operation
All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes high.
An instruction set is input in the order of start bit, instruction, address, and data.
Instruction input finishes when CS goes low. A low level must be input to CS between commands during
tCDS. While a low level is being input to CS, the S-93A66A is in standby mode, so the SK and DI inputs are
invalid and no instructions are allowed.
Start Bit
A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high,
a start bit is not recognized even if the SK pulse is input as long as the DI pin is low.
1. Dummy Clock
SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy clocks
are effective when aligning the number of instruction sets (clocks) sent by the CPU with those required
for serial memory operation. For example, when the CPU instruction set is 16 bits, the number of
instruction set clocks can be adjusted by inserting the 7-bit dummy clock in S-93A46A and the 5-bit
dummy clock in S-93A56A/66A.
• When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in
which the data output from the CPU and the serial memory collide may be generated, preventing
successful input of the start bit. Take the measures described in “ 3-Wire Interface (Direct
Connection between DI and DO)”.
3. Reading (READ)
The READ instruction reads data from a specified address.
After CS has gone high, input an instruction in the order of the start bit, read instruction, and address.
Since the last input address (A0) has been latched, the output status of the DO pin changes from high
impedance (Hi-Z) to low, which is held until the next rise of SK. 16-bit data starts to be output in
synchronization with the next rise of SK.
CS
SK 1 2 3 4 5 6 7 8 9 10 11 12 22 23 24 25 26 27 38 39 40 41 42 43
DI <1> 1 0 A5 A4 A3 A2 A1 A0
Hi-Z Hi-Z
DO 0 D15 D14 D13 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 D13
ADRINC ADRINC
CS
SK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 24 25 26 27 28 29 40 41 42 43 44 45
DI <1> 1 0 A6 A5 A4 A3 A2 A1 A0
x:S-93A56A
A7:S-93A66A
Hi-Z Hi-Z
DO 0 D15 D14 D13 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 D13
ADRINC ADRINC
tCDS
CS Standby
Verify
SK 1 2 3 4 5 6 7 8 9 10 25
DI <1> 0 1 A5 A4 A3 A2 A1 A0 D15 D0
tSV tHZ1
Hi-Z
DO busy
ready
tPR Hi-Z
tCDS
Standby
CS Verify
SK 1 2 3 4 5 6 7 8 9 10 11 12 27
DI <1> 0 1 A6 A5 A4 A3 A2 A1 A0 D15 D0
x:S-93A56A tSV tHZ1
Hi-Z A7:S-93A66 busy
DO ready
tPR Hi-Z
tCDS
Standby
CS Verify
SK 1 2 3 4 5 6 7 8 9
DI <1> 1 1 A5 A4 A3 A2 A1 A0
tSV
Hi-Z tHZ1
busy
DO ready
tPR Hi-Z
tCDS
Standby
CS Verify
SK 1 2 3 4 5 6 7 8 9 10 11
DI <1> 1 1 A6 A5 A4 A3 A2 A1 A0
x:S-93A56A tSV
Hi-Z tHZ1
A7:S-93A66A busy
DO ready
tPR Hi-Z
tCDS
CS Standby
Verify
SK 1 2 3 4 5 6 7 8 9 10 25
DI <1> 0 0 0 1 D15 D0
4Xs tSV tHZ1
Hi-Z
DO busy
ready
tPR Hi-Z
tCDS
Standby
CS Verify
SK 1 2 3 4 5 6 7 8 9 10 11 12 27
DI <1> 0 0 0 1 D15 D0
6Xs tSV tHZ1
Hi-Z busy
DO ready
tPR Hi-Z
Standby
CS Verify
tCDS
SK 1 2 3 4 5 6 7 8 9
DI <1> 0 0 1 0
4Xs tSV tHZ1
DO Busy
Ready
Hi-Z
tPR
Standby
CS Verify
tCDS
SK 1 2 3 4 5 6 7 8 9 10 11
DI <1> 0 0 1 0
6Xs tSV tHZ1
DO B usy
Ready
Hi-Z
tPR
CS Standby
SK 1 2 3 4 5 6 7 8 9
DI <1> 0 0
4Xs
11=EWEN
00=EWDS
CS Standby
SK 1 2 3 4 5 6 7 8 9 10 11
DI <1> 0 0
6Xs
11=EWEN
00=EWDS
Hysteresis
Power supply voltage About 0.3 V
CS
1 2 3 4 5 6 7 8 9 10 11
SK
DI
Erroneous recognition as 1 1 10 0 0 00 0 0 0 0 0 0
ERASE instruction due to
noise pulse
CPU S-93A46A/56A/66A
SIO DI
DO
R: 10 kΩ to 100 kΩ
Figure 18 Connection of 3-Wire Interface
I/O Pins
1. Connection of Input Pins
All the input pins of the S-93A46A/56A/66A employ a CMOS structure, so design the equipment so that
high impedance will not be input while the S-93A46A/56A/66A is operating. Especially, deselect the CS
input (a low level) when turning on/off power and during standby. When the CS pin is deselected (a low
level), incorrect data writing will not occur. Connect the CS pin to GND via a resistor (10 kΩ to 100 kΩ
pull-down resistor). To prevent malfunction, it is recommended to use equivalent pull-down resistors for
pins other than the CS pin.
CS
Figure 19 CS Pin
SK
Figure 20 SK Pin
DI
Figure 21 DI Pin
TEST
DO
Figure 23 DO Pin
Precaution
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
• SII claims no responsibility for any and all disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
Characteristics
1. DC Characteristics
1.1 Current consumption (READ) ICC1 1.2 Current consumption (READ) ICC1
vs. ambient temperature Ta vs. ambient temperature Ta
VCC=5.5 V VCC=3.3 V
fSK=1 MHz fSK=500 kHz
DATA=0101 DATA=0101
0.4 0.4
ICC1 ICC1
(mA) (mA)
0.2 0.2
0 0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
1.3 Current consumption (READ) ICC1 1.4 Current consumption (READ) ICC1
vs. ambient temperature Ta vs. power supply voltage VCC
VCC=2.7 V Ta=25°C
fSK=500 kHz fSK=1 MHz, 500 kHz
DATA=0101 DATA=0101
0.4 0.4
ICC1 ICC1 1 MHz
(mA) (mA)
0.2 0.2
500 kHz
0 0
–40 0 125 2 3 4 5 6 7
Ta (°C) VCC (V)
1.5 Current consumption (READ) ICC1 1.6 Current consumption (READ) ICC1
vs. power supply voltage VCC vs. Clock frequency fSK
Ta=25°C VCC=5.5 V
fSK=100 kHz, 10 kHz Ta=25 (°C)
DATA=0101
0.4 0.4
ICC1 ICC1
(mA) (mA)
0.2 0.2
100 kHz
10 kHz
0 0
2 3 4 5 6 7 1 k 100 k 1 M10 M
VCC (V) fSK (Hz)
1.7 Current consumption (WRITE) ICC2 1.8 Current consumption (WRITE) ICC2
vs. ambient temperature Ta vs. ambient temperature Ta
VCC=5.5 V VCC=3.3 V
1.0 1.0
ICC2 ICC2
(mA) (mA)
0.5 0.5
0 0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
1.9 Current consumption (WRITE) ICC2 1.10 Current consumption (WRITE) ICC2
vs. ambient temperature Ta vs. power supply voltage VCC
VCC=2.7 V Ta=25°C
1.0 1.0
ICC2 ICC2
(mA) (mA)
0.5 0.5
0 0
–40 0 125 2 3 4 5 6 7
Ta (°C) VCC (V)
1.11 Current consumption in standby mode ISB 1.12 Current consumption in standby mode ISB
vs. ambient temperature Ta vs. power supply voltage VCC
VCC=5.5 V Ta=25°C
CS=GND CS=GND
1.0 1.0
ISB ISB
(µA) (µA)
0.5 0.5
0 0
–40 0 125 2 3 4 5 6 7
Ta (°C) VCC (V)
1.13 Input leakage current ILI 1.14 Input leakage current ILI
vs. ambient temperature Ta vs. ambient temperature Ta
VCC=5.5 V VCC=5.5 V
CS, SK, DI, CS, SK, DI,
TEST=0 V TEST=5.5 V
1.0 1.0
ILI ILI
(µA) (µA)
0.5 0.5
0 0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
1.15 Output leakage current ILO 1.16 Output leakage current ILO
vs. ambient temperature Ta vs. ambient temperature Ta
VCC=5.5 V VCC=5.5 V
DO=0 V DO=5.5 V
1.0 1.0
ILO ILO
(µA) (µA)
0.5 0.5
0 0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
1.17 High-level output voltage VOH 1.18 High-level output voltage VOH
vs. ambient temperature Ta vs. ambient temperature Ta
VCC=4.5 V VCC=2.7 V
IOH=–400 µA IOH=–100 µA
4.6 2.8
VOH VOH
(V) 4.4 (V) 2.6
4.2 2.4
0 0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
1.19 High-level output voltage VOH 1.20 Low-level output voltage VOL
vs. ambient temperature Ta vs. ambient temperature Ta
VCC=2.7 V VCC=4.5 V
IOH=–10 µA IOL=2.1 mA
2.8 0.3
VOH VOL
(V) 2.6 (V) 0.2
2.4 0.1
0 0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
1.21 Low-level output voltage VOL 1.22 High-level output current IOH
vs. ambient temperature Ta vs. ambient temperature Ta
VCC=2.7 V VCC=4.5 V
IOL=100 µA VOH=2.4 V
0.03
–10
VOL IOH
(V) 0.02 (mA)
–20
0.01
0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
1.23 High-level output current IOH 1.24 High-level output current IOH
vs. ambient temperature Ta vs. ambient temperature Ta
VCC=2.7 V VCC=2.7 V
VOH=2.4 V VOH=2.5 V
–1 –1
IOH IOH
(mA) (mA)
–2 –2
1.25 Low-level output current IOL 1.26 Low-level output current IOL
vs. ambient temperature Ta vs. ambient temperature Ta
VCC=4.5 V VCC=2.7 V
VOL=0.6 V VOL=0.2 V
3
20
IOL IOL
(mA) (mA) 2
10
1
0 0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
1.27 High-level input voltage VIH 1.28 High-level input voltage VIH
vs. power supply voltage VCC vs. ambient temperature Ta
Ta=25°C
CS, SK
2 2
VIH VIH
(V) (V)
1 1
VCC=5.5 V
CS, SK
0 0
2 3 4 5 6 7 –40 0 125
VCC (V) Ta (°C)
1.29 High-level input voltage VIH 1.30 High-level input voltage VIH
vs. power supply voltage VCC vs. ambient temperature Ta
Ta=25°C
DI
2 2
VIH VIH
(V) (V)
1 1
VCC=5.5 V
DI
0 0
2 3 4 5 6 7 –40 0 125
VCC (V) Ta (°C)
1.31 Low-level input voltage VIL 1.32 Low-level input voltage VIL
vs. power supply voltage VCC vs. ambient temperature Ta
Ta=25°C
CS, SK
2 2
VIL VIL
(V) (V)
1 1
VCC=5.5 V
CS, SK
0 0
2 3 4 5 6 7 –40 0 125
VCC (V) Ta (°C)
1.33 Low-level input voltage VIL 1.34 Low-level input voltage VIL
vs. power supply voltage VCC vs. ambient temperature Ta
Ta=25°C
DI
2 2
VIL VIL
(V) (V)
1 1
VCC=5.5 V
DI
0 0
2 3 4 5 6 7 –40 0 125
VCC (V) Ta (°C)
1.35 Low supply voltage detection voltage −VDET 1.36 Low supply voltage release voltage +VDET
vs. ambient temperature Ta vs. ambient temperature Ta
2.0 2.0
–VDET +VDET
(V) (V)
1.0 1.0
0 0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
2. AC Characteristics
2.1 Maximum operating frequency fmax. 2.2 Write time tPR
vs. power supply voltage VCC vs. power supply voltage VCC
Ta=25°C Ta=25°C
10 M
4.0
fmax. 1 M tPR
(Hz) (ms)
100 k
2.0
10 k
0
2 3 4 5 6 7 2 3 4 5 6 7
VCC (V) VCC (V)
VCC=5.5 V VCC=3.3 V
4.0 4.0
tPR tPR
(ms) (ms)
2.0 2.0
0 0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
2.5 Write time tPR 2.6 Data output delay time tPD
vs. ambient temperature Ta vs. ambient temperature Ta
VCC=2.7 V VCC=4.5 V
0.3
4.0
tPR tPD
(ms) (ns) 0.2
2.0
0.1
0 0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
2.7 Data output delay time tPD 2.8 Data output delay time tPD
vs. ambient temperature Ta vs. ambient temperature Ta
VCC=3.3 V VCC=2.7 V
0.6 1.5
tPD tPD
(ns) 0.4 (ns) 1.0
0.2 0.5
0 0
–40 0 125 –40 0 125
Ta (°C) Ta (°C)
Burn-in specification
B: Dynamic burn-in
D: Wafer burn-in
Operation temperature
A: −40 ∼ +125°C
Fixed
Pin assignment
Product name
S-93A46A: 1 K-bit
S-93A56A: 2 K-bit
S-93A66A: 4 K-bit
5.02±0.2
8 5
1 4
0.20±0.05
1.27 0.4±0.05
No. FJ008-A-P-SD-2.1
No. FJ008-A-P-SD-2.1
SCALE
UNIT mm
ø1.55±0.05 0.3±0.05
6.7±0.1
1 8
4 5
Feed direction
No. FJ008-D-C-SD-1.1
No. FJ008-D-C-SD-1.1
SCALE
UNIT mm
60°
2±0.5
Enlarged drawing in the central part 13.5±0.5
2±0.5
ø21±0.8
ø13±0.2
No. FJ008-D-R-SD-1.1
TITLE SOP8J-D-Reel
No. FJ008-D-R-SD-1.1
SCALE QTY. 2,000
UNIT mm