TC58DVM92A5TA00

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

2
512-MBIT (64M × 8 BITS) CMOS NAND E PROM
DESCRIPTION
The device is a single 3.3 V 512Mbit (553,648,128 bit) NAND Electrically Erasable and Programmable Read-Only
Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 4096 blocks. The device has a 528-byte static
register which allows program and read data to be transferred between the register and the memory cell array in
528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes ×
32 pages).
The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.

FEATURES
• Organization
Memory cell allay 528 × 128K × 8
Register 528 × 8
Page size 528 bytes
Block size (16K + 512) bytes

• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read

• Mode control
Serial input/output
Command control

• Power supply
VCC = 2.7 V to 3.6 V

• Access time
Cell array to register 25 μs max
Serial Read Cycle 40 ns min

• Program/Erase time
Auto Page Program 300 μs/page typ.
Auto Block Erase 2.5 ms/block typ.

• Operating current
Read (40 ns cycle) 20 mA max.
Program (avg.) 20 mA max.
Erase (avg.) 20 mA max.
Standby 50 μA max

• Package
TSOPI48-P-1220-0.50 (Weight: 0.53g typ.)

1 2010-07-13
 TC58DVM92A5TA00
PIN ASSIGNMENT (TOP VIEW)

NC 1 48 NC
NC 2 47 NC
NC 3 46 NC
NC 4 45 NC
NC 5 44 I/O8
NC 6 43 I/O7
RY / BY 7 42 I/O6
RE 8 41 I/O5
CE 9 40 NC
NC 10 39 NC
NC 11 38 NC
VCC 12 37 VCC
VSS 13 36 VSS
NC 14 35 NC
NC 15 34 NC
CLE 16 33 NC
ALE 17 32 I/O4
WE 18 31 I/O3
WP 19 30 I/O2
NC 20 29 I/O1
NC 21 28 NC
NC 22 27 NC
NC 23 26 NC
NC 24 25 NC

PIN NAMES
I/O1 to I/O8 I/O port
CE Chip enable
WE Write enable
RE Read enable
CLE Command latch enable
ALE Address latch enable
WP Write protect
RY/BY Ready/Busy
VCC Power supply
VSS Ground
NC No connection

2 2010-07-13
 TC58DVM92A5TA00
BLOCK DIAGRAM

VCC VSS
Status register

I/O1 Address register Column buffer

to I/O Control circuit Column decoder

I/O8 Command register Data register

Sense amp

CE

Row address decoder

Row address buffer
CLE

decoder
ALE
Logic control Control Memory cell array
WE

RE
WP

RY/BY
RY/BY HV generator

ABSOLUTE MAXIMUM RATINGS

SYMBOL RATING VALUE UNIT

VCC Power Supply Voltage −0.6 to 4.6 V

VIN Input Voltage −0.6 to 4.6 V

VI/O Input/Output Voltage −0.6 V to VCC + 0.3 V (≤ 4.6 V) V

PD Power Dissipation 0.3 W

Tsolder Soldering Temperature (10s) 260 °C

Tstg Storage Temperature −55 to 125 °C

Topr Operating Temperature 0 to 70 °C

CAPACITANCE *(Ta = 25°C, f = 1 MHz)

SYMB0L PARAMETER CONDITION MIN MAX UNIT

CIN Input VIN = 0 V ⎯ 10 pF

COUT Output VOUT = 0 V ⎯ 10 pF

* This parameter is periodically sampled and is not tested for every device.

3 2010-07-13
 TC58DVM92A5TA00
VALID BLOCKS (1)

SYMBOL PARAMETER MIN TYP. MAX UNIT

NVB Number of Valid Blocks 4016 ⎯ 4096 Blocks

(1) The device occasionally contains unusable blocks. Refer to Application Note (14) toward the end of this document.
(2) The first block (block address #00) is guaranteed to be a valid block at the time of shipment.

RECOMMENDED DC OPERATING CONDITIONS

SYMBOL PARAMETER MIN TYP. MAX UNIT

VCC Power Supply Voltage 2.7 ⎯ 3.6 V

VIH High Level input Voltage VCC × 0.78 ⎯ VCC + 0.3 V

VIL Low Level Input Voltage −0.3* ⎯ VCC × 0.22 V

* −2 V (pulse width lower than 20 ns)

DC CHARACTERISTICS (Ta = 0° to 70°C, VCC = 2.7 V to 3.6 V)

SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT

IIL Input Leakage Current VIN = 0 V to VCC ⎯ ⎯ ±10 μA

ILO Output Leakage Current VOUT = 0 V to VCC ⎯ ⎯ ±10 μA

ICCO1 Operating Current (Serial Read) CE = VIL, IOUT = 0 mA, tcycle = 40 ns ⎯ ⎯ 20 mA

Operating Current
ICCO3 tcycle = 40 ns ⎯ ⎯ 20 mA
(Command Input)

ICCO4 Operating Current (Data Input) tcycle = 40 ns ⎯ ⎯ 20 mA

Operating Current
ICCO5 tcycle = 40 ns ⎯ ⎯ 20 mA
(Address Input)

ICCO7 Programming Current ⎯ ⎯ ⎯ 20 mA

ICCO8 Erasing Current ⎯ ⎯ ⎯ 20 mA

ICCS Standby Current CE = VCC − 0.2 V, WP = 0 V/VCC ⎯ ⎯ 50 μA

VOH High Level Output Voltage IOH = −400 μA 2.4 ⎯ ⎯ V

VOL Low Level Output Voltage IOL = 2.1 mA ⎯ ⎯ 0.4 V

IOL ( RY/BY ) Output Current of RY/BY pin VOL = 0.4 V ⎯ 8 ⎯ mA

4 2010-07-13
 TC58DVM92A5TA00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0° to 70°C, VCC = 2.7 V to 3.6 V)

SYMBOL PARAMETER MIN MAX UNIT NOTES

tCLS CLE Setup Time (*1) 20 ⎯ ns

tCLH CLE Hold Time 10 ⎯ ns

tCS CE Setup Time (*2) 30 ⎯ ns

tCH CE Hold Time 10 ⎯ ns

tWP Write Pulse Width 20 ⎯ ns

tALS ALE Setup Time (*1) 20 ⎯ ns

tALH ALE Hold Time 10 ⎯ ns

tDS Data Setup Time 20 ⎯ ns

tDH Data Hold Time 5 ⎯ ns

tWC Write Cycle Time 40 ⎯ ns

tWH WE High Hold Time 15 ⎯ ns

tWW WP High to WE Low 100 ⎯ ns

tRR Ready to RE Falling Edge 20 ⎯ ns

tRP Read Pulse Width 20 ⎯ ns

tRC Read Cycle Time 40 ⎯ ns

tREA RE Access Time (Serial Data Access) ⎯ 30 ns

tCEA CE Access Time (Serial Data Access) ⎯ 35 ns

tCLR CLE Low to RE Low 10 ⎯ ns

tALEA ALE Access Time (ID Read) ⎯ 40 ns

tCEH CE High Time for Last Address in Serial Read Cycle 100 ⎯ ns (2)

tOH Data Output Hold Time 10 ⎯ ns

tRHZ RE High to Output High Impedance ⎯ 30 ns

tCHZ CE High to Output High Impedance ⎯ 20 ns

tREH RE High Hold Time 15 ⎯ ns

tIR Output-High-impedance-to- RE Falling Edge 0 ⎯ ns

tWHC WE High to CE Low 30 ⎯ ns

tWHR WE High to RE Low 30 ⎯ ns

tR Memory Cell Array to Starting Address ⎯ 25 μs

tWB WE High to Busy ⎯ 100 ns

tAR2 ALE Low to RE Low (Read Cycle) 10 ⎯ ns

tRB RE Last Clock Rising Edge to Busy (in Sequential Read) ⎯ 130 ns

tCRY CE High to Ready (When interrupted by CE in Read Mode) ⎯ 5 μs (1) (2)

5 / 5 / 10 /
tRST Device Reset Time (Ready/Read/Program/Erase) ⎯ μs
500

*1: tCLS and tALS can not be shorter than tWP

*2: tCS should be longer than tWP + 10ns.

5 2010-07-13
 TC58DVM92A5TA00
Note: (1) CE High to Ready time depends on the pull-up resister tied to the RY / BY pin.

(Refer to Application Note (9) toward the end of this document.)

(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay is less than 30

ns , RY / BY signal stays Ready.

tCEH ≧ 100 ns

* *: VIH or VIL
CE

RE
A : 0 to 30 ns → Busy signal is not output.
525 527 A

RY/BY
Busy

tCRY

AC TEST CONDITIONS

PARAMETER CONDITION

Vcc 2.7V to 3.6V

Input level VCC − 0.2 V, 0.2 V

Input pulse rise and fall time 3 ns

Input comparison level VCC / 2

Output data comparison level VCC / 2

Output load CL (100 pF) + 1 TTL

PROGRAMMING AND ERASING CHARACTERISTICS

(Ta = 0° to 70°C, VCC = 2.7 V to 3.6 V)

SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES

tPROG Programming Time ⎯ 300 700 μs

Number of Programming Cycles on Same

N ⎯ ⎯ 3 (1)
Page

tBERASE Block Erasing Time ⎯ 2.5 7 ms

(1): Refer to Application Note (12) toward the end of this document.

6 2010-07-13
 TC58DVM92A5TA00
TIMING DIAGRAMS

Latch Timing Diagram for Command/Address/Data

CLE
ALE
CE
RE Setup Time Hold Time

WE

tDS tDH

I/O

: VIH or VIL

Command Input Cycle Timing Diagram

CLE
tCLS tCLH
tCS tCH

CE

tWP

WE

tALS tALH

ALE

tDS tDH

I/O

: VIH or VIL

7 2010-07-13
 TC58DVM92A5TA00
Address Input Cycle Timing Diagram

tCLS

CLE

tCS tCH tCH tWC

CE

tWP tWH tWP tWH tWP tWH tWP

WE

tALS tALH

ALE

tDS tDH tDS tDH tDS tDH tDS tDH

A0 to A7 A9 to A16 A17 to A24 A25

: VIH or VIL

Data Input Cycle Timing Diagram

tCLH

CLE

tCH tCS tCH

tCS

CE

tALS

tWC
ALE

tWP tWH tWP tWP

WE

tDS tDH tDS tDH tDS tDH

I/O DIN0 DIN1 DIN 527

: VIH or VIL

8 2010-07-13
 TC58DVM92A5TA00
Serial Read Cycle Timing Diagram

tRC

CE

tRP tREH tRP tCH tRP tCHZ

RE
tRHZ tRHZ tRHZ
tREA tOH tREA tOH tREA tOH

I/O

tRR tCEA

RY/BY

Status Read Cycle Timing Diagram

tCLR

CLE
tCLS tCLH

tCS

CE

tWP tCH

WE
tWHC tCEA tCHZ
tWHR

RE
tOH
tDS tDH tIR
tREA tRHZ

Status
I/O 70h*
output

RY/BY

* 70h represents the hexadecimal number : VIH or VIL

9 2010-07-13
 TC58DVM92A5TA00
Read Cycle (1) Timing Diagram

CLE
tCLS tCLH
tCEH
tCH
tCS
CE
tWC tCRY

WE

tALS tALH tAR2

tALH
ALE
tR tRR tRC

tWB
RE
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tREA

A0 A9 A17 DOUT DOUT DOUT DOUT

I/O 00h A25
to A7 to A16 to A24 N N+1 N+2 527
tRB
Column address
N*
RY/BY

* Read Operation using 00h Command N: 0 to 255

: VIH or VIL

Read Cycle (1) Timing Diagram: When Interrupted by CE

CLE
tCLS tCLH

tCH
tCS

CE
tWC tCHZ

WE

tALS tALH tAR2

tALH
ALE
tR tRR tRC

tWB
RE
tOH
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tREA tRHZ

I/O A0 A9 A17 DOUT DOUT DOUT

00h A25
to A7 to A16 to A24 N N+1 N+2
Column address
N*
RY/BY

*: Read operation using 00h command N: 0 to 255 : VIH or VIL

10 2010-07-13
 TC58DVM92A5TA00
Read Cycle (2) Timing Diagram

CLE
tCLS tCLH

tCS tCH

CE

WE
tALH tALS tALH tAR2

ALE
tR tRR tRC

tWB
RE
tDS tDH tDS tDH tREA

A9 A17
I/O 01h A0 to A7 A25 DOUT DOUT DOUT
to A16 to A24
Column address 256 + N 256 + N + 1 527
N*
RY/BY

: VIH or VIL
*: Read operation using 01h command N: 0 to 255

Read Cycle (3) Timing Diagram

CLE
tCLS tCLH

tCS tCH

CE

WE
tALH tALS tALH tAR2

ALE
tR tRR tRC

tWB
RE
tDS tDH tDS tDH tREA

A9 A17
I/O 50h A0 to A7 A25 DOUT DOUT DOUT
to A16 to A24
Column address 512 + N 512 + N + 1 527
N*
RY/BY

: VIH or VIL
*: Read operation using 50h command N: 0 to 15

11 2010-07-13
 TC58DVM92A5TA00
Sequential Read (1) Timing Diagram

CLE

CE

WE

ALE

RE

I/O1 A0 A9 A17
00h to to to A25 N N+1 N+2 527 0 1 2 527
to I/O8 A7 A16 A24
Column Page
address address tR tR
N M

RY/BY

Page M Page M + 1
access access
: VIH or VIL

Sequential Read (2) Timing Diagram

CLE

CE

WE

ALE

RE

I/O1 A0 A9 A17
01h to to to A25 527 0 1 2 527
to I/O8 A7 A16 A24
Column Page
address address tR 256 + 256 + 256 + tR
N M N N+1 N+2

RY/BY

Page M Page M + 1
access access
: VIH or VIL

12 2010-07-13
 TC58DVM92A5TA00
Sequential Read (3) Timing Diagram

CLE

CE

WE

ALE

RE

I/O1 A0 A9 A17
50h to to A25 527 512 513 514 527
to I/O8 to A7 A16 A24
Column Page
address address tR 512 + 512 + 512 + tR
N M N N+1 N+2

RY/BY

Page M Page M + 1
access access
: VIH or VIL

13 2010-07-13
 TC58DVM92A5TA00
Auto-Program Operation Timing Diagram

tCLS

CLE
tCLS tCLH
tCS

CE
tCH
tCS

WE
tALH tALH
tALS tALS tPROG
tWB
ALE

RE
tDS
tDS tDH tDS tDH tDH tDS tDH

A0 to A9 A17 DIN
I/O 80h A25 DIN0 DIN1 10h 70h
A7 to A16 to A24 527
Status
output

RY/BY

: VIH or VIL : Do not input data while data is being output.

Auto Block Erase Timing Diagram

CLE
tCLS
tCLH
tCS tCLS
CE

WE

tALS tALH tWB tBERASE

ALE

RE

tDS tDH

A9 A17 Status
I/O 60h A25 D0h 70h
to A16 to A24 output

RY/BY Auto Block Erase Erase Start Busy Status Read

Setup command command command
: VIH or VIL : Do not input data while data is being output.

14 2010-07-13
 TC58DVM92A5TA00
ID Read Operation Timing Diagram

CLE
tCLS
tCLS
tCS tCH tCS

CE

tCH

WE
tCEA
tALH tALS tALH tALEA

ALE

RE

tDS tDH tREA tREA

I/O 90h 00h 98h 76h

Address Maker code Device code

input

: VIH or VIL

15 2010-07-13
 TC58DVM92A5TA00
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.

Command Latch Enable: CLE

The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.

Address Latch Enable: ALE

The ALE signal is used to control loading of either address information or input data into the internal
address/data register. Address information is latched on the rising edge of WE if ALE is High. Input data is
latched if ALE is Low.

Chip Enable: CE
The device goes into a low-power Standby mode when CE goes High during a wait state. The CE signal is
ignored when device is in Busy state ( RY/ BY = L), such as during a Program or Erase or Read operation, and
will not enter Standby mode even if the CE input goes High.

Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.

Read Enable: RE
The RE signal controls serial data output. Data is available tREA after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + l) on this falling edge.

I/O Port: I/O1 to 8

The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.

Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.

Ready/Busy: RY/ BY
The RY/ BY output signal is used to indicate the operating condition of the device. The RY/ BY signal is in
Busy state ( RY/ BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY/ BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.

16 2010-07-13
 TC58DVM92A5TA00
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.

I/O1

512 16
I/O8 A page consists of 528 bytes in which 512 bytes are
used for main memory storage and 16 bytes are for
redundancy or for other uses.

32 pages 1 page = 528 bytes

1 block = 528 bytes × 32 pages = (16K + 512) bytes

=
131072 pages 1 block Capacity = 528 bytes × 32 pages × 4096 blocks
=

4096 blocks

An address is read in via the I/O port over four

8I/O consecutive clock cycles, as shown in Table 1.
528

Figure 1. Schematic Cell Layout

Table 1. Addressing

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

First cycle A7 A6 A5 A4 A3 A2 A1 A0 A0 to A7: Column address

A9 to A25: Page address
Second cycle A16 A15 A14 A13 A12 A11 A10 A9 A14 to A25: Block address
A9 to A13: NAND address in block
Third cycle A24 A23 A22 A21 A20 A19 A18 A17

Fourth cycle *L *L *L *L *L *L *L A25

* : A8 is automatically set to Low or High by a 00h command or a 01h command.

l/O2-8 must be set to Low in the fourth cycle.

17 2010-07-13
 TC58DVM92A5TA00
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the ten different command
operations shown in Table 4. Address input, command input and data input/output are controlled by the CLE,
ALE, CE , WE , RE and WP signals, as shown in Table 2.

Table 2. Logic table

*1
CLE ALE CE WE RE WP

Command Input H L L H *

Address Input L H L H *

Data Input L L L H H

Serial Data Output L L L H *

2
During Programming (Busy)* * * * * * H
2
During Erasing (Busy)* * * * * * H

Program, Erase Inhibit * * * * * L

Standby * * H * * 0 V/VCC

H: VIH, L: VIL, *: VIH or VIL

*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
*2: The CE signal is ignored when device is in Busy state ( RY/ BY = L), such as during a Program or Erase or Read operation,
and will not enter Standby mode even if the CE input goes High.

Table 3 shows the operation states for Read mode.

Table 3. Read mode operation states

CLE ALE CE WE RE I/O1 to I/O8 Power

Output Select L L L H L Data output Active

Output Deselect L L L H H High impedance Active

H: VIH, L: VIL

18 2010-07-13
 TC58DVM92A5TA00

Table 4. Command table (HEX)

First Cycle Second Cycle Acceptable while Busy

HEX data bit assignment
Serial Data Input 80 ⎯
(Example)
Read Mode (1) 00 ⎯
Serial data input: 80h
Read Mode (2) 01 ⎯

Read Mode (3) 50 ⎯

1 0 0 0 0 0 0 0
Reset FF ⎯ c
I/O8 7 6 5 4 3 2 I/O1
Auto Program 10 ⎯

Auto Block Erase 60 D0

Status Read 70 ⎯ c

ID Read 90 ⎯

19 2010-07-13
 TC58DVM92A5TA00
DEVICE OPERATION

Read Mode (1)

Read mode (1) is set when a 00h command is issued to the Command register. Refer to Figure 2 below for
timing details and the block diagram.

CLE

CE

WE

ALE

RE

RY/BY N Busy
M
I/O 00h

Start-address input

M 527 A data transfer operation from the cell array to the register
starts on the rising edge of WE in the fourth cycle (after the
address information has been latched). The device will be in
Select page Busy state during this transfer period.
N Cell array After the transfer period the device returns to Ready state.
Serial data can be output synchronously with the RE clock
Figure 2. Read mode (1) operation from the start pointer designated in the address input cycle.

Read Mode (2)

CLE

CE

WE

ALE

RE

RY/BY N Busy
M
I/O 01h

Start-address input

256 M 527 The operation of the device after input of the 01h command is
the same as that of Read mode (1). If the start pointer is to be
set after column address 256, use Read mode (2).
Select page
N Cell array

Figure 3. Read mode (2) operation

20 2010-07-13
 TC58DVM92A5TA00
Read Mode (3)
Read mode (3) has the same timing as Read modes (1) and (2), but it is used to access information in the extra
16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte
527.

CLE

CE

WE

ALE

RE

RY/BY Busy

I/O 50h

A0 to A3 Addresses bits A0 to A3 are used to set the start pointer for the
redundant memory cells, while A4 to A7 are ignored.
512 527
Once a 50h command has been issued, the pointer moves to the
redundant cell locations and only those 16 cells can be
addressed, regardless of the value of the A4 to A7 address. (An
00h or an 01h command is necessary to move the pointer back to
the 0 to 511 main memory cell location.)
Figure 4. Read mode (3) operation

Sequential Read (1) (2) (3)

This mode allows the sequential reading of pages without additional address input.

00h

01h

50h Address input Data output Data output

tR tR tR

RY/BY
Busy Busy Busy
(00h)
0 527 (01h) 527 (50h) 512 527

A
A A

Sequential Read (1) Sequential Read (2) Sequential Read (3)

Sequential Read modes (1) and (2) output the contents of addresses 0 to 527 as shown above, while Sequential
Read mode (3) outputs the contents of the redundant address locations only.

21 2010-07-13
 TC58DVM92A5TA00
Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result
(pass/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device
status is output via the I/O port on the RE clock after a Status Read command "70h" input. The resulting
information is outlined in Table 5 .

Table 5. Status output table for Status Read command "70h"

STATUS OUTPUT

I/O1 Pass/Fail Pass: 0 Fail: 1

I/O2 Not Used 0

I/O3 Not Used 0 The Pass/Fail status on I/O1 is only

I/O4 Not Used 0 valid when the device is in the Ready
state.
I/O5 Not Used 0

I/O6 Not Used 0

I/O7 Ready/Busy Ready: 1 Busy: 0

I/O8 Write Protect Protect: 0 Not Protected: 1

An application example with multiple devices is shown in Figure 5.

CE1 CE2 CE3 CEN CEN + 1

CLE
ALE Device Device Device Device Device
WE 1 2 3 N N+1
RE

I/O1
to I/O8
RY/BY

RY/BY Busy

CLE

ALE

WE

CE1

CEN

RE

I/O 70h 70h

Status on Device 1 Status on Device N

Figure 5. Status Read timing application example

System Design Note: If the RY/ BY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each
individual device.

22 2010-07-13
 TC58DVM92A5TA00
Auto Page Program
The device carries out an Automatic Page Program operation when it receives a “10h” Program command
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)

Pass
80 10 70 I/O
Data input Address Data input Program Status Read Fail
command input 0 to 527 command command

RY/BY RY/BY automatically returns to Ready after

completion of the operation.
Data input
Program Reading & verification

Selected The data is transferred (programmed) from the register to the selected
page page on the rising edge of WE following input of the “10h” command.
After programming, the programmed data is transferred back to the
register to be automatically verified by the device. If the programming
does not succeed, the Program/Verify operation is repeated by the
device until success is achieved or until the maximum loop number set in
Figure 6. Auto Page Program operation the device is reached.

Auto Block Erase

The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which
follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an ertra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.

Pass
60 D0 70 I/O
Block Address Erase Start Status Read Fail
input: 3 cycles command command

RY/BY Busy

23 2010-07-13
 TC58DVM92A5TA00
Reset
The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally
generated voltage is discharged to 0 volts and the device enters Wait state.
The response to an “FFh” Reset command input during the various device operations is as follows:

When a Reset (FFh) command is input during programming

Figure 7.

80 10 FF 00

Internal VPP

RY/BY
tRST (max 10 μs)

When a Reset (FFh) command is input during erasing

Figure 8.

D0 FF 00

Internal erase
voltage

RY/BY

tRST (max 500 μs)

When a Reset (FFh) command is input during Read operation

Figure 9.

00 FF 00

RY/BY

tRST (max 5 μs)

When a Status Read command (70h) is input after a Reset

Figure 10.

FF 70
I/O status: Pass/Fail → Pass
Ready/Busy → Ready
RY/BY

FF 70
I/O status: Ready/Busy → Busy

RY/BY

When two or more Reset commands are input in succession

Figure 11.

(1) (2) (3)

FF FF FF

RY/BY

The second FF command is invalid, but the third FF command is valid.

24 2010-07-13
 TC58DVM92A5TA00
ID Read
ID Read command 90h provides maker code and device code. The ID codes can be read out under the following
timing conditions:

CLE
tCEA
CE

WE
tALEA
ALE

RE
tREA
I/O 90h 00h 98h 76h

ID Read command Address Maker code Device code

00h
Figure 12. ID Read timing

Table 6. ID Codes read out by ID read command 90h

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data

Maker code 1 0 0 1 1 0 0 0 98h

Device code 0 1 1 1 0 1 1 0 76h

25 2010-07-13
 TC58DVM92A5TA00
APPLICATION NOTES AND COMMENTS

(1) Power-on/off sequence:

The WP signal is useful for protecting against data corruption at power-on/off. The following timing
sequence is necessary.
The WP signal may be negated any time after the VCC reaches 2.5 V and CE signal is kept high in
power up sequence.

2.7 V
2.5 V
VCC
0V
Don’t Don’t
care care
CE , WE , RE
CLE, ALE

VIH

VIL VIL
WP
Operation

In order to operate this device stably, after VCC becomes 2.5V, it should begin access after about 1ms.

Figure 13. Power-on/off Sequence

(2) Status after power-on

The following sequence is necessary because some input signals may not be stable at power-on.

Power on FF

Reset

Figure 14.

(3) Prohibition of unspecified commands

The operation commands are listed in Table 4. Input of a command other than those specified in Table 4 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.

(4) Restriction of command while Busy state

During Busy state, do not input any command except 70h and FFh.

26 2010-07-13
 TC58DVM92A5TA00
(5) Acceptable commands after Serial Input command “80h”

Once the Serial Input command “80h” has been input, do not input any command other than the Program
Execution command “10h” or the Reset command “FFh”.

If a command other than “10h” or “FFh” is input, the Program operation is not performed.

80 XX 10
For this operation the “FFh” command is needed.
Command other than Programming cannot be
“10h” or “FFh” executed.

(6) Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.

From the LSB page to MSB page Ex.) Random page program (Prohibition)
DATA IN: Data (1) Data (32) DATA IN: Data (1) Data (32)

Data register Data register

Page 0 (1) Page 0 (2)

Page 1 (2) Page 1 (16)
Page 2 (3) Page 2 (3)

Page 15 (16) Page 15 (1)

Page 31 (32) Page 31 (32)

Figure 15. page programming within a block

(7) Status Read during a Read operation

00

[A]
command 00 70

CE

WE

RY/BY

RE
Address N Status Read
command input Status Read Status output

Figure 16.

The device status can be read out by inputting the Status Read command “70h” in Read mode.
Once the device has been set to Status Read mode by a “70h” command, the device will not return to Read
mode.
Therefore, a Status Read during a Read operation is prohibited.
However, when the Read command “00h” is inputted during [A], Status mode is reset and the device
returns to Read mode. In this case, data output starts automatically from address N and address input is
unnecessary.

27 2010-07-13
 TC58DVM92A5TA00

(8) Pointer control for “00h”, “01h” and “50h”

The device has three Read modes which set the destination of the pointer. Table 7 shows the destination of
the pointer, and Figure 17 is a block diagram of their operations.

Table 7. Pointer Destination

Read Mode Command Pointer 0 255 256 511 512 527

A B C
(1) 00h 0 to 255

(2) 01h 256 to 511

(3) 50h 512 to 527

(1) 00h
(2) 01h Pointer control
(3) 50h
Figure 17 Pointer control

The pointer is set to region A by the “00h” command, to region B by the “01h” command, and to region C by
the “50h” command.

(Example)
The “00h” command must be input to set the pointer back to region A when the pointer is pointing to
region C.

00h 50h
Add Start point Add Start point Add Start point
A area A area C area

50h 00h
Add Start point Add Start point Add Start point
C area C area A area

01h
Add Start point Add Start point
B area A area

To program region C only, set the start point to region C using the 50h command.

50h 80h 10h

Add DIN Programming region C only
Start point
C Area

01h 80h 10h

Add DIN Programming region B and C
Start point
B Area

Figure 18. Example of How to Set the Pointer

28 2010-07-13
 TC58DVM92A5TA00

(9) RY/ BY : termination for the Ready/Busy pin ( RY/ BY )

A pull-up resistor needs to be used for termination because the RY/ BY buffer consists of an open drain
circuit.
VCC
Ready
VCC
R
Device Busy
RY/BY
CL tf tr

VSS VCC = 3.3 V

1.5 μs Ta = 25°C 15 ns
Figure 19. CL = 100 pF
tf
tr 1.0 μs 10 ns tf
tr
This data may vary from device to device. 0.5 μs 5 ns
We recommend that you use this data as a reference
when selecting a resistor value. 0
1 kΩ 2 kΩ 3 kΩ 4 kΩ
R

29 2010-07-13
 TC58DVM92A5TA00

(10) Note regarding the WP signal

The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:

Enable Programming

WE

DIN 80 10

WP

RY/BY

tWW (100 ns min)

Disable Programming

WE

DIN 80 10

WP

RY/BY

tWW (100 ns min)

Enable Erasing

WE

DIN 60 D0

WP

RY/BY

tWW (100 ns min)

Disable Erasing

WE

DIN 60 D0

WP

RY/BY

tWW (100 ns min)

30 2010-07-13
 TC58DVM92A5TA00

(11) When five address cycles are input

Although the device may read in a fifth address, it is ignored inside the chip.

Read operation

CLE

CE

WE

ALE

I/O

00h, 01h or 50h Address input ignored

RY/BY

Internal read operation starts when WE goes High in the fourth cycle.

Figure 20.

Program operation

CLE

CE

WE

ALE

I/O 80h

Address input Data input

ignored

Figure 21.

31 2010-07-13
 TC58DVM92A5TA00

(12) Several programming cycles on the same page (Partial Page Program)

A page can be divided into up to 3 segments. Each segment can be programmed individually as follows:

1st programming Data Pattern 1 All 1 s

2nd programming All 1 s Data Pattern 2 All 1 s

3rd programming All 1 s Data Pattern 3

Result Data Pattern 1 Data Pattern 2 Data Pattern 3

Figure 22

Note: The input data for unprogrammed or previously programmed page segments must be “1”

(13) Note regarding the RE signal

RE The internal column address counter is incremented synchronously with the RE clock in Read
mode. Therefore, once the device has been set to Read mode by a “00h”, “01h” or “50h” command, the
internal column address counter is incremented by the RE clock independently of the address input timing,
If the RE clock input pulses start before the address input, and the pointer reaches the last column
address, an internal read operation (array to register) will occur and the device will enter Busy state. (Refer
to Figure 23.)

Address input

I/O 00h/01h/50h

WE

RE

RY/BY

Figure 23.

Hence the RE clock input must start after the address input.

32 2010-07-13
 TC58DVM92A5TA00

(14) Invalid blocks (bad blocks)

The device contains unusable blocks. Therefore, at the time of use, please check whether a block is bad
and do not use these bad blocks.

At the time of shipment, all data bytes in a Valid Block are FFh. For Bad
Block, all bytes are not in the FFh state. Please don’t perform erase
operation to Bad Block.
Bad Block
Check if the device has any bad blocks after installation into the system.
Figure 25 shows the test flow for bad block detection. Bad blocks which are
detected by the test flow must be managed as unusable blocks by the
system.
A bad block does not affect the performance of good blocks because it is
Bad Block isolated from the Bit line by the Select gate

Figure 24
The number of valid blocks over the device lifetime is as follows:

MIN TYP. MAX UNIT

Valid (Good) Block Number 4016 ⎯ 4096 Block

Bad Block Test Flow

Start Read Check: Read column 517 of the 1st page

in the block. If the column is not
FFh , define the block as a bad
block.
Block No = 1

Fail
Read Check

Pass
Block No. = Block No. + 1 Bad Block *1

No
Block No. = 4096

Yes

End

*1: No erase operation is allowed to detected bad blocks

Figure 25

33 2010-07-13
 TC58DVM92A5TA00

(15) Failure phenomena for Program and Erase operations

The device may fail during a Program or Erase operation.

The following possible failure modes should be considered when implementing a highly reliable system.

FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE

Block Erase Failure Status Read after Erase → Block Replacement

Programming
Page Status Read after Program → Block Replacement
Failure

Programming
Single Bit Failure ECC
1→0

• ECC: Error Correction Code. 1 bit correction per 512 Bytes is necessary.

• Block Replacement

Program

Error occurs When an error happens in Block A, try to

Buffer reprogram the data into another Block (Block
memory Block A B) by loading from an external buffer. Then,
prevent further system accesses to Block A (by
creating a bad block table or by using an
another appropriate scheme).

Block B

Figure 26.

Erase
When an error occurs in an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).

(16) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.

34 2010-07-13
 TC58DVM92A5TA00
(17) Reliability Guidance
This reliability guidance is intended to notify some guidance related to using NAND flash with
1 bit ECC for each 512 bytes. For detailed reliability data, please refer to TOSHIBA’s reliability note.
Although random bit errors may occur during use, it does not necessarily mean that a block is bad.
Generally, a block should be marked as bad when a program status failure or erase status failure is detected.
The other failure modes may be recovered by a block erase.
ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.

• Write/Erase Endurance
Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read
after either an auto program or auto block erase operation. The cumulative bad block count will increase
along with the number of write/erase cycles.

• Data Retention
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge
gain. After block erasure and reprogramming, the block may become usable again.

Here is the combined characteristics image of Write/Erase Endurance and Data Retention.

Data
Retention
[Years]

Wr ite/Erase Endurance [Cycles]

• Read Disturb
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit
errors occur on other pages in the block, not the page being read. After a large number of read cycles
(between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another
state. After block erasure and reprogramming, the block may become usable again.

35 2010-07-13
 TC58DVM92A5TA00
Package Dimensions

Weight: 0.53 g (typ.)

36 2010-07-13
 TC58DVM92A5TA00
Revision History

Date Rev. Description

2009-11-24 1.00 Original version
2010-04-23 1.01 Described ECC as 1 bit correction per 512 Bytes.
2010-07-13 1.02 Deleted TENTATIVE notation.

37 2010-07-13
 TC58DVM92A5TA00
RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively “Product”) without notice.

• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.

• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
APPLICATIONS.

• Product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring
equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document.
Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or
reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious
public impact (“Unintended Use”). Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used
in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling
equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric
power, and equipment used in finance-related fields. Do not use Product for Unintended Use unless specifically permitted in this
document.

• Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.

• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.

• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.

• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE
FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR
LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND
LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO
SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.

• Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product
or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations.

• Product is subject to foreign exchange and foreign trade control laws.

• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.

38 2010-07-13