TC58NS256DC

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

2 TM
256-MBIT (32M × 8 BITS) CMOS NAND E PROM (32M BYTE SmartMedia )
DESCRIPTION
The TC58NS256 is a single 3.3-V 256-Mbit (276,824,064) bit NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 2048 blocks. The device has a 528-byte
static register which allows program and read data to be transferred between the register and the memory cell
array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes:
528 bytes × 32 pages).
The TC58NS256 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed.
The TC58NS256DC is a SmartMediaTM with ID and each device has 128 bit unique ID number embedded in the
device. This unique ID number is applicable to image files, music files, electronic books, and so on where copyright
protection is required.
The data stored in the TC58NS256DC needs to comply with the data format standardized by the SSFDC Forum
in order to maintain compatibility with other SmartMediaTM systems.
FEATURES
• Organization • Power supply
Memory cell array 528 × 64K × 8 VCC = 3.3 V ± 0.3 V
Register 528 × 8 • Access time
Page size 528 bytes Cell array-register 25 µs max
Block size (16K + 512) bytes Serial Read cycle 50 ns min
• Modes • Operating current
Read, Reset, Auto Page Program, Read (50-ns cycle) 10 mA typ.
Auto Block Erase, Status Read Program (avg.) 10 mA typ.
• Mode control Erase (avg.) 10 mA typ.
Serial input/output, Command control Standby 100 µA max
• Complies with the SmartMediaTM Electrical • Package
Specification and Data Format Specification TC58NS256DC: FDC-22A (Weight: 1.8 g typ.)
issued by the SSFDC Forum
PIN ASSIGNMENT (TOP VIEW) PIN NAMES
VSS CLE ALE WE WP I/O1 I/O2 I/O3 I/O4 VSS VSS I/O1~I/O8 I/O port
CE Chip enable
WE Write enable
RE Read enable
CLE Command latch enable
ALE Address latch enable
WP Write protect

1 2 3 4 5 6 7 8 9 10 11 RY/BY Ready/Busy
GND Ground Input
LVD Low Voltage Detect
22 21 20 19 18 17 16 15 14 13 12 VCC Power supply
VSS Ground

TM
is a trademark of Toshiba Corporation.
VCC CE RE RY/BY GND LVD I/O8 I/O7 I/O6 I/O5 VCC
000707EBA2

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or
damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.

2000-08-27 1/33
 TC58NS256DC
BLOCK DIAGRAM

VCC VSS
Status register

I/O1 Address register Column buffer

I/O control circuit Column decoder

~

I/O8 Command register Data register

Sense amp

CE

ROW address decoder

ROW address buffer
CLE

decoder
ALE Memory cell array
Logic control Control circuit
WE
RE
Extended area
WP (embedded ID)

RY/BY
RY/BY HV generator

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER RATING UNIT

VCC Power Supply Voltage −0.6~4.6 V

VIN Input Voltage −0.6~4.6 V

VI/O Input/Output Voltage −0.6 V~VCC + 0.3 V (≤ 4.6 V) V

PD Power Dissipation 0.3 W

Tstg Storage Temperature −20~65 °C

Topr Operating Temperature 0~55 °C

CAPACITANCE *(Ta = 25°C, f = 1 MHz)

SYMBOL PARAMETER CONDITION MIN MAX UNIT

CIN Input VIN = 0 V  10 pF

COUT Output VOUT = 0 V  10 pF

* This parameter is periodically sampled and is not tested for every device.

000707EBA2

• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
• The information contained herein is subject to change without notice.

2000-08-27 2/33
 TC58NS256DC
VALID BLOCKS (1)

SYMBOL PARAMETER MIN TYP. MAX UNIT

NVB Number of Valid Blocks 2008  2048 Blocks

(1) The TC58NS256 occasionally contains unusable blocks. Refer to Application Note 14 toward the end of this document.

RECOMMENDED DC OPERATING CONDITIONS

SYMBOL PARAMETER MIN TYP. MAX UNIT

VCC Power Supply Voltage 3 3.3 3.6 V

VIH High Level Input Voltage 2  VCC + 0.3 V

VIL Low Level Input Voltage −0.3*  0.8 V

* −2 V (pulse width ≤ 20 ns)

DC CHARACTERISTICS (Ta = 0°~55°C, VCC = 3.3 V ± 0.3 V)

SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT

IIL Input Leakage Current VIN = 0 V~VCC   ±10 µA

ILO Output Leakage Current VOUT = 0.4 V~VCC   ±10 µA

CE = VIL, IOUT = 0 mA,

ICCO1 Operating Current (Serial Read)  10 30 mA
tcycle = 50 ns

Operating Current
ICCO3 tcycle = 50 ns  10 30 mA
(Command Input)

ICCO4 Operating Current (Data Input) tcycle = 50 ns  10 30 mA

Operating Current
ICCO5 tcycle = 50 ns  10 30 mA
(Address Input)

ICCO7 Programming Current   10 30 mA

ICCO8 Erasing Current   10 30 mA

ICCS1 Standby Current CE = VIH   1 mA

ICCS2 Standby Current CE = VCC − 0.2 V   100 µA

VOH High Level Output Voltage IOH = −400 µA 2.4   V

VOL Low Level Output Voltage IOL = 2.1 mA   0.4 V

IOL ( RY/BY ) Output Current of RY/BY Pin VOL = 0.4 V  8  mA

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 TC58NS256DC
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = 0°~55°C, VCC = 3.3 V ± 0.3 V)
SYMBOL PARAMETER MIN MAX UNIT NOTES

tCLS CLE Setup Time 0  ns

tCLH CLE Hold Time 10  ns
tCS CE Setup Time 0  ns
tCH CE Hold Time 10  ns
tWP Write Pulse Width 25  ns
tALS ALE Setup Time 0  ns
tALH ALE Hold Time 10  ns
tDS Data Setup Time 20  ns
tDH Data Hold Time 10  ns
tWC Write Cycle Time 50  ns
tWH WE -High Hold Time 15  ns
tWW WP High to WE Low 100  ns
tRR Ready-to- RE Falling Edge 20  ns
tRP Read Pulse Width 35  ns
tRC Read Cycle Time 50  ns
tREA RE Access Time (Serial Data Access)  35 ns
tCEH CE -High Time for Last Address in Serial Read Cycle 100  ns (2)
tREAID RE Access Time (ID Read)  35 ns
tOH Data Output Hold Time 10  ns
tRHZ RE -High-to-Output-High Impedance  30 ns
tCHZ CE -High-to-Output-High Impedance  20 ns
tREH RE -High Hold Time 15  ns
tIR Output-High-Impedance-to- RE Rising Edge 0  ns
tRSTO RE Access Time (Status Read)  35 ns
tCSTO CE Access Time (Status Read)  45 ns
tRHW RE High to WE Low 0  ns
tWHC WE High to CE Low 30  ns
tWHR WE High to RE Low 30  ns
tAR1 ALE Low to RE Low (ID Read) 100  ns
tCR CE Low to RE Low (ID Read) 100  ns
tR Memory Cell Array to Starting Address  25 µs
tWB WE High to Busy  200 ns
tAR2 ALE Low to RE Low (Read Cycle) 50  ns
tRB RE Last Clock Rising Edge to Busy (in Sequential Read)  200 ns
600 + tr
tCRY CE High to Ready (When interrupted by CE in Read Mode)  ns (1)
( RY/BY )
tRST Device Reset Time (Read/Program/Erase)  6/10/500 µs

AC TEST CONDITIONS

PARAMETER VALUES

Input level 2.4 V, 0.4 V

Input pulse rise and fall time 3 ns
Input comparison level 1.5 V, 1.5 V
Output data comparison level 1.5 V, 1.5 V
Output load CL (100 pF) + 1 TTL

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 TC58NS256DC

Notes:
(1) CE High to Ready time depends on the pull-up resistor tied to the RY/ BY pin.
(Refer to Application Note (7) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns.
If the RE to CE delay is less than 30 ns, RY/ BY signal stays Ready.

tCEH ≥ 100 ns

* *: VIH or VIL
CE

RE
A A : 0~30 ns → Busy signal is not output.
525 526 527

RY/BY

Busy

PROGRAMMING AND ERASING CHARACTERISTICS

(Ta = 0°~55°C, VCC = 3.3 V ± 0.3 V)

SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES

tPROG Programming Time  200 1000 µs

Number of Programming Cycles on Same

N   10 (1)
Page

tBERASE Block Erasing Time  3 4 ms

P/E Number of Program/Erase Cycles   2.5 x 105 (2)

(1) Refer to Application Note 12 toward the end of this document.

(2) Refer to Application Note 15 toward the end of this document.

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 TC58NS256DC
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data

CLE
ALE
CE
RE Setup Time Hold Time

WE

tDS tDH

I/O1
~I/O8

: VIH or VIL

Command Input Cycle Timing Diagram

CLE
tCLS tCLH
tCS tCH

CE

tWP

WE

tALS tALH

ALE

tDS tDH

I/O1
~I/O8

: VIH or VIL

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 TC58NS256DC
Address Input Cycle Timing Diagram

tCLS

CLE

tCS tWC tWC

CE

tWP tWH tWP tWH tWP

WE

tALS tALH

ALE

tDS tDH tDS tDH tDS tDH

I/O1 A0~A7 A9~A16 A17~A24

~I/O8

: VIH or VIL

Data Input Cycle Timing Diagram

tCLH

CLE

tCH

CE

tALS tWC

ALE

tWP tWH tWP tWP

WE

tDS tDH tDS tDH tDS tDH

I/O1 DIN0 DIN1 DIN 527

~I/O8

: VIH or VIL

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 TC58NS256DC
Serial Read Cycle Timing Diagram

tRC

CE

tRP tREH tRP tRP tCHZ

RE
tOH tOH tOH
tREA tRHZ tREA tRHZ tREA tRHZ

I/O1
~I/O8
tRR

RY/BY

Status Read Cycle Timing Diagram

tCLS

CLE
tCLS tCLH

tCS

CE

tWP tCH

WE
tWHC tCSTO tCHZ
tWHR

RE
tOH
tDS tDH tIR
tRSTO tRHZ

I/O1 Status
70H*
~I/O8 output

RY/BY

* 70H represents the hexadecimal number 70. : VIH or VIL

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 TC58NS256DC
Read Cycle (1) Timing Diagram

CLE
tCLS tCLH
tCEH
tCS tCH

CE
tWC tCRY

WE
tALH tALS tALH tAR2

ALE
tR tRR tRC

tWB
RE
tDS tDH tDS tDH tDS tDH tDS tDH tREA

I/O1 DOUT DOUT DOUT DOUT

00H A0~A7 A9~A16 A17~A24
~I/O8 N N+1 N+2 527
tRB
Column address
N*
RY/BY

: VIH or VIL

Read Cycle (1) Timing Diagram: When Interrupted by CE

CLE
tCLS tCLH

tCS tCH

CE
tWC tCHZ

WE
tALH tALS tALH tAR2

ALE
tR tRR tRC

tWB
RE tOH
tDS tDH tDS tDH tDS tDH tDS tDH tREA tRHZ

I/O1 DOUT DOUT DOUT

00H A0~A7 A9~A16 A17~A24
~I/O8 N N+1 N+2
Column address
N*
RY/BY

* Read Operation using 00H Command N: 0~255 : VIH or VIL

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 TC58NS256DC
Read Cycle (2) Timing Diagram

CLE
tCLS tCLH

tCS tCH

CE

WE
tALH tALS tALH tAR2

ALE
tR tRR tRC

tWB
RE
tDS tDH tDS tDH tREA

I/O1 01H A0~A7 A9~A16 A17~A24 DOUT DOUT DOUT

~I/O8
Column address 256 + M 256 + M + 1 527
N*
RY/BY

* Read Operation using 01H Command N: 0~255 : VIH or VIL

Read Cycle (3) Timing Diagram

CLE
tCLS tCLH

tCS tCH

CE

WE
tALH tALS tALH tAR2

ALE
tR tRR tRC

tWB
RE
tDS tDH tDS tDH tREA

I/O1 50H A0~A7 A9~A16 A17~A24 DOUT DOUT DOUT

~I/O8
Column address 512 + M 512 + M + 1 527
N*
RY/BY

* Read Operation using 50H Command N: 0~15 : VIH or VIL

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 TC58NS256DC
Sequential Read (1) Timing Diagram

CLE

CE

WE

ALE

RE

I/O1 00H A0~A7 A9~A16 A17~A24 N N+1 N+2 527 0 1 2 527

~I/O8
Column Page
address address tR tR
N M

RY/BY

Page M Page M + 1
access access
: VIH or VIL

Sequential Read (2) Timing Diagram

CLE

CE

WE

ALE

RE

I/O1 01H A0~A7 A9~A16 A17~A24 527 0 1 2 527

~I/O8
Column Page
address address tR 256 + 256 + 256 + tR
N M N N+1 N+2

RY/BY

Page M Page M + 1
access access
: VIH or VIL

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 TC58NS256DC
Sequential Read (3) Timing Diagram

CLE

CE

WE

ALE

RE

I/O1 50H A0~A7 A9~A16 A17~A24 527 512 513 514 527
~I/O8
Column Page
address address tR 512 + 512 + 512 + tR
N M N N+1 N+2

RY/BY

Page M Page M + 1
access access
: VIH or VIL

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 TC58NS256DC
Auto-Program Operation Timing Diagram
tCLS

CLE
tCLS tCLH
tCS

CE

tCS tCH

WE
tALH tALH
tALS tALS tPROG
tWB
ALE

RE
tDS
tDS tDH tDS tDH tDH tDS tDH

I/O1 DIN
80H A0~A7 A9~A16 A17~A24 DIN0 DIN1 10H 70H
~I/O8 527
Status
output

RY/BY

: VIH or VIL : Do not input data while data is being output.

Auto Block Erase Timing Diagram

CLE
tCLS
tCLH
tCS tCLS
CE

WE

tALS tALH tWB tBERASE

ALE

RE

tDS tDH

I/O1 Status
60H A9~A16 A17~A24 D0H 70H
~I/O8 output

RY/BY Auto Block Erase Erase Start Busy Status Read

Setup command command command
: VIH or VIL : Do not input data while data is being output.

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 TC58NS256DC
ID Read Operation Timing Diagram

CLE
tCLS
tCLS
tCS tCH tCS

CE

tCH

WE
tCR
tALH tALS tALH tAR1

ALE

RE

tDS tDH tREAID tREAID tREAID

I/O1 90H 00 98H 75H A5H

~I/O8

Address input Maker code Device code Option code

: VIH or VIL

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 TC58NS256DC
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information. The device
pin-outs are configured as shown in Figure 1. TC58NS256DC

1 2 3 4 5 6 7 8 9 10 11
Command Latch Enable: CLE
VSS CLE ALE WE WP I/O1 I/O2 I/O3 I/O4 VSS VSS
The CLE input signal is used to control loading of the
operation mode command into the internal command register.
The command is latched into the command register from the I/O
port on the rising edge of the WE signal while CLE is High.

Address Latch Enable: ALE

The ALE signal is used to control loading of either address
information or input data into the internal address/data register.
Address information is latched on the rising edge of WE if ALE
is High. Input data is latched if ALE is Low.

22 21 20 19 18 17 16 15 14 13 12
Chip Enable: CE
VCC CE RE RY/BY GND LVD I/O8 I/O7 I/O6 I/O5 VCC
The device goes into a low-power Standby mode when CE
Figure 1. Pinout
goes High during a Read operation. The CE signal is ignored
when device is in Busy state ( RY/ BY = L), such as during a Program or Erase operation, and will not enter
Standby mode even if the CE input goes High. The CE signal must stay Low during the Read mode Busy
state to ensure that memory array data is correctly transferred to the data register.

Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.

Read Enable: RE
The RE signal controls serial data output. Data is available tREA after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + 1) on this falling edge.

I/O Port: I/O1~I/O8

The I/O1 to I/O8 pins are used as a port for transferring address, command and input/output data to and from
the device.

Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.

Ready/Busy: RY / BY
The RY/ BY output signal is used to indicate the operating condition of the device. The RY/ BY signal is in
Busy state ( RY/ BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY/ BY = H) after completion of the operation. The output buffer for this signal is an open drain.

Low Voltage Detect: LVD

The LVD signal is used to detect the power supply voltage level.

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 TC58NS256DC
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.

I/O1
A page consists of 528 bytes in which 512 bytes are
512 16
I/O8 used for main memory storage and 16 bytes are for
redundancy or for other uses.

1 page = 528 bytes

32 pages 1 block = 528 bytes × 32 pages = (16K + 512) bytes
Capacity = 528 bytes × 32 pages × 2048 blocks

=
65536 pages 1 block
=

2048 blocks An address is read in via the I/O port over three
consecutive clock cycles, as shown in Table 1.

8I/O

528
Figure 2. Schematic Cell Layout

Table 1. Addressing

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1

A0~A7: Column address
First cycle A7 A6 A5 A4 A3 A2 A1 A0 A9~A24: Page address
A14~A24: Block address
Second cycle A16 A15 A14 A13 A12 A11 A10 A9 A9~A13: NAND address in block
Third cycle A24 A23 A22 A21 A20 A19 A18 A17

*: A8 is automatically set to Low or High by a 00H command or a 01H command.

Operation Mode: Logic and Command Tables

The operation modes such as Program, Erase, Read and Reset are controlled by the ten different command
operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE,
ALE, CE , WE , RE and WP signals, as shown in Table 2.

Table 2. Logic table

CLE ALE CE WE RE WP

Command Input H L L H *

Data Input L L L H *

Address Input L H L H *

Serial Data Output L L L H *

During Programming (Busy) * * * * * H

During Erasing (Busy) * * * * * H

Program, Erase Inhibit * * * * * L

H: VIH, L: VIL, *: VIH or VIL

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 TC58NS256DC

Table 3. Command table (HEX)

First Cycle Second Cycle Acceptable while Busy

HEX data bit assignment
Serial Data Input 80 
(Example)
Read Mode (1) 00 
Serial data input: 80H
Read Mode (2) 01 

Read Mode (3) 50 

1 0 0 0 0 0 0 0
Reset FF  c
I/O8 7 6 5 4 3 2 I/O1
Auto Program 10 

Auto Block Erase 60 D0

Status Read 70  c

ID Read 90 

Once the device has been set to Read mode by a 00H, 01H or 50H command, additional Read commands are
not needed for sequential page Read operations. Table 4 shows the operation states for Read mode.

Table 4. Read mode operation states

CLE ALE CE WE RE I/O1~I/O8 Power

Output Select L L L H L Data output Active

Output Deselect L L L H H High impedance Active

Standby L L H H * High impedance Standby

H: VIH, L: VIL, *: VIH or VIL

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 TC58NS256DC
DEVICE OPERATION
Read Mode (1)
Read mode (1) is set when a 00H command is issued to the Command register. Refer to Figure 3 below for
timing details and the block diagram.

CLE

CE

WE

ALE

RE

RY/BY Busy
N
M
I/O 00H

Start-address input

M 527 A data transfer operation from the cell array to the register
starts on the rising edge of WE in the third cycle (after the
address information has been latched). The device will be in
Select page
Busy state during this transfer period. The CE signal must
N Cell array
stay Low after the third address input and during Busy state.
After the transfer period the device returns to Ready state.
Figure 3. Read mode (1) operation Serial data can be output synchronously with the RE clock
from the start pointer designated in the address input cycle.

Read Mode (2)

CLE

CE

WE

ALE

RE

RY/BY Busy
N
M
I/O 01H

Start-address input

256 M 527 The operation of the device after input of the 01H command is
the same as that of Read mode (1). If the start pointer is to be
set after column address 256, use Read mode (2).
Select page
However, for a Sequential Read, output of the next page
N Cell array
starts from column address 0.

Figure 4. Read mode (2) operation

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 TC58NS256DC
Read Mode (3)
Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra
16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte
527.

CLE

CE

WE

ALE

RE

RY/BY Busy

I/O 50H

Addresses bits A0~A3 are used to set the start pointer for the
A0~A3
redundant memory cells, while A4~A7 are ignored.
512 527
Once a 50H command has been issued, the pointer moves to
the redundant cell locations and only those 16 cells can be
addressed, regardless of the value of the A4-to-A7 address. (An
00H command is necessary to move the pointer back to the
0-to-511 main memory cell location.)
Figure 5. Read mode (3) operation

Sequential Read (1) (2) (3)

This mode allows the sequential reading of pages without additional address input.

00H

01H

50H Address input Data output Data output

tR tR tR

RY/BY
Busy Busy Busy
(00H)
0 527 (01H) (50H) 512 527

A
A A

Sequential Read (1) Sequential Read (2) Sequential Read (3)

Sequential Read modes (1) and (2) output the contents of addresses 0~527 as shown above, while Sequential
Read mode (3) outputs the contents of the redundant address locations only. When the pointer reaches the last
address, the device continues to output the data from this address ** on each RE clock signal.

** Column address 527 on the last page.

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 TC58NS256DC
Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result
(pass/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device
status is output via the I/O port on the RE clock after a 70H command input. The resulting information is
outlined in Table 5.

Table 5. Status output table

STATUS OUTPUT

I/O1 Pass/Fail Pass: 0 Fail: 1

I/O2 Not Used 0

I/O3 Not Used 0 The Pass/Fail status on I/O1 is only

valid when the device is in the Ready
I/O4 Not Used 0
state.
I/O5 Not Used 0

I/O6 Not Used 0

I/O7 Ready/Busy Ready: 1 Busy: 0

I/O8 Write Protect Protect: 0 Not Protected: 1

An application example with multiple devices is shown in Figure 6.

CE1 CE2 CE3 CEN CEN + 1

CLE
ALE Device Device Device Device Device
WE 1 2 3 N N+1
RE

I/O1
~I/O8
RY/BY

RY/BY Busy

CLE

ALE

WE

CE1

CEN

RE

I/O 70H 70H

Status on Status on
Device 1 Device N

Figure 6. Status Read timing application example

System Design Note: If the RY/ BY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each individual device.

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 TC58NS256DC
Auto Page Program
The device carries out an Automatic Page Program operation when it receives a 10H Program command after
the address and data have been input. The sequence of command, address and data input is shown below. (Refer
to the detailed timing chart.)

Pass
80 10 70 I/O
Data input Address Data input Program Status Read
Fail
command input 0~527 command command

RY/BY RY/BY automatically returns to Ready after

completion of the operation.
Data input
Program Reading & verification
Selected The data is transferred (programmed) from the register to the selected
page page on the rising edge of WE following input of the 10H command.
After programming, the programmed data is transferred back to the
register to be automatically verified by the device. If the programming
does not succeed, the Program/Verify operation is repeated by the
device until success is achieved or until the maximum loop number set in
Figure 7. Auto Page Program operation the device is reached.

Auto Block Erase

The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command D0H which
follows the Erase Setup command 60H. This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.

Pass
60 D0 70 I/O
Block address Erase Start Status Read Fail
input: 2 cycles command command

RY/BY Busy

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 TC58NS256DC
Reset
The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally
generated voltage is discharged to 0 volts and the device enters Wait state.
The address and data registers are set as follows after a Reset:
• Address Register: All 0
• Data Register: All 1
• Operation Mode: Wait state
The response to an FFH Reset command input during the various device operations is as follows:

When a Reset (FFH) command is input during programming

Figure 8.

80 10 FF 00

Register set
Internal VPP

RY/BY
tRST (max 10 µs)

When a Reset (FFH) command is input during erasing

Figure 9.

D0 FF 00

Internal erase
voltage
Register set
RY/BY
tRST (max 500 µs)

When a Reset (FFH) command is input during a Read operation

Figure 10.

00 FF 00

RY/BY

tRST (max 6 µs)

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 TC58NS256DC
When a Status Read command (70H) is input after a Reset
Figure 11.

FF 70
I/O status: Pass/Fail → Pass
Ready/Busy → Ready
RY/BY
However, the following operation is prohibited. If the following operation is executed, correct resetting of the
address and data register cannot be guaranteed.

FF 70
I/O status: Ready/Busy → Busy
RY/BY

When two or more Reset commands are input in succession

Figure 12.
(1) (2) (3)

10 FF FF FF

RY/BY

The second FF command is invalid, but the third FF command is valid.

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 TC58NS256DC
ID Read
The TC58NS256 contains ID codes which identify the device type and the manufacturer. The ID codes can be
read out under the following timing conditions:

CLE
tCR
CE

WE
tAR1
ALE

RE
tREAID
I/O 90H 00 98H 75H A5H

ID Read command Address Maker code Device code Option code

00

For the specifications of the access times tREAID, tCR and tAR1 refer to the AC Characteristics.

Figure13. ID Read timing

Table 6. Code table

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 Hex Data

Maker code 1 0 0 1 1 0 0 0 98H

Device code 0 1 1 1 0 1 0 1 75H

Option code 1 0 1 0 0 1 0 1 A5H*

* The A5H for the 3rd byte of ID read means the existence of 128 bit unique ID number in the device.

How to read out unique ID number

The 128 bit unique ID number is embedded in the device. The procedure to read out the ID number is available
using special command which is provided under a non-disclosure agreement.

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 TC58NS256DC
APPLICATION NOTES AND COMMENTS

(1) Prohibition of unspecified commands

The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.

(2) Restriction of command while Busy state

During Busy state, do not input any command except 70H and FFH.

(3) Pointer control for 00H, 01H and 50H

The device has three Read modes which set the destination of the pointer. Table 7 shows the destination of
the pointer, and Figure 14 is a block diagram of their operations.
0 255 256 511 512 527
Table 7. Pointer Destination
A B C
Read Mode Command Pointer

(1) 00H 0~255

(2) 01H 256~511

00H
(3) 50H 512~527 01H Pointer control
50H
Figure 14. Pointer control

The pointer is set to region A by the 00H command, to region B by the 01H command, and to region C by the
50H command.

(Example)
The 00H command must be input to set the pointer back to region A when the pointer is pointing to region
C.

00H 50H
Address Start point Address Start point Address Start point
A area A area C area

50H 00H
Address Start point Address Start point Address Start point
C area C area A area

01H
Address Start point Address Start point
B area A area

To program region C only, set the start point to region C using the 50H command.

50H 80H 10H

Address DIN Programming region C only
↓
Start point
C area
01H 80H 10H
Address DIN Programming regions B and C
↓
Start point
B area

Figure 15. Example of How to Set the Pointer

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 TC58NS256DC

(4) Acceptable commands after Serial Input command 80H

Once the Serial Input command 80H has been input, do not input any command other than the Program
Execution command 10H or the Reset command FFH.

80 FF

WE
Address input
RY/BY

Figure 16.

If a command other than 10H or FFH is input, the Program operation is not performed.

80 XX 10
For this operation the FFH command is needed.
Command Other than Programming cannot be executed.
10H or FFH

(5) Status Read during a Read operation

00

[A]
Command 00 70

CE

WE

RY/BY

RE
Address N Status Read
command input Status Read Status output

Figure 17.

The device status can be read out by inputting the Status Read command 70H in Read mode. Once the
device has been set to Status Read mode by a 70H command, the device will not return to Read mode.
Therefore, a Status Read during a Read operation is prohibited.
However, when the Read command 00H is input during [A], Status mode is reset and the device returns to
Read mode. In this case, data output starts automatically from address N and address input is unnecessary.

(6) Auto programming failure

Fail
80 10 70 I/O 80 10
Address Data Address Data
M input N input
80
10 If the programming result for page address M is Fail, do not try to program the
page to address N in another block. Because the previous input data has been lost,
M the same input sequence of 80H command, address and data is necessary.

Figure 18.

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 TC58NS256DC

(7) RY/ BY : termination for the Ready/Busy pin ( RY/ BY )

A pull-up resistor needs to be used for termination because the RY/ BY buffer consists of an open drain
circuit.
VCC
Ready
VCC VCC
R 3.0 V 3.0 V
Device 1.0 V Busy 1.0 V
RY/BY
CL
tf tr

VSS VCC = 3.3 V

1.5 µs Ta = 25°C 15 ns
Figure 19. CL = 100 pF
tf
tr 1.0 µs 10 ns tf
tr
This data may vary from device to device. 0.5 µs 5 ns
We recommend that you use this data as a reference
when selecting a resistor value. 0
1 KΩ 2 KΩ 3 KΩ 4 KΩ
R

(8) Status after power-on

The following sequence is necessary because some input signals may not be stable at power-on.

Power on FF

Reset

Figure 20.

(9) Power-on/off sequence:

The WP signal is useful for protecting against data corruption at power-on/off. The following timing
sequence is necessary:

3.0 V
2.8 V

VCC
0V
Don’t Don’t
care care
CE , WE , RE
CLE, ALE
VIH

VIL VIL
WP
Operation

Figure 21. Power-on/off Sequence

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 TC58NS256DC

(10) Note regarding the WP signal

The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:

Enable Programming

WE

DIN 80 10

WP

RY/BY

tWW (100 ns min)

Disable Programming

WE

DIN 80 10

WP

RY/BY

tWW (100 ns min)

Enable Erasing

WE

DIN 60 D0

WP

RY/BY

tWW (100 ns min)

Disable Erasing

WE

DIN 60 D0

WP

RY/BY

tWW (100 ns min)

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 TC58NS256DC

(11) When four address cycles are input

Although the device may read in a fourth address, it is ignored inside the chip.

Read operation

CLE

CE

WE

ALE

I/O

00H, 01H, 50H Address input Ignored

RY/BY

Internal read operation starts when WE goes High in the third cycle.

Figure 22.

Program operation

CLE

CE

WE

ALE

I/O 80H

Address input Data input

Ignored

Figure 23.

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 TC58NS256DC

(12) Several programming cycles on the same page (Partial Page Program)
A page can be divided into up to 10 segments. Each segment can be programmed individually as follows:

First programming Data Pattern 1 All 1s

Second programming All 1s Data Pattern 2 All 1s

Tenth programming All 1s Data Pattern 10

Result Data Pattern 1 Data Pattern 2 Data Pattern 10

Figure 24.

Note: The input data for unprogrammed or previously programmed page segments must be 1
(i.e. the inputs for all page bytes outside the segment which is to be programmed should
be set to all 1).

(13) Note regarding the RE signal

The internal column address counter is incremented synchronously with the RE clock in Read mode.
Therefore, once the device has been set to Read mode by a 00H, 01H or 50H command, the internal column
address counter is incremented by the RE clock independently of the address input timing. If the RE
clock input pulses start before the address input, and the pointer reaches the last column address, an
internal read operation (array → register) will occur and the device will enter Busy state. (Refer to Figure
25.)

Address input

I/O 00H/01H/50H

WE

RE

RY/BY

Figure 25.

Hence the RE clock input must start after the address input.

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 TC58NS256DC

(14) Invalid blocks (bad blocks)

The device contains unusable blocks. Therefore, the following issues must be recognized:

Referring to the Block status area in the redundant area allows the
system to detect bad blocks in the accordance with the physical data
Bad Block format issued by the SSFDC Forum. Detect the bad blocks by checking the
Block Status Area at the system power-on, and do not access the bad
blocks in the following routine.
The number of valid blocks at the time of shipment is as follows:

MIN TYP. MAX UNIT

Bad Block
Valid (Good) Block Number 2008  2048 Block

Figure 26.

(15) Failure phenomena for Program and Erase operations

The device may fail during a Program or Erase operation.

The following possible failure modes should be considered when implementing a highly reliable system.

FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE

Block Erase Failure Status Read after Erase → Block Replacement

Page Programming Failure Status Read after Program → Block Replacement

Programming Failure (1) Block Verify after Program → Retry

Single Bit
1→0 (2) ECC

• ECC: Error Correction Code

• Block Replacement

Program

Error occurs When an error happens in Block A, try to

Buffer reprogram the data into another (Block B) by
memory Block A loading from an external buffer. Then, prevent
further system accesses to Block A (by creating
a bad block table or by using an another
appropriate scheme).

Block B

Figure 27.

Erase
When an error occurs for an Erase operation, prevent future accesses to this bad block (again by
creating a table within the system or by using another appropriate scheme).

(16) Chattering of Connector

There may be contact chattering when the TC58NS256DC is inserted or removed from a connector.
This chattering may cause damage to the data in the TC58NS256DC. Therefore, sufficient time must be
allowed for contact bouncing to subside when a system is designed with SmartMediaTM.

(17) The TC58NS256DC is formatted to comply with the Physical and Logical Data Format of the SSFDC Forum
at the time of shipping.

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 TC58NS256DC
Handling Precaution

(1) Avoid bending or subjecting the card to sudden impact.

(2) Avoid touching the connectors so as to avoid damage from static electricity.
This card should be kept in the antistatic film case when not in use.

(3) Toshiba cannot accept, and hereby disclaims liability for, any damage to the card including data corruption
that may occur because of mishandling.

How to read out unique ID number

The 128 bit unique ID number is embedded in the device. The procedure to read out the ID number is available
using special command which is provided under a non-disclosure agreement.

SSFDC Forum
The SSFDC Forum is a voluntary organization intended to promote the SmartMediaTM, a small removable
NAND flash memory card. The SSFDC Forum standardized the following specifications in order to keep the
compatibility of SmartMediaTM in systems. The latest specifications issued by the Forum must be referenced when
a system is designed with SmartMediaTM, especially with large capacity SmartMediaTM.

SmartMediaTM Electrical Specifications

SmartMediaTM Physical Format Specification
SmartMediaTM Logical Format Specification

Some electrical specifications in this data sheet show differences from the Forum’s electrical specification.
Complying with the Forum’s electrical specification maintains compatibility with other SmartMedias.

Please refer folloing SSFDC Forum’s URL to get the detailed information of each specification.

URL http://www.ssfdc.or.jp

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 TC58NS256DC
PACKAGE DIMENSIONS
• FDC-22A

Unit: mm

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