1

Ultra Low Voltage High Speed 1-Bit

CMOS Adder
S. Wairya, Himanshu Pandey, R. K. Nagaria and S. Tiwari, Member, IEEE

Abstract— In this paper, we present a novel design for realize Different logic styles tend to favour one performance
full adder circuit. Our approach based on XOR-XNOR design aspect at the expense of the others. The logic style used in
full adder circuits in a single unit. Objective of this work is to logic gates basically influences the speed, size, power
investigate the power, delay and power delay product of low dissipation, and the wiring complexity of a circuit. The
voltage full adder cells in different CMOS logic styles. circuit delay is determined by number of inversion levels,
Simulation results illustrate the superiority of the proposed the number of transistors in series, transistor sizes (i.e.
adder circuit against the conventional CMOS, Hybrid, Bridge,
channel widths) and intra-cell wiring capacitances. Circuit
Xor-Xnor adder circuits in terms of power, delay, PDP. The
bridge design style enjoys a high degree of regularity, higher size depends on the number of transistors, their sizes and on
density than conventional CMOS design style as well as lower the wiring complexity. Some of them use one logic style for
power consumption, by using some transistors, named bridge the whole full adder and others use more than one logic style
transistors. The performance of the full adder circuits is based for their implementation.
on GPDK 90nm CMOS process models at all range of the
supply voltage starting from 0.65V to 1.5V evaluated by the Transistor sizes (widths) determine (i) Speed of circuit (ii)
comparison of the simulation results obtained from Cadence. Energy consumption (iii) Total area of circuit (iv)
Simulation results reveal that the proposed circuit exhibits Satisfaction of delay constraints. To bring the switching
lower PDP and is faster when compared with available 1-bit
point at VDD/2 for the basic invertors design, we denoted
full adder circuits. To summarize, some performance criteria
are considered in the design and evaluation of adder cells, of (W/L)n =N and (W/L)p=P where n is usually 1.5 to 2 for a
which some are at ease of design, robustness, silicon area, match design P=Un/Up*N. Thus we used to select individual
delay, and power consumption. The design is implemented on W/L ratios for all transistors in a logic gate so that the PDN
GDPK 90 nm process models in Cadence Virtuoso Schematic should be able to provide a capacitor discharge current at
Composer at 1.5V single ended supply voltage and simulations least equal to that of NMOS transistor with W/L=N and
are carried out on Spectre S. PUN should be able to provide a charging current at least
equal to that of a PMOS transistor with W/L=P .This will
Index Terms—XOR, Full adders, VLSI circuit, Bridge adder, guarantee a worst-case gate delay equal to that of the basic
Hybrid adder . inverter. It means that in deciding on device sizing ,we
should find the input combinations that result in the lowest
I. INTRODUCTION output current and then choose sizes that will make this

P ower consumption and signal delay are crucial to the

design of high-performance very large scale integration
(VLSI) circuits. A designer tries to save power, when
current equal to that of the basic inverter [1]-[4]. By
selecting proper (W/L) ratio we can minimize the power
dissipation without decreasing the power supply and varying
designing a system. The growth of the electronics market has these values to achieve minimized power delay product
driven the VLSI industry towards very high integration (PDP). The power-delay product (PDP) represents a tradeoff
density and system on chip designs. Moreover, with the to be optimized between two conflicting criteria of power
explosive growth the demand and popularity of portable dissipation and circuit latency in transistor sizing.
electronics is driving designers to strive for smaller silicon
area, higher speeds, longer battery life, and more reliability. Power dissipation is determined by the switching activity,
The XOR-XNOR circuits are basic building blocks in node capacitances and control circuit size. Dynamic power
various circuits’ especially- Arithmetic circuits (adder and constitutes the majority of the power dissipated in CMOS
multipliers), Comparators, Parity checkers, Code converters VLSI circuits. It is the power dissipated during charging or
etc. Adder is the core element of complex arithmetic circuits discharging of the load capacitance of a given circuit. The
like addition, multiplication, division, exponentiation, etc. average power dissipated in a generic digital CMOS gate is
To execute an arithmetic operation, a circuit can consume given by [1]-[5]:
very low power by clocking at extremely low frequency but Pavg = Pdynamic + Pshort-circuit + Pstatic
it may take a very long time to complete the operation. = V DD · fclk · Viswing · Ciload · i 
+ V DD ·  Iisc+VDD · Il
Where fclk is the system clock frequency, Viswing is the
Authors are with the Department of Electronics & Communication voltage swing at node i and Ci load is the load capacitance at
Engineering, Motilal Nehru National Institute of Technology, Allahabad- node i where as i is the activity factor at node i. Iisc and Il
211004, India: (e-mail: [email protected], [email protected], are the short circuit and leakage currents respectively.
[email protected], [email protected]).
Output and input capacitances should be low to reduce

978-1-4244-8542-0/10/$26.00 ©2010 IEEE

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dynamic power. Therefore, fewer nodes should be connected decreasing supply voltage is the large transistor count and
to SUM and COUT signals. Avoid using both VDD and GND Vth loss problem.
simultaneously in circuit components. It can reduce short
circuit and static power. Most important components of the There are standard implementations for the full-adder
power consumption in full adders are the XOR and XNOR cells. Among these adders there are the following:
gates. Reducing numbers of transistors usually lead to
reduce the power in full adders. However, sometimes it 1. The Complementary CMOS full adder (C-CMOS) has
does not improve PDP. Therefore, reducing transistor counts 28 transistors and is based on the regular CMOS
does not always lead to reduction in PDP or power structure (pull-up and pull-down networks).
consumption. 2. The Complementary pass-transistor logic (CPL) full
adder, it has 32 transistors and uses the CPL gates.
Static CMOS logic styles have been used to implement 3. The transmission-gate CMOS adder (TG-CMOS) and
low-power 1-bit adder cells. In general, they can be broadly transmission function adder (TFA) are based on
divided into two major categories: the complementary transmission gates logic.
CMOS and the pass-transistor logic circuits. The 4. The Hybrid full adder, which has 26 transistors, is
complementary CMOS full adder (C-CMOS) of Fig. 1(a) is based on a modified low-power XOR/XNOR circuit.
based on the regular CMOS structure with PMOS pull-up 5. The Bridge adder is based on CMOS mirror circuit
and NMOS pull-down transistors. The series transistors in with pass transistor logic gates.
the output stage form a weak driver. Therefore, additional
buffers at the last stage are required to provide the necessary A. Conventional CMOS Style full adders
driving power to the cascaded cells. The advantage of
complementary CMOS style is its robustness against voltage The complementary CMOS full adder (C-CMOS) is shown
scaling and transistor sizing, which are essential to provide in Fig. 1(a). C-CMOS generates carry throughout a single
reliable operation at low voltage and arbitrary transistor static CMOS gate [7]-[9]. The complementary CMOS logic
sizes. circuit has the advantages of layout regularity and stability at
low voltage due to the complementary transistor pairs and
This paper is organized as follows. Section II explores the smaller number of interconnecting wires.
basic full adder designs in different logic styles. The
proposed XOR-XNOR full adder is analyzed in section III.
In Section IV, the circuits are simulated for power, delay and
power-delay product performances and the results are
analyzed and compared. Finally Section V concludes the
paper.

II. PREVIOUS WORK

A basic cell in digital computing systems is the 1-bit full
adder which has 1-bit inputs (A, B, and C) and two 1-bit
outputs (Sum and Carry). The addition of 2 bits (A and B)
with input carry C generates the sum bit and the output carry
bit. The relations between the inputs and outputs are
expressed as: Sum= A⊕B⊕C and Carry= AB + C(A⊕B) Fig. 1(a) C-CMOS full adder cell [3]
Sum= C’(A⊕B)+C(AB) and Carry= C(A⊕B) + A(AB
Another adder is complementary pass transistor logic
Exclusive–OR and Exclusive-NOR, denoted by ⊕ and 
(CPL) with swing restoration, which uses 32 transistors
respectively, are binary operations that perform the
Some CPL gates show an interconnection complexity at the
following Boolean Functions- A⊕B = A’B + AB’ and AB layout level with subsequently increased power and delay.
= AB + A’B’
The Pass-Transistor Logic (PTL) is a better way to
implement circuits designed for low power applications. The
In recent years several variants of different logic styles
low power pass transistor logic and its design and analysis
have been proposed to implement 1-bit adder cells [5]-[19].
procedures were reported in [6]-[8]. The advantage of PTL
These papers have also investigated different approaches
is that only one PTL network (either NMOS or PMOS) is
realizing adders using CMOS technology; each has its own
sufficient to perform the logic operation, which results in
pros and cons. Scaling the supply voltage appears to be
smaller number of transistors and smaller input loads,
most well-known means to reduce power consumption.
especially when NMOS network is used. Moreover, VDD-to-
However, lowering supply voltage increases circuit delay
GND paths, which may lead to short-circuit energy
and degrades the drivability of cells designed with certain
dissipation, are eliminated.
logic style. One of the most important obstacles in
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sides of meshes. Inputs must be applied to the gates of

bridge transistors so as to obviate the possibility of
simultaneous activation of two bridge transistors.
In general, bridge style can result in very structured
designs. Variants of logic circuits can be easily realized
because it offers high flexibility of bridge methodology. A
bridge style enables implementation of CMOS circuits in a
symmetric manner which is very useful for VLSI layout
design, placement and routing [18].
Fig. 1(b) Hybrid full adder cell [6]
III. PROPOSED WORK
B. Hybrid Style full adders
We categorize hybrid CMOS full-adder cells in, broadly,
Some adder designs use more than one logic style for their various categories depending upon their structure and logical
implementation. We call this the hybrid-CMOS logic design expression of the sum output. Most adder topologies are
style. Hybrid full adder as shown in Fig. 1(b) designed with based on two XOR gates (one to generate H and H’, and the
pass logic circuit cogenerates the intermediate XOR and other to generate the Sum output), and one MUX (to
XNOR and improves outputs. This full-adder cell can work generate the Carry). The proposed full adder cell that has
at low supply voltage. It uses 26 transistors but has the full 16T is based on low power XOR/XNOR pass transistor logic
swing logic, balanced output and good output drivability. All design and transmission gates
hybrid designs use the best available modules implemented
using different logic styles or enhance the available modules Sum = A⊕B⊕C and Carry = AB + CA⊕B ,H = A⊕B ,
in an attempt to build a low power full-adder cell. Sum = H⊕C and Carry = A·H' + C·H
Examples of adders built with this design style are hybrid
pass logic with static CMOS output drive full adder [9] and
16T, 14T adder [10]. A high performance full adder cell 14T
has been designed using low power XOR/XNOR design and
transmission gates. The designs of the 8T & 10T [15] adder
cells are based on using an optimized design for the XOR
function and pass transistor logic to implement the addition
logic function. The limitation of 14T, 10T & 8T adder cell is (a)
non full swing output and driving capability when supply
voltage is less than 1V for 14T and 1.4V for 10T in nano
technology.

(b)
Fig. 2 General structure of proposed XOR-XNOR adder cells [13]

Fig. 1(c) Bridge full adder cell [17]

C. Bridge Style CMOS full adder

In conventional CMOS design realizations are obtained

through organized branches providing paths from supply
lines to output whereas in bridge design style each two
adjacent meshes are bridged by transistor as shown in Fig
1(c). Bridge transistors make it possible to create a new path
from supply lines to an output through sharing transistors of
different paths [17]. These transistors are arranged in such a
way that validates the correctness of the circuit, and also Fig. 3 Schematic for proposed adder cell
preserves pull-up and pull-down networks mutually
exclusive. In this style control signals can be applied to the
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The general structure of a XOR based full adder is shown Each one-bit full adder has been analyzed in terms of
in Fig. 2. It consists of one exclusive OR/NOR function propagation delay, average power dissipation and their
(XOR/XNOR) shown to the left, two transmission gates product. The values of power, delay and power-delay
shown in the middle, and one XOR gate shown to the right product of C-CMOS, Hybrid, Bridge and proposed full
in the figure. As above in the figure, the complementary adders are measured. For each transition, the delay is
outputs of the XOR/XNOR gate are used to control the measured from 50% of the input voltage swing to 50% of the
transmission gate which together realizes a multiplexer output voltage swing. The maximum delay is taken as the
circuit producing the carry. The complementary outputs are cell delay. It is apparent that among the existing adders in
also used to simplify the XOR gate that produces the sum. the paper proposed adder cell has smallest delay as shown in
The XOR-XNOR gates [19] are used in a proposed full Fig. 9.
adder circuits as shown in Fig.3.The proposed circuit is
designed combination of two logic style and offers high-
speed, low-power consumption and energy efficiency.
Lowering the supply voltage appears to be well known
means of reduce power consumption. However, lowering the
supply voltage also increases the circuit delay and degrades
the drivability of cells designed with certain logic styles.

IV. SIMULATION RESULTS AND DISCUSSIONS

All the circuits are designed in Cadence VIRTUOSO
environment using CMOS process design kit. Supply
voltage of 0.65V - 1.5V was employed. Temperature of
operation for circuits is kept at 27°C. Default values of the
width and length for NMOS and PMOS in GPDK 90 nm
technology, W=120nm, L=100nm, and W is varied upto
Fig.5 Simulation input and output signal patterns for C-CMOS adder
1200nm keeping L constant with proper transistor sizing.
The simulation test bench used is shown in Fig. 4.

Fig. 4 Simulation test bench

The proposed circuit is simulated for different supply

voltages ranging from 0.65V to 1.5V. The results of the
proposed circuit in this paper are compared with a standard
CMOS full adder. The number of transistors that are used in
Fig. 6 Simulation input and output signal patterns for Hybrid adder
our proposed circuit is 16 transistors. Thus the area overhead
of the proposed circuit is lower than conventional adder
designs and also some other circuits. The delay of the
proposed circuit is compared with other circuits in Fig. 9
which shows that the delay of the proposed circuit is very
low. Although the circuits proposed in this paper have
higher power dissipation than standard CMOS circuit due to
large glitch at the output, but they have a lowest PDP in
most cases.

By optimizing the transistor sizes of full adders

considered, it is possible to reduce the delay of all adders
without significantly increasing the power consumption.
Transistor sizes can be set to achieve minimum power delay
product (PDP). All adders were designed with minimum
transistor sizes initially and then simulated. The inputs are
fed from the buffers (two cascaded inverters) to give more Fig 7 Simulation input and output signal patterns for Bridge adder
realistic input signals. The snapshot output waveforms of
hybrid and proposed adder circuit are shown in Fig. 5-8.
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Fig. 10 Power (μW) comparison of adder cells

Fig. 8 Simulation input & output waveforms of proposed adder

The bridge adder shows better performance in delay

comparison as compared to conventional CMOS adder and
hybrid adder. According to CADENCE(VIRTUOSO)
simulation in 90 nm CMOS process technology at room
temperature, under given conditions, an improvement of
43% (@VDD =0.65V to 1% (@VDD=1.5V over conventional
adder and improvement of 12% (@VDD =0.65V to 0.5%
(@VDD=1.5V over hybrid adder is achieved. In addition,
average power consumption results depict impressive
improvement of 36% (@ VDD=0.65V to 12% (@ VDD=1.5V
over conventional adder and improvement of 18% (@
VDD=0.65V to 9% (@ VDD=1.5V over hybrid adder. Hence, Fig. 11 PDP comparison of adder cells at 0.8V VDD
inspite of 32 transistors in bridge style adder, its speed is
significantly increased and thus PDP is enhanced. Simulation results of delay, power consumption and
power delay product of C-CMOS, hybrid, bridge and
Table 1 proposed adder cells are measured at 0.8V VDD. A
Simulation results for the full adder at 0.8V VDD comparison of the power of proposed adder cell with some
DESIGN # of Tr Delay (ns) Power (μW) PDP (fj) conventional adder cells that can work properly at 0.8V VDD
is given in Fig. 10. The PDP is a quantitative measure of the
C-CMOS 28 0.524 2.24 1.17 efficiency and a compromise between power dissipation and
HYBRID 26 0.413 1.94 1.09 speed. PDP is particularly important when low power
BRIDGE 32 0.323 1.82 0.59 operation is needed and its comparison shown in Fig. 11.
PROPOSED 16 0.018 4.14 0.075
Table 1 illustrates the delay, power and PDP of the adder
cells at room temperature.

V. CONCLUSION

In this paper different adder logic styles have been

implemented, simulated, analyzed and compared. Using the
adder categorization and hybrid-CMOS design style, many
full adders can be conceived. As an example, a novel full
adder designed using hybrid-CMOS design style is presented
in this paper that targets low PDP. The characteristics of the
adder circuit are compared against previous designed adders
based on the worst case delay, average power dissipation
and power delay product (PDP). Cadence simulations show
that the proposed adder can work more reliable at different
range of supply voltages. The proposed design has the best
Fig. 9 Delay (ns) comparison of adder cells
PDP in comparison with the others.
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REFERENCES [12] Hanho Lee, G. E. Sobelman, “New XOR/XNOR and full adder
circuits for low voltage, low power application,” Microelectronics
[1] J. M. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Journal vol. 29, pp. 509-517, 1998.
Circuits, A design Perspective,” 2nd Prentice Hall, Englewood Cliffs, [13] M. Vesterbacka, “A 14-transistor CMOS full adder with full voltage
NJ, 2002. swing nodes,” Proc. IEEE Workshop Signal Processing Systems, Oct
[2] J. Uyemura, “CMOS Logic Circuit Design,” Kluwer, 1999. 1999, pp. 713-722.
[3] Sung-Mo Kang, Y. Leblebici, “CMOS Digital Integrated Circuits: [14] J. Wang, S. Fang, and W. Feng, “New efficient designs for XOR and
Analysis and Design,” Tata McGraw Hill, 2003. XNOR functions on the transistor level,” J. Solid State Circuits, vol.
[4] N. Weste, D. Harris, “CMOS VLSI Design,” Pearson Wesley, 2005. 29, pp. 780-786, July 1994.
[5] R. Pedram, M. Pedram, Low Power Design Methodologies, Kluwer, [15] H.T. Bui, Y. Wang, Y. Jiang, “Design and Analysis of low-power 10-
Norwell, MA, 1996 transistor full adders using novel XOR-XNOR gates,” IEEE
[6] R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS Transactions on Circuits & Systems II, vol. 49, pp. 25-30, Jan. 2002.
versus pass transistor logic,” IEEE J. Solid-State Circuit, vol. 32, [16] S. Goel, M. E. Elgamel, M. A. Bayouni, Y. Hanafy, “Design
pp.1079-1090, July 1997. Methodologies for high- performance Noise-tolerant XOR-XNOR
[7] U.Ko,P.T.Balsara, W. Lee, “Low Power Design Techniques for High Circuits,” IEEE Trans. Circuits and Syst. I, vol. 53, no. 4, pp. 867-
Performance CMOS Adders,” IEEE Trans. on VLSI System, vol. 3, 868, April 2006.
pp. 327-333, June 1995. [17] K. Navi, O. Kavehei, M. Rouholamini, A. Sahafi, S.Mehrabi, N.
[8] D. Radhakrishnan, “Low-voltage low-power CMOS full adder,” Proc. Dadkhahi, "Low-Power and High-Performance 1-bit CMOS Full-
Inst. Elect. Engg. Circuits Devices Systems, vol. 148, no. 1, Feb. Adder Cell," Journal of Computers, vol. 3,no. 2, pp. 48-54, Feb. 2008
2001, pp. 19-24. [18] O. Kavehie, Mostafa Rahimi Azghadi, Keivan Navi and amir Pasha
[9] C.H. Chang, J. Gu, M. Zhang, A review of 0.18um full adder Mirbaha, "Design of Robust and High –Performance 1 Bit CMOS Full
performances for tree structure arithmetic circuits, IEEE Trans. Very Adder for Nanometer Design," IEEE Computer Society Annual
Large Scale Integration (VLSI) Syst. 13 (6), June 2005. Symposium VLSI (ISVLSI), Montpellier Fr., 2008, pp. 10-15.
[10] A. M. Shams, T. K. Darwish, and M. A. Bayoumi, “Performance [19] Shiv Shankar Mishra, S. Wairya, R.K. Nagaria and S. Tiwari, “New
Analysis of low-power 1-bit CMOS full adder cells,” IEEE Trans. Design Methodologies for High Speed Low Power XOR-XNOR
Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp. 20–29, Feb. Circuits,” Journal of World Academy Science, Engineering and
2002. Technology (WASET) 09, vol. 55, no. 35, pp. 200-206, July 2009.
[11] S. Goel, Ashok kumar, M. A. Bayouni, “Design of Robust, Energy-
Efficient Full Adder for Deep-Submicrometer Design Using Hybrid-
CMOS Logic Style,” IEEE Trans. Very Large Scale Integr. (VLSI)
Syst., vol. 14, no. 12, pp. 1309-1321, Dec. 2006.