Design of Low Power Hybrid 1-bit Full

Adder
Salam Surjit Singh DollyLeishangthem Md. Nasiruddin Shah Biraj Shougaijam
Deparment of Electronics & Deparment of Electronics & Deparment of Electronics & Deparment of Electronics &
Communication Engineering Communication Engineering Communication Engineering Communication Engineering
Manipur Technical University, Manipur Technical University, Manipur Technical University, Manipur Technical University,
Takyelpat, Imphal-795004 Takyelpat, Imphal-795004 Takyelpat, Imphal-795004 Takyelpat, Imphal-795004
Manipur, India Manipur, India Manipur, India Manipur, India
[email protected] [email protected] [email protected] [email protected],
[email protected]

Abstract— In this paper, we designed a 1 bit hybrid full adder style. The most important logic style in conventional domain
by using both complementary metal oxide semiconductor are Standard Static Complementary metal-oxide-semiconductor
(CMOS) logic and transmission gate. Implementation of the (CMOS), dynamic CMOS logic, Complementary pass
circuit is performed in software, called Cadence Virtuoso tools in transistor logic (CPL) and Transmission gate full adder(TGA)
90nm technology. In this designed, we used various modules such [1]. Further, to improve the overall performance of the full-
as XOR module, Carry generation module, Sum generation adder designed can used more than one logic styles which
module. Moreover, an inverter is employ in order to get XNOR may be combination of hybrid logic (CMOS-CPL, PTL-TGA
output, which is required for designing a Full adder. The existing
and CMOS-TG etc.).
design such as complementary pass transistor logic, transmission
gate adder, transmission function adder, hybrid pass logic with Static and dynamic dissipation power:
static CMOS output drive full adder, etc. were compared with
respect to the various performance parameters like power, delay, Static power is the power consumption when there is no
area and power delay product (PDP). When 1V is applied into activity in the circuit, whereas, the dynamic power is the power
the circuit at 90nm technology, the average power consumption consumed while the inputs are active. When ac input is applied
and propagation delay of the circuit were found to be incredibly to closed circuits, the capacitance will start charging. After
low ~6.889uW and 20ns, respectively. Therefore, the power delay reaching a certain point where capacitors are fully charged, it
product (PDP) is remarkably low with the value 137.78 fJ. The will start discharging. As a result, the power will increase.
area is also satisfyingly less because the proposed design used Thus, the dynamic power includes both the ac component as
only 13 transistors. Hence, the proposed designed was found to well as the static component. The static power is associated
give a remarkable improvement in terms of power, speed and with dc current while dynamic power is associated with ac
area when comparing with the existing full adder designed such current. Therefore, the total power of a circuit is defined as the
as 27T full adder and 16T full adder. combination of total static power and total dynamic power.
Keywords—Hybrid full adder, Low power, average power i.e. Total power = Total static power + Total dynamic
consumption, propagation delay and power delay product (PDP) power
I. INTRODUCTION In short, the main source of static power dissipation is the
leakage current and reversed biased PN junction. However,
With the need of advanced battery technology in portable
dynamic power dissipation involves charging and discharging
devices such as mobile phones, notepads, personal digital
of capacitances. The benefits of Standard complementary
assistants, etc., Integrated Circuit designs are mainly focused
CMOS style based adders with 28 transistors are its firmness
on high speed, low power dissipation and small area. The
against voltage scaling and transistor sizing; however the
design of 1-bit full adder, which is basic building units of all
demerits are high input capacitance and buffers requirement [1,
the circuits, has been undergoing to reduce the number of
2]. The mirror adder is almost same in power consumption and
transistors, minimize power consumption and increase the
number of transistors as compare to complementary CMOS,
speed. Adder is one of the most significant logic blocks in
but the maximum carry propagation path or delay is
microprocessors and signal processors. In general, 1-bit hybrid
comparably smaller than the standard CMOS. In addition to
full adder has three inputs and two outputs.
this, CPL with 32 transistors have good voltage swing
The designs are classified into two categories: restoration, even so, CPL is not fully accessible for low power
application due to its high switching power, high transistor
1. Static style counts, static inverters and overloading of its inputs. The
2. Dynamic style obstacle encountered in CPL i.e., the voltage degeneration was
successfully dealt by TGA. In TGA, only 20 transistors are
Static full adder are simple, reliable and low power used for implementing a 1-bit full adder, still it has high power
requirement, however it has large area as compare to dynamic consumption and slow speed. So, in order to overcome all these

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disadvantages, researchers mainly focused on hybrid II. DESIGN OF PROPOSED FULL ADDER
technology by improving overall performance of the circuit [1].
Hybrid technology consists of two or more different logic A. Methodology
styles. 1-bit hybrid full adder comprises of the CMOS logic Here, the proposed full adder circuit is represented as
design style, transmission gate logic and passes transistor logic. shown in fig 3.1. (a), which is XOR modules that generates the
Most of the hybrid adders are lack of poor driving capability. SUM and fig 3.1. (b) generates the carry out signal (Cout). In
the proposed circuit the modules are designed individually so
as the entire adder circuit is optimized in terms of power, delay
and area. Thus, these modules are discussed in details below.”

Fig. 1. (a) XOR module. (b) Carry (Cout) generation module.

 Fig. 2. Circuit diagram of the proposed full adder

B. Modified XOR module A B Cin Sum Cout

In the proposed full adder circuit, the XOR module 0 0 0 0 0
consumes most of the power in the entire adder circuit which is
the major problem. Therefore, we need to design an XOR 0 0 1 1 0
module which consumes less power. For this problem we have 0 1 0 1 0
designed the above XOR module which is shown in fig3.1. (a)
0 1 1 0 1
[3]. Here, the modified XOR circuit is designed where the
power consumption is reduced significantly by using a weak 1 0 0 1 0
inverter formed by transistor PM2 and MN1.In this circuit we 1 0 1 0 1
use 3 transistors XOR [4, 5] which consumes less power.
1 1 0 0 1
TABLE I. THE TRUTH TABLE OF XOR IS GIVEN BELOW 1 1 1 1 1

A B A XOR B
III. SIMULATION RESULTS
0 0 0
The proposed full adder circuit is shown in the above fig
0 1 1 3.2. The output signal of the sum is implemented by PM5,
1 0 1 PM6, NM4, and NM5 which is shown in fig.3.2. The output of
the XOR is applied to the weak inverter which is comprised of
1 1 0 PM2 and NM1 transistors. The output of the XNOR is applied
in between PM3 and NM3 transistors of the carry generation
C. Carry generation module
module in order to complete the Cout module and the output of
In the proposed full adder circuit, output carry signal is the XNOR is also applied to NM4 and NM5 transistors so as to
implemented by transistor NM2, NM3, PM3, PM4 as shown in complete the SUM part. Table II shows the truth table of the
fig 3.2. The input carry signal (Cin) propagates through the Cout and SUM of the proposed Full adder circuit [4, 5].
transistor gate (NM2, PM3), reducing the overall carry
propagation path significantly. The ponder use of powerful A. Analysis of 13T Full Adder using 3T XOR
transistor gates guaranteed further reduction in propagation The simulation of the proposed 1 bit hybrid full adder was
delay of the carry signal [4]. performed by using 90nm technology. The aim of this
proposed hybrid full adder is to optimise the power
consumption as well as the delay of the circuit. In addition to
TABLE II. TRUTH TABLE OF 1-BIT FULL ADDER
this, the PDP is to be optimize in this design, that is, the
consumption of the energy has been reduced. In the present

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designed, it was marked as the power consumption could be upgraded by sizing the transistors of the transmission gate
reduced by mainly arranging the sizing of the transistor in present between the paths from Cin to Cout.
inverter circuit; while the carry propagation delay could be

Fig. 3. Schematic of proposed Hybrid Full Adder

Fig. 4. Schematic Schematic of 13T Full Adder

 Fig. 5. Schematic of 3T XOR for proposed Full Adder Design

B. Waveform Output for Proposed Design

Fig. 4.2.: Output waveform for hybrid full adder

The In the given waveform output of the proposed hybrid TABLE III. TRANSISTOR SIZES OF PROPOSED FULL ADDER IN 90NM
full adder, the sum and carry of the circuit is found to be same TECHNOLOGY
as the truth table (table 3.2) of a full adder. And the operations
of the logic in the given waveform are as follows:- Transistor Name Width (W) Length(L)

1) When input a = 0, b = 0, and Cin = 0, XOR_PM0 120nm 100nm

both the sum and carry is 0 or low. XOR_PM1 10um 100nm
2) When input a = 0, b = 0, and Cin = 1, the sum is 1 or high, XOR_NM0 120nm 100nm
however, the output carry, Cout is 0.
Adder_PM0 240nm 100nm
3) When input a = 0, b = 1, and Cin = 0, the sum is 1 and
cout is 0. Adder_PM1, 120nm 100nm
4) When input a = 0, b = 1, and Cin = 1, the sum is 0 and PM2, PM3,
cout is 1. PM4
5) When input a = 1, b = 0, and Cin = 0, the sum is 1 and Adder_NM0, 120nm 100nm
cout is 0. NM1, NM2,
6) When input a = 1, b = 0, and Cin = 1, the sum is 0 and NM3, NM4
cout is 1.
7) When input a = 1, b = 1, and Cin = 0, the sum is 0 and
TABLE IV. SIMULATION RESULTS FOR FULL ADDER AT 90NM
cout is 1.
TECHNOLOGY WITH 1V SUPPLY
8) When input a = 1, b = 1, and Cin = 1, the sum is 1 and
cout is 1. Design Power (uW) Delay (ns) PDP (fJ) No. of transistors
Full adder
Thus, the waveforms of proposed hybrid full adder fulfill 28.591 11.512 329.13 16
the logic representation of truth table of a full adder. existing [1]
Full adder
25.507 6.482 165.33 27
existing [2]
 Design Power (uW) Delay (ns) PDP (fJ) No. of transistors The designed is compared with various design approaches
Full adder such as CMOS, CPL, TGA, TFA, and other hybrid styles.
6.889 20 137.78 13 However, the proposed hybrid full adder is mainly compared
[proposed]
with 16T hybrid full adder and 27T hybrid full adder in
numerical computation of power consumptions, propagation
In the given table 4.3, the transistors of the proposed hybrid delay and PDP of the circuits. The simulation results of the
full adder for 90nm technology are given. In the table 4.3.1, the proposed design have improved in overall performance in
power consumption, propagation delay and PDP of the terms of power (i.e., 16.889 um) and delay (i.e., 20ns) and
proposed hybrid full adder comparing with the existing full PDP (137.78 fJ). Moreover, the sizing of the circuit is
adder are given. The simulation of the proposed circuit is significantly small as only 13 transistors is used in the
carried out by applying supply voltage of 1V in 90nm proposed design. The proposed hybrid full adder, which have
technology. high performance and operable at low voltages (i.e., 1V) was
The proposed design has been compared with other hybrid successfully implemented.
full adder reported in [6, 7, 8] in 90 nm technology. The
proposed hybrid full adder used only 13 transistors; however,
the other hybrid full adder used more than 16 transistors [7, 8]. ACKNOWLEDGMENT
The average power consumption of the circuit is remarkably The preferred spelling of the word “acknowledgment” in
lower than the other hybrid full adders. The speed of the full America is without an “e” after the “g”. Avoid the stilted
adder is also increased notably as less number transistors are expression “one of us (R. B. G.) thanks ...”. Instead, try “R. B.
used in the circuit. As the power consumption of the circuit G. thanks...”.Put sponsor acknowledgments in the unnumbered
was reduced remarkably, the PDP of the proposed hybrid full footnote on the first page.
adder is significantly improved by comparing with the existing
hybrid full adders. The comparison of the proposed hybrid full REFERENCES
adder and the existing hybrid full adder is shown in table 4.3.1.
[1] N.H.E. Weste and D. Harris, and A. Banerjee, CMOS VLSI design: A
In table 4.3.1, the existing full adder 1 [7] is shown in Circuit and system Perspective, 3rd ed. Delhi, India: Pearson Education,
details where the power consumption is 28.591μmand the 2006.
propagation delay is noted as 11.512 ns. Therefore, the PDP is [2] J.M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated
marked as 329.131 fJ. In this full adder1 [7] 16 transistors are Circuits: A desgn perspective, 2nd ed. Delhi, India Pearson education,
used. Moreover, in the existing full adder 2 [32], the power 2003.
consumption of the circuit is said to be as 25.507μm and the [3] C. H. Chang, J. Gu, and M. Zhang, “A review of 0.18-μm Full Adder
propagation delay is noted as 6.482ns .Thus, the PDP of the performances for tree structured arithmetic circuits,” IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 6, pp. 686–
circuit is 165.331 fJ. It used 27 transistors so, the sizing of the 694, 2005.
circuit is larger. However, in the proposed hybrid full adder [4] S. Wairya, R. K. Nagaria, and S. Tiwari, “A novel CMOS Full Adder
circuit, the power consumption is significantly low as compare topology for low voltage VLSI applications,” in Proceedings of the
to the power consumption of the two existing full adders i.e., International Conference on Emerging Trends in Signal Processing &
6.889 μm. The propagation delay of the proposed hybrid full VLSI Design (SPVL '10), pp. 1142–1146, Hyderabad, India, June 2010.
adder is 20ns, which is a satisfy value as the PDP of the [5] J. M. Wang, S. C. Fang, and W. S. Feng, “New efficient designs for
proposed circuit is 137.78fJ. Here, the PDP value is very much XOR and XNOR functions on the transistor level,” IEEE Journal of
Solid-State Circuits, vol. 29, no. 7, pp. 780–786, 1994.View at:
smaller by comparing with the PDP of the existing full adders
[6] Bhattacharyya P, Kundu B, Ghosh S, Kumar V, and Dandapat A,
[7,8]. The outstanding remark of the proposed full adder is the “Performance analysis of a low-power high-speed hybrid 1-bit full adder
sizing of the circuit. As the circuit used only 13 transistors i.e., circuit”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no.
3T XOR, 2T inverter, 4T sum generator module and 4T carry 10, Oct. 2015.
generator module, thus, the overall size of the proposed full [7] Kumar Pankaj, and Sharma Rajender Kumar, “Low voltage high
adder is significantly small. performance hybrid full adder”, Engineering Science and Technology,
an International Journal, vol.19, issue 1, March.2016, pp. 559–565.
[8] NancharaiahVejendla, R. Ramana Reddy, and N. Balaji, “Low Voltage
Full Swing Fin Fet Hybrid Full Adder”, International Journal of Recent
IV. CONCLUSION Technology and Engineering(IJRTE), ISSN: 2277-3878, Volumn-8
Issue-2, July 2019.
The proposed 1 bit hybrid full adder is implemented
using standard cadence virtuoso tools with 90nm technology.