DATA COMMUNICATION AND COMPUTER

NETWORKS

LABORATORY WORK BOOK

Name ______________________
Roll No ______________________
Semester ______________________
Program ______________________
Signature ______________________
 Data Communication and Computer Networks Laboratory

CONTENTS

S.No List of Experiment Date Remarks Signature

1 a. Introductory Study of Serial Port
b. PC to PC communication using serial port (RS-232)

2 Study of fiber optic Communication A) half Duplex B) Full

Duplex
3 Study Of Wireless Communication

4 Study of MODEM communication

5 Study of Flow Controlling Serial Communication

6 a. Study of Parallel Port

b. Study of PC to PC communication using Parallel port

7 Study of Protocols used in Parallel Communication

8 a. Crossover Cable Construction

b. Straight Through Cable Construction

9 Command Line Fundamentals

10 Review of Basic Router Configurations with RIP

11 Configuring the OSPF Routing Process

12 Configuring EIGRP Routes

13 a. Basic Switch Configuration

b. Managing the MAC Address Table

14 Configuring Static MAC Address

15 Configuring Static VLANS

 Experiment 1

Introductory Study of Serial Port

PC to PC communication using serial port (RS-232)

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Objective: Study of Serial Port

The serial port is an I/O (Input/Output) device. An I/O device is just a way to get data into
and out of a computer. There are many types of I/O devices such as serial ports, parallel
ports, disk drive controllers, Ethernet boards, universal serial buses, etc. Most PC's have one
or two serial ports. Each has a 9-pin connector (sometimes 25-pin) on the rear side of the
computer. Computer programs can send data (bytes) to the transmit pin (output) and receive
bytes from the receive pin (input). The other pins are for control purposes and ground.

The serial port is much more than just a connector. It converts the data from parallel to serial
and changes the electrical representation of the data. Inside the computer, data bits flow in
parallel (using many wires at the same time). Serial flow is a stream of bits over a single wire
(such as on the transmit or receive pin of the serial connector). For the serial port to create
such a flow, it must convert data from parallel (inside the computer) to serial on the transmit
pin (and conversely).

DCE and DTE Devices:

Two terms you should be familiar with are DTE and DCE. DTE stands for Data Terminal
Equipment, and DCE stands for Data Communications Equipment. These terms are used to
indicate the pin-out for the connectors on a device and the direction of the signals on the pins.
Your computer is a DTE device, while most other devices are usually DCE devices.

Pinout of 9-pin and 25-pin serial connectors:

The pin numbers are often engraved in the plastic of the connector. The numbering of the
pins on a female connector is read from right to left, starting with 1 in the upper right corner.

Only 3 of the 9 pins have a fixed assignment: transmit, receive and signal ground. This is
fixed by the hardware and you can't change it. But the other signal lines are controlled by
software and may do (and mean) almost anything at all. However they can only be in one of
two states: asserted (+12volts) or negated (-12volts). Asserted is "on" and negated is "off".
The hardware only sends and receives the signals, but what action (if any) they perform is up
to the software and the configuration/design of devices that you connect to the serial port.
However, most pins have certain functions which they normally perform but this may vary
with the operating system and the device driver configuration.

Cabling Between Serial Ports:

A cable from a serial port always connects to another serial port. An external modem or other
device that connects to the serial port has a serial port built into it. For modems, the cable is
always straight through pin 2 goes to pin 2, etc. Thus for connecting DTE-to-DCE you use
straight-through cable. For connecting DTE-to-DTE you must use a null-modem cable (also
called a crossover cable). There are many ways to wire such cable.

There are good reasons why it works this way. One reason is that the signals are
unidirectional. If pin 2 sends a signal out of it (but is unable to receive any signal) then
obviously you can't connect it to pin 2 of the same type of device. If you did, they would both
send out signals on the same wire to each other but neither would be able to receive any
signal. There are two ways to deal with this situation. One way is to have two different types
of equipment where pin 2 of the first type sends the signal to pin 2 of the second type (which
receives the signal). That's the way its done when you connect a PC (DTE) to a modem
(DCE). There is a second way to do this without having two different types of equipment:
Connect sending pin 2 to a receiving pin 3 on same type of equipment. That's the way it is
done when you connect 2 PCs together or a PC to a terminal (DTE-to-DTE). The cable used
for this is called a null-modem cable since it connects two PCs without use of a modem. A
null-modem cable may also be called a cross-over cable since the wires between pins 2 and 3
cross over each other.

Baud vs Bits per Second:

The baud unit is named after Jean Maurice Emile Baudot, who was an officer in the French
Telegraph Service. He is credited with devising the first uniform-length 5-bit code for
characters of the alphabet in the late 19th century. What baud really refers to is modulation
rate or the number of times per second that a line changes state. This is not always the same
as bits per second (BPS). If you connect two serial devices together using direct cables then
baud and BPS are in fact the same. Thus, if you are running at 19200 BPS, then the line is
also changing states 19200 times per second. But when considering modems, this isn't the
case.

Because modems transfer signals over a telephone line, the baud rate is actually limited to a
maximum of 2400 baud. This is a physical restriction of the lines provided by the phone
company. The increased data throughput achieved with 9600 or higher baud modems is
accomplished by using sophisticated phase modulation, and Data Compression Techniques.

Bi-Directional Communications:

The serial port on your PC is a full-duplex device meaning that it can send and receive data at the
same time. In order to do this, it uses separate lines for transmitting and receiving data. Some
types of serial devices support only one-way communications and therefore use only two wires in
the cable - the transmit line and the signal ground.
 Objective: To Study PC to PC Communication Using Serial Port (RS-232)

Accessories required:

1. ST5001 Trainer Kit

2. ST5001 Software
3. 3 Patch Cords (2mm)
4. 2 Serial Port Cables
5. Mains Power Cord

Procedure:

Figure 6

Connect patch cords as shown in Figure 6.

1. Connect mains power cord to the trainer and switch on the trainer.
2. Connect the serial port cables between one PC to Port1 & another PC to Port2.
3. To open the window as shown in Figure 7, follow the steps.
Run ST5001 software on both PCs >> Click “Serial Port Interface” image/press “Ctrl +
S”/click “Options” on menu bar.
4. The software will open with default settings. Select the desired port settings.
5. After the port settings are done, open the port by clicking “Open Port” button.
6. To send data to other node enter the text in the window titled as “Enter Data to Transmit”.
Click on “Send” button to transmit.
7. Transmitted data will be displayed in the “Received Data” window and the ASCII codes
of each byte received is displayed in “Received Data in ASCII” window.
8. A small window at the sender side is given for transmission of ASCII code. Enter an
ASCII code in the window and then click “Send” button.
9. “Clear” buttons have been given to clear all windows.
10. Before changing the port settings close the port by clicking “Close Port” button and after
changing the parameters click “Open Port” button to reopen the port.
11. For hardware safety of the CPU, it is very important to connect serial port cables only
after making all the connections on board and after switching ON the trainer.
12. To see transmitted data connect CRO probe between test points TP8/TP27 and ground,
similarly to see received data connect it between TP7/TP26 and ground.

The software window screen shot is as shown in Figure 7.

Figure 7
 Experiment 2

Study of Fiber Optic Communication

A) Simplex
B) Full Duplex

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Objective: To Study Fiber Optic Communication

Accessories required:

1. ST5001 Trainer Kit

2. ST5001 Software
3. 2 Patch Cords (2mm)
4. FOC cable(0.5m/1m)
5. 2 Serial Port Cables
6. Mains Power Cord

Theory:

The Fiber Optic Data Communications Link, End-to-End

We consider the simple fiber optic data link given below. This is the basic building block for
a fiber optic based network. A model of this simple link is shown in Figure 8

Figure 8

The illustration indicates the Source-User pair, Transmitter and Receiver. It also clearly
shows the fiber optic cable constituting the Transmission Medium as well as the connectors
that provide the interface of the Transmitter to the Transmission Medium and the
Transmission Medium to the Receiver.

All of these are components of the simple fiber optic data link.

Transmitter:

The Transmitter component of Figure 9 serves two functions. First, it must be a source of the
light coupled into the fiber optic cable. Secondly, it must modulate this light so as to
represent the binary data that it is receiving from the Source.

The Source provides the data to the Transmitter as some digital electrical signal. The
Transmitter can then be thought of as Electro-Optical (EO) transducer.

Within the context of a fiber optic data link the modulating signal , the Information, assumes
only the values of '0' and '1.' The demodulation function in the Receiver will just be looking
for the presence or absence of energy during a bit time interval.
 Figure 9

Receiver:

The Receiver component of Figure 10 serves two functions. First, it must sense or detect the
light coupled out of the fiber optic cable then convert the light into an electrical signal.
Secondly, it must demodulate this light to determine the identity of the binary data that it
represents. In total, it must detect light and then measure the relevant information bearing
light wave parameters in the premises fiber optic data link context intensity in order to
retrieve the Source's binary data.

The very heart of the Receiver is the means for sensing the light output of the fiber optic
cable. Light is detected and then converted to an electrical signal. The demodulation decision
process is carried out on the resulting electrical signal. The light detection is carried out by a
photodiode. This senses light and converts it into an electrical current.

Figure 10
SMA Connector:

The Connector is a mechanical device mounted on the end of a fiber optic cable, light source,
Receiver or housing. It allows it to be mated to a similar device. The Transmitter provides the
information bearing light to the fiber optic cable through a connector. The Receiver gets the
information bearing light from the fiber optic cable through a connector. The connector must
direct light and collect light. It must also be easily attached and detached from equipment.
This is a key point. The connector is disconnectable.

SMA - The connector features a threaded cap and housing.

The photograph of the SMA connector used is provided in Figure 11.

Figure 11
A) Half Duplex:

Procedure:

Figure 12
 Connect patch cords as shown in Figure 12

1. Connect mains power cord to the trainer and switch on the trainer.
2. Connect the serial port cables between one PC to Port1 & another PC to Port 2.
3. To open the window as shown in Figure 12, follow the steps.
Run ST5001 software on both PCs >> Click “Fiber Optics Communication”
image/press “Ctrl + F”/click “Options” on menu bar.
4. The software will open with default settings. Set the same parameters on both the
PCs. Baud rate can be varied from 2400bps to 115200bps. Select the desired baud
rate. Select the desired port settings.
5. After the port settings are done, open the port by clicking “Open Port” button.
6. To send data to other node enter the text in the window titled as “Enter Data to
Transmit”. Click on “Send” button to transmit.
7. Transmitted data will be displayed in the “Received Data” window and the ASCII
codes of each byte received is displayed in “Received Data in ASCII” window.
8. A small window at sender side is given for transmission of ASCII code. Enter an
ASCII code in the window and then click “Send” button.
9. “Clear” buttons are given to clear all windows.
10. Before changing the port settings close the port by clicking “Close Port” button and
after changing the parameters click “Open Port” button to reopen the port.

For hardware safety of the CPU, it is very important to connect serial port cables only after
making all the connections on board and after switching ON the trainer.

To see transmitted data connect CRO probe between test points TP14 and ground, similarly
to see received data connect it between TP15 and ground.
B) Full Duplex:

Procedure:

Figure 13

Connect patch cords as shown in Figure 13.

1. Connect mains power cord to the trainer and switch on the trainer.
2. Connect the serial port cables between one PC to Port1 & another PC to Port2.
3. To open the window as shown in Figure 14, follow the steps.
Run ST5001 software on both PCs >> Click “Fiber Optics Communication”
image/press “Ctrl + S”/click “Options” on menu bar.
4. The software will open with default settings. Set the same parameters on both the
PCs. Baud rate can be varied from 2400bps to 115200bps. Select the desired baud
rate. Select the desired port settings.
5. After the port settings are done, open the port by clicking “Open Port” button.
6. To send data to other node enter the text in the window titled as “Enter Data to
Transmit”. Click on “Send” button to transmit.
7. Transmitted data will be displayed in the “Received Data” window and the ASCII
codes of each byte received is displayed in “Received Data in ASCII” window.
8. A small window at sender side is given for transmission of ASCII code. Enter an
ASCII code in the window and then click “Send” button.
9. “Clear” buttons are given to clear all windows.
Before changing the port settings close the port by clicking “Close Port” button and after
changing the parameters click “Open Port” button to reopen the port.
For hardware safety of the CPU, it is very important to connect serial port cables only after
making all the connections on board and after switching ON the trainer.

To see transmitted data connect CRO probe between test points TP14 and ground, similarly to see
received data connect it between TP15 and ground.

The software window screen shot is as shown in Figure 14.

Figure 14
 Experiment 3

Study of Wireless Communication

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Objective: Study of Wireless Communication

Accessories required:

1. ST5001 Trainer Kit

2. ST5001 Software
3. 2 Patch Cords (2mm)
4. 2 Serial Port Cables
5. Mains Power Cord

Procedure:

Figure 15

Connect patch cords as shown in Figure 15.

1. Connect mains power cord to the trainer and switch on the trainer.
2. Connect the serial port cables between one PC to Port1 & another PC to Port2.
3. To open the window as shown in Figure 16, follow the steps.
Run ST5001 software on both PCs >> Click “Wireless Communication” image/press
“Ctrl + W”/click “Options” on menu bar.
4. The software will open with default settings. Set the same parameters on both the PCs.
Baud rate can be varied from 300bps to 2400bps. Select the desired baud rate. Select the
desired port settings.
5. After the port settings are done, open the port by clicking “Open Port” button.
6. To send data to other node enter the text in the window titled as “Enter Data to Transmit”.
Click on “Send” button to transmit.
7. Transmitted data will be displayed in the “Received Data” window and the ASCII codes
of each byte received is displayed in “Received Data in ASCII” window.
8. A small window at sender side is given for transmission of ASCII code. Enter an ASCII
code in the window and then click “Send” button.
9. “Clear” buttons are given to clear all windows.
10. Before changing the port settings close the port by clicking “Close Port” button and after
changing the parameters click “Open Port” button to reopen the port.

For the hardware safety of the CPU, it is very important to connect serial port cables
only after making all the connections on board and after switching on the trainer.

11. To see transmitted data connect CRO probe between test points TP18 and ground,
similarly to see received data connect it between TP19 and ground.

Figure 16
 Experiment 4

Study of MODEM Communication

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Objective: Study of MODEM Communication

Accessories required:

1. ST5001 Trainer Kit

2. ST5001 Software
3. 2 Patch Cords (2mm)
4. 2 Serial Port Cables
5. RJ11 Jack to Jack Cable
6. Mains Power Cord

Theory:

Modem

Short for Modulator-Demodulator. A modem is a device or program that enables a computer

to transmit data over, for example, telephone or cable lines. Computer information is stored
digitally, whereas information transmitted over telephone lines is transmitted in the form of
analog waves. A modem converts between these two forms.

Bits per Second (bps):

How fast can the modem transmit and receive data.

At slow rates, modems are measured in terms of baud rates. The slowest rate is 300 baud. At
higher speeds, modems are measured in terms of bits per second (bps). The fastest modems
run at 57,600 bps, although they can achieve even higher data transfer rates by compressing
the data. Obviously, the faster the transmission rate, the faster you can send and receive data.
Note, however, that you cannot receive data any faster than it is being sent. If, for example,
the device sending data to your computer is sending it at 2,400 bps, you must receive it at
2,400 bps. To get the most out of a modem, you should have a communications software
package, a program that simplifies the task of transferring data.

FSK:

Short for frequency-shift keying, a modulation technique used by modems in which two
different frequencies in the carrier signal are used to represent the binary states of 0 and 1.
Using FSK, a modem converts the binary data from a computer into a binary form in which
logic 1 is represented by an analog waveform at a specific frequency(referred to as mark
frequency) and logic 0 is represented by a wave at a different specific frequency(referred to
as space frequency).Waveforms in Figure 17 illustrate the FSK output.
 Figure 17

Procedure:

Figure 18

Connect patch cords as shown in Figure 18.

1. Connect mains power cord to the trainer and switch ON the trainer.
2. Connect the serial port cables between one PC to Port1 & another PC to Port2.
3. To open the window as shown in Figure 19, follow the steps. Run ST5001 software
on both PCs.
4. Click “MODEM Communication” image/press “Ctrl + M”/click “Options” on menu
bar.
5. The software will open with default settings. Set the same parameters on both the
PCs. Baud rate can be varied from 2400bps to 57600bps. Select the desired baud rate.
Select the desired port settings.
6. After the port settings are done, open the port by clicking “Open Port” button.
7. To send data to other node enter the text in the window titled as “Enter Data to
Transmit”. Click on “Send” button to transmit.
8. Transmitted data will be displayed in the “Received Data” window and the ASCII
codes of each byte received is displayed in “Received Data in ASCII” window.
9. A small window at sender side is given for transmission of ASCII code. Enter an
ASCII code in the window and then click “Send” button.
10. “Clear” buttons are given to clear all windows.
11. Before changing the port settings close the port by clicking “Close Port” button and
after changing the parameters click “Open Port” button to reopen the port.

For hardware safety of the CPU, it is very important to connect serial port cables
only after making all the connections on board and after switching on the trainer.

12. To see transmitted data connect CRO probe between test points TP18 and ground,
similarly to see received data connect it between TP19 and ground.

Figure 19
 Experiment 5

Study of Flow Control in Serial Communication

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Objective: Study of Flow Control in Serial Communication

Accessories required:

1. ST5001 Trainer Kit

2. ST5001 Software
3. 2 Patch Cords (2mm)
4. 2 Serial Port Cables
5. Mains Power Cord

Theory:

Because a sender and receiver can't always process data at the same rate, some method of
negotiating when to start and stop transmission is required.

The Serial Driver supports two methods of controlling serial data flow. One method relies on
the serial port hardware, while the other is implemented in software.

Hardware data flow control:

Hardware flow control uses two of the serial port signal lines to control data transmission.
When the Serial Driver is ready to accept data from an external device, it asserts the Data
Terminal Ready (DTR) signal on pin 1 of the serial port, which the external device receives
through its Clear to Send (CTS) input.

RTS/CTS and DTR/DSR Flow Control:

This is "hardware" flow control. Only RTS/CTS flow control will be discussed since
DTR/DSR flow control works the same way. To get RTS/CTS flow control one needs to
either select hardware flow control in an application program.

When a DTE (such as a PC) wants to stop the flow into it, it negates RTS. Negated "Request
To Send" (-12 volts) means "request NOT to send to me" (stop sending). When the PC is
ready for more bytes it asserts RTS (+12 volts) and the flow of bytes to it resumes.

Flow control signals are always sent in a direction opposite to the flow of bytes that is being
controlled. DCE equipment (modems) works the same way but sends the stop signal out the
CTS pin. Thus its RTS/CTS flow control using 2 lines.

On what pins is this stop signal received? That depends on whether we have a DCEDTE
connection or a DTE-DTE connection.

For DCE-DTE its a straight-through connection so obviously the signal is received on a pin
with the same name as the pin its sent out from. Its RTS-->RTS (PC to modem) and CTS<--
CTS (modem to PC).

For DTE-to-DTE the connection is also easy to figure out. The RTS pin always sends and the
CTS pin always receives. Assume that we connect two PCs (PC1 and PC2) together via their
serial ports. Then its RTS (PC1) -->CTS (PC2) and CTS (PC1) <-- RTS (PC2). In other
words RTS and CTS cross over. Such a cable (with other signals crossed over as well) is
called a "null modem" cable.

The DTR and DSR Pins:

Just like RTS and CTS, these pins are paired. For DTE-to-DTE connections they are likely to
cross over. There are two ways to use these pins. One way is to use them as a substitute for
RTS/CTS flow control. The DTR pin is just like the RTS pin while the DSR pin behaves like
the CTS pin. DTR flow control is the same as DTR/DSR flow control but its only one-way
and only uses the DTR pin at the device. Many text terminals and some printers use
DTR/DSR (or just DTR) flow control.

Software data flow control:

Flow control can also be handled in software by using an agreed-upon set of characters as
start and stop signals. The Serial Driver supports XON/XOFF flow control, which typically
assigns the ASCII DC1 character (also known as control-Q) as the start signal and the DC3
character (control-S) as the stop signal, although you can choose different characters

Handshaking:

a) comXon-Xoff Handshaking:

In this type of handshaking two pins are important DTR & DSR; these are used by both
nodes for handshaking while communicating with each other. Basically this is a software type
handshaking. These pins are used to indicate X on i.e. transmission ON and Xoff i.e.
transmission OFF. When transmission is on DTR pin is set as enabled, as start signal.

b) comRTS Handshaking:

RTS & CTS pins of Serial port are used as handshaking signal. This is hardware type
handshaking.

c) comRTSXon-Xoff :

Both type of handshaking i.e. hardware & software handshaking used.

Procedure:

Figure 20

1. Connect patch cords as shown in Figure 20.

2. Connect mains power cord to the trainer and switch on the trainer.
3. Connect the serial port cables between one PC to Port1 & another PC to Port2.
4. To open the window as shown in Figure 21 follow the steps.
Run ST5001 software on both PCs and then >> Click on “Protocols by Interface”
image/press “Ctrl + T”/click “Options” on menu bar. Click “Flow Control”.
5. The software will open with default settings. Select a Handshaking.
6. Select the option for handshaking.
7. Enter data in the window of sender side for transmission.
8. Select either “Write all bytes” or enter a numeric value in the small window given in
“Write Options” the transmitter will write only these many.
9. Similarly “Time Out” options are given.
10. After selections are done click “Send” button.
11. “Send Break” & “Clear Break” are given to send the break of transmission & clear the
break of transmission.
12. “Transmit Queue” & “Receive Queue” windows show the bytes in transmit queue &
receive queue in “Break” condition.
13. Similar options on the receiver side are given i.e. “Receive all bytes”, “Never time
out”, and “Receive___ bytes”, “Time out after ___ms”. Select desired options and
then click “Receive” button to receive data.
Figure 21
 Experiment 6

Study of Parallel Port

Study of PC to PC Communication using Parallel Port

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Objective: Study of Parallel Port

Parallel port is a simple and inexpensive tool for building computer controlled devices and
projects. The simplicity and ease of programming makes parallel port popular in electronics
hobbyist world. The parallel port is often used in Computer controlled robots, Atmel/PIC
programmers, home automation, etc.

Everybody knows what is a parallel port, where it can be found, and for what is it being used. The
primary use of a parallel port is to connect printers to computer and is specifically designed for
this purpose. Thus it is often called as printer Port or Centronics port (this name comes from a
popular printer manufacturing company 'Centronics' who devised some standards for parallel
port). You can see the parallel port connector in the rear panel of your PC. It is a 25 pin female
(DB25) connector (to which printer is connected). On almost all the PCs only one parallel port is
present, but you can add more by buying and inserting ISA/PCI parallel port cards.

Hardware:

The pin outs of DB25 connector is shown in the below diagram in Figure 24.

Figure 24

The lines in DB25 connector are divided in to three groups, they are:

1. Data lines (data bus)

2. Control lines
3. Status lines

As the name refers, data is transferred over data lines, Control lines are used to control the
peripheral and ofcourse, the peripheral returns status signals back to the computer through
Status lines. These lines are connected to Data, Control and Status registers internally. The
details of parallel port signal lines are given below.
Parallel port registers:

As you know, the Data, Control and status lines are connected to their corresponding registers
inside the computer. So by manipulating these registers in program , one can easily read or
write to a parallel port with programming languages like 'C' and BASIC.

The registers found in standard a parallel port are,

1. Data register
2. Status register
3. Control register
As their names specify, Data register is connected to Data lines, Control register is connected
to Control lines and Status register is connected to Status lines. (Here the word connection
does not mean that there is some physical connection between data/control/status lines. The
registers are virtually connected to the corresponding lines.). So whatever you write to these
registers, will appear in corresponding lines as voltages, ofcourse, you can measure it with a
multimeter. And whatever you give to Parallel port as voltages can be read from these
registers (with some restrictions). For example, if we write '1' to Data register, the line Data 0
will be driven to + 5V. Just like this, we can programmatically turn on and off any of the data
lines and Control lines.

Where are these registers are?

In an IBM PC, these registers are IO mapped and will have a unique address. We have to find
these addresses to work with parallel port. For a typical PC, the base address of LPT1 is
0x378 and of LPT2 is 0x278. The data register resides at this base address, status register at
base address + 1 and the control register is at base address + 2. So once we have the base
address, we can calculate the address of each registers in this manner. The table below shows
the register addresses of LPT1 and LPT2

Parallel port modes:

The IEEE 1284 Standard which has been published in 1994 defines five modes of data
transfer for parallel port. Each mode provides a method of transferring data in either the
forward direction (PC to peripheral), reverse direction (peripheral to PC) or bi-directional
data transfer (half duplex). The defined modes are:

1) Compatibility Mode (Forward direction only):

This mode defines the protocol used by most PCs to transfer data to a printer. It is commonly
called the "Centronics" mode and is the method utilized with the standard parallel port. In this
mode, data is placed on the port's data lines, the printer status is checked for no errors and
that it is not busy, and then a data Strobe is generated by the software to clock the data to the
printer. Figure 25 describes this transfer.
 Figure 25

Compatibility Mode phase transitions:

1. Write the data to the data register

2. Program reads the status register to check that the printer is not BUSY
3. If not BUSY, then Write to the Control Register to assert the STROBE line
4. Write to the Control register to de-assert the STROBE line

As can be seen, in order to output one byte of data it requires four I/O instructions and at least
as many additional instructions. The net effect of this is a limitation on the bandwidth
capabilities of the port on the order of 150K bytes per second. This bandwidth is sufficient
for communicating with dot matrix and many older laser printers, but a limitation when
communicating with pocket LAN adapters, removable disk drives, and the newest generation
of laser printers, to name a few. ofcourse, this mode is for the forward channel only and must
be combined with a reverse channel mode in order to have a complete bi-directional channel.
This mode was included as a way to provide backward compatibility with the huge base of
installed printers and peripherals. The other modes are used to provide the reverse channel
and high performance communication links. Many of the integrated 1284 I/O controllers have
implemented a mode that uses a FIFO buffer to transfer data with the Compatibility mode
protocol. This mode is referred to as "Fast Centronics" or "Parallel Port FIFO Mode". When
this mode is enabled, data written to the FIFO port will be transferred to the printer using
hardware generated strobes for the handshaking. Since there is very little latency between
transfers, and the software does not have to do any of the strobing or handshake checking,
data rates over 500K bytes per second are achievable with some systems. This mode,
however, is not an IEEE 1284 defined mode and is not described in the standard.

2) Nibble Mode (Reverse direction only):

The Nibble mode is the most common way to get reverse channel data from a printer or
peripheral. This mode is usually combined with the Compatibility mode or a proprietary
forward channel mode to create a complete bi-directional channel.

All of the standard parallel ports provide 5 lines from the peripheral to the PC to be used for
external status indications. Using these lines, a peripheral can send a byte of data (8-bits) by
sending 2 nibbles (4-bits) of information to the PC in two data transfer cycles. Unfortunately,
since the n ACK line is generally used to provide a peripheral interrupt, the bits used to
transfer a nibble are not conveniently packed into the byte defined by the Status register. For
this reason, the software must read the status byte and then manipulate the bits in order to get
a correct byte.

Table 1 identifies the signal names for the Nibble mode. Figure 26 shows the basic data
handshake for a nibble mode transfer from the peripheral to the host.

Figure 26
1. Host signals ability to take data by asserting HostBusy low
2. Peripheral responds by placing first nibble on status lines
3. Peripheral signals valid nibble by asserting PtrClk low
4. Host sets Host Busy high to indicate that it has received the nibble and is not yet ready for
another nibble.
5. Peripheral sets PtrClk high to acknowledge host
6. States 1 through 5 repeat for the second nibble

Nibble mode, like the Compatible mode, requires that the software drive the protocol by
setting and reading the lines on the parallel port. Nibble mode is the most software intensive
mode for reverse channel data communication. For this reason, there is a severe limitation of
approximately 50K bytes per second for this type of data transfer. The major advantage of
this combination of modes is the ability to operate on all PCs that have a parallel port. The
performance limitations incurred by the Nibble mode operation does not have much visible
effect on peripherals that have low reverse channel requirements, such as printers, but can be
nearly intolerable when used for LAN adapters, disk drives or CD ROM drives.

3) Byte Mode (Reverse direction only):

With later implementations of the parallel port interface, some manufacturers, led by IBM on
the PS/2 parallel port, added the capability to disable the drivers used for driving the data
lines, and allowed the data port to become an input read data port. This enables a peripheral
to send an entire byte of data to the PC in one data transfer cycle by using the 8 data lines,
rather than the two cycles required using the Nibble mode.

This ability enables a Byte mode for reverse channel data transfer that can be used to provide
data rates into the PC approaching that of the Compatibility mode, from the PC. This type of
port is sometimes referred to as a "enhanced bi-directional" port, and has caused some
confusion when mistaken for an Enhanced Parallel Port (EPP). The following Table 2
identifies the Byte mode signal names, and Figure 27 shows the handshake for a Byte mode
data transfer.
 Figure 27

Byte Mode signal transitions:

1. Host signals ability to take data by asserting Host Busy low

2. Peripheral responds by placing first byte on data lines
3. Peripheral signals valid byte by asserting PtrClk low
4. Host sets Host Busy high to indicate that it has received and is not yet ready for
another byte
5. Peripheral sets PtrClk high to acknowledge host. Host pulses HostClk as an
acknowledgement to the peripheral
6. States 1 through 5 repeat for additional bytes

4) EPP (Bi-directional):

The Enhanced Parallel Port protocol was originally developed by Intel, Xircom and Zenith
Data Systems, as a means to provide a high performance parallel port link that would still be
compatible with the standard parallel port. This protocol capability was implemented by Intel
in the 386SL chipset (82360 I/O chip). This was prior to the establishment of the IEEE 1284
committee and the associated standards work.

The EPP protocol offered many advantages to parallel port peripheral manufactures and was
quickly adopted by many as an optional data transfer method. A loose association of around
80 interested manufacturers was formed to develop and promote the EPP protocol. This
association became the EPP Committee and was instrumental in helping to get this protocol
adopted as one of the IEEE 1284 advanced modes.

Since EPP capable parallel ports were available prior to the release of the 1284 standard,
there is a small deviation between the pre-1284 EPP ports and 1284 EPP protocol. This will
be made clearer later.

The EPP protocol provides four types of data transfer cycles:

1. Data Write Cycle

2. Data Read Cycle
3. Address Write Cycle
4. Address Read Cycle

Data cycles are intended to be used to transfer data between the host and the peripheral.
Address cycles may be used to pass address, channel, or command and control information.
These cycles can be viewed as just two different data cycles. The developer may use and
parse the address/data information in any method that makes sense for a particular design.
Table 3 describes the EPP signals and their associated SPP signals.
Figure 28 is an example of a Data_Write cycle. The CPU signal nIOW is shown just to
emphasize that this entire handshake occurs within a single I/O cycle.

Figure 28

Data Write cycle phase transitions:

1. Program executes an I/O write cycle to port 4 (EPP Data Port)

2. The nWrite line is asserted and the data is output to the parallel port
3. The data strobe is asserted, since nWAIT is asserted low
4. The port waits for the acknowledge from the peripheral (nWAIT deasserted)
5. The data strobe is deasserted and the EPP cycle ends
6. The ISA I/O cycle ends
7. nWAIT is asserted low to indicate that the next cycle may begin
One of the most important features to note here is that the entire data transfer occurs within
one ISA I/O cycle. The effect is that by using the EPP protocol for data transfer, a system can
achieve transfer rates from 500K to 2M bytes per second. In this fashion, parallel port
peripherals can operate at close to the same performance levels as an equivalent ISA plug-in
card. The ability to get this level of performance from a parallel port attached device is one of
the major features of the EPP protocol. With interlocked handshakes, the data transfer will
happen at the speed of the slowest of the interfaces, the host adapter or the peripheral device.
This "speed adaptive" property is transparent to both the host and peripheral. All 1284
transfer modes are implemented with interlocking handshakes.

Interlocking refers to the criteria that each control signal transition is acknowledged by the
opposite side of the interface. In the above diagram, nDataStrobe can be asserted because
nWAIT is low, nWAIT deasserts in response to nDataStrobe be asserted, nDataStrobe
deasserts in response to nWAIT being deasserted, and finally nWAIT asserts in response to
nDataStrobe being deasserted. In this way the peripheral can control the setup time required
for its operation. This is done in the following manner: the setup time is the time from the
assertion of nDataStrobe to the deassertion of nWAIT, the peripherals controls this time.
Interlocking also has the advantage of making the transfer cycle independent of the cable
length. The Nibble, Byte, EPP and ECP modes all have interlocked protocols.

As previously mentioned, the pre-1284 EPP devices deviated from the 1284 protocol. At the
start of the cycle, the nDataStrobe or nAddrStrobe would assert regardless of the state of the
nWAIT signal. This means that the peripheral could not hold off the start of a cycle by having
nWAIT deasserted. This is sometimes referred to as EPP 1.7, in reference to a Xircom
proposal version 1.7. This is the version that Intel implemented in the original 82360 I/O
controller. A 1284 EPP compatible peripheral will work properly with an EPP 1.7 version
host adapter, but an EPP 1.7 peripheral may not operate properly with a 1284 compliant host.
Figure 29 is an example of an Address Read cycle.

Figure 29

EPP Register Interface:

The simplest software view of EPP is that of an extension to the register definitions for the
standard parallel port. As shown earlier, the SPP consists of three registers, offset from the
port's base address: Data port, Status port, and Control port. The most common EPP
implementations expand this to use ports not defined by the SPP. See Table 4.
By generating a single I/O write instruction to "base_address + 4", the EPP controller will
generate the necessary handshake signals and strobes to transfer the data using an EPP
Data_Write cycle. I/O instructions to the base addresses, ports 0 through 2, will cause
behavior exactly as that as to a standard parallel port. This guarantees compatibility with
standard parallel port peripherals and printers. Address cycles are generated when read or
write I/O operations are generated to "base_address + 3".

Ports 5 through 7 are used differently by various hardware implementations. These may be
used to implement 16 or 32-bit software interfaces, or used for configuration registers, or not
used at all. For example, the Warp Nine Engineering's' F/PortPlus card has only an 8-bit data
interface, but can be accessed using 32-bit I/O, for EPP data operations. The ISA controller
will intercept the 32- bit I/O and actually generate 4 fast 8- bit I/O cycles. The first cycle will
be to the addressed I/O port using byte 0 (bits 0-7), the second cycle will be to port +1 using
byte 1, then port +2 using byte 2 and finally port+3 using byte 3. These additional cycles are
generated by hardware and are transparent to the software. The total time for these four
cycles will be less than 4 independent 8 bit cycles. For example, the F/PortPlus card (from
Warp Nine Engineering) maps 4 I/O ports (offset 4 to 7) to the internal EPP Data register.
This enables the software to use 32-bit I/O operations for EPP data transfer. Address cycles
are still limited to 8-bit I/O.
The ability to transfer data to or from the PC by the use of a single instruction is what enables
EPP mode parallel ports to transfer data at ISA bus speeds. Rather than having the software
implement an I/O intensive software loop, a block of data can be transferred with a single
REP_IO instruction. Depending upon the host adapter port implementation and the capability
of the peripheral, an EPP port can transfer data from 500K bytes to nearly 2M bytes per
second. This data transfer rate is more than enough to enable network adapters, CD ROM,
tape backup and other peripherals to operate at nearly ISA bus performance levels.

The EPP protocol and current implementations provide a high degree of coupling between
the peripheral driver and the peripheral. What this means is the software driver is always able
to determine and control the state of communication to the peripheral at any given time.
Intermixing of read and write operations as well as block transfers are readily done. This type
of coupling is ideal for many register-oriented or real-time controlled peripherals such as
network adapters, data acquisition, portable hard drives, and other devices.

5) ECP (Bi-directional):

The Extended Capability Port, or ECP, protocol was proposed by Hewlett Packard and
Microsoft as an advanced mode for communication with printer and scanner type peripherals.
Like the EPP protocol, ECP provides for a high performance bidirectional communication
path between the host adapter and the peripheral.

The ECP protocol provides the following cycle types in both the forward and reverse
directions:

Data cycles
Command cycles

The command cycles are divided into 2 types, Run-Length Count and Channel address.

Unlike EPP, when the ECP protocol was proposed, a standard register implementation was
also proposed. This can be found in the Microsoft document "The IEEE 1284 Extended
Capabilities Port Protocol and ISA Interface Standard" available from Microsoft Corp. This
document defines features that are implementation specific which the IEEE 1284 standard
could not address. These features include Run_Length_Encoding (RLE) data compression for
the host adapters, FIFOs for both the forward and reverse channels, and DMA as well as
programmed I/O for the host register interface.

The RLE feature enables real time data compression that can achieve compression ratios up
to 64:1. This is particularly useful for printers and scanners that are transferring large raster
images that have large strings of identical data. In order for the RLE mode to be enabled,
both the host and the peripheral must support it.

Channel addressing is, conceptually, a little different than the EPP addressing. Channel
addressing is intended to be used to address multiple logical devices within a single physical
device. Think of this in terms of a new multi-function device such as FAX/Printer/Modem.
Within one physical package, having a single parallel port attached, there is a printer, fax and
modem. Each of these separate functions can be thought of as separate logical devices within
the same package. Using the ECP channel addressing to access each of these devices, you
could receive data from the modem data device while the printer data channel is busy
processing a print image. With the compatibility mode protocol, if the printer gets busy then
no more communication can occur until the printer data channel is free. With ECP, the
software driver simply addresses another channel and communication can continue.

As with the other 1284 modes, the ECP protocol redefines the SPP signals to be more
consistent with the ECP handshake. Table 5 describes these signals.

Figure 30 shows two forward data transfer cycles. When HostAck is high it indicates that a
data cycle is taking place. When HostAck is asserted low, a command cycle is taking place
and the data represents either an RLE count or a Channel address. Bit 8, of the data byte is
used to indicate RLE vs. Channel address. If bit 8 is 0, then bits 1-7 represent a Run_Length
Count (0-127). If bit 8 is 1, then bits 1-7 represent a Channel address (0-127) Figure 31
shows a data cycle followed by a command cycle.
Figure 31 shows a reverse channel command cycle followed by a reverse channel data cycle.
The I/O read or write strobes are not shown in these figure this is because the ECP FIFOs are
used to decouple the ISA data transfers, either DMA or programmed I/O, from the actual
host/peripheral data transfers. It is this decoupling of the transfer states that makes the ECP
protocol a "loosely coupled" protocol. The software driver does not know the exact state of
the data transfers. If a large block is being transferred via DMA, the driver does not know if
the 123rd byte is being transferred or the 342,201st byte. As in the case of printers, the
software may not care. The only concern is whether the transfer was completed or not.

Figure 30

Forward Transfer phase transitions:

1. The host places data on the data lines and indicates a data cycle by setting HostAck
high.
2. Host asserts HostClk low to indicate valid data
3. Peripheral acknowledges host by setting PeriphAck high
4. Host sets HostClk high. This is the edge that should be used to clock the data in to the
peripheral.
5. Peripheral sets PeriphAck low to indicate that it is ready for the next byte.
6. The cycle repeats, but this time it is a command cycle because HostAck is low.

Note: Since ECP transfers are loosely coupled, with a FIFO possibly on both sides of the
interface, it is important to note at which step the data is considered "transferred". This point
occurs at step 4, when the HostClk goes high. At this time, the data should be clocked in to
the peripheral, and any data counters updated. There is a condition in the ECP protocol that
could cause the transfer to abort at between steps 3 and 4. In this case the data should not be
considered to have been transferred.

Figure 31 shows another of the differences between the ECP and EPP protocols. With EPP,
the software driver may intermix read and write operations without any overhead or protocol
handshaking. With the ECP protocol, changes in the data direction must be negotiated. The
host must request a reverse channel transfer by asserting nReverse Request and then wait for
the peripheral to acknowledge the request by asserting nAck Reverse. Only then can a reverse
channel data transfer take place. In addition, since the previous transfer may have been DMA
driven, the host software must either wait for the DMA to complete, or interrupt the DMA,
back flush the FIFO to determine the exact transferred byte count, and then request the
reverse channel. This adds a fair amount of overhead with peripherals that require a lot of
intermixed reading and writing of registers or small buffers.
 Figure 31

Reverse Transfer phase transistions:

1. The host requests a reverse channel transfer by setting nReverseRequest low.

2. The peripheral signals that it is OK to proceed by setting nAckReverse low
3. The peripheral places data on the data lines and indicates a data cycle by setting
PeriphAck high.
4. Peripheral asserts PeriphClk low to indicate valid data
5. Host acknowledges by setting HostAck high
6. Peripheral sets PeriphClk high. This is the edge that should be used to clock the data
in to the host.
7. Host sets HostAck low to indicate that it is ready for the next byte.
8. The cycle repeats, but this time it is a command cycle because PeriphAck is low.

ECP Software and Register Interface:

The Microsoft specification, "The IEEE 1284 Extended Capabilities Port Protocol and ISA
Interface Standard", defines a common register interface for ISA based 1284 adapters with
ECP. This specification also defines a number of operational modes that the adapter can
operate under. Table 6 identifies these modes.
Note 1) This mode is implemented by the SMC FDC37C665/666 controller and is not
defined by the ECP specification. Most 1284 I/O controllers implement the EPP mode in a
similar fashion.

The register model for an ECP port is similar to that of the standard parallel port, but takes
advantage of a significant design oddity of the ISA bus architecture. In the IBM compatible
PC architecture, only the first 1024 I/O ports, or addresses, are used. This is the basic I/O
space of 0x000h to 0x3ffh. In order to address this range of addresses, only 10 address bits
are needed (AD0-9). In order to save cost, older PC's only drove and decoded these address
bits on the ISA bus and therefore limited the available I/O space to these 1024 registers.
Newer PC's, actually drive and decode more address bits, enabling a larger available I/O
space. This creates, in effect, multiple "pages" of the first 1K I/O ports. A software driver can
access these pages by adding 1024 (0x400h hex notation) to the base address being accessed.
Therefore, addressing addresses 0x378h and 0x778h can access 2 registers on two separate
pages, but be guaranteed not to interfere with any other installed ISA device. The advantage
is that by using this "aliasing" effect, new cards can have "hidden" registers, thus expanding
the available number of registers available, and still maintain compatibility with older ISA
cards that only decode 10 address bits.

The ECP register model takes advantage of this and defines 6 registers that only require 3
actual I/O ports. Table 7 identifies these registers. Note that the register definition may be
dependent upon the current mode of operation. The ECR register is the most important aspect
of this register configuration. This is the register that is used to set the current operational
mode. Additionally, this register can be used by software to determine if an ECP-capable port
is installed in the PC. Detection software can try to access any ECR registers by adding
0x402h to the base address of the LPT ports identified in the BIOS LPT port table.
 Objective: Study of PC to PC communication using Parallel Port

Accessories required:

1. ST5001 Trainer Kit

2. ST5001 Software
3. 11 Patch Cords (2mm)
4. 2 Parallel Port Cables
5. Mains Power Cord

Procedure:

Figure 32

Connect patch cords as shown in Figure 32

1. Connect mains power cord to the trainer and switch on the trainer.
2. Connect the parallel port cables to both node1 & node2.
3. To open the window as shown in Figure 33, follow the steps.
Run ST5001 software on both PCs
Click “Parallel Port Interface” image/press “Ctrl + P”/click “Options” on menu bar.
4. The very first step is to select the port address of parallel port. Choose one correct
option from the given three options.
5. Generally the address is “378”, so the window will open with this option selected.
6. To send data to the other node enter the text in the window titled as “Enter Data to
Transmit”. Click on “Send” button to transmit.
7. Transmitted data will be displayed in the “Received Data” window and the ASCII
codes of each byte received is displayed in “Received Data in ASCII” window.
8. A small window at sender side is given for transmission of ASCII code. Enter an
ASCII code in the window and then click “Send” button.
9. “Clear” buttons are given to clear all windows.

Note: In parallel communication software window check whether the tristate (5) (check box)
bit is working or not. If it is not working then follow the steps Restart the computer >> Keep
pressing “Del” button of key board >> Now system will enter in BIOS settings >> Select
“Integrated Peripherals” >> Select “Parallel port” >> Select “Mode” >> Select
“Bidirectional” or “EPP” mode >> Save settings.

The software window screen shot is as shown in Figure 33

Figure 33
 Experiment 7

Study of Protocols used in Parallel Communication

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Objective: Study of Protocols used in Parallel Communication

Accessories required:

1. ST5001 Trainer Kit

2. ST5001 Software
3. 11 Patch Cords (2mm)
4. 2 Parallel Port Cables
5. Mains Power Cord

Theory:

a) Stop N Wait protocol:

Stop and Wait transmission is the simplest reliability technique and is adequate for a very
simple communications protocol. A stop and wait protocol transmits a Protocol Data Unit
(PDU) of information and then waits for a response. The receiver receives each PDU and
sends an Acknowledgement (ACK) PDU if a data PDU is received correctly, and a Negative
Acknowledgement (NACK) PDU if the data was not received. In practice, the receiver may
not be able to reliably identify whether a PDU has been received, and the transmitter will
usually also need to implement a timer to recover from the condition where the receiver does
not respond.

Procedure:

Figure 34
 Connect patch cords as shown in Figure 34

1. Connect mains power cord to the trainer and switch on the trainer.
2. Connect the parallel port cables to both node1 & node2.
3. To open the window as shown in Figure 35, follow the steps.
Run ST5001 software on both PCs >> Click “Protocols by Interface” image/press
“Ctrl + T”/click “Options” on menu bar >> Click “Stop-N-Wait Protocol”.
4. The very first step is to select the port address of parallel port. Choose one correct
option from the given three options.
5. Generally the address is “378”, so the window will open with this option selected.
6. Select one node as sender and other as receiver, for that click “Options” on menu bar
or press “Ctrl + S” for sender & “Ctrl + R” for receiver.
7. Select a text file to transmit by clicking “Open” button. Click “Send” button to send
the file, at the same time receiver should press “Receive” button.
8. The packets are numbered in modulo-7 type of numbering.
9. Transmitted packet & particular packet number is displayed on the sender side.
10. At the receiver side received packet and its packet number is displayed.
11. There is a checkbox is given at the receiver side, titled as “Don’t send
Acknowledgment”, by clicking on it you can decide whether to send an ACK or not.
12. After complete reception click “Save” button to save the received file at the desired
location.

The software window screen shot is as shown in Figure 35

Figure 35
b) Go Back N protocol:

The receiver sends an ACK for each frame as it is received. If a corrupted frame, F(n), is received
or F(n) is missing (didn't arrive) then the receiver sends a special NACK(n) to request that the
sender start retransmitting from frame F(n).

Figure 36

Procedure:

Figure 37
1. Connect patch cords as shown in Figure 37 for Stop N Wait protocol.
2. Connect the parallel port cables to both node1 & node2.
3. To open the window as shown in Figure 38, follow the steps.
Run ST5001 software on both PCs
Click “Protocols by Interface” image/press “Ctrl + T”/click “Options” on menu bar.
Click “Go Back N Protocol”.
4. The very first step is to select the port address of parallel port. Choose one correct
option from the given three options.
5. Generally the address is “378”, so the window will open with this option selected.
6. Select one node as sender and other as receiver, for that click “Options” on menu bar
or press “Ctrl + S” for sender & “Ctrl + R” for receiver.
7. Select a text file to transmit by clicking “Open” button. Click “Send” button to send
the file, at the same time receiver should press “Receive” button.
8. The packets are numbered in modulo-7 type of numbering.
9. Transmitted packet & particular packet number is displayed at sender side.
10. At the receiver side received packet and its packet number is displayed.
11. There is a checkbox is given at receiver side titled as “Send Acknowledgment
Number” and a small window is given. Enter an acknowledgment number; the sender
will resend the packets from that ACK number.
12. After complete reception click “Save” button to save the received file at the desired
location.

The software screen shot of this protocol is as shown in Figure 38.

Figure 38
c) Selective Repeat Protocol : The receiver sends an ACK for each frame as it is received. If
a corrupted frame, F(n), is received or F(n) is missing (didn't arrive) then the receiver sends a
special NACK(n) to request that the sender retransmit frame F(n).

Figure 39

Procedure:

Figure 40
1. Connect patch cords as shown in Figure 40 for Stop N Wait protocol.
2. Connect the parallel port cables to both node1 & node2.
3. Connect the parallel port cables to both node1 & node2.
4. To open the window as shown in Figure 41, follow the steps.
Run ST5001 software on both PCs >> Click “Protocols by Interface” image/press
“Ctrl + T”/click “Options” on menu bar. >> Click “Selective Repeat Protocol”.
5. The very first step is to select the port address of parallel port. Choose one correct
option from the given three options.
6. Select one node as sender and other as receiver, for that click “Options” on menu bar
or press “Ctrl + S” for sender & “Ctrl + R” for receiver.
7. Select a text file to transmit by clicking “Open” button. Click “Send” button to send
the file, at the same time receiver should press “Receive” button.
8. The packets are numbered in modulo-7 type of numbering.
9. Transmitted packet & particular packet number is displayed at sender side.
10. At the receiver side received packet and its packet number is displayed.
11. There is a checkbox is given at receiver side titled as “Send Acknowledgment
Number” and a small window is given. Enter an acknowledgment number; sender will
resend the particular packet.
12. After complete reception click “Save” button to save the received file at desired
location

Figure 41
 Experiment 8

Crossover Cable Construction

Straight Through Cable Construction

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Experiment 8A
Crossover Cable Construction
 Experiment 8B
Straight Through Cable Construction
 Experiment 9

Command Line Fundamentals

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Experiment 9
Command Line Fundamentals
 Experiment 10

Review of Basic Router Configurations with RIP

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Experiment 10
Review of Basic Router Configurations with RIP
 Experiment 11

Configuring the OSPF Routing Process

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Experiment 11
Configuring the OSPF Routing Process
 Experiment 12

Configuring EIGRP Routes

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Experiment 12
Configuring EIGRP Routes
 Experiment 13

Basic Switch Configuration

Managing the MAC Address Table

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Experiment 13A
Basic Switch Configuration
 Experiment 13B
Managing the MAC Address Table
 Experiment 14

Configuring Static MAC Address

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Experiment 14
Configuring Static MAC Address
 Experiment 15

Configuring Static VLANS

Name ___________________
Roll No ___________________
Date ___________________
Marks Obtained ___________________
Signature ___________________
 Experiment 15
Configuring Static VLANS