Casio ctk-630 PDF
Casio ctk-630 PDF
Casio ctk-630 PDF
CTK-630
CONTENTS
Page
Specifications ................................................................................................................................... 2
Block Diagram .................................................................................................................................. 3
Circuit Description ............................................................................................................................ 4
Troubleshooting ............................................................................................................................. 10
Major Waveforms ........................................................................................................................... 11
Printed Circuit Boards .................................................................................................................... 12
Schematic Diagrams ...................................................................................................................... 13
Exploded View ............................................................................................................................... 16
Parts List ........................................................................................................................................ 17
ELECTRONIC KEYBOARD
SPECIFICATIONS
GENERAL
Number of keys: 61
Polyphonic: 24-note
Preset tones: 100, Tone expander: Layer On/Off, Split On/Off
Keyboard controls: Touch response: On/Off, Key transpose: Range from F# to F by
a semitone increment, Pitch bend: 12 steps up and down (a seminote at
muximum)
Auto-rhythms: 100, Tempo control: 40 to 255
Auto-accompaniment: Mode: CASIO Chord/Fingered/Full-Range Chord 1/
Full-Range Chord 2
Controller: Intro/Fill-In, Synchro/Ending, Normal/Variation
Easy presets: 50, including — Free Session (Chord): 30, Free Session (Song): 10,
Melody Composition: 10
Reverb effects: Hall/Stage/Room
Musical pads: 8
Pad variations: 50, including — Pops: 10, Rock: 10, Jazz/Fusion: 10, Dance/Funk: 10
European: 2, Latin/Various: 5, Drums/Percussion: 5
Song memory: 3, Real-time recording, Memory capacity: Approx. 1200 notes in total
Demo tunes: 3, including — A Night has 9000 Bars (arranged and programmed by
Thomas Hirsch), Wanting This (Edward Alstrom), Supersonic Remorse
(Edward Alstrom)
Demo tune program: Repeat/Skip
Tuning control: 440Hz ± 50 cents
Built-in speakers: 12 cm dia. 2 W input rating: 2 pcs.
MIDI: 16 multi-channel reception
Terminals: Phone Jack [Output impedance: 90 Ω, Output voltage: 4.6 V(rms)
MAX], Sustain Jack, MIDI Jacks (IN, OUT), AC Adapter Jack (9 V)
Auto power off: Approximately 6 minutes after the last operation
Power source: 2-way AC or DC source
AC: AC adapter
DC: 6 D size dry batteries
Power consumption: 7.7 W
Dimensions (HWD): 104 x 931 x 353 mm (4-1/16 x 36-5/8 x 13-7/8 inches)
Weight: 4.7 kg (10.4 lbs) including batteries
—2—
BLOCK DIAGRAM
Power Switch
VDD
Working Storage
RAM (64K-bit) MIDI Buttons
LSI103 OUT IN
SRM2264LM90
CPU
FI0 ~ FI10
Sound Source ROM MD0 ~ MD15 SI0 ~ SI19
(16M-bit) LSI105
Keyboard
LSI104
MX23C1610MC- UPD912GF-3BA
MA0 ~ MA19
12CA20 KC0 ~ KC7
LRCK SO BCK
D/A Converter
IC102
UPD6379GR
LVDD DVDD VC
VCC AVDD VDD
Filter
Q108, Q109
Output Q119, Q120
APO Power Supply Circuit
Q101 ~ Q106
Main D101, D103, D104
Speakers Volume
Power Amplifier
IC101
LA4598
—3—
CIRCUIT DESCRIPTION
KEY MATRIX
—4—
Key
Note: Each key has two contacts,
the first conatct (1) and second contact (2).
FI
Second contact (2) First contact (1)
KC
SI
NOMENCLATURE OF KEYS
C#2 D#2 F#2 G#2 A#2 C#3 D#3 F#3 G#3 A#3 C#4 D#4 F#4 G#4 A#4 C#5 D#5 F#5 G#5 A#5 C#6 D#6 F#6 G#6 A#6
C2 D2 E2 F2 G2 A2 B2 C3 D3 E3 F3 G3 A3 B3 C4 D4 E4 F4 G4 A4 B4 C5 D5 E5 F5 G5 A5 B5 C6 D6 E6 F6 G6 A6 B6 C7
The power supply circuit generates six voltages as shown in the following table. VDD voltage is always
generated. The others are controlled by APO signal from the CPU.
RESET CIRCUIT
When batteries are set or an AC adapter is connected, the reset IC provides a low pulse to the CPU. The
CPU then initializes its internal circuit, and clears the working storage RAM.
When the power switch is pressed, the CPU receives a low pulse of POWER signal. The CPU sends
APO signal to supply ground source for the DSP, also sends a reset signal to the DSP.
Battery set VDD VDD
VDD
Reset signal
DSP
RESET PLE
LSI101
Reset IC CPU HG51B227FB
IC105 LSI105
RE5VA35AA UPD912GF-3BA
APO
POWER SCKO
NMI
From power switch
—5—
CPU (LSI105: UPD912GF-3BA)
The 16-bit CPU contains a 1k-byte RAM, three 8-bit I/O ports, two timers, a keycontroller and serial interfaces.
The CPU detects key velocity by counting the time between first-key input signal FI and second-key SI from
the keyboard. The CPU reads sound data and velocity data from the sound source ROM in accordance with
the selected tone; the CPU can read rhythm data simultaneously when a rhythm pattern is selected. Then the
CPU provides 16-bit serial sound data to the DSP. The CPU also controls MIDI input/output and stores
sequencer data into the working storage RAM.
The following table shows the pin functions of LSI105.
—6—
Pin No. Terminal In/Out Function
80 VCC In +5 V source
81 GND In Ground (0 V) source
82 MRDB Out Read enable signal output for the sound source ROM
83 ~ 98 MD0 ~ MD15 In/Out Data bus
99 PLE Out Reset signal output for the DSP
100 P17 In APO cancellation signal input
The DSP receives 16-bit serial sound data output from the CPU and adds the selected effect to the sound
data using the effect RAM. Then the DSP provides the sound data to the DAC. The DSP contains two I/O
ports, which controls LEDs.
The following table shows the pin functions of LSI101.
Pin No. Terminal In/Out Function
1 ~ 4, 80 PB0 ~ PB4 Out LED drive signal output
5 SO Out Serial sound data output for the DAC
6 WCKO Out Word clock output for the DAC
7 VDD3 In +5 V source
8 TEST — Not used.
9 RESB In Reset signal input
10 VSS2 In Ground (0 V) source
11, 12 XIN, XOUT In/Out 16 MHz clock input/output
13 WCKI In Word clock input from the CPU
14 SI In Serial sound data input from the CPU
15 BCKI In Bit clock input from the CPU
16 SINC In 1 MHz synchronizing pulse input
17 VDD2 In +5 V source
18 ~ 25 IO0 ~IO7 In/Out Data bus
26 RCEB Out Chip enable signal output for the working storage RAM
27 VSS3 In Ground (0 V) source
28 AD1 In Address bus
29 OEB In Not used. Connected to +5 V source.
30 WEB In Write enable signal input
31 VDD3 In +5 V source
32 CE2 In Chip enable signal input. High active.
33 AD0 In Address bus
34 CE1B In Chip enable signal input. Low active.
35 ~ 41, 43 EIO0 ~EIO7 In/Out Data bus for the effect RAM
42 , 44, 46 ~ 48,
EA0 ~ EA12 Out Address bus for the effect RAM
51 ~57, 59
45 ECEB Out Chip enable signal output for the effect RAM
49 EOEB Out Read enable signal output for the effect RAM
—7—
Pin No. Terminal In/Out Function
50 VSS3 In Ground (0 V) source
58 EA13 Out Not used
60 EWEB Out Write enable signal output for the effect RAM
61 EA14 Out Not used
62, 66, 70, 74, 78 VSS2 In Ground source
63, 67, 71, 75, 79 VDD2 In +5 V source
64, 65, 68, 69,
PA0 ~ PA7 Out LED segment signal output
72, 73, 76, 77
The DAC receives 16-bit serial data output from the DSP. The data contains digital sound data of the
melody, chord, bass, and percussion for the right and left channels. The DAC converts the data into
analog waveforms and output them to each channel separately.
Synch signal
SINC SCK1
L OUT Data Data
DSP CPU
SI SO LSI101 SI SO
DAC LSI105
Word clock HG51B227FB Word clock UPD912GF-3BA
IC102
UPD6379GR LRCK WCKO WCKI LRCK
R OUT Bit clock Bit clock
CLK BCKI BCK
FILTER BLOCK
Since the sound signals from the DAC are stepped waveforms, the filter block is added to smooth the
waveforms.
AVDD
AVDD
22K
To main volume
47K
1K
C332(H)
470
10V22µ C333(H)
AG AG
AG AG
—8—
POWER AMPLIFIER (IC101: LA4598)
LED DRIVING
LVDD
LC0 ~LC4
PB0 ~ PB4
IC103
BA612
LED Driver
LG
—9—
TROUBLESHOOTING
— 10 —
MAJOR WAVEFORMS
0.1 s 20 µs 2 µs 2 µs
1 CH1 D
CH1
A CH1
CH2 E
4 CH1
CH2 CH2
2 B
3
CH3
C CH3 F
CH1: 5 V CH2: 5 V CH1: 5 V CH1: 5 V CH2: 5 V CH3: 5 V CH1: 5 V CH2: 5 V CH3: 5 V
1 POWER ON signal 4 Synchronizing pulse A Word clock LRCK D Word clock LRCK
UPD912GF-3BA pin 21 UPD912GF-3BA pin 6 UPD912GF-3BA pin 13 UPD6379GR pin 1
2 APO signal B Data signal SO E Data signal SI
UPD912GF-3BA pin 3 UPD912GF-3BA pin 12 UPD6379GR pin 2
3 Reset signal for the DSP C Bit clock BCK F Bit clock CLK
UPD912G-3BA pin 99 UPD912GF-3BA pin 11 UPD6379GR pin 3
Note: On
50 µs 5 ms 1 ms 1 ms
5 CH1
CH1
CH1 CH1
8 G I
6 CH2
9 CH2
CH2
7 CH3
H J CH2
0 CH3
~ ~ ~ ~
CH1: 5 V CH2: 5 V CH3: 5 V CH1: 5 V CH2: 5 V CH3: 5 V CH1: . 1 V CH2: . 1 V CH1: . 1 V CH2: . 1 V
5 Key scan signal KC0 8 LED drive signal PB0 G DAC output (R-ch) I Amp. input (R-ch)
UPD912GF-3BA pin 31 HG51B227FB pin 80 UPD6379GR pin 5 LA4598 pin 6
6 Key scan signal KC1 9 LED drive signal PB1 H DAC output (L-ch) J Amp. input (L-ch)
UPD912GF-3BA pin 32 HG51B227B pin 1 UPD6379GR pin 8 LA4598 pin 10
7 Key scan signal KC2 0 LED drive signal PB2
UPD912GF-3BA pin 33 HG51B227FB pin 2
— 11 —
D451
C
D450
C177 D102
PS
VC
R
C101 R101
Q103
E
R102
W
L102
PZ
D449
C175
R103
B
D106
BK R
L101
Q104
D448
L107
D103
B
Q101
R106 B E
L103
1
E
C103
E
C176 100
75
R107
D447
Q102
B
C187
J101
D446 D101 C110 VCC C178
R104
100
E B D104
Q106
E
Q105
R105
D445 2 1 3
D105
.
.
D444 3
125
2 1
C104
150
C102
175
C105
C109
300
D107 275 FB101
5
D443 R146
VR101
75 FB102 J102
Main PCB JCM461-MA1M
C116
L VDD
FB104
100
125
C114
D441 5
100
C113
2
D440 75 R129
C123
R125
1
125 R126
B E B E C117
Q109 75 5
Q108 R136
D439 R133 AVDD R134
R131
DVDD
75 R135
C126
R108
D438 C124 5
FB117
C127 C122
R137
C125
R122
R114
R132 C121 C128 5
R130
D437
JC
R144 R140
D436 C136 C118 J103
75
C135 C129
R145 C107
R141
R286
19 20
R283
5
E
E
5 15 1 Q120 R110
15 JD 1 JD R109 R118
C106
Q119
R117 5
16
R284
R281
R127
17
B
L109
R113 C119
C137
R285 R282
100
LED416
LED415
J104
125
R121
VDD
C131
C145
C144
3
C133
C108
R112
R119 R147 L110
R128
IC101
R120
C112
18
C180
R148
IC102
C132
LED413
D108
5
150
C147
175
D432
D435
D434
LED414 D431
C138
R298
D429
R149
Q123
D109
1
D425
C184
D421 FB116
R150
C143
B
D111
L108
5 5 5
C142
B
16 14
D433
D430
IC104
R116
R115
FB119
Q124
R299
R297
FB123
E
Q122
C183 R157
E L111
B C153
B
R164
R222 Q110 C193
JA
R223 B E
15
R156
C192
Q107
R224 Q111
E
R226 Q112
J105
Q118
R151
R291
B
4
E
R124
R227 B E
C115
B E IC103 R165
FB124
R216 125
R290
Q115 5
D420 D419 E 125
5 5 D422 R184 B R288
Q116 C182
B
10
D418 R185
D426 B E
R186
5
D424 D423 Q117 FB115
FB114
395
R187 C203
5
5
5
D428
5
5 D427
9
5 R188 C204
5 C158
— 12 —
R189 C159
Top View
Top View
R190 C157
C161
75 R269
R191 FB110
8
R268
D417
100
R266 FB111
R300
R265
C194
R264 R172
D416
C200
R263
5
X101
R262
250
R261
LED401
R260
R296
R293
LSI102
R259
PRINTED CIRCUIT BOARDS
R258 R294
D415 D414
R257 R295
LSI101
5
R256 5
100
1
R255
497 R192 R254
R193 R253
- (TT)
5
5
LED412
R194 R252
IC106
LN882RPX
R195 R251
5
5
5
5 R196 R250
5 R197 R249
5 5 C205
R198 R248
5 5
5
R199 R247
C201
JB
75
R246 75
D411
D412
D413
D410
D408
D409
D406
D407
LSI103
LED410
C202
R245
R200 175
6
R203 R292
16
C160
R204
7
R205
R206 200
17
R207
R208 R279
NO.
12
R209
R278
JC
JC
R210 R277
R211
LSI104
R276
R212
4
1
C195
C186
R307
R301 R309
R308
5
R303
C207 FB122
5 150
200 C163
R305
R306
D403
R181
3
R272
125
R273
R271
175
R274
C199
R275
LSI105
2
225
C198
C208
D405
D404
D402
11
75
R310
FB118
LED402
R178
C173
R179
C166
R280
C165
LED409
LED408
LED407
LED406
LED405
LED404
LED403
C164 C174
13
R302 R180
C196 R182
R183
X102
L105
D110
1 3
1
IC105
R241
R240
R239
R238
R230
R231
R232
R233
R234
R235
R236
R237
R244
R243
R242
15 JD 1
PR
Y
C167
BL
245
SCHEMATIC DIAGRAMS Notes:
1. All capacitance values are indicated in "µF" (p=10-6 µF).
Main PCB JCM461-MA1M
2. All resistance values are indicated in "Ω" (k=103 Ω, M=106 Ω).
2 4
11 12 13
14 15 16 9 10 1
8
5 6 7
17
20
18
19
— 13 —
Console PCB JCM461-CN1M
— 14 —
Keyboard PCBs JCM617T-KY1M/KY2M
— 15 —
EXPLODED VIEW
15
14
12
13
3 1
4
5 2
16
8
12 6 9
7
10
17
18
19
— 16 —
11
20
21
21-2
22
23
21-1
24
25
27
26
PARTS LIST
CTK-630