PRELIMINARY

CONNECTION DIAGRAMS
SO

NC 1 44 RESET#
RY/BY# 2 43 WE#
A17 3 42 A8
A7 4 41 A9
A6 5 40 A10
A5 6 39 A11
A4 7 38 A12
A3 8 37 A13
A2 9 36 A14
A1 10 35 A15
A0 11 34 A16
CE# 12 33 BYTE#
VSS 13 32 VSS
OE# 14 31 DQ15/A-1
DQ0 15 30 DQ7
DQ8 16 29 DQ14
DQ1 17 28 DQ6
DQ9 18 27 DQ13
DQ2 19 26 DQ5
DQ10 20 25 DQ12
DQ3 21 24 DQ4
DQ11 22 23 VCC

21505C-3

PIN CONFIGURATION LOGIC SYMBOL

A0–A17 = 18 addresses
18
DQ0–DQ14 = 15 data inputs/outputs A0–A17 16 or 8
DQ15/A-1 = DQ15 (data input/output, word mode), DQ0–DQ15
A-1 (LSB address input, byte mode) (A-1)

BYTE# = Selects 8-bit or 16-bit mode

CE#
CE# = Chip enable OE#
OE# = Output enable
WE#
WE# = Write enable RESET#
RESET# = Hardware reset pin, active low BYTE# RY/BY#
RY/BY# = Ready/Busy# output
VCC = +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage 21505C-4
supply tolerances)
VSS = Device ground
NC = Pin not connected internally

Am29F400B 5
 PRELIMINARY

ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.

Am29F400B T -55 E C

OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)

TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION
See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector

DEVICE NUMBER/DESCRIPTION
Am29F400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase

Valid Combinations Valid Combinations

Valid Combinations list configurations planned to be sup-
Am29F400BT-55, ported in volume for this device. Consult the local AMD sales
EC, EI, FC, FI, SC, SI
Am29F400BB-55 office to confirm availability of specific valid combinations and
Am29F400BT-60, to check on newly released combinations.
Am29F400BB-60

Am29F400BT-70,
Am29F400BB-70
EC, EI, EE,
Am29F400BT-90,
FC, FI, FE,
Am29F400BB-90
SC, SI, SE
Am29F400BT-120,
Am29F400BB-120

Am29F400BT-150,
Am29F400BB-150

6 Am29F400B
 PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the the register serve as inputs to the internal state ma-
device bus operations, which are initiated through the chine. The state machine outputs dictate the function of
internal command register. The command register it- the device. Table 1 lists the device bus operations, the
self does not occupy any addressable memory loca- inputs and control levels they require, and the resulting
tion. The register is composed of latches that store the output. The following subsections describe each of
commands, along with the address and data informa- these operations in further detail.
tion needed to execute the command. The contents of

Table 1. Am29F400B Device Bus Operations

DQ8–DQ15
BYTE# BYTE#
Operation CE# OE# WE# RESET# A0–A17 DQ0–DQ7 = VIH = VIL
Read L L H H AIN DOUT DOUT High-Z
Write L H L H AIN DIN DIN High-Z
VCC ± VCC ±
CMOS Standby X X X High-Z High-Z High-Z
0.5 V 0.5 V
TTL Standby H X X H X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Hardware Reset X X X L X High-Z High-Z High-Z
Temporary Sector Unprotect
X X X VID AIN DIN DIN High-Z
(See Note)

Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.

Word/Byte Configuration device data outputs. The device remains enabled for
read access until the command register contents are
The BYTE# pin controls whether the device data I/O
altered.
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in See “Reading Array Data” for more information. Refer
word configuration, DQ15–DQ0 are active and control- to the AC Read Operations table for timing specifica-
led by CE# and OE#. tions and to Figure 9 for the timing diagram. ICC1 in the
DC Characteristics table represents the active current
If the BYTE# pin is set at logic ‘0’, the device is in byte
specification for reading array data.
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins Writing Commands/Command Sequences
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function. To write a command or command sequence (which in-
cludes programming data to the device and erasing
Requirements for Reading Array Data sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power For program operations, the BYTE# pin determines
control and selects the device. OE# is the output con- whether the device accepts program data in bytes or
trol and gates array data to the output pins. WE# should words. Refer to “Word/Byte Configuration” for more in-
remain at VIH. The BYTE# pin determines whether the formation.
device outputs array data in words or bytes.
An erase operation can erase one sector, multiple sec-
The internal state machine is set for reading array data tors, or the entire device. Tables 2 and 3 indicate the
upon device power-up, or after a hardware reset. This address space that each sector occupies. A “sector ad-
ensures that no spurious alteration of the memory con- dress” consists of the address bits required to uniquely
tent occurs during the power transition. No command is select a sector. The “Command Definitions” section
necessary in this mode to obtain array data. Standard has details on erasing a sector or the entire chip, or
microprocessor read cycles that assert valid addresses suspending/resuming the erase operation.
on the device address inputs produce valid data on the

Am29F400B 7
 PRELIMINARY

After the system writes the autoselect command se- In the CMOS and TTL/NMOS-compatible DC Charac-
quence, the device enters the autoselect mode. The teristics tables, ICC3 represents the standby current
system can then read autoselect codes from the inter- specification.
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this RESET#: Hardware Reset Pin
mode. Refer to the “Autoselect Mode” and “Autoselect The RESET# pin provides a hardware method of reset-
Command Sequence” sections for more information. ting the device to reading array data. When the RE-
ICC2 in the DC Characteristics table represents the ac- SET# pin is driven low for at least a period of tRP, the
tive current specification for the write mode. The “AC device immediately terminates any operation in
Characteristics” section contains timing specification progress, tristates all output pins, and ignores all
tables and timing diagrams for write operations. read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
Program and Erase Operation Status chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
During an erase or program operation, the system may
to accept another command sequence, to ensure data
check the status of the operation by reading the status
integrity.
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation Current is reduced for the duration of the RESET#
Status” for more information, and to “AC Characteris- pulse. When RESET# is held at VIL, the device enters
tics” for timing diagrams. the TTL standby mode; if RESET# is held at VSS±0.5
V, the device enters the CMOS standby mode.
Standby Mode
The RESET# pin may be tied to the system reset cir-
When the system is not reading or writing to the device, cuitry. A system reset would thus also reset the Flash
it can place the device in the standby mode. In this memory, enabling the system to read the boot-up
mode, current consumption is greatly reduced, and the firmware from the Flash memory.
outputs are placed in the high impedance state, inde-
pendent of the OE# input. If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
The device enters the CMOS standby mode when the ternal reset operation is complete, which requires a
CE# and RESET# pins are both held at VCC ± 0.5 V. time of tREADY (during Embedded Algorithms). The
(Note that this is a more restricted voltage range than system can thus monitor RY/BY# to determine whether
VIH.) The device enters the TTL standby mode when the reset operation is complete. If RESET# is asserted
CE# and RESET# pins are both held at VIH. The device when a program or erase operation is not executing
requires standard access time (tCE) for read access (RY/BY# pin is “1”), the reset operation is completed
when the device is in either of these standby modes, within a time of tREADY (not during Embedded Algo-
before it is ready to read data. rithms). The system can read data tRH after the RE-
The device also enters the standby mode when the RE- SET# pin returns to VIH.
SET# pin is driven low. Refer to the next section, “RE- Refer to the AC Characteristics tables for RESET# pa-
SET#: Hardware Reset Pin”. rameters and to Figure 10 for the timing diagram.
If the device is deselected during erasure or program-
ming, the device draws active current until the Output Disable Mode
operation is completed. When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.

8 Am29F400B
 PRELIMINARY

Table 2. Am29F400BT Top Boot Block Sector Address Table

Sector Size Address Range (in hexadecimal)

(Kbytes/ (x8) (x16)
Sector A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range
SA0 0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh
SA1 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA2 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA3 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA4 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA5 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
SA6 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh
SA7 1 1 1 0 X X 32/16 70000h–77FFFh 38000h–3BFFFh
SA8 1 1 1 1 0 0 8/4 78000h–79FFFh 3C000h–3CFFFh
SA9 1 1 1 1 0 1 8/4 7A000h–7BFFFh 3D000h–3DFFFh
SA10 1 1 1 1 1 X 16/8 7C000h–7FFFFh 3E000h–3FFFFh

Table 3. Am29F400BB Bottom Boot Block Sector Address Table

Sector Size Address Range (in hexadecimal)
(Kbytes/ (x8) (x16)
Sector A17 A16 A15 A14 A13 A12 Kwords) Address Range Address Range
SA0 0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh
SA1 0 0 0 0 1 0 8/4 04000h–05FFFh 02000h–02FFFh
SA2 0 0 0 0 1 1 8/4 06000h–07FFFh 03000h–03FFFh
SA3 0 0 0 1 X X 32/16 08000h–0FFFFh 04000h–07FFFh
SA4 0 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh
SA5 0 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh
SA6 0 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh
SA7 1 0 0 X X X 64/32 40000h–4FFFFh 20000h–27FFFh
SA8 1 0 1 X X X 64/32 50000h–5FFFFh 28000h–2FFFFh
SA9 1 1 0 X X X 64/32 60000h–6FFFFh 30000h–37FFFh
SA10 1 1 1 X X X 64/32 70000h–7FFFFh 38000h–3FFFFh
Note:
Address range is A17:A-1 in byte mode and A17:A0 in word mode. See “Word/Byte Configuration” section for more information.

Autoselect Mode
The autoselect mode provides manufacturer and de- the sector address must appear on the appropriate
vice identification, and sector protection verification, highest order address bits (see Tables 2 and 3). Table
through identifier codes output on DQ7–DQ0. This 4 shows the remaining address bits that are don’t care.
mode is primarily intended for programming equipment When all necessary bits have been set as required, the
to automatically match a device to be programmed with programming equipment may then read the corre-
its corresponding programming algorithm. However, sponding identifier code on DQ7–DQ0.
the autoselect codes can also be accessed in-system
To access the autoselect codes in-system, the host
through the command register.
system can issue the autoselect command via the
When using programming equipment, the autoselect command register, as shown in Table 5. This method
mode requires VID (11.5 V to 12.5 V) on address pin does not require VID. See “Command Definitions” for
A9. Address pins A6, A1, and A0 must be as shown in details on using the autoselect mode.
Table 4. In addition, when verifying sector protection,

Am29F400B 9