| Service Manual ~CHROMA SERVICE MANUAL ‘TABLE OF CONTENTS SECTION 1 SYSTEM OVERVIEW SECTION 6 SCHEMATICS AND DRAWINGS GENERAL DESCRIPTION 14 ‘COMPUTER BOARD ASSEMBLY 6-2 DUAL CHANNEL ARCHITECTURE 12 COMPUTER BOARD SCHEMATIC 6-3 SYSTEM INTERFACING 1-3 VO BOARD ASSEMBLY 6a SYSTEM BLOCK DIAGRAM 18 VO BOARD SCHEMATIC 1 6-5 SYSTEM STRUCTURE 14 VO BOARD SCHEMATIC 2 67 CHANNEL MOTHER BOARD ASSEMBLY 6-8 SECTION 2 CIRCUIT DESCRIPTIONS CHANNEL MOTHER BOARD SCHEMATIC 6-9 QUAL CHANNEL BOARD SCHEMATIC 1 6-10 COMPUTER BOARD aa DUAL CHANNEL BOARD SCHEMATIC 2 6-11 VO BOARD 22 DUAL CHANNEL BOARD ASSEMBLY 6-11 DUAL CHANNEL BOARD 2-7 LEFT STACK SIWITCH ASSEMBLY 6-12 CHANNEL MOTHER BOARD 210 LEFT STACK SWITCH SCHEMATIC 8-13 POWER SUPPLY an RIGHT STACK SWITCH ASSEMBLY 9-19 FO BOARO 2-13 RIGHT STACK SWITCH SCHEMATIC 6-13. STACK SWITCH BOARDS 2-14 EQ BOARD SCHEMATIC 6-15 EQ BOARD ASSEMBLY 6-15 SECTION 3 DISASSEMBLY POWER SUPPLY ASSEMBLY 8-16 POWER SUPPLY SCHEMATIC 6.17 OPENING FoR SERVICE aa INTERCONNECTION DIAGRAM 1 6-18 BOARD LOCATIONS 3.2 INTERCONNECTION DIAGRAM 2 6-19 POWER SUPPLY CONNECTIONS 3-3 BALANCED OUTPUT SCHEMATIC 6-21 EXTERNAL INTERFACE CABLE SCHEMATIC SECTION 4 DIAGNOSTICS 6-21 SET SPLIT FUNCTIONS an SECTION 7 PARTS LIST TRIGGERED SWEEPS 42 comPUTEA BOARD 7 SECTION 5 CALIBRATION & CHECKOUT VO BOARD at CHANNEL MOTHER BOARD 72 POWER SUPPLY RIPPLE DUAL CHANNEL BOARD. 2-3 PREREGULATOR D.C. VOLTAGE ~ LEFT STACK SWITCH ASSEMBLY 2-8 +8V ANALOG D.C.VOLTAGE RIGHT STACK SWITCH ASSEMBLY 7-3 DAC OUTPUT NULL TRIM EO BOARD 24 THE “SCRATCH PATCH” POWER SUPPLY 7-4 OSCILLATOR TRIM PROCEDURE ALTERNATE TRIM PROCEDURE CHANNEL ASSIGNMENT TUNING CHECK ‘SWAPPING CHANNEL BOARDS ALTERNATE TUNING CHECK DAMPER BAR ADJUSTMENT STACK SWITCH ADJUSTMENT SECTION 8 MNEMONICS SIGNAL LISTING a1 The information contend herein i sontientsh and pro: piesary to 8S Ine. Ite dclored 10 you soley for purvoses ff instrction ay to operation of the eeulpment and main tenance a appropriate. Te ig not to bw disclosed #0 others vwathout the express Bermision of CRS Ine Copycight 1989 CBS IneSECTION 1. SYSTEM OVERVIEW ‘Chroma synthesizers are an extraordinary achievement ‘of America’s rascarch and engineering sciences, The ‘Chroma ig a sixtoon chanoel fully programmable poly: phonic synthesizer with fifty prasut sounds complete with touch responsive keyboard. ‘Tho Chroma is computer-based using two micro: processors, one for keynoare dynamics, the other tor high-speed digital control of the analog channels. In its most basic form, the Chroma consists of a com- outer {in the digital domain}, syathesizer channels (in the analog domain) and inputloutput support hardware (interfacing between the digital and analog domains) as illustrated in Figure 1-1 DIGITAL COMPUTER INTERFACE ANALOG FIG.1-1 BASIC SYSTEM The computer consists of 2 contral processing unit {CPU} and memory. The CPU is a 68809 micro- processor clocked at @MHz, Memory consists of 7K random access memory andi 16K read only memory. RAM js divided into 4K NMOS for data structoring (read/write memory} and 3K CMOS non-volatile for Horage of the fifty sounds. The 16K ROM contains ‘the eontvol program for the system using eight 2K EPROMs. The system is memory mapped and as shown in Figure 1-2 even the MO read/write opera: tions appear as memory locations to the 68809. Eight Dual Channel Boards rake up the sixteen syn- thesizer channels. Each board contains two voltage controlled oscillators, two voltage controlled filters, wo voltage controlled amplifiers, selectable waveforms and CMOS switching for versatile patching between circuits. These are supplemented with four envelope generators, two sweep generators (each capable of sheteen sweep waveforms from sine wave to random} land two glides per board, The envelopes, sweeps and Glides are software generated, no hardware circuits exist for these functions. Figure 1-3 illustrates the basic architechture of a Dual Channel Bosrd.(hex) SCRATCH PAD DATA STRUCTURING 3K 1400 émos ~<_—__—--— PROGRAM/SOUND Ram_| 1C00 STORAGE 2000 YO vn <_—__-— 25 BYTES 200F OVERLAPPED co00 <—_—_——— 16K CONTROL EPROM | erp PROGRAM MOTOROLA 68609 FIG. 1-2 CHROMA MEMORY MAPPED SYSTEM. osc oie FILTER AMP A A A A osc SNE FILTER AMP 8 2 B B (HARDWARE CIRCUITS) GLIDE SWEEP ENV ENV A A 1A 2A GLIDE SWEEP ENV ENV B B 1B 2B (GENERATED IN SOFTWARE) ' t t ' t ' ' t l FIG. 1-3 DUAL CHANNEL BOARD BASIC ARCHITECTURE“The interconnections between the blocks showin in Figure 1 - 3 are a function of the preset sound selected for the sound programmed by the user. For example! ‘Sweep "8" might go to Oscillator "A," Oscillator “A” to Filter "A," Filtor "A" to Filter “8,” Filter "B” to Amplifier A,” while Envelope "78" might go to Filter A" with Envelope "2A" going to Filter "B,"” ec. | think you got the idea, The patehing is extremely versetile, the synthesizer very powerful. Remember, signt Dual Channel Boards result in thirty-two enve. lopes, and sixteen sweeps, oscillators, filters and ‘The channel boards ave divided into twa sections, "A" and “B."" The "A" section is controlled by “A” parameters and the “B" section by “B” param: eters called up from the front pane! individually or together. ‘The 1/0 oF inputioutput chiefly consists of a keyboard scanning computer, a timer for cassette and auto-tune measurements and’ system timing, various decoders! drivers and two important converter circuits, The ADC (oF "AY to "D converter looks at analog levels such 28 9 slider or volume pedel and corverts it to digital computer data, The DACs or "D'" to “AY converters change digital computer data to analog voltages to operate the VGOs, VCFs and VCAs on the Dual Channel Boards, Figura 1-4 illustrates this hand: shaking. DIGITAL INTERFACE ANALOG SYNTH FIG. 1-4 SYSTEM INTERFACING A. system block diagram is shown in Figure 1-8. ‘When a keyboard switch it depressed the keyboard scanning emputer (Intel 8039) generates the note umber and velocity then interrupts the CPU (Motorola 68809), The CPU responds by fetching @ vector address from EPROM memory which puts it Into a sub-outine to read the note number then the velocity from the Bbit bi-directional bus. The CPU. manipulates this data using NMOS RAM under conteol of the EPROM firmware and writes digital data to the DACs for conversion ta analog voltages. A serial stream of 64 discrete varying voltages from the DAC circuitry is continually sampled to provide oscillator piten, pulse width, filter cutoff and volume. Other data structured by the CPU (iofluenced by the program selected from CMOS RAM} is written to the strobe decoder to establish the correct patches or inter- connections on the Dual Channel oards Control changes such as volume pedsl, levers or sliders are read from the ADC by the CPU, manipulated in NMOS RAM, and subsequently change the sound. Changes in program selected or editing from the panel switch atray, will also ater the data in NMOS RAM, ‘This will affect the sound and change the display. The sudio out from the Dual Channel Board is folded back during auto-tune operations to a zero crossing detector. “The period of the output square wave is timed and read by the CPU. Pitch corrections are then written to the DACs for proper volts per octave and offset by the CPU, During auto-tune the CPU measures each of the sixteen oscillators twiee, six octaves apart to establish correct valts per octave then a third time to adjust any offset, The filters are patched into self-esonance and also tuned during autotune, The entire auto-tune cycle takes about five seaonds and should be done one or two times within an hour by the user. The timer 2is0 provides the CPU with cassette times for differentiating between the 1200Hz and GOOHz tones used to re- present data bit fevels on tape, Additionally, the timer helbs reguiate the main software loop, Not shown on the system block diagram are the cassette interface, the audio EQ chain or the external computer interface. The externsl computer interface is a parallel port extending the B-it bivirectional bus complete with Bbit input and output buffering, ‘An expander module (with 8 more dual channels) may bbe connacted 10 this port or an external computer may be connected for sequencing, multi-tracking, tte., or both expander and computer may be connected. at the same time, You can se from the previous description that the computer (68B09) is central to everything else in the system, Figure 1 - 6 illustrates the structure of the overall system, ‘An indepth description of all Chroma circuits is detailed in Seetion 2.COMPUTER SYNTH ANALOG CONTROLS ANALOG AUDIO TOEQ DACS & VCO/VCF S&H ADDR. [— "| _vcaP.w. ANALOG SYNTH ZCD DIGITAL 8 BIT BIDIRECTIONAL DATA BUS PATCHES PANEL SWTICH ARRAY DISPLAY KEYBOARD KEYBOARD SCANNING COMPUTER, SWITCHES EXPANDER CENTRAL Siren SEINE KEYBOARD CASSETTE CONTROL PANEL FIG, 1-6 SYSTEM STRUCTURE 14 LEVERS & PEDALSSECTION 2. CIRCUIT DESCRIPTIONS COMPUTER BOARD ‘The Computer Board consists of the following sections, as outlined on the schematic: Glock generator CPU {central processing unith Address decoder RAM cwios RAM EPROM CMOS RAM power switching Each will be covered individually in the following descriptions. 1. CLOCK GENERATOR Tho clock generator is 3 simale TTL erystal oscillator running at 16MHz, It foods a divideby-two flip. flop that produces 9 2-ohase SMH? square wave, suitable for clocking both the 68809 CPU on board and the 8039 keyboard sesnning processor on the 1/0. boare. 2. CENTRAL PROCESSING UNIT The CPU eicuit consists mainly of the 68809 cho. Guttering is provided for the lower-order aderess Tine, the contra lines, and the data bus. The keyooare inzerupt tine (RTI) drves te fost interrupt request {FIRO} line on the CPU, The external input ard! out fut interrupt tines (TINT and KOTNT) both arve fhe normal intercup: request (THO) in'on the CPU Tho E and © signals that emanete from the CPU consists of wo 2MHz square waves in quadrature {90° gut of phase, ond these signals, “Ofted” co gether by 210A, provide 0 75% duty cycle actwetow nable signal that establishes the timing of each bus eyele. All ondboard. memocier are connected %0 the CPU by the "sirect bus” {D0 through D7}, all off board circuits are connected to the “buffered bus” {BO through 87) which ts isolated from the direct bus by a bus trarsce'ver, 22. This transceiver is onal ed only when oftiboard devices are accested. The ireuit consisting of Rad, RAB, C31, 28D ond Z8F slightly delays the enable signe to th transceiver until the dats ourtout by the CPU. chip it vad (during writes to oftboard devies) 3. ADDRESS DECODER ‘Tho address decoder routes the 2MHz onable signal produced by ZIQA to whatever device is being ad: dressed during each bus cycle. The decoder is in two stages. The first stage consists of 27, and routes the fenabie signal to one of It’s eight outputs depending ‘upon the three most significant address bits. Addrasses in the range 0000 (hex) to TFFF cause an enable pulse to be generated at pin 15, addressos in the range 2000, ‘to JFFF pulse pin 14, ete. The second stage consists of Z8 and 26. ZS is activated by addresses in the ange C000 to FFFF and routes the signal to one of the eight EPROMs on the board. (The R/T signal on Bin 6 prevents any spurious write cycles from attempt ‘ng to write into the EPROM.) 26 is activated by addrassas in the cange O00 to TFFF and routes the signal to one of the eight pairs of RAM sockets an the board. Pin 14 of 27 is gated with both polarities of the R/V signal to produce LORD and IOWR, These signals activate the inputfoutput devices on the 1/0 board. Nove that all inputfoutout is memory mapped in {6BB09 syscems, 4. RAM “The system uses 4K bytes of RAM for storage of data structures during operation, Eight 1K by 4 static RAM chips are used, 5. CMOS RAM The system requires 3K bytes of non-volatile storage for the synthesizer “programs.” This is provided by six 1K by 4 static RAM chips. These chips have thei ‘own VDD line which remains powered when al else is shut off. Each transistor circuit fungtions as an isolator for the chip selects, Whon RESET is low (which It naturally is when the power is shut off} the transistors allow the chip select {C5} inputs to the CMOS RAMS to rest high (inactive) oven though the enable signals, {from tho address decoder ace all low. 6. EPROM ‘The firmware that controls the operation of the 68809 processor amounts to almost 16K bytes, This is contained in eight 2K by 8 EPROMs. Their anly peculiarity is that they are read-only devices. Hence the WR line is used to disable them during write cycles. 7. CMOS RAM POWER SWITCHING ‘This cireuit contains two AA cells, which provides power to the CMOS RAMs when the instrument is turned off, and two trensistors to select between the battery and the main power supply, When the insteument is off, the battory is supolying 2 few volts, ‘This is applied through the germanium diode CRI to tha CMOS RAMs, Since the rest of the circuit has no power, everything wise is at O volts, meaning that Qt and CR2 are reversed biased, As soon as the main power starts to rise above the battery voltage, CR2 ‘becomes foward biased and CRI becomes reversed biased. Now the CMOS RAMs ore being powered from the main supply, However, the drop across GR2 can be nearly & volt under load. When the system RESET signal disappears (goes high}, O2 and QI turn fon, shorting out CR2 and applying the full 5 volts to the CMOS RAMs. Capacitor C3 slows down this final transition to 5 volts. When the power shuts 2down, the procass is reversed, ond the first thing thet happens is the arrival of the system RESET signal, CR2 is a power diode because the CMOS RAMS consume significant current during operation. CRT Js a germanium ciede for it’s lover voltage drop, (Also, it leaks shout 10UA when the msin power 's on, tickle charging the batteries.) VO BOARD The 1/0 Board consists af the following sections, as outlined on the schematie: SWITCH/DISPLAY MATRIX CASSETTE 1/0 1. YO STROBE DECODER 2, KEYBOARD SCANNING COMPUTER 3, COMPUTER INTERFACE 4. TIMER 5. A/D CONVERTER & D/ACONVERTER 7 8. 8, 1. CASSETTE MOTOR SENSE/CONTROL, 10, LED DRIVERS 11. TAPPER DRIVER 12, MISCELLANEOUS 1/0 Each will be covered individually in the following escriptions, with particular attention paid to the keyboard seanning computer and the timer, 1, UO STROBE DECODER [sheot 1) The main computer selects each device it wants to communicate with by using the 1/0 strobe decoder and the data bus. Whenever the computer wants to reed & byte {8 bits) of information from any de- vice vt located on the computer board, It activates the TORD line by bringing it low for 375ns (nano- seconds). During this time, the sddress bits AO, At, AZ and Ad will contain a number that identities ‘the device that the computer wants to read date from, The decoder 1239 for reads} generates @ pulse nore of its wight outputs that looks just like the TORD pulse: activelow TTL level, 375ns wide._In other words, the decoder steers the master [ORD pulse from the computer to one of eight devices. Each individual RD pulse causes the appropriate device connected to the data bus to turn en its output drivers. AC the instant the TORD pulse is over, the computer samples the data on the Pus. ‘The computer writes data to devices in a similar manner, although of eourse, the direction of the data flow is the opposite. The computer will activate the TOWR line for 375ns, snd during this time the four address bits will contain a number identifying the device that the data is to go to, The decoder chips [240 and 241 far writes) steer this pulse to one of 16 places. Meanwhile, the computer also drives the data bus with data, Each WR strobe line causes the aparo- priate device to sample the data bus and pick up the ata, All communication between the computer and the “outside world” i performed by time-sharing or multiplexing data over eight bus lines, and each byte fof data takes 375ns to transfer. (There is an ad- ditional 128ns idle time between bus cycles, which means that thy bus can tansfer data at up to 2 million bytes per second.) In order to "500" what's going fon im a computer system, it is necessary to examine: ‘the data bus during 8 specitic time slot, not ust all the time. If you look at a data bus fine with an oscllo: scape (without triggering off anything in particular! You will not see anything meaningful, Debugging such civcults require as an absolute minimum a dual ‘race oscilloscope with enough bandwidth to trigger off and see subrmicrococond events. The tochnigue [5 to use one trace to trigger off and view one of the RD or WR strobes, and then use the other trace to examine each data bit in turn to sen whether it is at 3 logic 0 of 1 at the trailing edge of the strobe. ‘The three decader chips thus provide eight read strabe lines and sixteen write strobe lings, After the first small produetion run, i was decided thst one more bit of input to the ‘computer was required. 255, 2 triple thvee-input open-collector NAND gate was added to sense the EOC {endof-conversion) output from she A/D converter {description 5}, Whenever ‘the computer performs a read from location 2008 bhex, address bit AS will be high during the TORO pulse, This will cause data bus 87 10 be pulled low if the conversion is not complete. 2. KEYBOARD SCANNING COMPUTER {sheet 1} ‘The Keyboard scanning in the Chroma is performed by a separate processer, an Intel 8039. This proc: esser has its own local date bus (DB lines, pins 12, ‘through 19) which connaets the 8039 to its program memory (EPROM 233} and 10 the keyswitch boards, The operation of this data bus is similar to the oD eration of the main data bus, except that there is rho separate address bus. Instead, there are four control signals associated with the bus that contrat the timing of all dsta wanafers in and out of the 8039. Ail bus ycles begin with the 8039 asserting ALE (Address Latch Enable, an active high pulse). During the pulse period, the ous will contain an actress. (Certain bits in port 2 are also used, but the keyboard scanning firmware only ruquires 8 address bits.) The address laten {232} is responsible tor holding the address during the dsta transfer partion of the cycle, Shortly after ALE gous low, the data transfer commences, lunder contro! of one of three activedowr strobe lines, PSEN (pragcam store enable}, AD and WA, ‘This particular circuit uses PSEN to enable the EPROM conigining the koyboard scanning ficrwsre, It also. uses the AD strobe ta fetch date trom the Keyswitch boards, but it uses this strobe in an unconventional manner. The keyswitch boards accept a 4 bit code that selects one of 18 banks of keyswitches, and returns eight lines corresponding to the switches within the salected bank, The amaunt of time ittakes to return this data is (oo long for the entire communication to take place within one bus eyele se it i done in two, The fiemware sotually reads two barks of switches in a row, an A bark and a B bank for s particular graup of eight Keys. A tots! of three cycles are used. In the first cycle, the computer supplies the number of a bank on the address lines, strobes FD, and ignores the data that it recoives, “This effectively writes the dats to latch 235 which drives the keyswiteh beards. On the second cycle, it supplies the number_of the second bank on the address lines, strabes AD, and reeds in the data from the previous bank, The number Of the second ank is latched by 235. On the third cycle it reads the data that returns from the second bank, ‘The Keyboard scanning computer scans the keys about 1000 times per second. It measures, for Goch Key, the time between the opening of one swith contact and the closing of the opposite contact in rmiltisecond ineremunts, Whenwver a contact closes, the key numaer and the time messurement is sent to the main computer. The port pins {Pt and P2) fon the 8039 are used for this purpose, Whenever information is to be transmitted to the main computer, the 8039 supplies the time measurement on port 2 bits 60 (pins 21-24, 35-37). Bie 7 (pin 38! will be high for a release snd tow for an sttack, It then puts the key number {from 0 10 63) on port 1 (pins 27-34) anc then sets pin 34 high, Thus pin 24 prox duces a short negativegoing pulse whenever neve information is present, The two NAND gates (249) form a set/raset flip-flop that performs interruot hhandshaking between the two computers, Whenever information is sent by the 8029, the pulse_trom pin 34 sets the flip-flop 10 one state, bringing RINT low and interrupting the main computer. The main coms auter temporarily suspends what it is daing and reads first the key number, and then the time measurement bby activating the RD NOTE and RD VEL strobes The RO VEL strobe sets the flipflap to the apposize state, clearing the interrupt Note thot the interrupt ine RINT also connects to the interrunt pin {INT, pin 6} on the 2039. This does rt interrupt tre 8030," Insteac, ths pn Te sd by the Keyboard scanning firmware to chock to sev if the provious cate tensor ie complete. The KMASK ling server 2 simple purpoce uring auto-tune and catette operations, When low, it hold the thp-lop it its rewet state (240 nigh}. This causes any Keve played on the Keyboare’ to be ignored by 00 ing the 8039 into thinking that its interrupts are being immedistly handled. Thus, any notes accidentally ‘trace while the Chrome isin auto-tune, for instance, wil not Vaile uo” and suddenly be heard when the auto tune is complete, ‘The oniy other details of the keyboard scanning circuit are the clock ines, Tae 8039 gets its clack in two-phase form at SMHz from the main computer, $0 both computers are actually synchvonized. This synchrony isn't important to the operation, but doas save the cost of another erystal oscillator, The port 2 lines emanating fram the 8039 are not static lines, and as such, have to be latched (whereas the port | lines are perfectly staticl. The port 2 data is always valid during the tise of ALE, and so the ALE signal is usd t0 clock the data inta latch 236, The ALE signal, which runs at about SOOKHz, is also used 25 3 clock signal for the A/D convertor, as itis @ con: venient frecuency 3, COMPUTER INTERFACE (sheet 1) ‘The computer interface consists of an B-bit input part with handshaking and an B-bit output port with hands shaking, If you are wondering what the port might onnect to, imagine it connected to an exact duplicate of itself; “that is, imagine each input port line (memenies starting with XI) connecting to the corresponding output port line (mnemonics starting with XO) at the other end of she interface, The interface only consists of the output leten (2261, the input tistate driver (227) and the five NAND ‘gates. (248, 49}. The cost of tho cireult is just for noise rejection and isolation when the power is shut off When Uw Chroma wants to wansmit a byte of dats, it checks the XO FULL line to see if tho lost byte it sent has been receved yet, When it has, it writes the byte into the latch with the WR EXTO strobe. This causes the flip-lop consisting of gates Z48-A and 248-8 to be set, and pulls the XO FULL line low. This tells the computer that the autput part is full (and nat t0 send any more dsta yet) and tells the other end of the intertace that there is fresh data to be had, When the ether end resds the data, it will pulse the acknow- Jeage ine XO_ACK, winich resets the flip-top and razats XO FULL high inactive) again, This tells the computer that it can send another byte of data, The input interface performs the other side of the same task, When data arrives from the other end vis the XI ‘ings, the XT FULL line will go lov. telling the com- puter the fresh date has atrived, When it reads it, using the RD EXTT strobe, the acknowledge XI ACK will be pulsed, eausing the flip-top at the other end 10 be cleared, and ceusing XI FULL to go high Linactive} again, Tne remaining gates are used to generate interrupts. Normaliy, the Chroma is ready to accept data from the interface, and the XI MASK line Is high (inactive, ‘This means that_an incoming byte, which is accom: panied by XT FULL going low, will cause XTINT to go low, interrupting the main computer, The only time the computer activates XT MASK to prevent input interrupts is during auto-tune and cassette operations, fof if the device at the other end of the interface is sending data fester then the Chroma can process it, Normally, the Chroma has no deta to transmit, and if it 60es, the interface is usually ready for it, 3s signi- fied by a high (inactive) XO FULL. 4, however, the Chroma has data to send and the output port is stil full from the previous data transfer, the Chroma will ‘only wait a short amount of time before it decides thas better things to do than ws't around, When this brappens, the Chroma will stash the byte of date in a 2 3FIFO (frst in first out) queue in its memory and set XO MASK nigh (inactive, thus unmasking output port interrupts. The output port interrupt XO INT} ‘occurs whenever the device at the other end of the interface gets sround to reading the deta off the interface and sonding back an XO-ACK pulse, Then ‘the Chroma will take time out from whatever it is doing to pull a byte from the end of the FIFO queue and output it. Only when the queue is empty does the main computer_mask output interrupts egain. by setting XO MASK low (active), 4, TIMER (shoot 1) “The Chroma usas a timer implemented with TTL MSI {mediurmscate integration) parts, as there are no LSI Hlarge-scale integration} time: chips available that perform the specific functions neeced. The timer con: sists mainly of a 16 bit resettable counter cunning at 2MHz (244 and 245), a 16 bit latch (246 and 247} and a status flio-flop (250C and Z51B). The rest of, the sireuit simply connects these basic slements to various signals, The timer has five operational modes that the Chroma uses under differant circumstances. The timer mode is set, and the timer’s operation is started, by verting the appropriate number to the timer mode latch (242), The modes, as raflected in 2 binary numer that appears on pins 7, 14 and 2 of 242, are as fotiows: 0, 1024us mode - used to regulate the spved ‘of the main software loop during normal ‘operation 1. Tape mode ~ used to messure the period of the signal received from the cassette during LOAD ONE and LOAD ALL opere ‘iors, Synth mode ~ used to measure the period of the synthesizer signsl during auto-tune. 3. Synth/64 made ~ used to measure the accu: mulated period of 64 cycles of a high fre ‘quency during auto-tune. 4. 416us mode ~ used to regulate the feequen: cy of the cassette signals generated during SAVE ONE and SAVE ALL operations. Each mode shares the same timing resources: a re- settable counter, a teteh, and a status flipciop, What dliffers is how they are connected together, 0: 1024us MODE This mode is used to regulate the speed that the Chroma cepeats its calculations for each synthesizer ‘channel, If the currently selacted program contains little modulation, the amount of time the computer will take to compute each sample of the control signals may only be a few hundred microseconds, Ina very complox program, the computing time is ‘much longer, although it doesn’t often got any longer 2-4 ‘shan a millisecond. When the computer begins the ca: culations, it sets the timer mode to zero. The wri pulse, WA THOD, also resets the counter to zero throush 250 and sets the flip-flop not ready (TROY high}, The timer is designad so that the current count will be latched and the counter reset whenever a negative pulse comes out of either data selector [243A 7 2438}. In made 0, this oceurs when the counter eaches 2 count of 2048 and 2466 goes low. The falling edge of this signal is differentiated by RO@, R6E and C18 into a very narrow pulse (about S0ns) which is routed througn data selector 2438, When the computer has Finished its caleulations for a particus Jar synthesizer channel, it pails TROY until it goes active (low), signifying thet the 1024us time has expired 1: TAPE MODE This meda is used during cassotte load operations to measure the signal recoived from the cassette, ‘The cassette uses a simple FM (frequency mod: ulation) scheme operating at 1200 baud {bits per second]. A 1 bit is represented by a full cycle of 1200 HZ and a 0 bit is represented by a half cycle of 600 HZ, Thus, a 1 bit is ceceived as two 41Bus Periods between ‘ero-crossings and a 0 bit is received as a single 833u: poriod between 22r0- crossings. The tape signa) is presented to the timer ‘two signals, ane being the invarsion of the other, Each signal is connected to a differentiating network 20 generate @ tiny negativegoing pulse on the fall Cf the signal, Since the two signals are out of ahase, 4 pulse js generated on one edge by one RC network and on the other edge by the other RC network, “The data selectors route these pulses into the timer where they cause the current count 10 be [stched and the counter to be resut, Whon the computer Sonses thet the timer is thus ready_(TRDY low), it reads the two-byte_time value (AD TIME ond RD TIME+1), The RD TIME strobe automatically sets the timer not ready again (via 250 pin 10} even while the next time poriod is being measurad The lefimost bit of the counter (245 pin 9) is feo through its own differentiating network back to the status flip-iop. This is in case the cassette for auto-tune) isn't generating any signal. When the timer overflows its maximum count of 32767 {about 16ms), this line causes the status flip-flop to be set ready and 0 to be latched as the time value, 2: SYNTH MODE ‘This mode functions similarly to the tape mode, except that the entire period of the incoming signal (in this ease, from a synthesizer oscillstor fF filter) is maasured, instead of the time between successive zero-crossings. In other words, the timer ‘eed only be latched and rese: an falling edges of the incoming signal, Therefore, onty one phase of the signal is used. Data selector 243A selects the dif ferentiated falling edgo of the signal. The auto-tune routine first selects this mode {which always setsthe timer not ready) and waits for it to become reody. Meanwhile, It refreshes ll the sample-and: holds on the synthesizer channels, When the timer becomes ready, it reads in the two-byto value, If the valuo Is 6, it assumes that the channel isn't functioning properly and that the timer overflowed. If the value is non-zero, the channel is probably making sounds but the reading still isn’t valid, as it isn't ref erenced to anything. However, reading the tine value sets the timer not ready again, 2, vvithout reseting the timer mode, the auto-tune waits 8 second ‘ime for the timer to become ready. When it’s ready this time, the reading vill scourately reflect the amount of elapsed time since the previous reding 3: SYNTH/64 MODE ‘This mode Is exactly like the grevious mode, except ‘that the signal whose period is being measured comes trom a six stage binary counter (Z11}_ This counter functions as @ prescaler Tor measuring high frequencies produced by the synthesizer channels during auto- tune, 4: 416us MODE This made functions exactly like the 1024us mode with one difference. Since the mace number is 100 in binary {a5 compared to 000 for the 1024us mode), the line from Z42 pin 7 10 Z51 pin 13 1s high in this mode, The fourinput NAND gate (251A), when thus enabled, produces negative-going signal when the count reaches @ count of 832. This is routed ‘through date selector 243A to set the timer ready. During cassetto saves, the computer waits for the ‘Timer to be ready, performs the necessary ser‘al output, and then reads the timer (to set it net ready without resetting the counter). Thus, the serial output occurs at a 2400H2 rate. To output a 1 bit, the computer outputs 2 consecutive transitions, To output a O bit, the computer leaves out the first transition, generating half cycle at half the froquancy. 5. A/D CONVERTER (sheet 2) The snalog to distal converter is responsible for messuring the physical position of the two levers, ‘wo variable positions, and the TUNE and PA: FAMETER CONTROL sliders on the panel. It is also wired up to messure the voltage from the pressure sensor assembly or from the CMOS RAM. battery. The circuit consists mainly of an ADC 0809 converter chip, which is a CMOS device that ‘operates on a single ‘SV supply. It includes an on- board Binput multiplexer for selecting one ot eight ‘analog voltages, an 8-bit D/A converter and suc. cessive approximation register, The computer selects, @ voltage to be measured by writing 2 number to the AID converter (WR ADCO is the strove). This activates the ALE input on the chip which causes ‘the channel select number to be latched. The same strobe also activates the start conversion (SC) input to the chip. In order to allow the analog signal time to settle internaliy, the computer repeats the strobe 2.5us later, just to make sure, Then the com: puter goes off and performs other functions “hile the converter converts the voltage {which must be between 0 and $ volts) to 3 number between O and 255, This takes about 180us, The computer ntually comes aack to it and reeds the converted value using the RD ADCT strobe. The inputs to the A/D converter are all buffered by op-emps. The levers produce a voltage swing that's ‘only about 0 to 2 volts, sa the lever inputs are am: plifed, The pedal inputs require @ pullup resistor, as the pedale contain nothing more that 2 goten: tiometer to ground, but these ievels need no ampli fication, However, dll these signals need to be clamped 50 thet they don't exceed SV, The transistars on the ‘op-airp outputs provide this function, as thay are powered from 5 volts wiile the op-amps are powered. from 12V. This scheme is used because the voltage would otherwise dofinitaly exceed SV. The TUNE and PARAMETER CONTROL slider inouts come fram sliders that are “hung” benween O and 6 volts, because they don’t require accurste clamping, There ere, however, diodes on the slider buffer op-amp outputs {0 protect the A/D against catastrophic op-amp failure, “The pressure input is buffered off board. The remain: Ing input, which comes from the battery, is buffered with a FETinput opamp for two reasons. First, the ‘op-smp input must rot drain the battery. Second, when the power is shut off, the inout must not pull the battery voltage down. The P-channel JFETs used in the opramp allow the Input to exceed the positive ‘all oF the device without condueting current. ZA inverts the EOC (end of conversion} signal generated by the A/D converter chip and delivers It to the other two sections of 255, shown on sheet 1 immediately above the I/O Strobe Decoder. This IC wes added following the initial pilot production run 10 provide meens for the computer to sense if an analog to digital conversion is successful. A particular ‘quirk oF the 0809 converter chip is that it occasionally doesn’t work! Since this is pretty much a random cowurrence, rarely happening for two conversions in @ row, the computer handles it by simply ignoring the bad’ conversion, Since each anaiog input is measured fifty times @ second, occasionally doing only forty-nine conversions doesn't cause any pro bles, 6. D/A CONVERTER [sheet 2) ‘The digital to anslog converter generates all the volt- ‘ges that are noaded to control the analog circuits on the synthesizer channel boards. The main DAC (224) is 8 12-bit DAC that uses a FET-input opamp for an ‘output buffer. Since ene Ieb (lesst significant bit) change corresponds to about 1.25my, it is necessary that the op-amp offset voltage be well below this level, A null trimmer is provided, and can be adjusted by putting 2 DVM (with 100uy resolution) between the two test points and adjusting for 28,With a -5 volt reference on pin 17, the range of the DAG would be 0 to +5 volts {it inverts). The refar- ence voltage can, havever, be “crimmed" under computer central by the use of the other DAC, 220, This Bit DAC has a reference of 45 volts and hence Produces an cutput of DV to BY, Op-amp Z21B and associated resistors reduce this range to approximately AAV to BV. If the Bit DAC is centered, the refer ence to the 12bit DAC will be about 47V, The ‘oscillators and filters are scaled such that each step af the 12bit DAC value corresponds to a 32nd ‘of @ semitone in pitch, which is a nice ezsy number for a computer to deal with. (Perfect semitone scales can be generated by counting with the five least Significant bits set to zero.) Howaver, no analog Circuit is perfectly accurate. In conventional analog synthesizers, trimmer potentiometers are provided to adjust the scale factor of the pitch {so that an octave is really sn octave), In the Chroma, this trimming is cone by the computer by outputting the zopropriste number to the Bbit DAC. Gt course, tuning offset can be corrected for by adding or suds twacting & constant from the aumber sent to the 12 bit DAC. ‘There is nothing fancy about the DAC circuit, The Bebit DAC uses two CMOS 4-hit latches for its data, which are written into by the comauter with the WA ADAC strobe. CMOS latches are used aucause the 7823 DAC reauires higher than TTL voltage levels, The 12-it DAC occupies two bytes in the computer's address space, The _four_mast signiticent bits are written into with the WR MDAC strobe. The remain ing bits are written into with the WR MDAC#T steabe. ‘TTL latches suffice with 7541 type DACs. 7, SWITCH/DISPLAY MATRIX {sheet 2) The 71 switches and 80 display segments on the Chroma panel are arranged in matrices, The 10 columns" of the matrix are driven by the outputs of 213, a BCD-to-decimal decoder with high-current fopen-colitetor outputs, The computer can select 2 bank of switches anda display digit by writing 2 umber into latch 217 (using the WR'SDS strobe), The computer ean then turn on any segments in the stlected digit by writing a pattern of bits to latch Z18, (using the WR SECS strobel. The two large digits (19) require che full grive capability of the decoder and fateh, but the small digits (12) require less current, (Note that the latch is Series Showtky, not LS.) ‘This is the purpose of the resistor network 214, The computer multipiexes the display every 20ms In 16 time slots (each slot being 1.25ms}, The small digits are lit in time slots 0 threugh 7, and the large digits alternate back and forth during time slots 8 through 6, ‘The computer can read the selected switch bank by reading from tristate driver 216 (usicg the RD SWB strobe). To guarantee that the switches can be resd correctly, the computer only reads the switches in the brief intervals between the illumination of each display igit, The sequence, which only takes 6 few miro: 2-6 seconds, consists of turning off the display (writing 0 40 Z15), selecting the next digit and switch bank (writing to 217), inputting the switeh bank cata (reading from 216), and turning on the next digit {writing to 718). The firmware compares each switch bank reading with 3 memory image of what the bank looked tike last time it was read, This allows the com: puter (0 detect the initio! depression of a switch Independent of haw long it is hel. 8. CASSETTE INPUT/OUTPUT {sheet 2) “The square waves generated by the computer {TAPE UT} are attenuated by R21 and R20 to a level suit able for feeding into $ microphone jack an a cheap ceassette recorder. The signal that comes beck from the earphone output of the recorder during playback is much stronger, but onty vaguely resembies the ariginal signel ond erust be squared up again. Comparator ZB performs this. Note the large amount of positive feed back necessary to clean up the signal. The D-flip-fiop (Z10A} synchronizes the signal to the 2MHz clock (sa ‘hat if will work correctly with the timer) and ro: vides the necessary complementary versions of the signal for detecting positive and negative edges, 9. CASSETTE MOTOR SENSE/CONTROL (shaet 2} ‘This circuit uses a dual opto isolator to isolate the Chroma circuitry from the voltages used to srive the cassette motor. When the MOT OUT signal is driven high, apte Z9A turns on, which, if there is eny voltage in the motor circuit, turns Q2 on, allowing the motor to run, There will be a significant drop between MOTOR+ and MOTOR-, due to the Vbe drop of O2, the diede drop of CR20, and the saturation drop af ‘the transistor in Z9A. But this voltage is what allows the other half of the circuit to sense the state of the cassette recorder controls. If the cassette is set 10 STOP (or there is no cassette connected), obviausly there will be no voltage on the MOTOR lines. Thus, opta 298 will be off, and Q3 will be off, and MOT IN will be high. If the cassatte recorder is turned on, but the Chroma’s control of the cassette (02) is off, the full motor voltage usually 6 volts or so) will appear across opto 298 and FET O10, The FET functions 25 a resistor, allowing enaugh current to flow to turn on the opto and Q3 and pull down MOT IN, but not enough for the motor to tuen, If the Chrome cam puter decides to let the cassotte run, it turns on O2, ‘but there is stil enough of a voltage drop across the circuit t0 wen en opto 298 and hold MOT IN down. This i becouse the FET acts as a norlinesr resistor, with a lower resistance at lower voltages (nearly constant current sink}. This arrangement allows the computer to sense whether the cassette controls are fon oF off, independent of whether the Chroma is allowing the cassette to actually run, Diode CR31 is there to protect against inductive kick back when the moter is turned off, Capacitor C6 is there to slow the rise of MOT IN way down, This Is necessary because a cassette recorder operated fromAC With no batteries installed usually uns its motor off unfiltered recsified AC. Were it not for C6, the MOT IN line would toggle 120 times a second, 10. LED DRIVERS (sheet 2) ‘The sixteen LEDs on the panel are driven from twa faiches (25 and 26) that can be written inte using the WR LEDS and WR LEDS'1 strobes. Using LS latches 8 current sources dieectly driving the LEDs (with ‘only the internal latch resistance to limit the current) Vieldee a reasonable brightness, without wasting board spsce for 16 resistors. All blinking of the LEDs is performed by the computer, 5 is only strobed when 4 panel switch is pressed, Z6 is strobed several tines a sacond, 95 it drives the LEDs that must flash. 11. TAPPER DAIVER (shoot 1) Since membrane switches provide no tactile feedback, 2 solengid tapper is provided in the Chroma. Whenever tha WR TAP strobe is actwated, flip-flop Z38A is set, ‘This turns on Q1 and gpplios @ hefty current feom the unregulated power supply to the solenoid. Rather then have the computer turn the transistor off 20ms later (that's about 3 months in computer time}, a feed back network is provided that makes the flin-flo unotion as 2 crude one-shot. RB2 provides the nega- tive feedback that ultimately resets the flip-flop. Capacitor C20 provides the time constant. And connecting the other side of C20 to the opposite ‘output of the filp-flop {rather then te ground) provides, some positive feedback to make sure that the switching is clean. Diode CR23 protects against inductive ‘kickback when the solenoid shuts off Otwiously, there Is no direct connection between the panel ewitehes and the tapper circuit. Instead, pressing 2 switen eauses the computer to exccute a certain dart fof its program that handles the appropriate switey function. One of the instructions in each switen hrandler is an instruction that writes 10 the memory lecation_that corresponds to the tapper, ectivating the WH TAP strobe, The tapper can be cissbled from the panel, but this is not done elecircally. Rather, the location ‘hat the computer enites to is changed so ‘that the taper won't be triggered. 12. MISCELLANEOUS INPUT/OUTPUT (sheet 1) ‘There is @ G-bit output port (230) that is strobed by ‘WH PRES, This Istcn is used to select one of the 64 keys on the keyboard and deliver the voltage from its pressure sensor to the PRESS input on the A/D con: varter, There is also an outout port strobes by WA FSCO that contains miscellaneous output bits. Latch 229 is activated by this steobe, and drives the three interrupt masks, tho cassetie date output and the arselte mater control. The same strobe also goes to the Channel Mother Board, where two more bits are latched from the BO and 61 data bus bits. When the computer strobes it reads in eight mis callaneous input bits, including the state of the external computer interface ports, the timer, the cassette motor sense, the TOGK switch on the ret ‘panel, and the thrae footsnitches, There ave also three other strobes_thst_go to the Channel Mother Booed via Z41. The WA SHA strobe ‘s used to write 3 samplo-and:hold addoss into a latch. The WR SYND strobe is used to write 6 bits of data dostined for one fof the synthesizer channels into a bu‘fer (atch. The WR SYNA sirobe is used to transfer the contents of the buffer latch into any of the 24 latches on the individual chennel boards. DUAL CHANNEL BOARD CIRCUIT DESCRIPTION Each Dus! Channel Board in the Chroma consists of ‘he following sections, as outlived in the schematic: Sample and hold bank Dts latches Oscillators (A and 8) Filters (A and 8 Amplifiers (A and 8) Each ssetion will be covered individually inthe follow: ing descriptions, except that the B channel circuits wilt only be described as they differ from the A channet, 1. SAMPLE AND HOLO BANK {sheet 2) This circuit consists of eight sample and holds and their aesociated switching logic, These samale and holds each employ two holding espacitors separated by 2 rasistor, allowing the output voltage produced to be filtered, avoiding sudden step changes, A particular ‘output is set ta 2 voltage by applying the desired volt age to the DAC input, putting the appropriste sample ‘and hold_adidrass code on the three SHA lines, and bringing SHEN (ow to enable the selected sample and hold, This causes one of the channels in 219, 3 4061 CMOS switch, to turn on, connecting the DAC voltage to one of the 0,033uf eapecitors. This voltage doesn’t immediately appear at the corresponding opamp ‘output, as it must first go through a iow-pass network consisting of @ IM resistor anc O.0068ut capacitor. Tris slows down the sudden transition that could be ‘caused if the current sample is different from the pre vious sample apalied to this channel, The Chroma computer enables each sample and hold sbout 50 times a second, The filtration due to the resistor and s2cond capacitor in each channel allows the Chroma to generate rapid portamentos snd envelopas without the listener cing able to hesr that they are comprised only of a few disorete steps. It is often necessary for the computer to change particular voltage instantly. This is used for pitch changes without portamento, envelopes with sharp attacks, and trils, The computer can cause any indi- vidual ‘sample and hold to produce a sudden, unfilter 2d, chenge in output voltage by merely bringing the FAST line low during the sample period. _Z25B func- tions, in this circuit, like an OR gate: if FAST is low and SHEN is low, 20's enable line will also be low. Tous, there will be a switch turned on in both Z19 and in 220, connecting the DAC voltage to both capecitors 2-7Jn the selected sample and hold. Since beth eapa tors are thus charged to the desired voltage, there will be no filtering effect on the control signal The computer leaves each sample and hold selected vihile it calculates the voltage level to be sent 10 the next sample and hold, This allows somewnere between 180us and 600us for each sample and hole to acquire the DAC voltage, There are G4 sample and holds in the Chroma, and they are sampled in order of board umber, board 0 first, and, on each boerd, in the forder that they appear in the schematic, producing the PITCH A signal first and the VOLUME 8 signal last 2. DATA LATCHES There is 9 6:bit data “bus” that connects to all the Dual Channel Boards, This bus is not the same as the main system data bus, as tre bus is too noisy to bring up onto the channel boards. This 6-bit bus is loaded with data by the computer whenever it wants to set any of the data latches on any channel board. Once the data is set up, either the STBO, STB1 or STB? line willbe given 2 pulse, writing into the approoriate latch. ‘Most of the latch bits connect directly t0 various places within the channel circuits, The two leftmost bits are decodes to produce_an_gctive-low level on_one (or nore} of three lines, SYNC, RING MOD or FILT FM. ‘The SYNC, RING MOD, FILT FM and PATCH bits are updated whenever the Patch parameter is changes. ‘The OUT bits are updated whenever the Output Select parameter is changed, The WAVE, MODE and RES bits similarly correspond to the Weve Shave, Filter LP/HP and Resonance parameters, Ifthe Patch Parameter is 0 in the program that is controiling @ Particular board, the 0 and 1 latches (228 and 227) will both be controlled by the same “A” parameters If the Patch parameter is non-zero, the A and B ‘channels are controlled independently. 3, OSCILLATORS (sheet 1) EXPO CONVERTER. 21 and Z4, and associated Rs and Cs form two identical garden-variety expo con- verters. They accept tinear control voltages (from the PITCH A and B sample and holds) in the range of 0 10 5 volts and produce an exponentially controlled current canging from 120uA down to about 100nA. ‘These circuits have negative control, meaning that the highest oscilistor pitch is attained at the lowest control voltage, The sealing is euch that the ouzput current (21-1 or Z1-11) changes by a factor of 2 (and the pitch changes by an octave) 35 the control voltage changes by slightly less than 0.6 volts. Thus, the ‘oscillator has a typical range of somewhat more than ten octaves CHARGE PUMP OSCILLATOR. The design of the ‘oscillators themselves is unconventional in the domain of electronic music, but have been around in the field of data acquisition for years. They are called “charge ump vottage-to-frequency” converters. The basic 2-8 oscillating element is 8 4151. It consists of @ compare: tor, a one-shot, and a switehad precision current souree. Basically, the eusrent from the expo converter is integrated by opamp 25 and capacitor C3 (or Ca), causing the op-amp output voltage to ramp upwards at a rate proportional to the contrat current, Pins 6 and 7 an the 4152 ace the comparator inputs, Wher the op-amp outout, which drives pin 7, reaches 5 ‘olts, the voltage on pia 8, the one-shot inside the 4161 is triggered. So far this is just like any other synthesizer oscillator; but most synthesizer oscitlators use the one-shot output to essentially short circuit the integrating capacitor, forcing the output back to zero. Ideally, this discharge, or retrace, should happen instantly, as it is not “taken into secount” by the circuit in determining the rate of osciliation. Untor- tunately, it is never instentaneous, and at high fe ‘quencies this ratrace time can appreciabiy lengthen each cycle, causing the characteristic “high-end droop" that most synthesizer oxcllators have compensating adjustments for, A charye pume oscillator doos not use the one-shot {0 force the integrating capacitor back to zero volts, but rather uses the one-shot to pump a fixed quantum cf charge into the capécitor in the opposite direction than the steady current from the expo converter, ‘This fixed charge is created by turning on a constant current source for & fixed ammount of time, In this Circuit, the one-shot time is quite long compared to ‘other synthesizer oscillator retrace circuits, about 20us. “This is acceptable because the retrace time is inherently perfectly compensated for. At low frequencies, the charge purep (which, by the wey, comes out pin'T of ‘the 4051) is adjusted by means of a trim to kick the integrating capacitor voltage back to exactly zero volts. At high frequencies, this charge is “working against” higher currents from the expo converter, and 0 the retrace, which is ellowed the same amaunt of ime, doesn’t kick the capacitor voltage all the way ‘s0ck to ground. This compensates for the extra time spent retracing, ‘The linearity of this ircuit can be easily proven by reasoning that the total current fram the expo ‘converter during each cycle must exactly counter- balance the total current from the charge pump. during each eycle, If it didn’t, the integration in each cycle would nat wind up at the seme 6 valt level. Thus, the following identity hotds Since the frequency is the reciprocal of time: 1 1 t "pump x * pump Teycie In other words, tis proportional 10 lexgo, LOOK ‘at it on an oscilloscope if you can’t vsuslize it, The output of the oscillator on Z5 pin 1 {or pin 7) isa stutooth whose relrace ig rather slow compared to ‘most synthesizer oscillators, Pin 3 on the 4161 is an‘open collector thet turns on during this retrace period, ‘Thus the voltage on the right side of R17 (or RIB} is 2 sawtooth with a very fast retrece SYNC CIRCUIT The B oscillator differs from the A in that itis provided with a method for hard synchroniza tion. The theae discrete transistors, Q1, 2 and 3 pro- vide this function. Whenever the A oscilator's cycle completes, its sawtooth output snaps from & volts back to ground, This sudden transition is cifferent! ated by C19 and R79 and fed as a very narrow pulse through Q1 to the base of O3. When this occurs, 03 shorts aut integrating capacitor C4, resetting oscillator B to the start af lis ayele, If, however, the SYNC con: trol line from the data latch is high, 02 will be satura: tod on, Its collector will be at about 0,7 volts, and the tiny pulse will be absoried without passing through Q1. Resistor R81 keeps Q3 solidly off except during synchronizing pulses. PULSE COMPARATOR Resistors R19 for RO} and A121 tor R22) mix the sawtooth produced by the cscillator with the pulse width contro! voltage from WIDTH A {or B} sample and hold, This signal is compared t0 a fixed 25V reference by comparator 26. (The feedback components are simply to prevent oscillations at the transition point.) Since the saw: tooth and the pulse width control veltage are both 0 10 5 volt signals, the input to the comparator on pin 2 (er 6) will be a 2.5Vpp sawtooth whose average loval can be adjusted from 1.25V to 3.78V, Thus, the comparator output will be 2 pulse whose duty cycle is varisbie across the entire cange trom 0 to 100%, WAVE SHAPE SELECTOR CMOS switch 28 (or 20} selects one of four wave shapes. The upper two are, obviously, the pink and white noise signals that are produced on the Channel Mother Board, The lower ‘wo inputs select oscillator signals. Pin § is provided with a combination of the pulse signa, the pulse width control voltage and a fixed bias that yields a pulse signal that has no DC component. As the pulse wicth Js variod, the pulse wid:h control voltage raises and lowers the signal keeping its average DC level at zero volts. Pin 1 of the CMOS switch gets a combinaton of the pulke, the pulse width control voltage, a fixed bias and the sewtooth. This produces a mix that is indistin- Quishable from two sawtooth, If you can't visualize this, set the Weve Shape parameter (No. 33) to 0 and look at the output of 210 while varying the Width parameter (No. 34). This signal is also DC free, The A oscillator differs from the 8 in that its output signal ‘can be replaced with a ring modulator signal when the RING MOD line from the data Iateh is low, The four NAND gates perform a digital exclusive-or function on ‘he pulse signals from the two oscillators. This pro: ‘duces 3 perfect ring mod signal if the inputs are square ‘waves, and a reasonable ring mod effect if the inputs aren't square, 210 buffers whatever wave shapes are selected, Note: the signals at the inputs to the CMOS switches disoppear whan you select them, because they are connected through the switch to ‘the summing Junction of 210, In other words, the CMOS switches are used as current switches. FILTERS, ‘The filters are implemented using Doug Curtis’ dual state-veriable filter chips, A compiete analysis of these cchigs will not be attempted here, but this is basically What occurs in the circuit, 211 ig @ CMOS switch, cornmon to both filters, that determines, under control ‘of the Patch parmeter, what signals foud the filters, These switches operate in the current mode, as they feed the singel into a 10 ahm resistor RB7 for RE8I, Thus the signal that appears on pin 3 (or 13} of the GMOS switch is very small, typically SOMV pp, The filter chip requiras signols that small to avoid distar tion, The output amplifier, which brings the signal level back up to normat, consists of op-emn 216 and sociated rasistors, This circuit provides differential ain, and blocking capacitor C13 (or C14) assures that the offset voltages in the filter chip are not amplified as well. The filter is basically connected as 2 high-pass filter, where the signal is spolied to the lower end of 9 (oF C10} and taken off the upper end of the same capacitor. The filter chip, in this case, looks like a shunt inductance and resistance to ground, If CMOS switch Z128 (or 212C} is switched to yrourd, this is al the cirauit does, and the output buffer provides single tended qain, If the switch Is switched the other way, ‘the input signal is delivered to the IN 2 pin on the chip, ‘hich is & band-pass input, and to the inverting input of the cutout buffer, The OUT 1 line thus produces 4 combination of band-pass and hich-pass response which, when combined out of phase with the input siunal, yields a low-pass response, Remember, low: pass + band-pass + high-pass = everything, This con- figuration was chosen because it has few parts, and because it can perform switching bewaen the’ low: ess and high-pass function without generating 2 DC twansient, The three feedback resistors, R69, 71 and 73 for R70, 72 and 74) provide a tiny amount of positive feedback around the filter that, when the resonance i raised far enough, causes the flter to oscillate, The parallel NPN/PNP transistors counter this effect with vegative foadback when the output signal reaches about +3V, ‘This prevents the filter from hard clipping at high resonance levels, providing instead 2 soft “rounded” cortion. ‘Tha F terminais on the filter chip are the inputs to the comechip expo converters that contro! the tuning of the filter. Like the oscillator expo converters, these pro- vide negative contral, Resistors RS and RAS for RE and R46) scale these inputs at slightly under 0.5V/ ‘octave, just ike the oscillator, The O terminals provide negative exporantial control of the resenance of the filters. The three resonance control bits from the data fatch for each channel are used to encode the setting ‘of the Resonanos parameter. When the parameter is 6, the three bits areal! logie 1 15 volts), and when the parameter is 7, the thrae bits are all at zero. Resistors R47, 49 and 61 tor RAB, 50 and 52] combine these in 4 binary weighted manner, The purpose of the tran. sistor is to provide a resonance boost when the para meter is set to 7. Normally (that Is, when the filter 2-8Jan't being used as an oscillator) at least one of the resonance control bits is high. This urns the transistor fon hard, so that the current that flows inte the 100 ‘ohm summing resistor R63 (or REA) is thus equal 10 ‘the sum of the control currents fed into the base of the tansistor and the currant through the 23K resistor (on the collector. As the resonance parameter is in creased, less current flows through the bage, but the transistor remains saturated. When the resonence orameter makes the final transition from 6 to 7 and all three bits go low, the transistor shuts off and the current through the ‘emmitter drone sharply to zero, causing 2 targe increase in Q, This guarantees that all iters will oslllate when set to 7, But not when set to 6. The aided 33K resistor (R115 or R116} causes the resonance to be increased slightly at higher frequencies, to overcome a slight reluctance to oscillate Opamp 229A isn't really part of the fitter at all, and shouid have been drawn someplace ele. It's a current inverter. Op-smp 2298 is connected in the rather un conventional “loft-facing ground buffer" configuration. Unfortunately, the theory behind this circuit is beyond the scope of this document. Suffice to eay that it works perfectly, 5. AMPLIFIERS. CMOS switch 215 (common to both amplifiers) selects 8 signal to be controlled and feeds it, 25 a current, inte the low impedance Isumming junction) input of tho VCA chip Z16. The output of this chip Is slo a current {The output stage of the chip is similar to that fof ¢ 3080 OTA chip). The control voltage from the VOLUME A for 8) sample and hold is atienvated 10 the required Q t@ 3V level and applied to the chip's linear control input, The 0.1uf capacitor on this input slows the control voltage chsnges down just enough to make a sharp attack or release sound like @ soft 000. and not a sharp tick, The A amplifier’s output current is routed t0 one of the four summing busses in the Channel Mother Board by 217. The & amnlifie’s ‘output current is routed to one of three places. IF the Patch parameter selects filter FM, this signal ‘current is fed into the frequency contro! input of the A Filter, If the Patch parameter selects the series or por alle! filter configuration without filter FM, the signal current is fed back and mixed with the A oscillator Otherwise, the signal current is mixed into the ouput, The rest of the signal routing an board is tedious but simpte and is easily taced with the help of the Patch parameter diagrams in the Chroma Programming Marval CHANNEL MOTHER BOARD CIRCUIT DESCRIPTION ‘The Channal Mother Board consists of the following circuits, as outlined on the schematic: 1. Sample and hold decoder 2 Datalatch 3, Data strobe decader 4. Oscillator and output mute latch 5. Noise generetor = 10 2 8. Ourpur suring amps 7. Zero crossing detector Each section will be covered individually in the follow. ing deseriptions. 1. SAMPLE AND HOLD DECODER This circuit is usad to selectively enable one of che 64 sample and held circuits on the channel boards, Z1 and 22 form an Bbit latch that can be written to by the main computer using strobe WA'SHA. The low order six bits address the sempl¢ and told, bit 6 is an active low enable signal, and bit 7 is the active low “fast signal described in the Dual Channel Board Circuit Description. The upger half of the sample and hold address ffram data bus bits B3, 84 and BB) are decoded by Z7A, Z7B ancl 28, These three bits ap- pear on 22-2, 21-10 and Z1-7, and the last bit also appears compleimanted on 27-6. The two OR gatas and the two oneof-four decoders function as 2 one-of ‘eight decorder, enabled by 21-15, The three low order bits of the sample and hold address (fram 22-10, -7 ‘and-15) are decoded on the channel boars themcelves, ‘The firmware always manipulates tho sample and hold latch in the same three steps. First, it turns off the current sampie and hold by writing the samole and hholel number to this port with bit 6 {the enable bit) ins active (high). Second, it selects the next sample and hold by writing the new sample and hold nuinber 10 this port with ait 6 stil high. The “fast” bit, bit 7, will be sat as necessary and the DAC output voltage will be changes ar this time. Third, the sample anc hold is enabled by repeating the last operation with Bit 6 low. This entire sequence takes approximately 10us and eliminates any possible glitches that might distur’ other sample and holds, Each sample and hold is left selected for at least 100us \while the computer does other work. Thus, the enable bit, 21-15 will be active (low) most of the time, Each of the sample and hold address bits will look remotely like @ square wave, as each sample and hold is address fed in a squence, from 0 to 63, This sequence is dis: turbed every time & new note is struck. 2. DATALATCH “The main computer sends digtal control signals to each board in 9 cwo-step process. First_a 6-0it word is writ ten to the data latch using strobe WR SYND. Second, the data strobe decoder (explained below) is used to ‘transfer the data to the desired latch on any of the cchennel boards, 3. DATA STROBE DECORDER Once a word is st up in the data latch, it can be copied. into any of the latches on the individual channel bostds by writing the number of the latch using the WR SYNA strobe. Each channai board has three lateh- 8, ond therefore has three strobes for triggering them, ‘A fourth strobe to each bosrd is provided for future expansign, Thus, there are 32 total strobes that must bbe individually controllable by the main computer Latch Z5 and the right half of flip-flop 24 form abit{atch to which can bo wéritton 2 five bit address code. ‘The left side of flip-flop 24 i configured as a crude ‘one-shot by connecting its output through @ lag net work back into its reset input. Whenever one of the channel board latches is to be strobed, the WI'SYNA strobe (wihich ig en active low pulse} will trigger this ‘one-shot on its trailing frising} edge. 27C, 270 and 22 form a oneoFeight decoder that routes this one-shot pulse according 10 the lowest 3 bits in the latch num ber. (Those 3 bits come from data bus bits BO, 81 and B82, and appear on 25-15, 25-2 and 24-1, and the last bit also appears inverted on 24-2), Each of the eight lines coming out of decoder 20 corresponds to one of the dual channel boards, The strobe pulse is further routed 10 one of the four strobe lines on the selected channel board by one of the one-offour decoders 220A through 2138. (The hits that select which of the four strobes to activate are the upper wo bits ia the latch number, These bits come from data bus bits 83 ond B4 and appear on 25-10 and Z6-7.) 4. OSCILLATOR AND OUTPUT MUTE LATCH Whenever the main computer dees a write operation Using the WR MSCO strobe, the upper six bits of the data bus ara latched on the I/O board and the tower two bits of the data bus are latched by 25 on this board. All the bits in this “port” are miscellaneous in nature, The two that appear here are mute bits The low order bit, which appears on Z6 pin 13 (and inverted on 26 pin 12h is used as an output mute. The next bit, which appears on Z6 pin 1, is used as an oscillator mute bit. It disables the audio input to each filter on the ual Channel Soares. 5. NOISE GENERATOR ‘Tao cigital noise generator chips, 214 and 216, are employed in this circuit. Each chip has its own on-chip lock and a shiftregister type noise generator that ginerates 3 pseudo-random sequence of Os and 1s at 12 volt logic levels, Since the two chips run asynchron- ously, tha pseudo-randomness is turned into something uly randam and free of repetition. By itself, a ran- dom stream of bits sounds like white noise. This signal is buffered and attenuated and dolivared to J, pin 6 on each Dual Channel Board. The roise genera tor output is also filzered by 2 network that approxi mates 2 Sib per octave rolloff, yielding pink noise. This signal Is buffered snd delivered to JB pin 8 on ‘each Dual Channel Board. 6 OUTPUT SUMMING AMPS The signa) currents from each of the Dual Channel Boards are mixed using four summing busses, SUM 0 through SUM 3, CMOS switches 216 and Z17 route these currents into summing amps 21B and 219, for divert them, under contral of the output mute bit. The voltage outputs are roughly line level signals, and are sent to the EQ Board, 7. ZERO CROSSING DETECTOR When the outputs are mutes, as during autotune, the signal current from SUM 0 ‘summing bus is fed into comparator 220. This comparator “squares up" the ignal and feuds it to the I/O Bosed for measurement, During fitter tuning, the signal being processed is 2 sine wave, and so some positive feedback is utilized (Ghrough R11) to keep the comparator from oscils ting at the signat slowly passes through zero, The two diodes clemp the input to the comparator. The nega: tive clamp uses @ germanium diode for its lower forward drop. The intent here is to protect Z16 pin 4 from excessive voltages, POWER SUPPLY ‘The power supply consists of the following circuits: Primary and transformer Analog SV regulator Analog 12V rogulator Analog -12V «egulator Digital BV regulator Digital SV prevegulator Reset cirucit| Each will be covered indivie descriptions. in the following 1, PRIMARY AND TRANSFORMER ‘The power transformer in the Chrama is a dual primary design. The DPDT line voltage selection switch $1 Is used {© covnect the two identical primaries in paral- lel for operation at 120VAC, or in series for opera tion at 220VAC, RI and R2 are metal oxide varistors Which act as e low impedance clamp at voltages above those expected from the power line. This prevents high voltage transients from entering the unit. The rear panel power connector includes an RFI filter 10 further isolate the inside and outside of the instrument from each other. ‘The transformer has only one secondary winding with 2 grounded center tap. All voltages in the system ultimately come from one of three fullswave rect: fiers connected to this winding. CR1 and 2 (the large ‘ectifiers on the board) provide power to the digital preregulator and regulator. CRG and 7 provide power to the positive analog regulators. CRB and 9 power the negative anelog regulator, 2. ANALOG SV REGULATOR This regulator takes its input from filter capacitor C7, which has somewhere between 16 and 33 volts ‘on'it, and generates 2 very stable, bet not particularly Powerful, 5 volt reference. Op-amp Z1A and transis- tor O8 make up the sctive part of the ragulator. Resistor £19 sets the current limit at roughly 250m. 23, though it behaves tike @ zener diode, is actuslly an IC reference that has a very low dynamic impedance and temperature coefficient, It establishes pin 2 of the opamp at 1.2 volts below the output voltage of the circuit. 17 and R20 control the gain of the ci cenit, and R21 and trimmer R22 allow the ouput to be set at exactly 5.000. R42 is only there to make sure that the circuit starts up correctly 2-13. ANALOG 12V REGULATOR ‘aking its input from the same filter capacitor, this icuit amplifies the SV reference and produces 12¥ at up to about 700mA. Op-amp Z2A and transistor Q7 make up the active part of the regulator, R23 and R24 set the gain at 12/5, and OB, R25 and R26 pro: vide current limiting 4. ANALOG -12V REGULATOR ‘This circuit tekes its input from filter capacitor C11 and its reference from the output of the 12V reguis: tor. Op-amp 228 is connucted as a unity gsin inverting amplifior (R27 and A2B set the goin). Its output, which can only go 35 low 35 ground, drives cascode transistor Q11, which in turn drives pass transistor 09, The current limiting circuit is slightly “upside-down due to the fact that the pass transistor inverts. R31 seis the limit at about 700mA, and when this is excee fed current is divurtad from the input of the cascode Wensistor. Diode CR13 is only there #0 protect the input of the op-amp from negative voltages. 5. DIGITAL BV REGULATOR ‘This circuit, based around opamp Z1B and power MOSFET 04, acts as a voltege follower, boosting the available current to several amps. A MOSFET vas ‘chosen because of ts high input impedance and its ability £0 operate with only a few tenths of a volt across it, At high currents, the resistor in a conven: tional current limiting circuit begins to dissipate appre- ciable currant becauso it can have up to 0,7V across it. This circuit uses differentia! sonsing to reduce the voltage across sense rasistor RV2, The 12K and 120 ‘ohm rsistors (R13 anc AIS} are driven with SV be- ‘ween them, while the 310 ohm and 6.8 ohm resis: tors (RIT and R14) see between them whatever the current sensing voltage is. This extra bias means that the current sense resistor only need have about a quarter of a volt across it to start current limiting, ‘The difference in ratio beween R13/R11 and R15/ R14 results in a foldback limiting charscteristic as well. 6. DIGITAL SV PREREGULATOR ‘The SV. regulator takes its input from the large filter capacitor C3, To keep the dissipation in the regulator down, this voltage is preregulated to about 6V. In fact, there is a crowbar-type overvoltage protector (ZA) mounted right across the fitter capscitor terminals that makes sure this vattage doesn’t get much highar than 7V, The preregulator takes its input trom the secondary through CRI and CR2, but no filtering is Performed prior to the prereguistor. Instead, the preregulator functions 2s a switch that turns on and off at the 120Hz rectified ine vottage rate, ‘The switch consists of power transistor Q1 {the TO-3 package) driven by power MOSFET Q2. This combina- tion was chosen beacuse of its low on voltage {not much more than a volt) at high currents (20A pulses 2-12 are found in this circuit), The gate of the MOSFET is normally pulled up to the unregulated plus suppty voltage by RG (through Ra}, meaning that the switch is cormally on. As the power line voltage rises during any particular half-eyete, 9 point is reached where ‘the switch becomes forward biased. At this poi fitter capacitor C3 starts to charge, IF you look at the junction of CRI and CR2 with a scope, you should see the voltage rising to about 7 and then leveling off when hit with the heavy load of the filter capacitor [As soon as the filter capacitor is charged sufficiently 10 run the SV regulator, the switch is turned off This appears 25 the sudden vise in the rectifier output voltage. Thus, the rectifier outout looks like a conven: jonat fullwave rectifed sine wave with a triangular ‘ite taken out of it during its rise by the temporary connection to the large filter capacitor, When the switch turns off, the transformer secondary voltage continues on up in voltage to where it charges the ‘analog supply filter capacitors, C7 and C11, The rest of the preregulator cireutt is involved with determining whan in each cycle to turn off the switeh, Transistor O3 senses (through A3 and R7} when the ‘ectifier voltage gets a few volts above the final output voltage, When it does, it starts to turn off the switch circuit. The sudden removal of the load causes the voltage being sensed to rise sharply. Thus there Is positive feedback in the citcuit, assuring that the switching wit! occur quickly. The emitter of the sense transistor 03 is connected to the top of the currant sensing resistor A'12 and not to the output in erder 10 allow for its voltage drop, Resistor 97 is connected 10 the bottom of the currant sense resistor, causing ‘he drop across the resistor to be overcompensated for, which allows for the rasistance of, and voltage drop In, pass transistor Q4 at higher output currents, The trimmer R46 allows the trip point of this circuit to be adjusted, Note that the preregulator is referenced 10 the digital ‘SV output, and not to some absolute reference, Under Normal operation, the prerequlater will be putting out about BVDC, with 6 volts of ripple, and the regutator will be cutting thet down to a smooth SV. If the out put is shorted, the preregulator voltage wilh automatic ally come down to about 1V, maintzining constant drop across psss transistor Od, This keeps the power dissipation down under shortcireuit conditions 7. RESET CIRCUIT In_any. computer system, there is a need for @ system RESET signat that remains active until the powor supply Is fully stabilized and the processor clock has run for a bit, This is usually attained with a simple RC network. But in a computer system chat employs non-volatile RAM, the RESET signal must also be asorted agein before the supply drops out of regula- tion when the power is shut off. If this requirement, isn’t met, the computer can produce sourious signals When the supaly falls below 4,78V, damaging the in- tegrity of its own memory. In order to sense power failure “before it happens,” itis necessary to create afiltered version of she rectified line voltage that has a faster “droop” than that of the main filter capacitor, €3. Capacitor C10 performs this function. C10 ‘Takes its charge from the same rectifiers as the analog positive supplies, but is isolated from filter capacitor G7 by the extra diode, CR10, C10 is pulled down, ot to ground, but towaed the opposite supply by RAO (CRIG prevents this voltage from over actually going negative), Thus, the voltage on C10 will be a crude, rounded, sawtooth at 120Hz, that charges up to 25V for 30 and then droops sharply. 39 and C12 form a low-pass filter, or would if it weren't for CRIS. During power up, C10 shows its characteristic sawtooth, and C12 shows & gradual rise in voltage towards the OC level of the sawtooth. CRIS keeps this voltage from getting any higher than the negative most oxtreme of the sawtooth, During power-down, the sawtooth stops abruptly and CR16 quickly puis the voltage on C12 beck to ground, before the supply has = chance 10 come aut of regulation, 3B couples this signal into the Schmitt tigger ciceult consisting of Q12 and Q13, This eircuTt “squares up" the very slow rise of C12's voltage during poweraup, and Its rather slow fall during power-down. Note the Positive feedback loop in this circuit. The voltage an C12 has ta rise to about SV before the cieuit switches e0, Then, the voltage on C12 has to drop to about AV before it switches off again, Zener diode CRIA ‘opens up the loop and forces RESET active if the digital SV supply (which powers this circuit) falls out of regulation, EQ BOARD The EQ Board consists of the following circuits, as outlined on the schematic: Volume and ground isolation Custom equalization Audio mixer and mute Tone controls Bolanced output amplifiers Each will 08 covered individually in the following descriotions. 1. VOLUME AND GROUND ISOLATION ‘This circuit controls the volume of the signals from the ‘quad outouts of the Channel Mother Board, The VA chips that are used ore the same as those used in the channels themselves, The input terminals look like summing junctions and are thus fed through resistors ‘The outputs are currents that are converted zo voltages by og-amps Z3 and Z4. Note that the VCA chips ere the only circuits on the board that are referenced 10 ‘the normal ground line from the power supply. Though hot shown on the schematic, this line actually comes from the Channel Mother Board along with the quad audio signals. All the remaining circuits are roferenced to the OUTPUT GND line which eames dicectly fram the rear panel. If any differential voltage exists between these two grounds, it will not affect the signal, a5 the signal is passed in the form of 8 current from the high cutout impedance of the VCAs to the low input impedance of the op-smps. ‘The control voltage inputs on the VCA chins are sll tied in parallel and driven by tho VOLUME potentio- meter RS. The contro! voltage inputs have a linear twanster function and exgect voltages from 0 to about 2 volts. RE and A? civide the slider valtoge down to this tevel, and incidentally make the apparent taper of the volume control a little more “audio” by loading down the slider when itis set near mide Note that the cassette audio signal is mixed in with the 0 channel, This allows easy cueing of tapes by ear, without having 10. unplug the varphone jzck on the cassette recorder. Note also that the VCAs are power ed from a heavily fitered 4.3V supply shown on the right side of the schematic. It is derived from the analog +6V reference to the TUNE slider, and is intended to reduce noise coupled into the VCAs. 2. CUSTOM EQUALIZATION NNo circuits are actually installed for this function, but there are solder pads on the board for possible installa- tion of fixed equalization modules in channels 1, 2 end 3. Tha quad outputs are wired up to stereo phone jacks that function as combination sandirecsive jacks. ‘The tip of each jack is drivan with the (unequalized) output signal, The ring can be used as an input to the final mono mix. If plug is not inserted into the jack, the ting i driven (via the cing shunt with the equalized output signal, Thus, using a jack a6 a sendiceceive connector esuses any internal custom EQ to he by- passed, IF the jack is left empty, the austom EQ for that channel remains in the circuit, and may be select- ed using the Output Select parameter. Channel 0 has no provision for custom EQ. 3. AUDIO MIXER AND MUTE “The quad outputs (or the signals fed in on the the four outputs jacks) are mixed in this SFET Q1 and CRY form an analog syitch that inter rupts the signal during system RESET (power-up and powerdown), R25 and R26 level shift the RESET signal, as the JFET expects a negative control voltage. C17 ig necessary to filter any computer noise from this, line 4. TONE CONTROLS This is an ordinary three-band tone control circuit. C10 and C11 “short out” the BASS control at high frequencies, allowing it to affect the response only at low frequencies. C16 "disconnects" the TREBLE ‘control fram the op-smp at low frequencies, allowing it to affect the response only at high frequencies, The MIDDLE control uses @ combination of the two effects, 135. BALANCED OUTPUTS These two circuits are simple power amplifiers using op-amps Z6A and 268 as voltage followers. Increased current output capability is provided by the NPN/PRP ‘output stage added inside each feedoack loop. The diodes and 22 ohm resistors make the transistors ‘operate class AB. STACK SWITCH BOARDS The Right Stack Switch Boerd contains the following circuits, as outlined on the schematic: 1, Bank select decoder 2. Switch banks a. Sense amps ‘The Left Stack Switch Board is an extension of the Right Steck Switen Board and has the same circuits minus the sense amps. These circuits will be covered Individually in the following descriptions. The term “stack switch” eomes from the way each switch is assembled as 2 stack of different layers 1. BANK SELECT DECODER When the keyboard scanning computer on the 1/0. Board wants to read the state of a bank of eight key- switches, it addresses the bank by putting one of 16 binary numbers on the KA lines, These lines drive the bank select decoders (Z1} on each board (KAZ {s inverted on the right board), causing exactly one of the 16 decoder outputs to be activated. These outouts are open-collectors, and, when activated, connect @ sow of eight switch contacts to ground. 2. SWITCH BANKS Each Keyswitch has a lower, normally closed, contact called the A contact, an upper, normally open, contact called the 8 contact, and a center wiper contact that is moved by the key. The keyboard has 64 keys which are grouped into eight banks of eight keys each, Half fof thase banks are handled by each Stack Switch Board, The keyboard scanning computer reads the state of a bank of A contacts or a bank of B contacts the row of contacts to ground. All the Wiper contacts connect, through resistor packs, to the keyboard bus KBO through KB7. This is a current summing bus, and any closed contacts in tho solacted: lbank will cause 500UA to be sinked from the appro: priate line on the bus, 3. SENSE AMPS ‘The keyboard bus is pulled up to the +5V rail by the 100 ohm resistors in ZG, A closed contact in the selected switch bank will pull BDOUA from a bus line, which will pull it, and one of the comparator (27 and 28) inputs, down S0mV. The other inputs on the tight comparators are connected to @ constant voltage that is about 26mV below the +5V ail, Thus, each ‘comparator resolves the state of one switch in the 2.14 selected bank and produces a standard 8V logie level (07 one of the keyboard data lines KDO through KD7, Each data line that goes back to the keyboard seanning computer will be a 0 if the corresponding switch ‘contact is open or 0 1 if tis closed. ‘The sense amps sre powered from the +12V supply,SECTION 3. DISASSEMBLY Access 10 the Chrome for troubleshooting is quite streightforward. Figure 3- 1 shows an exploded view of the screws holding the top cover in place, Remove the nine black serews (1-9) from the bsck and the four bronze screws {11-14} from the wood rail above the control panel. Do not remove screw 10 until you gently remove the cover. Screw 10 hoids 2 green ground strap under @ nut inside the cover (see Figure 3 - 2) which may be removed after you lift off the Romove four screws {15-18} from the sloping panel (Figure 3 - 2}. Tho panel is pivoted and may be raised Up and back as shown in Figure 3-3, As can be seen from Figure 3 - 3, most electronic bboards sre easily accessible with the Chroma open. Notice the order of the Dual Channel oards. They are numbered from left to right in a “U" shaped con figuration, while facing the Keyboard. These numbers tr FIG. 3-1 are silksoreened on the Channel Mother Board {not shown} into which the Dual Channe! Boards are plugged. Any of taese boards may be replaced without the need for soldering, Whore a cable terminates on fone board with solder joints, the other end of the same cable will have connectors. Visual examination of the assembly of these boards will reveal the pro- cedures necestary for successful disassembly, It is not s0 obvious how the Power Supply may be removed. Ten screws up from underneath the Chroma secure the supply. All ten (see Figure 3-4} should be moved from the bottom to detach the supply, The screws are threaded into standoffs holding the supply Off the bed of the Chroma. The supply and rear panel are removed in one piece, When Bulling the connectors. from J1, J2 and J3, notice they are keyed identical'y ‘and can be inadvertently connected incorrectly when winstslled. Refer to the Connection Diagram (Figure 3. B} and go by the colors of the wiresSCREW 10 a GREEN GROUND STRAP : DUAL CHANNEL FIG. 3-2 BOARDS 1654 2% COMPUTER e 1 9. EQ BOARD \ GREEN POWER SUPPLY GROUND 1/0 BOARD e ‘STRAP FIG, 3-3 32BOTTOM OF CHROMA FIG, 3-4 REAR @ OF INSTRUMENT ua R= RESET +T == TAPPER SUPPLY (+24V) TG = TAPPER GROUND AG = ANALOG GROUND e@ DG = DIGITAL GROUND -12 —12V ANALOG SUPPLY 412 = +12V ANALOG SUPPLY 45A = +5V ANALOG SUPPLY FIG. 3-5 CONNECTION DIAGRAM POWER SUPPLY +5D_ = +5V DIGITAL SUPPLYSECTION 4, DIAGNOSTICS —_———— During the auto tune routine, each of the 16 osciators and filters are checked and tuned. This happens whenever the Chrome is turned on, when the [AUTO TUNE] switch is used or if a reset occurs, The eight Dual Channel Boards in the Chroma are tabelted 0" through "7." (See Page 3 - 2 for board locations.} Tho computer will automatically turn off any Dual Channel Board that malfunctions and display an error message in the Data Readout, The message (ERR 6). for example, means that Dual Channel Board number "G" failed and has been turned off, Subsequently pressing [AUTO TUNE] will not affect the cisabled board, The computer will ignore this Dual Channel Until reset or pewerup occurs. The Chroma will ‘operate normally, but with two less channels. Thare are easily accessed hidden functions available by pressing [SET SPLIT] chen a numborad switch on the sight panel, While many of these are outlined in the oviner’s manual, certain ones are most useful in diagnosing problams. These are described in the follewing outline (SET SPLIT] (5] BATTERY TEST Displays the non-volatile memory battery voltage in the Data Readout window, A typical reading displays [cali 9.16]. When the reading drops below 2.5 volts, the two “AA” size batteries on the Computer Board should be replaced, {SET SPLIT] [7] DISABLE CHANNEL BOARD “This may be used to manually turn off a Dual Channel Board, If a channe! board malfunctions, but was not automatically turned off during auto tune, it can be disabled manually. Play the keyboard until you hear the bad note, then while holding the key down ibefore playing anccher note} press [SET SPLIT] [7]. The cchannol Board will turn off and be displayed #s an error ‘message in the Data Resdout, [SET SPLIT] [8] DISPLAY DISABLED BOARDS If channel baard has been disabled, the Chroma will operate normally with two less channels, Selecting programs or editing will cause the Data Readout to Gisplay relevant data in place of the error message, To display the number of any disabled boarts, use this, function, [SET SPLIT] (9) TAPPER ON/OFF Alternately turns the Tapper aff and on [SET SPLIT] (10] CASSETTE MODE Selects automatic {motor sensing) or menual cassette mode. If the cassette will not load, this is the first thing to try — it may be in the wrong mode, The rormal mode senses and controls the cassette moter, providing the polarity is such that the tio of the remote jack on the cessette recorder is positive in respect to the sleeve, The alternate mode allows use with cassettes that have no motor control, ie, 90 remote jock [SET SPLIT] [26] MUTE A ‘Suppose you hear a bad note while playing up seale on the keyboard. Before turning it off with [SET SPLIT] (7), ey muting all the "A" channels using (SET SPLIT] {26}. Now only the “B" channels will func: ton. If 2 channel still outouts a bad note, it will, of course, be a B" channel. Now you may held down the bad note, turn it off with {SET SPLIT] [7] and read the board number in the Data Readout. You wit! have pinpointed the malfunction down to a single channat on a single board. (SET SPLIT] [27] MUTE S Tuen off all “B” channels, similar to Mute A. [SET SPLIT] (29) MUTE ALL When using Mute A or Mute 8, the “A or "2" channels are silenced by turning off the “A”-VCA for the "B”-NCA through the sample and hold circuitry, "Mute All" differs in that the oscillators (both A’ and “B") are disconnected from the filters but the fiisers and amplifiers ean still function, This lends itself to helping vou differentiate between an oscillator and filter problem, After determining a bad note is coming from a single channel on a single board you may use [SET SPLIT] [29] to mure all oscillators. A. continuing bad sound suggests problems in the filters or mare remately in the amplifiers, No sound iicates the bad note was produced by the oscilla: tor circuitry. [SET SPLIT) (28) UNMUTE Unmute channels. This unmutes [SET SPLIT] [26], [27] , and [28] [SET SPLIT] [30] TEST LEDS Turns on all LEDs and display segments. This will provide maximum load to the Power Supply. Use this for checking @ suspected marginat supply and for testing the LEDs. Select a program to restore normal operation (SET SPLIT] [31] SPECIAL RESET 1 Is possible to use some of the previously described functions to pinpoint an offending note only if the bad note plays, What iT it was turned off automatically ‘by the computer during an auto tune routine? No problem, use [SET SPLIT] 132] Special Reset. This ‘will reset the main computer and call up an auto tune 4routine but the computer is instructed to ignore any channels thet malfunction. This will permit you to listen to all channels, even bad ones and to apply the previously described functions to help diagnose the problem. Additionally, this Function orders an ascend: ing channel assignment from board "0" to 7" with oscillator "8" first then escilletor “A.” For exarnpl if parameter 1° is sat to value “O" (individual oscilla tots), the first note played will be channet board “0” oscillator “B,” the secard note will be channel board '0” oscillator “A” and so forth to the sixteonth note which will be channel board "7" oscillator ““a,"" With parameter "1" sot to value "1" (paired oscilla tors), the first note will ba channel “0 both oscillators "B" and “A and the eighth nate channel 7" both oscillators "3" and "A." ISET SPLIT] (50) RESET ‘This acts a5 3 computer reset, It callsup an auto tune routine but differs from the [SET SPLIT} [31] Special eset by ordering a descending cnanne! assignment anc the computer is not instructed ta ignore malfunctions, ‘The computer will automatically turn off malfunctien: ing boards, The descending channel assignment causes the first note to play oseillater "8" on board “2 the second note oscitator “A on board “7” and the sixteenth note, oscillator "A" on board “0,” providing you have selactes the 16 channel made with parameter "1" and! no channels have been turned off automatical: Iv by the computer. POWER DOWN/POWER UP By turning off the Chroms and turning it on again, you will nitiete = complete system reset, This calls up an auto tune routine, provides automatic fail/pass channel control to the computer but differs from previous fesots by activating the power supply reset circuitry ‘The supply reset Jocks out the CMOS RAM (program memory) by desctivating the chip select fines until al supplies are in regulation. Further, the power down eycle deactivates these chip select lings prior to the supplies dropping cut of regulstion. Should you have Problems zelating to loss of program memory oF over: wwiting garbage into program memory, be sure to check the power supply ceset tine curing power down! power up, In diagnosing Chroma problems, you will undoubtedly find a scope useful. Unfortunately, the strobe signals in the Chrome ate fast pulses and may occur only once, depending on the system routine. The scope must be Set up using a triggered sweep. An easy way t0 obtain correct sweep settings is 10 use the write tanper strobe fon pin 7 of 241, on tha I/O Board, Sequentially, press 4 right panel memorane switch as you adjust the sweep, to capture the write tapper steobe, Each time you press the membrane switch, a write tapper strobe Is genereted. Once the sueep is set correctly, you ean “look” for other sirabes as dictated by the problem at hand, The 1/0 strobe decoder is a good place to start in most cases. If you are looking at the write timer mode line with a scope, you may see that this write strobe is cepeated 2.5us apart, This was done to et around a round noise problem that cropoed up in some early units. Protend there is only ane strobe pulse for the point of view of analysis, Also, you may notice that the timer mode bits come out of latch 242 with the ‘middle bit inverted, This was a. layout error that Was easier 10 corraet in the computer firmware. The computer thinks it is using modes 2,3, 0, 1 and 6; but the three latch cutputs wili show modes 0, 1, 2, 3and 4 Listed below are valuas of supply current in two columns. The nominal current draw is measured ‘under maximum load usiag [SET SPLIT] [30]. The ther column lists the maximum currert the supply will deliver before current limiting occurs, Calibra: tion and cheekout of the supply voltage levels are covered in Section 5, SUPPLY NOMINAL MAXIMUM 48V analog 126 milliamps 250 milliamps 48V digital 23 amperes. 2.5 ampuras 412V analog 800 milliamas 700 milliamps 12V analog 500 milliamas 700 miliompsSECTION 5. CALIBRATION AND CHECKOUT Al service centers are urged 10 obtain copies of the Chroma user manuals for performance, programming, sequencing and interfacing to have on hand as a refer ance source covering all aspects of operation, A good starting point for calibration and checkout is the power suoply, All three rectifier circuits are ful: wave, But an open diode or trace may result in halt wave’ operetion, The regulators will still work but filtering becornes less affective, increasing noise on the corvespanding supply line output, This may cause erratic operation, intermittent glitches or tuning pro- blems. Far this reason, itis desirable to chack ripple frequency wherever a Chroma is in for sertvice, Check she peried of the ripple in all three circuits, on 3, C7 and C21, The period should be 8.3 millisec for 320Hz fullwave ripple, In addition, measure the amaliuide of the preregulator ripple.” This should fnover excsed O.5Vp-p._ If higher than 0.5Verp tighten she mounting screws on C3 that hold the evervolcage protector. It Is good practice to mount the wire terminals beneath the Qvervoltage Protector Bosrd for maximum conductivity. These connections ore critica ‘The preregulator DC voltage on C3 (in reference to ground) should be adjusted so. the minimum ip in the ripple waveform is at a DC level of 6.2 volts. The peak should be about 6.6 volts, Minimum dip should not drop bolow 6.0VDC, Maximum peak should not tise above 7.0VDC. The adjustment is made by changing the bias on teansistor Q3, Two versions of the printed cirauit fabrication exist for this supply, In one version a porentiomerer |R48) is proviced to correctly bis O3, Simply adjust RA6 for ripple dip of 6.2VDC on C3, In the other version, resistor RS. must be changed in value (usually by shunting it] to. set the dip t0 6.2 VDC, We suggest using a decade bbox first, thon soldering in the correct vaiue, Use a DC scope to check the DC level of the dip and peak, 2 DVM will not suffice. Preregulator voltage that is ‘wo (ow will cause stratic operstion.. ‘The #8V snalog supply provides the reference voltage tor the D/A converters. Calculations indicate that the auto-tune functions operate closer to center range ‘when the +$¥ analog supply is adjusted slightly on the high side, Empirical data from the field reinforces this condition. Set the +8V. analog supply to +5.05VDC by adjusting potentiometer R22. Use 2 DVM to measure from the yellow wire at J7-4 on the supply to chassis ground, This supply voltage if set two low will adversely affect tuning anc’ may cause the computer to fall Dual Channel Boards Atthough 0 adjustments are necessary for the +12V for -12V analog, check them anyway to ensure they are within 5% of their nominal voltage. The *5V digital should not dip below 4.9V ond will usually be slightiy high after setting the +5V analog to +5.05, it takes its reference. as this is wher The next circuit aeeding calibration is on the 0 Board, The output buffer in the DAC circuit is a FET. input op-amp with an offset null wirmmer. The offset voltage must be set to within 100uy of zero. Connect. a DVM 13% er 4 digit) botween test point O and test Point 1 on the 170 Beard. Adjust potentiometer RY for £.0001VDC. This calibration must be correct to preveat tuning problems, Prior to further calibration and checkout, it is maces: sary to set-up a “scratch” patch. Activate both [EDIT A] and [EDIT B} functions, then while pressing and holding the (PARAM SELECT) switch, press esch of the 50 numbered switches on the right panel, This isables all pitch and pulse width modulation. AIK parameters will now be set to their default “scratch” setting, Be sure the (NO LINK) LED is on and that afi transpose LEDs are off. Playing 2 Key using this un modified scratch’ patch results in 2 raw sawtooth wave sound. The "scratch’ patch will not affect any of the 0 programs stored in memory unless you use the (STORE] switch, You may now check and caliarate the Dual Channe) Bosrds following one of the procedures outlined below: TRIM PROCEDURE: They only adjustment in the synthesizer circuit isthe charge putno current, which is adjusted by R1 (R2}, This adjustment affects the vott age level at the bottom of the sawtooth swing (the top is fixed at volts), This in turn affects the pulse width, which suggests an easy wey to do the trim, After’ setting up the “seratch"” patch, modify para meter 3 {keyboard alg) to value 3 fall ehannel poly}, this gives @ common contrel voltage value to all 16 oscillators for wate of calibration. Set wave shape parameter (No, 33) to value 1 (pulse), and set pulse width parameter (No, 34) to 32 (50% duty cycie). Connect your scape to TP1 on any channel board, set it for negative edge triggering, and adjust for a stable display, It is important that you trigger off the falling edge of the pulse that you see. Fine-adjust the horizontal sweep rate until the low portion of the focillator pulse cycle lasts from exactly the first graticule division on the scope to the middle division, If you are looking at a perfect square wave, obviously the next falling edge of the eycte will appeer pertectiy Jined up with the rightmast division on the scope face. Turning the trimmer R1 will not affect the lor portion of the eycle, but will only shorten or lenghten the the high portion of the cycie, Adjust this until you sae the second falling edge perfectly lined up with the last sraticule division, Repeating this tst for each ehanne! simply involves moving the probe 10 the next test point, readjusting the horizontal sweep speed so that the low part of the cycle takes exactly half the soreen, land adjusting the trim so that the entire cycle takes up the full screen.ALTERNATE TAIM PROCEDURE: The pulse width can be trimmed well enough without a scope by ear. This takes a bit longer, ae one has to get the correct oscillator to sound before doing each adjust iment. Tha easiost way 10 da this, i to set up a simple sound fone without pitch or pulse width modulation) using Patch 0, so that each note is played by a single oscillator 1 the Wave Shape parameter (No. 33) is s#t to 0 and he Width parameter (No, 24) is set 10. 22, the fundamental frequency of each note should be suporessed, causing the notes to sound an octave higher. To understand this better, try varying the With parameter on either side of Setting 32. If an oscillator Is incorrectly trimmed, the fundemental ‘frequency yall bo nulled out at some setting other than 32. Once you have established that you are adjusting the owcitlator you ate listening to, you can easily perform the trim. Don’t be thrown by the fact that the itch i varied too, Just adjust t@ null out the fundamental. When you ate through, you ean do an autostune, ‘The easiest way to determine which channel you are playing is to reset the insteurent (press {SET SPLIT [501). If you subsequently play sixtegn different notes {a chromatic scale, for instance), the channels will ‘always be heard in’ reverse order, starting with the 8 ‘oscillator (R2 trim) on board 7. Board 7 is the board closest to the right rear corner of the instrument, The boards are ordored in @ U-shaped sequence, 50 that ‘board is the boatd closest to the audio outputs, {F you bump an exirs note during this procedure, oF Get othorwise confused, just press [SET SPLIT) 150] again to reorder the channel assignment. Once the Dual Channels neve been “rimmed” you may want to check tuning. Use the “seratch'” patch ‘out change patch parameter [1] from valve "O"t0 value “7.” “Instead of one oscillator par note the Chroma will assign two per note, Tuning ie checked Dy listening to the osciltators beat together, Proceed Dy resetting the Chroma pressing (SET SPLIT]. [31] Play the “"C” one ocatve above middle “C” and count the beats over a 10 second period then divide by 10 to determine actual beats for one second. Repeat this going up-seale until eight notes have been played, Anything over two beats per second Is unacceptable. ‘An offending Dual Channel Board may be shut off by pressing (SET SPLIT] [7], {see the Diagnostic Chart). The dato readout in the litte display window will show an error followed by the board number that was shut off. Of course more than one beard may be shuz off using this feature, Example: The display [ERR 05] means that board “0 and boars “5” are shut off If you find an unacceptable Dual Channel Board, swap- ping positions may help in analyzing the preblem. Suppose the tuning is out of specification on the third note you play. Activating [SET SPLIT) [7] causes [ERR 2) to be displayed. Swap board "2" with board “1” (with powor shut off) then try again, If the out of tune condition moves to position “1” (ERR 1] the problem is on that Dual Channel Board, If the out 5.2 of tune condition still indicates [ERR 21, the problem is not on the Dual Channel, but likely in the strobing Eircuits on tho Channel Mother Board. Random aut of tune conditions are likely to be in the DAC circuits on the 1/0 Bosrd, or problems in the +6V anslog supply, An alternate method (0 check tuning follows: Use the “scratch” patch but set Wave Shape parameter (No, 33) to value "1” and With parameter (No. 34) to value "32." Press (SET SPLIT] [31] to auto-tune and ordet the channels. Using a tunizg strobe or meter ‘check each of the 16 oscillators starting with middle "* and play chromatically upscale, Do not stop ot fone octave, continue vatil 16 different notes have been played. Measure each note individually for umber of hundreds of semitones off center fre quency, Each note should be within 2,8 cents of its center frequency, ‘The remaining adjustments have to do with keyboard action. Refer to Figure 8 - 1. Measure the dapth of Keydown on a low, midele and high note, The depth should be 3/8 inch from keytop 20 keytop et the front edge of the key. Less than 3/8 Inch key travel means the Damper Bar is too low. Figure 5 «2 ils ‘ates the hardware securing the Damper Bsr, Loosen serews 1 and 2 and ruts 3, 4, 5 and 6, The Damper Bar should be positioned £0 that the lead weight just ouches the felt with normat full keydown pressure, Check this on both ends and near the two center brackets {some early Chroma’s have only one center bracket}. After tigntening all mounting hardware, check Damper Bsr height. Press a key down with fone hand and with the other hand grasp the wood key shank just forward of the lead weight, Pull against the Damper Bar felt, Proper adjustment results in restraint of further movement, If the Damper Bar is too high, the lead weighted end of the koy will pull up higher against the felt even though you are holding the key full down with your other hand, As mentioned pre: viously, adjusting the Damper Bar too low will ras ict the keydown movement te less then 3/8 inch, The left and right stack switch boards are mounted with three {3} screws going through elongated holes imo "T"" nuts (see Figure 8 - 3), Loosening these Screws allows the stack switches to be moved up or down to their correct position, Set the stack switch boards so that the top (normally open) leaf travels Upward about 1/32” after closing (as shown in Figure 5-4} before the key stops, 3/8 FIG. 5-1 KEV DEPTH MEASUREMENTFIG. 5-2 DAMPER BAR ASSEMBLY 19 SWITCH ASSEMBLY NOTE: NUTS” OTHER SIDE 18 SWITCH ASSEMBLY FIG. 5-3 STACK SWITCH ASSEMBLIES DAMPER BAR 132 | FELT FIG. 6-4Fas Lia so! x main sia s22-1 9D BNAASY JP2nk ss oa Jt De | suai, J22-8)7 Pressii2ee: PRES 215) (19-18, 83 aC CHROMA MODELS 2101 ~ 2104 VO BOARD SCHEMATIC (1 of 2)GND REF 13-2 Gs REF 13-4 Lever 213-5 Jadjae08 ie ia bg = | ep bel f [Be hemes Sth, St } os Bee Tsai" cu Fo 2 ciauesr REF DE SIMIATIONS wegen ean ao ase EE » couveuTious uses FoR, PF maces ANALOG Hav T FP isrries AvALOG 1SY ArT, wont ANA GND Jin 38 ANA QHD 31-e fos = LIES ANALOG “Av E IMOLES D GiTAL ev FP wEs SIGITAL CuO | IE MPLIES ANALOw GND = evau sh eezneed beebUBSEE CHROMA MODELS 2101 — 2104 1/0 BOARD SCHEMATIC (2 of 2)T = 7 mall gobod » 1 CHROMA. MODELS 2101 — 2104 WOBOARO ASSEMBLYiy > fo i" Lena 0} faut 9 © “361 oe Prinit, RAL PLI-1G, KAS P2i-10, KAO P29, KAS. NES paris. Pais, 45v, pomee Mores Paina, RBS Pen 3, BBE > P21-2, RET 8 (N10) CONTACTS. ae WIPER CONTACTS = A(NS) CONTACTS RiaHT Most tore Pel-8) RBT | Ness OTHERWISE SPECIFIED, Pai, BBE ACL RESISTOR VALUES ARE IN OHMS, /4W, 5% . PLi-G, GBS 2, HIGHEST _REF DESIaNATIONS: + + e2i-5, Ra C1 BS, P2t 3. CONVENTIONS FOR SUPPLY VOLTAGE CONNECTIONS A IMPLIES Di@iTAL 4BV [YAGER DaiTAL GNE Y | CHROMA MODELS 2101-2104 LEFT STACK SWITCH ASSEMBLY and SCHEMATICkas, 421-9 CO ResisTOR VALUES ARE IN uM, /9W/,5% WMPOES Denar eum Vy oi niuo\courner sae “Anie) couraera = LeeTMosT woreA c D E F 6 H | a K L M N ee T COCECCreT obit ff Le Penge SuPrLY BOARD SUS SRR Se Pee eee eee CHANNEL MOTHER BoaRD | SET JU ay UU Rian WEY GWiTGH BOARD rae LEFT KEY Switch BOARD “HW EERIE Ke 7 1 i : i 1 weasit Tels [sTe} resi Ts laisie)] pel ETI sielelele ste) slg OESCENE) a Oni Aitet eee ee. [Tf Leash ey ole SSL Tt COTE TTL f i Tee piiiads inp uEe nH Jo acane COMPUTER BOARD. oof STIS] sof f a cd oe - SUESSEDI CHROMA Sflewest | cucu Le? = fuser Pages Serve RignT PANEL Switen aneay | ace LLid iel+[o] shel ebsleel7 eof le? ease) vl MODELS 2101-2104 Seat ae ST an ewer 2 INTERCONNECTION DIAGRAM (1 of 2) 18 sonene ruveraee on cordt IS III) STII) i)Rov 10 Bone a4 aha [oa [Se as SB [om me | LL Le oe Lok PaAraror yr ss. —" : LEET PANEL SWITCH ARRAY Pararor gr) as, tee | OTL ee eQURNEE e) rie ls | w aol Ses Paka bab abs eg Jeep LL Oe) Qyararar se we ~le ele le coo eats :. Katara Pot asm. ifues; bKokahokoats ss. i a | az | a | ae | as vf] te pe For gr se.) weeee J fates Fo HES FEL Ls a | 40 | a | 50 3 Lt meer . seateaake, RIGHT PAREL SWITCH ARRAY a Note ade wor “Seo ZUNESS OTHERWISE speci TED: ALL RESISTOR VALUES ame IN CMG, Jaw 5 CHROMA % ALL CAPACITOR VALURS ARE 108 BICOFARADS, SON, 10% MODELS 2101-2104 INTERCONNECTION DIAGRAM (2 of 2)CHROMA MODELS 2101 — 2104 COMPUTER BOARD SCHEMATIC.DELS 2101 — 2104 EI R BOARD ASSEMBLY CHROMA mot PIPrimary WIRING alli, ov 2% Se RAN AC CIRCUIT (Penwary 4 SECONDARY) DIGITAL RECTIFIER ANALOG RECTIFIER; CIRCUIT 48V ANALOG m2 REGULATOR RESET CIRCUIT Pan PRE-REGULATOR, +5V DIGITAL, Pes CIRCUIT LINEAR Big ano Pace REGULATOR TAPPER ONO nag Pia 150 ANA a2 TAPPERS pees pa Pace sev sey Ana one REGULATOR Pi-3 Pi-e P31 Ann ano pes e+ nav ANA pan pase (Nor connected) Reset bin Notes: LUNKESS OTHERWISE SPECIFIED: ALL RESISTOR VALUES ARE IN OMS low 5% ALL RESISTOR VALUCS ARE IN uf, (P=PICOFARADS) 2MIGIEST REFERENCE DESIGNATIONS: AT, C17, CRIB, QI, EIB, BA, SI, TH, FB a. comleetons PI UO BOARD (ANALOG), 6 PINS P2- 1p BOARD (DIGITAL), & PINS Pa uoTukR BOARO, © PINS Pa EQ BOARD, 3 PINS CONVENTIONS USED FOR GROUNDS: SE PPcres Aunwsa Ges = TMELIES BratTAL eon 6. ups PANEL @eoUNS 7h CHROMA MODELS 2101-2104 POWER SUPPLY SCHEMATICCHROMA MODELS 2101-2104 POWER SUPPLY ASSEMBLYZERO CROSSING DETECTOR eqieoe BE ta, TBS 5 4 rts . Sere ceaaastS sais “AE MOSER ae > ash8 | | eon R mt eset SP | ue e He Sot t ure ils : | | i 1 { | aes t | = TONE | BALANCED CONTROLS ‘OUTPUT AMPLIFIER (MONO) Ces oii Ti Mores: be bee ¢8$ Gee sé TUMLESs OTHERWISE seecimIED £6 885 454 8445 4a Rit ReSeror VALUES ARE I OMS /aw 5x ee es ce AtL SaracrroR Vatues ane Ne ous - S oo acy ok : 28 2. WiGnEST REF CESi@nIATIONS Bs te PSF PEP FEE 33 ey ecztr ck) deme Lasse « nd pa 22 be 7 a 0 io a e3 Teromory BALANCED 3 ~ SCHEMATIC, PC BD, ‘OUTPUT AMPLIFIER (3) ne swo] 0] 30-7232 [¢CHROMA MODELS 2101-2104 BALANCED OUTPUT SCHEMATIC CHROMA EXTERNAL, 25 PIN 25 PIN v 1 T+ 14 2 z 1S 5 3 3 Te. Te. 4 = 7 17 5 L-PO NOT CONNECT: ie. 7 e e 7 20. 6 21 S 22, 10. 23. uf 24 12 25) iE} CHROMA MODELS 2101—2104 INTERFACE CABLE SCHEMATIC CABLE WIRING DIAGRAMSECTION 7. PARTS LIST COMPUTER BOARD, 30-7225301 o 301103008, (CAP ELECT 10UF av 60-10 3 30-1103201 (CAP ELECT 1UF 35 20% crt '30-1200101 an3a0 DIODE GE cra ‘301200208 4001 AECTEAV 1A, 023.45 30-1307901 3908 TSTR NPN GP ar 0:1305001 Tira08, TTSTR NPN POWER 210 2osa01a03 74802 Ie GATE 4x21 zn ao-02403, 74508 IC GATE 421, AND zs ‘01406602 74808 ICHEX INVERT 29 ‘0-1406701 vans IC DUAL D FF PRST CLEAR z 30972101 e000 Ic micro computer 2128 0-1472601 ana ICRAM 1K x 4 NMOS 2 301612701 718245 Ic DRIVER BEDIRECT oct z67 301413101 748138 11 0F 6 DEC 2a 01473501 7.8967 IC HEX SUFFER 3 57 21348 301414001 55149, 6517420,4220F.3 1G RAM 1K X 4 CMOS 300NS z2 03414104 IC RES NETWORK 1K 16 PIN XW 2%. For 220-56 90:2102708, SOCKET DUAL IN LINE 26 PIN LP For 21 302102706 SOCKET DUAL IN LINE.40 PIN LP. For 213-18, 291.28 302102707 SOCKET DUAL IN LINE 18 PIN LP. ForP3.10, 302107701 ‘CONN HOUSING FLAT FLEX 15 PIN P90 302209701 GABLE FLAT FLEX 15 COND 18" ev ‘202800202 CRYSTAL 16MHZ Zz 305603201 IC EPROM PROGRANMED 230 305903202 1C EPROM PROGRAMMED e zr 30-8803203 IC EPROM PROGRAMMED. z32 305602204 IC EPROM PROGRAMIFED 233 308605205, IC EPROM PROGRAMMED Zsa ‘305002208 IC EPROM PROGRAMMED 35 305609207 Ic EPROM PROGRAMMED 236 308603208 IC EPROM PROGRAMMED 1/0 BOARD, 30-7225801 REFERENCE CHROWA PART NO, MFG. No, DESCRIPTION a 30-1000909 POT ROTARY TRIMMER 10K %W 30% Ra ‘20-1002001 POT SLIDE LINEAR 10K ¥¥ 20%, cs ‘30-1103002 CAP ELECT 100UF 10V +60.10% c12s.a6 30-1103005 CAP ELECT 10UF 35v 50-10% cs 30:1103201 CAP ELECT 1UF 35V 20% 20 30:1103202, ——- (CAP ELECT 22UF 36V 20% (R23 24.25,26.27.31 20-1200201 4001 RECT 50v 14 6R17-22,26,29,30 '30-1200301 ana, DIODE SIONAL oni.36.3,14 021201602 DIODE LIGHT EMIT 1oMA GAEEN 6R2.4,7.9,12,15 30-1201603 DIODE LIGHT EMIT 10MA RED 6R5.8,10,13,16 ‘0e1201604 ——- DIODE LIGHT EMIT 10MA YELLOW a 301300801 22 TSTR NPN GP a0 03901201 4302 TSTA N CHANNEL 03055788 30-130280 3908 STA NPN GP a 30-1305501 Tip294 TSTR NPN PR 2 30-140101 1458 IC DUAL OF AML a8 301401702 7aLs00 Ne GATE 4X21 NANO @ zw a0r402102 7aisio 1eGATE 5x31 NANO. 255 301402201 7412 1¢ GATE 5x31 NAND OC zr '30-1402302 vavs20 IC GATE 2x41 NAND zz 301400401 4858 NCOP AMPL OUAL1/0 BOARD, 30-7225801 (contd.) 21038 39.1409701 225,53 30140601 z13 s0-1408001 212,228.42 soaot09 z0 anvao9702| zinaeas, s0-1a10501 2 301471001 218,10 301411601 230 201811701 28 04812001 231 301412404 23 50-1412802 25.6,29,28,96,08.47 soar2aor 215 nostat2a0 232 20-2412901 74,10,27,28.2437 301413001 239,408 goaa1a102 220 304413201 203 nosataaot 2 soais701 24 sotaraiot 252 po4i4102 Zz 30-1414103 zt soearatos a nosara7ar " ‘0-1800901 2 30:1801001 2 302101307 20.24 302101302 For 210,58 so2w2702 For 220 302102705, For 233 30-2102705, Forza 30.2102708 For 224 302109707 For 255.15 30-2402708 For 23 302102708 ow ‘302202002 a3, 302100002 ae 07100008 a an2108405 214,18,18 302106807 29,10 302107401 7 30-2107801 30:2107601 a2 ‘20-2100001 233 306603301 CHANNEL MOTHER BOARD, 30-7225401 REFERENCE CHROMA PART NO. ers ap-r02002 ca 0:1102000 a 30-1102006 c23 30-1102007 cre 30:1200101 ort 30:1200301 az 20307901 ze8 0-1204402 2167 ‘20-1404507 a 20-1208101 zras8 or 0640% 7-2 rens74 ot reisies raist75 1323) vaLsie3 an a8 ane 1543 029 808 raLso76 asaze mALs73 aLs2a4 ra1s198 rausi7a pausisa meres Pay weaneoor weoera pun =F ote AN rene veronr opm zc rerconen DESCRIPTION CAP ELECT 100UF 10¥ 20% (CaP ELECT 2200F 8.3 +50:10, (AP ELECT 1OUF 35V 50.15% (CAP ELECT “000UF 15 ¥50:10 tone Ge DIODE SIGNAL TSR NPN GP ICDUAL 0 FF SETIRESET IC QUAD BILAT swiTCH Ie GATE 4x21 OF IOP AMPL OUALz20 30-1811007 Z125 301811607 zs 01411701 Zaa8 ao arazr 783,10,11,12.13 doatag00 1501234557 302108403 Y7011,2,3,458,2 180234567 28.012.3.4557 30:2108601 pat ‘an2200807 DUAL CHANNEL BOARD, 30-7225601 ReFERENCE CHROMA PART NO R34 58 201000105 Ria 30-1001607 o234 30-1102301 es 43021303005 e31418,17.8 301103201 052,38,38,36,38,87,38,99 301103301 (024,25,26.27.28.29,30,31 30-1103802 cara 301200201 14589 301302901 02.367 ao4a0z001 a 430-1400509 2 ‘30-1400601 219.20 30-3404001 22 sos406201 z6.10.29 30405408 25,14,21,29.23.28 so-403001 28.3,11.18,10,18 30.1409501 226,27.28 sonar 70t 25 201419601 223 S9.1¢xa901 225 s01atasa1 216 304414401 213 301814501 LEFT STACK SWITCH ASSEMBLY, 30-7543601 REFERENCE CHROMA PART NO. a 30:1408001 72348 ‘soraratos, For P21 302107707 pat 0-2208707 905710701 an aus 4174 ses7/206 452 9827353 40528 “74 393 ast 4955 2380 380 MFG. NO, ery RIGHT STACK SWITCH ASSEMBLY, 30-7543701 REFERENCE ‘CHROMA PART NO. 28 0405401 2 ‘t0-y<08001 26 aorerat02 223488 01414103, a 302707401 P20 30:2200805 sos71070: MFG.no. 339 rasta, Ic VOLTAGE COMPARATOR IC QUAD DUAL FLIP FLOP Ie Hex DUAL FLIP FLOP IC NOISE GEN Ie + OF a DECODER DUAL CONN WAFER PC BD 8 PIN CONN WAFER PC aD ar ‘CASLE RIBBON 25 AWG 16 PIN 24° DESCRIPTION ES WAN TC 1.87% 1 3% POT ROTARY TRIMMER 10K 1/514 20% CAP PLASTIC FILM OO1UF to9y 10% CAP ELECT 10UF 25 ¥ 60-10% (CAP ELECT TUF 35v 20% ‘CAP POLY FILtO0G8UF SOV 10% CAP POLY FILM O33LF SOV 10% DIODE Ge STR NPR GP STR PNP GP lc TsTa ARRAY Ie GATE ax21 NAND Ie SINGLE B-CHAN MULTIPLEXER 16 TRIPLE 2.CHAN MULTIPLEXER ICO? AMPL DUAL IC OP AMPL DUAL FET IC DUAL 4.CHAN MULTIPLEXER ICHEX DUAL FLIP FLOP . Ic DUAL COMPARATOR OC Ic VCr CHARGE PUM le 1 OF 4 DECODER DUAL Ie DUAL vea Ic buat ver DESCRIPTION Ie 8C-0Fe DECODER DRIVER IC RES NETWORK 16 PIN 10% 2 2% CONN HOUSING FLAT FLEX 15 PIN CABLE FLAT FLEX 18 COND 25! SWITCH LEAF LOW BOUNCE DESCRIPTION Ic quan come 1¢ BDG-DEC DECODER DRIVER JO RES NEFWORK 16 PIN 100 OHM HAW 2% IG RES NETWORK 14 PIN 10K HW 256 (CONN RECPT SIP 15 POS CABLE RIBSON 25 AWG 16 PIN 9 SWITCH LEAP LOW BOUNCEEQ BOARD, 30-7225501 REFERENCE CHROMA PART NO. Ris 30-100200 ras ‘30-1002902 e021 301702001 ow '30-1902001 oz -30:1703005 om2345 '30.1200301 ass, 30300401 as 301900801 2 301302801 ar 07204901 23458 30-1406401 z2 goaaraeot 5 so210aa02 a0 so2108a08 a 302108002 POWER SUPPLY ASSY, 30-7543901 REFERENCE CHROMA PART NO, Ra 201000132, 18,2520, 301000113, R22 30-1000909 Reo. 30-1001001 Riz 30-1002801 ont 30:1701301 069.15,16 ‘01103008 10.12 90103405 oni 50200101 6R11,12.15,16, 301200301 cra '30-1200508 cnn 301200806 em2 301201701 crs 304201901 R6.7.89.10 ‘04202101 03,5,10,13 0-1302808 ana 30-1303008 23 s0-a14g01 212 304418101 ‘30-1700801 3123 '30-2108001 “ soarao02 cs 30-1104001 ara 30-1305301 os 301308501 ons 30305401 a 301306801 3041901501 st 0-1008101 30-2102101 02108201 1 305710601 930:7226001 MEG.NO, rPn0 THP29A, InFSa1 e258 DESCRIPTION POT SLIDE LINEAR 10K 1/59 20% POT SLIDE LINEAR 100K 1/51 20% (CAP ELECT AP 70UF 16 ¥50-105 (CAP ELECT 4,7UF 38 +100.10% (CAP ELECT 10UF 35V +50-108% DIODE SIGNAL TSTR PNP Ge TST NPN GP STR NPN GP STR N CHAN FET 1C.OP AMPL DUAL 1e-VoA DUAL CONN WAFER PC 806 PIN CONN WAFER PC 80 14 PIN CONN WAFER PC 8D 3 PIN DESCRIPTION RES WHY 120 CHES 1H 5 RES URE 1K TW 70% POT ROTAAY TRIMMER 10K W 30% POT ROTARY TRIMMER 100K 1/540 50% VARISTOR METAL OXIDE 150VAC CCAP ELECT 1000UF SOV 75-10% CAP ELECT 10UF 35V 50-10% GAP ELECT 3.3UF 35 +100:10% DIODE GE DIODE SIGNAL DIODE ZENER 39 5% DIODE ZENER 3.9V 5% DIODE RECT SOV 6A DIODE ZENER 12V 5% DIODE 100v 1A, STA NPN GP TSTR PNP ce Ic VOLTAGE REFERENCE 1e DUAL OP AML Fuse cL? CONN RECPT FC 8D6PIN ‘CONN RECPT PC AD 3 FIN ‘CAP ELECT 47000UF 7 5V 75-10% TSTA NPR DARL CTSTR NPN PRR TSTA OS FET POWER TSTR NPN PWR SWITCH SLIDE DPOT ‘SWITCH SLIDE OPDT 118V/230V UL. CONN AECET 3 PIN, CONN RECT 5 PIN, ‘TRANSFORMER POWER, °C BO ASSY OVERVOLTAGE PROTECTORSECTION 8. MNEMONICS a0 nea @ rite 20 vet fo corer save eet fis TIME ‘Timer reading (requires both strobes} TIME +1 Tine are (acute ton seein ae Seco ee NOTE Note number (keyboard) ve vaca tye oe ceesrtoa te WR ADCO A/D converter charinel select (starts conversion} eee “iene stone ote eral stoate ana ote ob seen sess iy ens | ote Se ee te we tes ine (epee tes wR SYND ‘Synthesizer data latch (Mother Board) ana Sirota se cen tetera fone Sea sera nde won Bere Diaconis oth rch Moe tia 13 or orA cour fetes om arabes e rae Peers sooradee vu eu era comput nr ater a sek Ec corbue eras Wt seae a aL eae ree eta conan oe al Ps sex Ena coriu Peatocs soc tote 8 is Seen ee ee a ae Nov soe an Leona enue