Dvd985 171 Manual

DVD-Video Recorder DVDR985 /171
CL 26532011_000.eps
160102
Contents Page Contents Page

1 Technical Specifications and Analog Board: Digital In / Out (Diagram 11) 119 121->
Connection Facilities 2 Analog Board: Fan Control (Diagram 12) 120 121->
2 Safety Instructions, Warnings, Notes, and DVIO Front Board 129 129
Service Hints 4 DVIO Board: 1394 Interface (Diagram 1) 130 135->
3 Directions for Use 6 DVIO Board: Microprocessor (Diagram 2) 131 135->
4 Mechanical, and Dismantling Instructions, and DVIO Board: Fifo & Control (Diagram 3) 132 135->
Exploded Views 36 DVIO Board: DVCODEC (Diagram 4) 133 135->
5 Diagnostic Software and Faultfinding Trees 41 DVIO Board: A/V Output (Diagram 5) 134 135->
6 Block and Wiring Diagram Digital Board: VSM, Buffer Mem. (Diagram 1) 139 148->
Block Diagram 95 Digital Board: AV Dec. STI5508 (Diagram 2) 140 148->
Wiring Diagram 96 Digital Board: AV Decoder Mem. (Diagram 3) 141 148->
7 Electrical Diagrams And Print-Layouts Diagram PWB Digital Board: Video Enc, Empr. (Diagram 4) 142 148->
Power Supply (Diagram 1) 97 99-102 Digital Board: VIP CVBS Y/C (Diagram 5) 143 148->
Power Supply (Diagram 2) 98 99-102 Digital Board: Analog Board Cons.(Diagram 6) 144 148->
Display Panel 103 104-> Digital Board: Progressive Scan (Diagram 7) 145 148->
Front AV Part 107 108 Digital Board: Progressive Scan (Diagram 8) 146 148->
IR and Standby Panel 109 109 Digital Board: Power, Clock (Diagram 9) 147 148->
Analog Board: All In One 1 (Diagram 1) 110 121-> 8 Alignments 157
Analog Board: All In One 2 (Diagram 2) 111 121-> 9 Circuit, IC Descriptions and 160
Analog Board: Tuner / Demod. (Diagram 3) 112 121-> List of Abbreviations 322
Analog Board: In / Out 1 (Diagram 4) 113 121-> 10 Spare Parts List 327
Analog Board: In / Out 2 (Diagram 5) 114 121->
Analog Board: In / Out 3 (Diagram 6) 115 121->
Analog Board: Sound Processing (Diagram 7) 116 121->
Analog Board: Power Supply (Diagram 8) 117 121->
Analog Board: Audio Converter (Diagram 9) 118 121->
Analog Board: RGB-YUV Conv. (Diagram 10) 119 121->
©
Copyright 2002 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Published by MT 0262 Service PaCE Printed in the Netherlands Subject to modification EN 3122 785 11950
EN 2 1. DVDR985 /171 Technical Specifications and Connection Facilities
1. Technical Specifications and Connection Facilities

1.1 General: 1.2.7 Tuning
Mains voltage : 120V (90 -140VAC) Automatic Search Tuning

Mains frequency : 50 Hz - 60Hz scanning time without antenna : ≤ 2,5 min
Power consumption mains : 32 W (typical, record) stop level (vision carrier) : ≥ 65dBµV, 75 Ω
Power consumption standby : <7W Maximum tuning error of a recalled
Power consumption low power program : ± 62,5 kHz
stand-by : <3W Maximum tuning error during
operation : ± 100 kHz
1.2 RF Tuner Tuning Principle

Automatic detection
Test equipment :Fluke 54200 TV Signal generator Manual channel activation
Test streams :PAL BG Philips Standard test pattern
1.2.1 System:
1.3 Analogue inputs
1.3.1 Audio/video Front Input Connectors

NTSC-M (USA/BTSC-Stereo+SAP)
1.2.2 Rf - Loop Through: Audio

Input voltage : 2 Vrms
Input impedance : >10k Ω
Frequency range : 45 MHz - 860 MHz
Gain: (ANT IN - ANT OUT) : -4 dB /±2 dB
Video - Cinch
Input voltage : 1 Vpp ± 0.1V
1.2.3 Radio Interference:
Input impedance : 75 Ω
input voltage /3 tone method (+40

Video - YC (Hosiden)
dB min) : typ. 80 dBµV at 75 Ω
Input voltage Y : 1Vpp ± 0.1V (with
sync)
1.2.4 Receiver: Input impedance Y : 75 Ω
Input voltage C : burst 286 mVpp ± {x}
PLL tuning with AFC for optimum reception dB
Frequency range: : 45.25 MHz - 860 MHz Input impedance C : 75 Ω
Sensitivity at 40 dB S/N : ≥ 60dBµV at 75 Ω
(video unweighted ) 1.3.2 Cinch Audio/video Line Input Rear
1.2.5 Video Performance: Audio (EXT1/2 and EXT3)

Input voltage : 2 Vrms
Channel 25 / 503,25 MHz Input impedance : >10k Ω
Test pattern: PAL BG PHILIPS standard test pattern
Modulation 54 % Video (EXT2-USA)
RF Level 74 dBV Input voltage : 1 Vpp ± 0.1V (with
Measured on YUV-EXT1 sync)
Frequency response: : 0.5 MHz - 4,00 MHz Input impedance : 75 Ω
± 2 dB
Group delay ( 0.1 MHz - 3.3 MHz ) : 0 nsec ± 30 nsec
1.3.3 Yc Input Rear (Hosiden; Ext1-usa)
1.2.6 Audio Performance:

1 GND
- !
2 GND
- !
Audio-BTSC: 3 Input
- voltage Y 1Vpp ± 0.1V/ 75 Ω (with sync)
Frequency response at audio cinch 4 Input
- voltage C Burst 286mVpp ± {x} dB/ 75 Ω
output: : 40 Hz - 15 kHz / ± 1,5
dB
1.3.4 Ypbpr Cinch Input Rear (Ext3)
S/N according to DIN 45405, 7, 1967 :
and PHILIPS standard test pattern
video signal: : ≥ -50 dB unweighted Input voltage Y : 1Vpp ± 0.1 (with sync)
Input voltage Pr : 0.7 Vpp
Harmonic distortion ( 1 kHz, ± 25
kHz deviation ): : ≤ 0.5 % Input voltage Pb : 0.7 Vpp
Input impedance : 75 Ω
Audio-SAP:
Frequency response at audio cinch 1.4 Video Performance
output: : 40 Hz - 15 kHz ± 1,5
dB All outputs loaded with 75 Ohm
S/N according to DIN 45405, 7, 1967 : SNR measurements over full bandwidth without weighting.
and PHILIPS standard test pattern
video signal : ≥ -60 dB unweighted
1.4.1 Cvbs Output Rear (Ext2)
Harmonic distortion (1 kHz): : ≤ 0.5 %
SNR Luminance : > -65 dB

Technical Specifications and Connection Facilities DVDR985 /171 1. EN 3
SNR Chrominance AM : > -65 dB 1.6 Digital Output

SNR Chrominance PM : > -65 dB
Bandwidth Luminance : 5 MHz ± 1dB
1.6.1 Coaxial Output
1.4.2 Yc Output Rear (Hosiden ; Ext1)

CDDA/LPCM (incl. MPEG1) : According IEC958
MPEG2, AC3 audio : According IEC1937
SNR : > -65 dB DTS : According IEC1937
SNR Chrominance AM : > -65 dB
SNR Chrominance PM : > -65 dB
1.6.2 Optical output
Bandwidth Luminance : 5 MHz ± 1dB
Identical to coaxial
1.4.3 Ypbpr Out (Ext3)
SNR : > -65 dB 1.7 Digital Video Input/output (Iee 1394)

Bandwidth : 5 MHz ± 1dB
1.7.1 Applicable Standards
1.4.4 Ypbpr Out (Progressive Scan)
Implementation according:
Progressive scan is off during stand-by mode IEEE Std 1394-1995
Progressive scan resolution : 525 lines x 60 frames/ IEC 61883 - Part 1
second IEC 61883 - Part 2 SD-DVCR (02-01-1997)
Output impedance : 75 Ω Specification of consumer use digital VCR’s using 6.3 mm
Output amplitude Y : 700mV (100% white, magnetic tape - dec.1994
without sync) Mechanical connection according:
Output amplitude PrPb : 700mV (100% level) Annex A of 61883-1
SNR : > 60dB (all channels)
Bandwidth Y : > 12 MHz ± 3dB 1.7.2 Audio Quality
Bandwidth PrPb : > 6 MHz ± 3dB
YprPb crosstalk : < -50dB (bandwidth < Output voltage 2 channel mode : 2Vrms +/- 1.5dB
10 MHz) Channel unbalance (1kHz) : Tbd
Crosstalk 1kHz : > 95 dB
1.5 Audio Performance Crosstalk 20Hz-20kHz : > 85 dB
Frequency response 20Hz- 12kHz : +/- 1dB max
Signal to noise ratio : >95 dB
1.5.1 Cinch Output Rear (Ext1/2)
Dynamic range 1kHz : Tbd
Dynamic range 20Hz-20kHz : Tbd
Output voltage 2 channel mode : 2Vrms ± 1.5dB Distortion and noise 1kHz : >65dB
Output voltage 5.1 channel Dolby : 1.41Vrms ± 1.5dB Distortion and noise 20Hz-20kHz : >65dB
Channel unbalance (1kHz) : <0.85dB Intermodulation distortion : >80dB
Crosstalk 1kHz : >105dB Phase non linearity : +/- 1 degree
Crosstalk 20Hz-20kHz : > 95dB Level non linearity : Tbd
Frequency response 20Hz- 20kHz : ± 0.1dB max Mute (spin-up, pause, access) : Tbd
Signal to noise ratio : >100 dB Outband attenuation : Tbd
Dynamic range 1kHz : >90dB
Dynamic range 20Hz-20kHz : >88dB
Distortion and noise 1kHz : >90dB 1.8 Dimensions And Weight
Distortion and noise20Hz-20kHz : >80dB
Intermodulation distortion : >87dB Height of feet : 12 mm
Phase non linearity : ± 1( max. Apparatus tray closed : WxDxH :435 x 325 x
Level non linearity : ± 0.5dB max. 107
Mute (spin-up, pause, access) : >100dB Apparatus tray open : WxDxH :435 x 465 x
Outband attenuation: : > 50dB above 25kHz 107
Weight without packaging : 5.670 g
1.5.2 Cinch Output Rear (Ext3) Weight : 1.675 g
Output voltage 2 channel mode : 2Vrms ± 1.5dB 1.9 Laser Output Power & Wavelength
Output voltage 5.1 channel Dolby : 1.41Vrms ± 1.5dB
Channel unbalance (1kHz) : <0.85dB
1.9.1 DVD
Crosstalk 1kHz : >105dB
Crosstalk 20Hz-20kHz : > 95dB
Frequency response 20Hz- 20kHz : ± 0.1dB max Output power during reading : 0.8mW
Signal to noise ratio : >100 dB Output power during writing : 20mW
Dynamic range 1kHz : >90dB Wavelength : 660nm
Dynamic range 20Hz-20kHz : >88dB
Distortion and noise 1kHz : >90dB 1.9.2 CD
Distortion and noise20Hz-20kHz : >80dB
Intermodulation distortion : >87dB Output power : 0,3mW
Phase non linearity : ± 1( max Wavelength : 780nm
Level non linearity : ± 0.5dB max
Mute (spin-up, pause, access) : >100dB
Outband attenuation: : > 50dB above 25kHz
EN 4 2. DVDR985 /171 Safety Instructions, Warnings, Notes, and Service Hints
2. Safety Instructions, Warnings, Notes, and Service Hints

2.1 Safety Instructions 2.2 Warnings
2.1.1 General Safety 2.2.1 General
Safety regulations require that during a repair: • All ICs and many other semiconductors are susceptible to
• Connect the unit to the mains via an isolation transformer. electrostatic discharges (ESD, "). Careless handling
• Replace safety components, indicated by the symbol , during repair can reduce life drastically. Make sure that,
only by components identical to the original ones. Any during repair, you are at the same potential as the mass of
other component substitution (other than original type) may the set by a wristband with resistance. Keep components
increase risk of fire or electrical shock hazard. and tools at this same potential.
Available ESD protection equipment:
Safety regulations require that after a repair, you must return – Complete kit ESD3 (small tablemat, wristband,
the unit in its original condition. Pay, in particular, attention to connection box, extension cable and earth cable) 4822
the following points: 310 10671.
• Route the wires/cables correctly, and fix them with the – Wristband tester 4822 344 13999.
mounted cable clamps. • Be careful during measurements in the live voltage section.
• Check the insulation of the mains lead for external The primary side of the power supply (pos. 1005), including
damage. the heatsink, carries live mains voltage when you connect
• Check the electrical DC resistance between the mains plug the player to the mains (even when the player is 'off'!). It is
and the secondary side: possible to touch copper tracks and/or components in this
1. Unplug the mains cord, and connect a wire between unshielded primary area, when you service the player.
the two pins of the mains plug. Service personnel must take precautions to prevent
2. Set the mains switch to the 'on' position (keep the touching this area or components in this area. A 'lightning
mains cord unplugged!). stroke' and a stripe-marked printing on the printed wiring
3. Measure the resistance value between the mains plug board, indicate the primary side of the power supply.
and the front panel, controls, and chassis bottom. • Never replace modules, or components, while the unit is
4. Repair or correct unit when the resistance ‘on’.
measurement is less than 1 MΩ.
5. Verify this, before you return the unit to the customer/ 2.2.2 Laser
user (ref. UL-standard no. 1492).
6. Switch the unit ‘off’, and remove the wire between the
• The use of optical instruments with this product, will
two pins of the mains plug.
increase eye hazard.
• Only qualified service personnel may remove the cover or
2.1.2 Laser Safety attempt to service this device, due to possible eye injury.
• Repair handling should take place as much as possible
This unit employs a laser. Only qualified service personnel may with a disc loaded inside the player.
remove the cover, or attempt to service this device (due to • Text below is placed inside the unit, on the laser cover
possible eye injury). shield:
Laser Device Unit CAUTION VISIBLE AND INVISIBLE LASER RADIATI ON WHEN OPEN AVO ID EXPOSURE TO BEAM
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING VED ÅBNING UNDGÅ UDSÆTTELSE FOR STRÅLING
!
Type : Semiconductor laser ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING NÅR DEKSEL ÅPNES UNNGÅ EKSPONERING FOR STRÅLEN
VARNING SYNLIG OCH OSYNLIG LASERSTRÅLNING NÄR DENNA DEL ÄR ÖPPNAD BETRAKTA EJ STRÅLEN
VARO! AVATT AESSA OLET ALTTIINA NÄKYVÄLLE JA NÄKYMÄTT ÖMÄLLE LASER SÄTEILYLLE. ÄLÄ KAT SO SÄT EESEEN
GaAlAs VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEÖFFNET NICHT DEM STRAHL AUSSETSEN
DANGER VISIBLE AND INVISIBLE LASER RADIATI ON WHEN OPEN AVO ID DIRECT EXPOSURE TO BEAM
Wavelength : 650 nm (DVD) AT TENTION RAYO NNEMENT LASER VISIBLE ET INVISIBLE EN CAS D'OUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU
: 780 nm (VCD/CD)
Output Power : 20 mW
Figure 2-2
(DVD+RW writing)
: 0.8 mW
(DVD reading) 2.2.3 Notes
: 0.3 mW
(VCD/CD reading) Dolby
Beam divergence : 60 degree Manufactered under licence from Dolby Laboratories. “Dolby”,
“Pro Logic” and the double-D symbol are trademarks of Dolby
Laboratories. Confidential Unpublished Works.
©1992-1997 Dolby Laboratories, Inc. All rights reserved.
Figure 2-3
Figure 2-1
Trusurround
TRUSURROUND, SRS and symbol (fig 2-4) are trademarks of
SRS Labs, Inc. TRUSURROUND technology is manufactured
Note: Use of controls or adjustments or performance of under licence frm SRS labs, Inc.
procedure other than those specified herein, may result in
hazardous radiation exposure. Avoid direct exposure to beam.
Figure 2-4
Safety Instructions, Warnings, Notes, and Service Hints DVDR985 /171 2. EN 5
Video Plus
“Video Plus+” and “PlusCode” are registered trademarks of the
Gemstar Development Corporation. The “Video Plus+” system
is manufactored under licence from the Gemstar Development
Corporation.
Figure 2-5
Macrovision
This product incorporates copyright protection technology that
is protected by method claims of certain U.S. patents and other
intellectual property rights owned by Macrovision Corporation
and other rights owners.
Use of this copyright protection technology must be autorized
by Macrovision Corporation, and is intended for home and
other limited viewing uses only unless otherwise authorized by
Macrovision Corporation. Reverse engineering or disassembly
is prohibited.
EN 6 3. DVDR985 /171 Direction for Use
3. Direction for Use

Direction for Use DVDR985 /171 3. EN 7
EN 36 4. DVDR985 /171 Mechanical, and Dismantling Instructions, and Exploded Views
4. Mechanical, and Dismantling Instructions, and Exploded Views

4.1 Service Positions DVIO 2
4.1.1 Front
Front
Figure 4-4
4.1.3 Digital Board
Figure 4-1 After demounting of DVIO board, the top side of the digital
board is in reach. To reach the bottom side of the digital board,
4.1.2 DVIO Board the DVDR module must be demounted together with the digital
board. Connected to each other, the assembly can be set in a
service position. In this position, the bottom side of the digital
To put the DVIO board in a service position, an extender board
board and the servo board are in reach to be serviced.
must be used. This extender board can be ordered with
codenumber 3104 128 07770.
Digital 1
DVIO Extender
Figure 4-5
Figure 4-2
Digital 2
DVIO 1
Figure 4-6
Figure 4-3
Mechanical, and Dismantling Instructions, and Exploded Views DVDR985 /171 4. EN 37
4.1.4 Analog Board
To put the analog board in service position, demount the

assembly of analog board and backplate as follows:
1. Remove 3 screws from the backplate to the frame
2. Remove the screw from the backplate to the mains inlet of
the power supply
3. Remove the screw of the analog board to the frame
4. Release the snaps of the 4 spacers of the analog board to
the frame.
Turn the assembly of the backplate and the analog board
against the loader.
Analog Europe
Figure 4-7
Analog NAFTA
Figure 4-8
4.2 Exploded View of the Set
Complete Set EV
SOPS
I/O ANALOG PCB
DVDR LOADER
DIGITAL PCB
DVIO PCB
CL 26532020_002.eps
240102
Figure 4-9
4.3
DISMANTLING INSTRUCTIONS
See exploded view for item numbers Cover 151
⇒ Remove 9 screws
mounting
171→174 at both sides ↑
175→179 at the rearside ↓
⇒ Lift the cover at the demounting
rearside to remove
Front assy DVDR LOADER 81 Switched Operating Power supply 1002

Analog board 1003 DVIO board 1005 (DVDR985)
⇒ open the tray and remove the ⇒ Remove the connections
tray front 65 ⇒ remove the connections ⇒ Remove 2 screws 217 and 218 ⇒ Remove the connections ⇒ Remove screws 204 → 206
⇒ remove 1 screw(215)
Dismantling Instructions
⇒ remove 4 screws 75 → 78 (DVIO board → frame 181) ⇒ Remove 4 screws (192 → 195) (board → frame)
(front assy → frame 181) (board → frame) ⇒ Release the snaps of 2 spacers (air filter 198 → loader 81) ⇒ Remove screw 268
⇒ remove screws 271 → 279
⇒ unlock the front from the (DVIO board → Digital board) ⇒ Remove screw 196 (mains inlet → backplate)
(cinches→ backplate) ⇒ demount carefully the board. (air filter inlet 191 → frame 181)
frame by releasing ⇒ Release the snaps of 2 spacers
Dismantling Instructions
⇒ remove nut 269 (board to board connection to ⇒ Remove air filter assy
successively 6 snaps (tuner → backplate) 183 and 184 (board → frame)
(1 on the left, 2 in the middle, the Digital board) ⇒ Open the tray and remove
⇒ Demount the board
1 on the right and 2 in the ⇒ release the snaps of 4 spacers the tray front 65
bottom of the frame. The 185 → 188 (board → frame) ⇒ Remove 4 screws
snaps in the bottom can be ⇒ demount the board 200 → 203 (loader 81→ frame 181)
released inside the set Digital board 1001 ⇒ Demount the DVDR loader
via the holes in the bottom. ⇒ Remove the connections
⇒ Remove 4 screws 207 → 210
(Digital board → frame 181)
⇒ demount the board.
Manually removal of tray front 65
See exploded view of front assy
In case the loader is defective and cannot be
opened electrically, you can open the tray
as follows:
FRONT DV Board 1006(DVDR985) Display board 1001 IR/STBY Board 1001 FRONT AV Board1007
⇒ Remove screw 17 ⇒ Remove 8 screws 31 → 38 ⇒ remove screws 41+42 ⇒ remove screws 48+49
(board → front) (board → front) (board → front) (board → front) ⇒ Via a hole in the frame and by way of a
⇒ demount the board ⇒ demount the board ⇒ demount the board ⇒ demount the board screwdriver, it is possible to unlock the tray.
Push the white pin of the slider at the bottom
side of the loader to the left.
⇒ Open the unlocked tray.
Figure 4-10
Mechanical, and Dismantling Instructions, and Exploded Views
240102
CL 26532020_001.eps
DVDR985 /171
4.
EN 39
4.4 Exploded View of the Front Assembly
DISPLAY
FRONT AV IN
FRONT DV IN
IR/STBY
CL 26532011_019.eps
160102
Figure 4-11
Diagnostic Software and Faultfinding Trees DVDR985 /171 5. EN 41
5. Diagnostic Software and Faultfinding Trees

Due to the complexity of the DVD recorder, the time to find a 5.1.2 Contents
defect in the recorder can become long. To reduce this time,
the recorder has been equipped with Diagnostic and Service
Unplug the power cord
software (DS). The DS offers functionality to diagnose the Hold key <PLAY> pressed
DVDR hardware and tests the following: while you plug the recorder
• Interconnections between components

• Accessibility of components
• Functionality of the audio and video paths During the test, the following display
is shown: the counter counts down
This functionality can be accessed via several interfaces: from the number of nuclei to be run
before the test finishes. Example:
1. End user/Dealer script interface
2. Player script interface
3. Menu and command interface NO
SET O.K.?
YES
5.1 End User/Dealer Script Interface
5.1.1 Description
The End user/Dealer script interface gives a diagnosis on a To exit DEALER SCRIPT, unplug the power cord
stand alone DVD recorder; no other equipment is needed. CL 16532095_068.eps

150801
During this mode, a number of hardware tests (nuclei) are
automatically executed to check if the recorder is faulty. The
diagnosis is simply a "fail" or "pass" message. If the message Figure 5-1
"FAIL" appears on the display, there is apparently a failure in
the recorder. If the message "PASS" appears, the nuclei in this The End use/Dealer script executes all diagnostic nuclei that
mode have been executed successfully. There can be still a do not need any user interaction and are meaningful on a
failure in the recorder because the nuclei in this mode don't standalone DVD recorder. The nuclei called in the End user/
cover the complete functionality of the recorder. Dealer script are the following:
Counter Nucleus Name Description

22 104 HostdSdramWrR checks all memory locations of the 4MB SDRAM
21 106 HostdDramWrR checks all the DRAM connected to the microprocessor of the digital board
20 123 HostdI2cNvram checks the data line (SDA) and the clock line (SCL) of the I2C bus between the host decoder
and NVRAM
19 202 SAA7118I2c checks the interface between the Host I2C controller and the AVENC SAA7118 Video Input
Processor
18 200 VideoEncI2c checks the interface between the host I2C controller and Empress SAA6752
17 207 AudioEncI2c checks the I2C connection between the host decoder and Empress SAA6752
16 204 AudioEncAccess tests the HIO8 interface lines between the host decoder and the audio encoder
15 203 AudioEncSramAccess checks the access of the SRAM by the audio encoder (address and data lines).
14 205 AudioEncSramWrR tests the SRAM connected to the audio encoder
13 206 AudioEncInterrupt tests the interrupt line between the host decoder and the audio encoder
12 300 VsmAccess checks whether the VSM interrupt controllers and DRAM are accessible
11 303 VsmInterrupt checks both interrupt lines between the VSM and the host decoder
10 302 VsmSdramWrR tests the entire SDRAM of the VSM
9 1400 Clock11_289MHz switches the A_CLK of the micro clock to 11.2896 MHz
8 1401 Clock12_288MHz switches the A_CLK of the micro clock to 12.288 MHz
7 601 BeS2Bengine checks the S2B interface with the Basic Engine by sending an echo command
6 500 DisplayEcho checks the interface between the host processor and the slave processor on the display
board
5 700 AnalogueEcho checks the interface between the host processor and the microprocessor on the analogue
board
4 711 AnalogueNvram checks the NVRAM on the analogue board
3 706 AnalogueTuner checks whether the tuner on the analogue board is accessible
2 901 LoopAudioUserDealer This nucleus tests the components on the audio signal path The host decoder
- The analogue board
- The audio encoder
- The VSM
On the analogue board the audio is internally looped back to the digital board
1 906 LoopVideoUserDealer Nucleus for testing the components on the video signal system path:
- The VIP
- The video encoder
- The VSM
- The host decoder
- The analogue board
On the analogue the video signal is internally routed back to the digital board.
EN 42 5. DVDR985 /171 Diagnostic Software and Faultfinding Trees
5.2 Player Script Interface 5.2.2 Structure of the Player Script
5.2.1 Description The player script consists of a set of nuclei testing the hardware
modules in the DVD recorder: the Display PWB, the Digital
PWB, the Analogue In/Out PWB and the DVDR module.
The Player script will give the opportunity to perform a test that
will determine which of the DVD recorder's modules are faulty, Nuclei run by the player test need some user interaction; in the
to read the error log and to perform an endurance loop test. To next table this interaction is described. The player test is done
in two phases:
successfully perform the tests, the DVD recorder must be
connected to a TV set. • Interactive tests: this part of the player test depends
To be able to check results of certain nuclei, the player script strongly on user interaction and input to determine nucleus
results and to progress through the full test. Reading the
expects some interaction of the user (i.e. to approve a test
picture or a test sound). Some nuclei (e.g. nuclei that test error log information can be useful to determine any errors
functionality of the DVDR module) require that a DVD+RW disc that occurred recently during normal operation of the DVD
player.
is inserted.
Only tests within the scope of the diagnostic software will be • The loop test will perform the same nuclei as the dealer
executed hence only faults within this scope can be detected. test, but it will loop through the list of nuclei indefinitely.
STEP DESCRIPTION NUCLEUS

1 Press OPEN/CLOSE and PLAY at the same time and POWER ON the recorder to start the playerscript 2
2 The local display shows FPSEGMENTS. Press PLAY to start the test. 502
First the starburst pattern is lit, then the horizontal segments are lit, followed by the vertical segments and the
last test is light all segments test. After each of the 4 tests the user has to confirm that the correct pattern was
lit.
Press PLAY to confirm that the correct pattern was lit (four times if the FPSEGMENTS test was successful).
Press RECORD to indicate that the correct pattern was not successfully lit.
Press STOP to skip this nucleus.
3 The local display shows FPLABELS. Press PLAY to start the test. 503
Press PLAY to confirm that all labels are lit.
Press RECORD to indicate that not all labels are lit.
4 The local display shows FPLIGHT ALL. Press PLAY to start the test. 520
Press PLAY to confirm that everything was lit.
Press RECORD to indicate that not all patterns are lit.
5 The local display shows FPLED. Press PLAY to start the test. 504
Press PLAY to confirm that the led is lit.
Press RECORD to indicate that the led is not lit.
6 The local display shows FPFLAP OPEN. Press PLAY to start the test. 522
Press PLAY to confirm that the flap has opened.
Press RECORD to indicate that the flap did not open.
7 The local display shows FPKEYBOARD. Press PLAY to start the test. 505
Attention all keys have to be pressed to get a positive result!
Press PLAY for more than one second to confirm that all the keys were pressed and shown on the local dis-
play. If not all the keys were pressed, a FAIL message will appear on the local display.
Press RECORD for more than one second to indicate that not all keys were pressed and shown on the local
display.
Press STOP for more than one second to skip this nucleus.
8 The local display shows FPREMOTE CONTROL. Press PLAY to start the test. 506
Press PLAY to confirm that a key on the remote control was pressed and shown on the local display. Only
one key has to be pressed to get a successful result.
Press RECORD to indicate that the key on the remote control was pressed but not shown on the local display.
9 The local display shows FPDIMMER. Press PLAY to start the test. 518
Press PLAY to confirm that the text on the local display was dimmed.
Press RECORD to indicate that the text on the local display was not dimmed.
10 The local display shows FPBEEPER. Press PLAY to start the test. 514
Press PLAY to confirm that the beeper on the front panel sounded.
Press RECORD to indicate that the beeper on the front panel did not sound.
11 The local display shows FPFLAP CLOSE. Press PLAY to start the test. 523
12 The local display shows ROUTE VIDEO. Press PLAY to start the test. 712
13 The local display shows ROUTE AUDIO. Press PLAY to start the test. 713
14 The local display shows COLOUR-BAR ON. Press PLAY to start the test. 120
STEP DESCRIPTION NUCLEUS

15 The local display shows PINK NOISE ON. Press PLAY to start the test. 115
16 The local display shows PINK NOISE OFF. Press PLAY to start the test. 116
17 The local display shows SINE ON. Press PLAY to start the test. 117
Press STOP to stop the sine.
18 The local display shows COLOUR-BAR OFF. Press PLAY to start the test. 121
19 The local display shows BERESET. Press PLAY to start the test. 603
20 The local display shows BETRAY OPEN. Press PLAY to start the test. 616
21 The local display shows BETRAY CLOSE. Press PLAY to start the test. 615
22 The local display shows BEWRITE READ. Press PLAY to start the test. 617
23 The local display shows BETRAY OPEN. Press PLAY to start the test. 616
24 The local display shows BETRAY CLOSE. Press PLAY to start the test. 615
25 The local display shows READ ERRORLOG. Press PLAY to start the test. 633
If the player test succeeded, the user/dealer script will start in an endless loop.
If the player test failed, the local display will display FAIL and the error code
Remark
In case of failure, the display shows " FAIL XXXXXX ". The
description of the shown error code can be retrieved in the
survey of Nuclei Error Codes (paragraph 5.4). Once an error
occurs, it is not possible to continue the player script. Unplug
the set and restart the player script. By pressing the STOP key,
it is possible to jump over the failure and to continue the player
script.
Unplug the power cord
Hold 2 keys
<OPEN/CLOSE> + <PLAY>
EN 44
simultaneously pressed while
you plug the recorder
5.
Player Script
FRONTPANEL TEST
PRESS <PLAY> PRESS <STOP> PRESS <PLAY> PRESS <STOP> PRESS <PLAY> PRESS <STOP>
PRESS <PLAY> PRESS <STOP> PRESS <PLAY> PRESS <STOP> TO START TEST TO SKIP TEST TO START TEST TO SKIP TEST
TO START TEST TO SKIP TEST TO START TEST TO SKIP TEST TO START TEST TO SKIP TEST
HEXADECIMAL XX TIMES HEXADECIMAL XX TIMES
KEY CODE PRESSED RC KEY CODE PRESSED
DVDR985 /171
TITLE TRACK CHAPTER TOTAL TRACK TIME REMAIN CHANNEL VPS/PDC
AM
PM
DVD RW SAVCD HQ SP L:P EP+ MONITOR SAT TIMER RECORD DECODER
I II
PROLOGIC MPEG DD DIGITAL DTS PCM MANUAL DIGITAL NICAM STEREO SAP
PRESS <PLAY> IF OK
PRESS <PLAY> IF OK PRESS AT LEAST ONE KEY
PRESS <STOP> TO ABORT PRESS ALL KEYS AT LEAST ONCE
PRESS <RECORD> IF NOT OK ON THE REMOTE CONTROL
SEE TABLE FOR KEY CODES SEE TABLE FOR RC KEY CODES
TO EXIT TEST: PRESS ONE OF FOLLOWING KEYS

PRESS <PLAY> MORE THAN 1S IF TEST IS OK ON THE LOCAL KEYBOARD
PRESS <RECORD> MORE THAN 1S IF TEST IS NOT OK PRESS <PLAY> IF TEST IS OK
PRESS <RECORD> IF TEST IS NOT OK
PRESS <PLAY> IF OK PRESS <PLAY> IF OK
PRESS <STOP> TO ABORT PRESS <PLAY> PRESS <STOP> PRESS <RECORD> IF NOT OK
TO START TEST TO SKIP TEST
RC KEY NAME RC KEY CODE
TITLE TRACK CHAPTER TOTAL TRACK TIME REMAIN CHANNEL VPS/PDC FRONT KEY NAME FRONT KEY CODE MONITOR EE
AM
PM
ON/OFF 0C
DVD RW SAVCD HQ SP L:P EP+ MONITOR SAT TIMER RECORD DECODER
STANDBY/ON 00E
STOP 31
MONITOR 00F
REC/OTR 37
-40 -30 -20 -10 0 OVER -40 -30 -20 -10 0 OVER OPEN/CLOSE 001
I II
PROLOGIC MPEG DD DIGITAL DTS PCM MANUAL DIGITAL NICAM STEREO SAP
Figure 5-2
PLAY 2C
STOP 002 PRESS <PLAY>
PRESS <PLAY> IF OK REVERSE 29
PRESS <PLAY> IF OK PLAY 003 TO START TEST
PRESS <STOP> TO ABORT PAUSE 30
PRESS <RECORD> IF NOT OK RECORD 004 SLOW 22
AUTOMAN 00D FORWARD 28
REC VOLUME PREVIOUS 21 BEEP IS AUDIBLE
MANUAL UP 00B FSS CF
MANUAL DOWN 00C NEXT 20
PRESS <PLAY> IF OK
CHANNEL UP 009 DISC 54 PRESS <RECORD> IF NOT OK
CHANNEL DOWN 00A SYSTEM 0F
UP 58
PRESS <PLAY> PRESS <STOP>
LEFT 5A
TO START TEST TO SKIP TEST
RIGHT 5B DIGITAL BOARD TEST
DOWN 59
RETURN 83
PRESS <PLAY> IF OK OK 5C
PRESS <RECORD> IF NOT OK CLEAR 41
TIMER FE
SELECT FA
Diagnostic Software and Faultfinding Trees
LED BECOMES RED VOL + ONLY FOR TV

VOL - ONLY FOR TV
CH + 1E
CH - 1F
MUTE ONLY FOR TV
1 01
2 02
3 03
4 04
5 05
PRESS <PLAY> IF OK
6 06
PRESS <RECORD> IF NOT OK
7 07
8 08
9 09
0 00
T/C C8
A/CH EE
ZOOM F7
ANGLE 85
SUBTITLE 4B
AUDIO 4E
DIM 13
REPEAT 1D
REPEAT A-B 3B
160102
CL 265362011_022.eps
SCAN 2A
DIGITAL BOARD &

FRONTPANEL ANALOG BOARD BASIC ENGINE
TEST TEST TEST
press <PLAY> to execute

press < STOP > to skip press <PLAY> to execute
press <NEXT > to skip

press < STOP > to skip press <PLAY> to execute
press <STOP> to skip
INSERT DVD +RW DISC TO EXECUTE

WRITE / READ TEST

press < STOP > to skip

press <PLAY> to execute press <STOP> to skip

press <PLAY> to execute press <NEXT > to skip
press <NEXT > to skip

press <PLAY> to execute press <STOP> to skip

press <STOP> to continue press <STOP> to skip
<PLAY>
press <STOP> to skip PRESS <STOP>

press <PLAY> to execute TO STEP DOWN
NO ERRORS LOGGED
PRESS <STOP> PRESS <RECORD>

TO STEP DOWN TO STEP UP
PRESS <RECORD>
TO STEP UP
PRESS <PLAY> TO CONTINUE
IF ERROR
CL 16532095_070.eps
To exit PLAYER SCRIPT, unplug the power cord
031201
Figure 5-3
5.2.3 Error Log
Explanation:
The application errors will be logged in the NVRAM. The
maximum number of error bytes that will be visible is 19. The
last reported error is shown as DN D0000000, the oldest visible
error as D0000000 UP and the errors in between as DN
D0000000 UP. DN stands for DOWN, UP stands for
UPWARDS. The shown
D error codes are identical to the Nuclei Error Codes
(paragraph 5.4).
5.2.4 Trade Mode 5.3.2 Error Handling
Each nucleus returns an error code. This code contains six

TRADE MODE
When the recorder is in Trade Mode, the recorder cannot be
numerals, which means:
controlled by means of the front key buttons, but only by means
of the remote control.
[ XX YY ZZ ]
IF TRADE MODE OFF IF TRADE MODE ON
Error code
UNPLUG THE RECORDER UNPLUG THE RECORDER
Nucleus number
Nucleus group number
CL 06532152_013.eps
051200
PRESS 2 KEYS PRESS 2 KEYS
SIMULTANEOUSLY SIMULTANEOUSLY
<STOP> + <OPEN/CLOSE> <STOP> + <OPEN/CLOSE>
PLUG THE RECORDER PLUG THE RECORDER
Figure 5-6
The nucleus group numbers and nucleus numbers are the

RECORDER IS IN TRADE MODE RECORDER IS IN NORMAL MODE
WHEN PRESSING FRONT WHEN PRESSING FRONT same as above.
KEYS, THE RECORDER KEYS, THE RECORDER
DOESN'T RESPOND WILL RESPOND
CL 16532095_071.eps 5.3.3 Command Mode Interface

150801
Set-Up Physical Interface Components

Figure 5-4 Hardware required:
• Service PC
5.2.5 Virgin Mode • one free COM port on the Service PC
• special cable to connect DVD recorder to Service PC
If you want that the recorder starts up in Virgin mode, follow this The service PC must have a terminal emulation program (e.g.
procedure: OS2 WarpTerminal or Procomm) installed and must have a
• Unplug the recorder free COM port (e.g. COM1). Activate the terminal emulation
• plug the recorder again while you keep the STAND BY/ON program and check that the port settings for the free COM port
key pressed are: 19200 bps, 8 data bits, no parity, 1 stop bit and no flow
• the set starts up in Virgin mode. control. The free COM port must be connected via a special
cable to the RS232 port of the DVD recorder. This special cable
will also connect the test pin, which is available on the
5.3 Menu and Command Mode Interface connector, to ground (i.e. activate test pin).
Code number of PC interface cable: 3122 785 90017
5.3.1 Nuclei Numeration
Activation
Each nucleus has a unique number of four digits. This number Plug the recorder to the mains and the following text will appear
is the input of the command mode. on the screen of the terminal (program):
[ XX YY ] DVD Video Recorder Diagnostic Software version 48

Basic SDRAM Data bus test passed
Basic SDRAM Address bus test passed
Basic SDRAM Device test passed
Nucleus number (M) enu, (C) ommand or (S) 2B-interface? [M] : @ C

DD:>
Nucleus group number CL 16532095_073.eps
150801
CL 06532152_012.eps
051200
Figure 5-7
Figure 5-5
The first line indicates that the Diagnostic software has been
The following groups are defined: activated and contains the version number. The next lines are
Group number Group name the successful result of the SDRAM interconnection test and
0 Basic / Scripts the basic SDRAM test. The last line allows the user to choose
between the three possible interface forms. If pressing C has
1 Host decoder (Sti5505 and memory)
made a choice for Command Interface, the prompt ("DD>") will
2 Audio / video encoder (DVDR only) appear. The diagnostic software is now ready to receive
3 VSM (DVDR only) commands. The commands that can be given are the numbers
4 NVRAM of the nuclei.
5 Front Panel
6 Basic Engine
7 Analogue board (DVDR only)
8 DVIO (DVDR only)
9 Loop nuclei (DVDR only)
10 Library sub nuclei (I2C nuclei)
11 User interface
12 Furore (SACD only)
13 DAC (SACD only)
14 Miscellaneous
Command Overview [xx yy] Nuclei

We provide an overview of the nuclei and their numbers. This Number
overview is preliminary and subject to modifications.
402 Modify
403 UniqueNr Read
Host Decoder [01]
404 Read Error Log
[xx yy] Nuclei
407 Reset Error Log
Number
409 Line2 Region-Code Reset
100 Checksum Flash
410 UniqueNr Store
101 Flash Write Access 1
102 Flash Write Access 2
Front Panel [05]
103 Flash Write Read
[xx yy] Nuclei
104 SdRam Write Read
Number
105 SdRam Write Read Fast
500 Echo
106 Dram Write Read
501 Version
107 Dram Write Read Fast
502 Segment
108 Hardware Version
503 Label
109 Mute On
504 Led
110 Mute Off
505 Keyboard
115 Pink Noise On
506 Remote-Control
116 Pink Noise Off
507 Segment Starburst
117 Sine On
508 Segment Vertical
118 Sine Burst 1kHz
509 Segment Horizontal
119 Sine Burst 12kHz
514 Beeper
120 Colour-bar On
515 Discbar
121 Colour-bar Off
516 Discbar Dots
122 NvramWrR
517 Vu / Grid
123 NvramI2c
518 Dimmer
130 Boot Version
519 Blinking
131 Application Version
520 Light All Segments
132 Diagnostics Version
522 Flap Open
133 Download Version
523 Flap Close
134 Write / read I2C message to / from digital board
135 Video Test Signal On Basic Engine [06]
136 Video Test Signal Off
[xx yy] Nuclei
137 Macrovision Off Number
600 S2B Pass
Audio Video Decoder [02]
601 S2B Echo
[xx yy] Nuclei
602 Version
Number
603 Reset
200 Video Encoder I2C
604 Focus On
202 SAA7118 I2C
605 Focus Off
203 Audio Encoder SRAM Access
606 Disc Motor On
204 Audio Encoder Access
607 Disc Motor Off
205 Audio Encoder SRAM Write Read
608 Radial On
206 Audio Encoder Interrupts
609 Radial Off
207 Audio Encoder I2C
615 Tray In
208 SAA7118 select input
616 Tray Out
209 Empress Version
617 Write Read
VSM [03] 618 Write Read Endless Loop
[xx yy] Nuclei 619 Selftest

Number 620 BE Test
300 Register Access 621 Laser Test
301 SDRAM Access 622 Spindle (Disc) Motor Test
302 SDRAM Write Read 623 Focus Test
303 Interrupt lines 624 Sledge Motor Test
304 VSM Interconnection 625 Sledge Motor Slow
305 UART 626 Tilt
627 EEPROM Read
NVRAM [04] 628 EEPROM Write
[xx yy] Nuclei 629 Optimise Jitter
Number 630 Radial ATLS Calibration
400 Reset 631 Get Statistics Information
401 Read 632 Reset Statistics Information
[xx yy] Nuclei [xx yy] Nuclei

Number Number
633 BE Read Error Log 906 User / Dealer Video Loop
634 BE Reset Error Log 907 User / Dealer Video VBI Loop
638 Get Self Test Result 908 System Audio Loop SCART
639 Radial Initialisation 909 System Audio Loop CINCH
640 Get OPU info 910 Digital DVIO Video Loop
641 Write read +R 911 System Video Vip
642 Write read +R endless loop
Miscellanious [14]
Analog Board [07] [xx yy] Nuclei
[xx yy] Nuclei Number
Number 1400 Clock 11.289 MHz
700 Echo 1401 Clock 12.288 MHz
703 Boot Version 1412 Progressive Scan I2C
704 Hardware Version 1413 Progressive Scan test image on
705 Clock Adjust 1414 Progressive Scan test image off
706 Tuner 1415 Progressive Scan Route Enable
707 Frequency Download 1416 Progressive Scan Route Disable
708 Data Slicer
Scripts [00]
709 Sound Processor
710 AV Selector [xx yy] Nuclei
Number
711 Nvram
1 UserDealer Script
712 Route Video
2 Player Script
713 Route Audio
715 Set Slash Version 5.3.4 Menu Mode Interdace
716 Application Version
717 Diagnostics Version Activation
718 Download Version Plug the recorder to the mains and the following text will appear
720 Bargraph Level Adjustment on the screen of the terminal (program):
721 Clock correction
722 Clock reference DVD Video Recorer Diagnostic Software version 48
Basic SDRAM Data bus test passed
723 Re-virginise Recorder Basic SDRAM Address bus test passed
Basic SDRAM Device test passed
724 Flash Checksum
725 Tuner frequency selection (M) enu, (C) ommand or (S) 2B-interface? [M] : @ M
727 Set virgin bit Main Menu
728 Clear Virgin Bit 1. Digital Board ->
729 Write / read I2C message to / from analogue board 2. Analogue Board ->
3. Front Panel ->
730 Store external presets 4. Basic Engine ->
5. DVIO ->
731 Get slash version 6. Progressive Scan Board ->
732 AFC Reference Voltage Tuner 7. Loop tests ->
8. Log ->
9. Scripts ->
DVIO [08]
Select>
[xx yy] Nuclei CL 16532095_074.eps
150801
Number
800 Check DVIO board presence Figure 5-8
801 Reset DVIO
802 DVIO Access The first line indicates that the Diagnostic software has been
803 Get DVIO error codes activated and contains the version number. The next lines are
the successful result of the SDRAM interconnection test and
804 Get DVIO module Ids
the basic SDRAM test. The last line allows the user to choose
805 Execute DVIO module SelfTest between the three possible interface forms. If pressing M has
806 Set DVIO led on. made a choice for Menu Interface, the Main Menu will appear.
807 Set DVIO led off.
Loop Nuclei [09]

[xx yy] Nuclei
Number
900 Digital Audio Loop
901 User / Dealer Audio Loop
902 Digital Video Loop
903 Digital Video VBI Loop
904 System Video Loop
905 System Video VBI Loop
Menu Structure AVENC Menu

The following menu structure is given after starting up the DVD 1.Empress ->
recorder in menu mode. The symbol -> indicates that the 2.Video Input Processors ->
current menu choice will invoke the display of a submenu.
Empress Menu
Main Menu 1.Version number
1.Digital Board ->
2.Analogue Board -> Video Input Processors Menu
3.Front Panel -> 1.SAA7118 I2C Access
4.Basic Engine ->
5.DVIO ->
NVRAM Menu
6.Progressive Scan Board ->
1.Read Error Log
7.Loop Tests ->
2.Reset Error Log
8.Log ->
3.Read DVIO Unique ID
9.Scripts ->
Analogue Board Menu

Digital Board Menu
1.Echo
1.Host Decoder ->
2.Obsolete
2.VSM ->
3.Route Video Input back to Digital board
3.AVENC ->
4.Route Audio Input back to Digital board
4.NVRAM ->
5.Flash Checksum
6.Versions ->
Host Decoder Menu 7.Components ->
1.Flash Checksum 8.Re-virginize Recorder ->
2.Flash1 Write Access
3.Flash2 Write Access
Analogue Board Versions Menu
4.Flash Write/Read
1.Hardware Version
5.Host SDRAM Write/Read
2.Bootcode version
6.Host SDRAM Fast Write/Read
3.Application version
7.Host DRAM Write/Read
4.Diagnostics version
8.Host DRAM Fast Write/Read
5.Download version
9.I2C NVRAM
10.NVRAM Write/Read
11.Engine S2B Echo Analogue Components Menu
1.Tuner
12.Versions ->
13.Audio Mute -> 2.Data Slicer
3.Sound Processor
14.Colourbar ->
15.Pink Noise -> 4.AV Selector
16.Sine Generate -> 5.NVRAM
Analogue Board Re-virginize Menu

Digital Board Versions Menu
1.Hardware Version 1.Re-virginize Recorder
2.Bootcode version 2.Set Virgin-bit
3.Clear Virgin-bit
3.Applications Version
4.Diagnostics Version 4.Store external presets
5.Download Version
Front Panel Menu
1.Echo
Audio Mute Menu
1.Audio Mute On 2.Version
2.Audio Mute Off 3.Flap Control ->
4.Segment Test ->
5.Light Labels
Colourbar Menu
6.Led test
1.Colourbar On
7.Keyboard test
2.Colourbar Off
8.Remote Control
9.Beep
Pink Noise Menu 10.Disc Bar
1.Pink Noise On 11.Disc Bar Dots
2.Pink Noise Off 12.Vu Grid
13.Dimmer
Sine Generate Menu 14.Blink
1.Sine On 15.Light All Segments
2.Sine Burst 1kHz
3.Sine Burst 12kHz Flap Control Menu
1.Open Flap
VSM Menu 2.Close Flap
1.Register Access
2.SDRAM Access Segment Test Menu
3.VSM SDRAM Write/Read 1.Starburst
4.Interrupt Lines 2.Light Horizontal Segments
5.VSM Interconnection 3.Light Vertical Segments
6.UART 4.Light All Segments
Basic Engine Menu User/Dealer Loops Menu

1.Reset 1.User/Dealer Audio Loop
2.S2B Pass-through 2.User/Dealer Video Loop
3.S2B Echo 3.User/Dealer Video Loop VBI
4.Focus On
5.Focus Off System Loops Menu
6.Version 1.System Video Loop
7.Self Test 2.System Video Loop VBI
8.Get Self Test Result 3.System Audio Loop SCART(EURO)
9.Basic Engine Test 4.System Audio Loop CINCH (NAFTA)
10.Laser Test
11.Focus Test
Basic Engine Loops Menu
12.Tilt Test
1.Basic Engine write read
13.Optimise Jitter
2.Basic Engine write read endless loop
14.Statistics Info
15.Log ->
Log Menu
16.Spindle Motor ->
17.Radial -> 1.Read Error Log
18.Sledge -> 2.Reset Error Log
19.Tray ->
Script Menu
Basic Engine Error Log 1.User/Dealer Script
1.Read Error Log 2.Player Script
2.Reset Error Log
5.4 Nuclei Error Codes
Basic Engine Spindle Motor Menu
1.Spindle Motor On In the following table the error codes will be described.
2.Spindle Motor Off
3.Spindle Motor Test Error Nr Error String
10000 "Checksum is OK"
Basic Engine Radial Menu 10001 "segment name Checksum doesn't match" or "seg-
1.Radial On ment name segment not found"
2.Radial Off 10100 ""
3.Radial Initialisation 10101 "FLASH 1 Write access test failed"
4.Radial ATLS Calibration
10200 ""
10201 "FLASH 2 Write access test failed"
Basic Engine Sledge Menu
1.Sledge test 10300 ""
2.Sledge test slow 10301 "FLASH write test failed"
10302 "FLASH write command failed"
Basic Engine Tray Menu 10303 "FLASH write test done max. number of times"
1.Tray In 10400 ""
2.Tray Out
10401 "HostDec SDRAM Memory data bus test goes
wrong."
DVIO Menu
10402 " HostDec SDRAM Memory address bus test goes
1.Check Presence
wrong."
2.Reset
3.Access 10403 " HostDec SDRAM Physical memory device test
4.Error Codes goes wrong."
5.Module Identifiers 10500 ""
6.Led -> 10501 " HostDec SDRAM Memory data bus test goes
wrong."
DVIO Led Menu 10502 " HostDec SDRAM Memory address bus test goes
1.Led On wrong."
2.Led Off 10503 " HostDec SDRAM Physical memory device test
goes wrong."
Progressive Scan Board Menu 10600 ""
1.I2C Access
10601 "HostDec DRAM Memory data bus test goes
2.Test Image On
wrong."
3.Test Image Off
10602 "HostDec DRAM Memory address bus test goes
wrong."
Loop Tests Menu
1.Digital Board Loops -> 10603 "HostDec DRAM Physical memory device test
2.User/Dealer Loops -> goes wrong."
3.System Loops -> 10700 ""
4.Basic Engine Loops -> 10701 "HostDec DRAM Memory data bus test goes
wrong."
Digital Board Loops Menu 10702 "HostDec DRAM Memory address bus test goes
1.Obsolete wrong."
2.Digital Video Loop 10703 "HostDec DRAM Physical memory device test
3.Digital Video Loop VBI goes wrong."
Error Nr Error String Error Nr Error String

10800 "Host Decoder version(cut) number: version 20004 "No data send/received to or from Video Encoder"
number""Digital hardware version" 20005 "SAA7118 VIP can not be initialised"
10801 "Can not find version in FLASH." 20200 ""
10900 "" 20201 "I2C bus busy before start"
10901 "Error muting audio" 20202 "SAA7118 VIP access time-out"
11000 "" 20203 "No acknowledge from SAA7118 VIP"
11001 "Error demuting audio" 20204 "No data received from SAA7118 VIP"
11500 "" 20300 ""
11501 "Init of I2C failed" 20301 "Error audio encoder SRAM access cannot initial-
11502 "The selection of the clock source failed" ise I2C"
11504 "The demute of the audio failed" 20302 "Error audio encoder SRAM access cannot reset
11600 "" DSP through I2C"
11601 "Init of I2C failed" 20303 "Error audio encoder SRAM access cannot down-
11602 "The mute of the audio failed" load boot"
11700 "" 20304 "Error audio encoder cannot download test code"
11701 "Init of I2C failed" 20305 "Error audio encoder cannot obtain result of test"
11702 "The muting of the audio failed" 20306 "Error audio encoder SRAM access stuck-at-zero
data line "
11703 "The demute of the audio failed"
20307 "Error audio encoder SRAM access stuck-at-one
11704 "The selection of the clock source failed"
data line "
11707 "Setup of Front panel failed"
20308 "Error audio encoder SRAM access stuck-at-one
11708 "Sine on Front panel keyboard failed" address line "
11800 "" 20309 "Error audio encoder SRAM access address line
11801 "Init of I2C failed" address line x is connected to data line data line y"
11802 "The muting of the audio failed" 20310 "Error audio encoder SRAM access address lines
11803 "The demute of the audio failed" address line x and address line y are connected "
11804 "The selection of the clock source failed" 20311 "Error audio encoder SRAM access data lines data
11805 "Error cannot start VSM audio in port" line x and data line y are connected "
11900 "" 20312 "Error audio encoder SRAM access illegal data re-
ceived"
11901 "Init of I2C failed"
20400 ""
11902 "The muting of the audio failed"
20401 "Error audio encoder access cannot initialise I2C"
11903 "The demute of the audio failed"
20402 "Error audio encoder access cannot reset DSP
11904 "The selection of the clock source failed"
through I2C"
11905 "Error cannot start VSM audio in port"
20403 "Error audio encoder accessing ICR register"
12000 ""
20404 "Error audio encoder access stuck-at-zero of data
12001 "Invalid input line "
12100 "" 20405 "Error audio encoder access stuck-at-one of data
12200 "" line "
12201 "I2C bus busy before start" 20406 "Audio encoder access data lines data line x and
12202 "NVRAM access time-out" data line y are interconnected "
12203 "No NVRAM acknowledge" 20500 ""
12204 "NVRAM time-out" 20501 "Error audio encoder SRAM WRR cannot initialise
I2C"
12205 "NVRAM Write/Read back failed"
20502 "Error audio encoder SRAM WRR cannot reset
12300 ""
DSP through I2C"
12301 "I2C bus busy before start"
20503 "Error audio encoder WRR cannot download boot"
12302 "NVRAM read access time-out"
20504 "Error audio encoder cannot download test code"
12303 "No NVRAM read acknowledge"
20505 "Error audio encoder SRAM WRR cannot obtain
12304 "NVRAM read failed"
result of test"
13000 "Bootcode application version : bootversion"
20506 "Error audio encoder WRR SRAM stuck-at-zero
13001 "Can not find version in FLASH." data bit "
13100 "Recorder application version : recorderversion" 20507 "Error audio encoder WRR SRAM stuck-at-one
13101 "Can not find version in FLASH." data bit "
13200 "Diagnostics application version : diagversion" 20508 "Error audio encoder WRR SRAM data lines data
13201 "Can not find version in FLASH." line x and data line y are connected"
13300 "Download application version : downloadversion" 20509 "Error audio encoder WRR SRAM illegal data re-
ceived"
13301 "Can not find version in FLASH."
20600 ""
13700 ""
20601 "Error audio encoder interrupt cannot initialise I2C"
13701 "Turning off MacroVision failed"
20602 "Error audio encoder interrupt cannot reset DSP
20000 ""
through I2C"
20603 "Error audio encoder cannot download test code"
20002 "Video Encoder access time-out"
20604 "Error occurred accessing VSM"
20003 "No acknowledge from Video Encoder"
20605 "Audio encoder interrupt not received"

20606 "Error occurred while activating the encoder" 30203 "VSM SDRAM Bank1 Physical memory device test
20607 "Error audio encoder interrupt cannot initialise em- goes wrong."
press" 30204 " VSM SDRAM Bank2 Memory databus test goes
20608 "Error occurred while getting interrupt reason" wrong."
20700 "" 30205 " VSM SDRAM Bank2 Memory addressbus test
goes wrong."
20701 "Error audio encoder I2C cannot reset DSP
through I2C" 30206 " VSM SDRAM Bank2 Physical memory device
test goes wrong."
20702 "Error audio encoder cannot download boot"
30300 ""
20703 "Error audio encoder cannot download TEST
code" 30301 "VSM interrupt register A has a -stuck at- error for
value:"
20704 "Error audio encoder I2C bus busy"
30302 "VSM interrupt register B has a -stuck at- error for
20705 "Error audio encoder I2C cannot write slave ad-
dress" value:"
20706 "Error audio encoder I2C no acknowledge re- 30303 "Interrupt A wasn't raised."
ceived" 30304 "Interrupt B wasn't raised."
20707 "Error audio encoder I2C cannot send/receive da- 30305 "Interrupts A and B were raised."
ta" 30400 ""
20708 "Error audio encoder received data through I2C 30401 "VSM SDRAM Bank1 Memory databus test goes
was invalid" wrong."
20800 "" 30402 "VSM SDRAM Bank1 Memory addressbus test
20801 "I2C access failed." goes wrong."
20802 "SAA7118 VIP can not be initialised." 30403 "VSM SDRAM Bank1 Physical memory device test
goes wrong."
20803 "Invalid input"
20900 "B1.B2. B3.B4. B5.B6. B7.B8. B9.B10. B11.B12." 30404 " VSM SDRAM Bank2 Memory databus test goes
wrong."
20901 "Firmware download of EMPRESS failed"
30405 " VSM SDRAM Bank2 Memory addressbus test
goes wrong."
20903 "EMPRESS access time-out"
30406 " VSM SDRAM Bank2 Physical memory device
20904 "No acknowledge from the EMPRESS" test goes wrong."
20905 "No data send to the EMPRESS" 30500 ""
20906 "No data received from the EMPRESS" 30501 "Communication with the analogue board fails."
30000 "" 30502 "Echo test to analogue board returned wrong
30001 "VSM SDRAM Bank1 Memory databus test goes string."
wrong." 40000 ""
30002 "VSM SDRAM Bank1 Memory addressbus test 40001 "NVRAM Reset; I2C failed"
goes wrong."
40100 "NVRAM address = 0xaddress -> Byte value =
30003 "VSM SDRAM Bank1 Physical memory device test 0xvalue"
goes wrong." 40101 "NVRAM Read; I2C failed"
30004 " VSM SDRAM Bank2 Memory databus test goes 40102 "NVRAM Read; Invalid input"
wrong."
40200 ""
30005 " VSM SDRAM Bank2 Memory addressbus test
40201 "NVRAM Modify; I2C failed"
goes wrong."
40202 "NVRAM Modify; Invalid input"
30006 " VSM SDRAM Bank2 Physical memory device
test goes wrong." 40300 "DV Unique ID = id"
30007 "VSM SDRAM Bank1 VSM interrupt register A has 40301 "NVRAM Read DV Unique ID; I2C failed"
a -stuck at- error for value:" 40400 "\r\n Error log:\r\n errorString \r\n Ö "
30008 "VSM SDRAM Bank2 VSM interrupt register A has 40401 "NVRAM error log; I2C failed"
a -stuck at- error for value:" 40402 "NVRAM error log is invalid"
30100 "" 40403 "Front panel failed"
30101 "VSM SDRAM Bank1 Memory databus test goes 40700 ""
wrong." 40701 "NVRAM error log reset; I2C failed"
30102 "VSM SDRAM Bank1 Memory addressbus test 40900 "Region code Change counter is reset"
goes wrong."
40901 "NVRAM region code reset; I2C failed"
30103 "VSM SDRAM Bank1 Physical memory device test
41000 ""
goes wrong."
41001 "NVRAM Store DV Unique ID; I2C failed"
30104 " VSM SDRAM Bank2 Memory databus test goes
wrong." 41002 "NVRAM Store DV Unique ID; Invalid input"
30105 " VSM SDRAM Bank2 Memory addressbus test 50000 ""
goes wrong." 50007 "Execution of the command on the analogue board
30106 " VSM SDRAM Bank2 Physical memory device failed."
test goes wrong." 50008 "The frontpanel could not be accessed by the ana-
30200 "" logue board."
30201 "VSM SDRAM Bank1 Memory databus test goes 50009 "The echo from the frontpanel processor was not
wrong." correct."
30202 "VSM SDRAM Bank1 Memory addressbus test 50100 " Front panel version: FPversion "
goes wrong."

50102 "Execution of the command on the analogue board 50901 "Execution of the command on the analogue board
failed." failed."
50103 "The frontpanel could not be accessed by the ana- 50902 "The frontpanel could not be accessed by the ana-
logue board." logue board."
50200 "" 50903 "The frontpanel did not show horizontal segments."
50204 "Execution of the command on the analogue board 50904 "The user skipped the FP-horizontal segments
failed." test."
50205 "The frontpanel could not be accessed by the ana- 50905 "The user returned an unknown confirmation: con-
logue board." firmation "
50206 "The frontpanel did not show a starburst." 51400 ""
50207 "The user skipped the FP-which pattern test." 51401 "Execution of the command on the analogue board
50208 "The user returned an unknown confirmation: con- failed."
firmation " 51402 "The frontpanel could not be accessed by the ana-
50209 "The frontpanel did not show horizontal segments." logue board."
50210 "The frontpanel did not show vertical segments." 51403 "The beeper did not sound."
50300 "" 51404 "The user skipped the FP-Beep test."
50304 "Execution of the command on the analogue board 51405 "The user returned an unknown confirmation: con-
failed." firmation"
50305 "The frontpanel could not be accessed by the ana- 51500 ""
logue board." 51501 "Execution of the command on the analogue board
50306 "The frontpanel did not light all labels." failed."
50307 "The user skipped the rest of the FP-label test." 51502 "The frontpanel could not be accessed by the ana-
logue board."
50308 "The user returned an unknown confirmation: con-
firmation" 51503 "The discbar did not display properly."
50400 "" 51504 "The user skipped the discbar test."
50404 "Execution of the command on the analogue board 51505 "The user returned an unknown confirmation: con-
failed." firmation"
50405 "The frontpanel could not be accessed by the ana- 51600 ""
logue board." 51601 "Execution of the command on the analogue board
50406 "The LED's could not be turned on." failed."
50407 "The user skipped the rest of the FP-LED test." 51602 "The frontpanel could not be accessed by the ana-
logue board."
firmation" 51603 "The discbar dots did not display properly."
50500 "" 51604 "The user skipped the discbar dots test."
50502 "Front panel Keyboard; test failed" 51605 "The user returned an unknown confirmation: con-
50503 "Front panel Keyboard; test aborted" firmation"
50504 "Front panel Keyboard; not all keys were pressed" 51700 ""
50505 "Front panel keyboard I2C connection failed" 51701 "Execution of the command on the analogue board
failed."
50506 "Unable to get slashversion"
51702 "The frontpanel could not be accessed by the ana-
50600 ""
logue board."
50602 "Front panel Remote control; test failed"
51703 "The VU grid did not display properly."
50603 "Front panel Remote control; test aborted"
51704 "The user skipped the VU gridtest."
50604 "Front panel remote control; can not access FP"
50605 "Front panel remote control; no user input re- firmation"
ceived"
51800 ""
50700 ""
51801 "Execution of the command on the analogue board
50701 "Execution of the command on the analogue board failed."
failed."
50702 "The frontpanel could not be accessed by the analogue board."
logue board."
51803 "The frontpanel could not be dimmed."
50703 "The frontpanel did not show a starburst."
51804 "The user skipped the FP-Dim test."
50704 "The user skipped the FP-starburst test."
50705 "The user returned an unknown confirmation: confirmation"
firmation "
51900 ""
50800 ""
50801 "Execution of the command on the analogue board failed."
failed."
50802 "The frontpanel could not be accessed by the analogue board."
logue board."
51903 "The frontpanel did not show segments blinking."
50803 "The frontpanel did not show vertical segments."
51904 "The user skipped the FP-blinking test."
50804 "The user skipped the FP-vertical segments test."
50805 "The user returned an unknown confirmation: confirmation"
firmation "
52000 ""
50900 ""

52001 "Execution of the command on the analogue board 60803 "Communication time-out error"
failed." 60804 "Unexpected response from Basic Engine"
52002 "The frontpanel could not be accessed by the ana- 60805 "Radial loop could not be closed"
logue board."
60900 ""
52003 "The frontpanel did not show all segments lit."
60901 "Basic Engine returned error number
52004 "The user skipped the FP-light all segments test." 0xerrornumber"
52005 "The user returned an unknown confirmation: con- 60902 "Parity error from Basic Engine to Serial"
firmation"
60903 "Communication time-out error"
52200 ""
60904 "Unexpected response from Basic Engine"
52201 "Communication with Analogue Board fails."
61500 ""
52202 "Frontpanel can not be accessed by the Analogue
Board."
0xerrornumber"
52300 ""
61502 "Parity error from Basic Engine to Serial"
52301 "Communication with Analogue Board fails."
52302 "Frontpanel can not be accessed by the Analogue
Board."
61600 ""
60000 ""
60100 ""
0xerrornumber"
0xerrornumber"
61700 ""
61701 "BE tray-in command failed"
60105 "Echo loop could not be closed"
61702 "BE read-TOC command failed"
60106 "Wrong echo pattern received"
61703 "BE VSM interrupt initialisation failed"
60200 "Version: nr1.nr2.nr3"
61704 "BE set irq command failed"
0xerrornumber" 61705 "BE no disc or wrong disc inserted"
60202 "Parity error from Basic Engine to Serial" 61706 "BE rec-pause command failed"
60203 "Communication time-out error" 61707 "BE VSM BE out DMA initialisation failed"
61708 "BE VSM BE out initialisation failed"
61709 "BE VSM BE out DMA start failed"
60205 "Front Panel failed."
61710 "BE VSM BE out start failed"
60300 ""
61711 "BE rec command failed"
60301 "Basic-Engine time-out error"
61712 "BE VSM out underrun error occurred"
60400 ""
61713 "BE record complete interrupt not raised"
0xerrornumber" 61714 "BE get irq command failed"
60402 "Parity error from Basic Engine to Serial" 61715 "BE no interrupt was raised by BE"
60403 "Communication time-out error" 61716 "BE VSM DMA out not finished"
60404 "Unexpected response from Basic Engine" 61717 "BE stop command after writing failed"
60405 "Focus loop could not be closed" 61718 "BE VSM Sector processor initialisation failed"
60500 "" 61719 "BE VSM sector processor DMA initialisation
60501 "Basic Engine returned error number failed"
0xerrornumber" 61720 "BE VSM sector processor DMA start failed"
60502 "Parity error from Basic Engine to Serial" 61721 "BE VSM sector processor start failed"
60503 "Communication time-out error" 61722 "BE seek command failed"
60504 "Unexpected response from Basic Engine" 61723 "BE VSM sector processor error occurred"
60600 "" 61724 "BE read timeout occurred"
60601 "Basic Engine returned error number 61725 "BE stop command after reading failed"
0xerrornumber" 61726 "BE difference found in data at disc sector
60602 "Parity error from Basic Engine to Serial" 0xdiscsector"
60603 "Communication time-out error" 61727 "This nucleus cannot be executed because the
Self-Test failed"
61800 ""
60700 ""
61801 "BE i2c initialisation failed"
0xerrornumber" 61802 "This nucleus cannot be executed because the
60702 "Parity error from Basic Engine to Serial" Self-Test failed"
60703 "Communication time-out error" 61900 ""
60704 "Unexpected response from Basic Engine" 61901 "The SelfTest failed with result: 0xnr1 0xnr2 0xnr3"
60800 "" 61902 "Basic Engine returned error number

0xerrornumber"
0xerrornumber" 61903 "Parity error from Basic Engine to Serial"
60802 "Parity error from Basic Engine to Serial" 61904 "Communication time-out error"

61905 "Unexpected response from Basic Engine" 63100 " Number of times Tray went Open/Closed : nr1""
62000 "" Total hours the CD laser was on : nr2"" Total hours
the DVD laser was on : nr3"" Total hours the write
62001 "Self-Test : errorstring1 Laser-Test :
laser was on : nr4"
errorstring2 SpindleM-Test: errorstring3 Sledg-
eM-Test : errorstring4 Focus-Test : errorstring5" 63101 "Basic Engine returned error number
0xerrornumber"
62100 "The forward sense level is 0xlevel"
0xerrornumber" 63103 "Communication time-out error"
62102 "Parity error from Basic Engine to Serial" 63104 "Unexpected response from Basic Engine"
62104 "Unexpected response from Basic Engine" 63201 "Basic Engine returned error number
0xerrornumber"
62200 ""
62201 "The BE-self-diagnostic-spindle-motor-test failed"
0xerrornumber" 63204 "Unexpected response from Basic Engine"
62203 "Parity error from Basic Engine to Serial" 63300 Momentary errors (Byte 1 - Byte 7) : 0xb1 0xb2
0xb3 0xb4 0xb5 0xb6 0xb7 Cumulative errors
(Byte 1 - Byte 7): : 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6
0xb7 Fatal errors (Oldest - Youngest) : : 0xb1
62300 "" 0xb2 0xb3 0xb4 0xb5
62301 "The BE-focus-test failed" 63301 "Basic Engine returned error number
62302 "Basic Engine returned error number 0xerrornumber"
0xerrornumber" 63302 "Parity error from Basic Engine to Serial"
62303 "Parity error from Basic Engine to Serial" 63303 "Communication time-out error"
62304 "Communication time-out error" 63304 "Unexpected response from Basic Engine"
62305 "Unexpected response from Basic Engine" 63400 ""
62400 "" 63401 "Basic Engine returned error number
62401 "The BE-self-diagnostic-sledge-motor-test failed" 0xerrornumber"
62402 "Basic Engine returned error number 63402 "Parity error from Basic Engine to Serial"
0xerrornumber" 63403 "Communication time-out error"
62403 "Parity error from Basic Engine to Serial" 63404 "Unexpected response from Basic Engine"
62405 "Unexpected response from Basic Engine" 63501 "Basic Engine returned error number
62500 "" 0xerrornumber"
62600 "" 63502 "Parity error from Basic Engine to Serial"
62700 "BE EEPROM address = address -> Byte value = 63503 "Communication time-out error"
0xvalue" 63504 "Unexpected response from Basic Engine"
62701 "Basic Engine returned error number 63505 "errorstring ÖThe basic engine will reject all player
0xerrornumber" commands"
62702 "Parity error from Basic Engine to Serial" 63900 ""
62703 "Communication time-out error" 63901 "Basic Engine returned error number
62704 "Unexpected response from Basic Engine" 0xerrornumber"
62705 "BE read EEPROM; invalid input" 63902 "Parity error from Basic Engine to Serial"
62800 "" 63903 "Communication time-out error"
62801 "Basic Engine returned error number 63904 "Unexpected response from Basic Engine"
0xerrornumber" 64000 "BE OPU number = opunumber"
62802 "Parity error from Basic Engine to Serial" 64001 "Basic Engine returned error number
62803 "Communication time-out error" 0xerrornumber"
62804 "Unexpected response from Basic Engine" 64002 "Parity error from Basic Engine to Serial"
62805 "BE write EEPROM; invalid input" 64003 "Communication time-out error"
62900 "" 64004 "Unexpected response from Basic Engine"
62901 "Basic Engine returned error number 64100 "The data was successfully written on and read
0xerrornumber" from a DVD disc"
62902 "Parity error from Basic Engine to Serial" 64101 "The tray-in command failed"
62903 "Communication time-out error" 64102 "The read-TOC command failed"
62904 "Unexpected response from Basic Engine" 64103 "The VSM interrupt initialisation failed"
62905 "Radial loop could not be closed" 64104 "The set irq command failed"
63000 "" 64105 "No disc or wrong disc inserted"
63001 "Basic Engine returned error number 64106 "The rec-pause command failed"
0xerrornumber" 64107 "The VSM BE out DMA initialisation failed"
63002 "Parity error from Basic Engine to Serial" 64108 "The VSM BE out initialisation failed"
63003 "Communication time-out error" 64109 "The VSM BE out DMA start failed"
63004 "Unexpected response from Basic Engine" 64110 "The VSM BE out start failed"
64111 "The rec command failed"

64112 "The VSM out underrun error occurred" 71001 "Test of the AV Selector on the Analogue Board
64113 "The record complete interrupt was not raised" fails."
64114 "The get irq command failed" 71002 "Communication with Analogue Board fails"
64115 "There was no interrupt raised by BE" 71100 "NVRAM test OK"
64116 "The VSM DMA did not finished" 71101 "Test of the NVRAM on the Analogue Board fails."
64117 "The stop command after writing failed" 71102 "Communication with Analogue Board fails"
64118 "The VSM Sector processor initialisation failed" 71200 "Video routing on the Analogue Board OK"
64119 "The VSM sector processor DMA initialisation 71201 "Routing the video on the Analogue Board fails."
failed" 71202 "Invalid input."
64120 "The VSM sector processor DMA start failed" 71203 "Communication with Analogue Board fails"
64121 "The VSM sector processor start failed" 71300 "Audio routing on the Analogue Board OK"
64122 "The seek command failed" 71301 "Routing the audio on the Analogue Board fails."
64123 "The VSM sector processor error occurred" 71302 "Invalid input."
64124 "The read timeout occurred" 71303 "Communication with Analogue Board fails"
64125 "The stop command after reading failed" 71500 ""
64126 "There was a difference found in data at a specific 71501 "Invalid slash version, default slash version is set."
disc sector" 71502 "Setting the slash version on the Analogue Board
64127 "The result of the self test contains errors" fails."
64128 "An error interrupt was raised by BE" 71503 "Communication with Analogue Board fails"
64129 "The calibrate-record command failed" 71600 "ApplicationVersion"
64130 "To many retries" 71601 "Can not find segment in FLASH ROM on the Ana-
64131 "BE update RAI command after writing failed" logue Board"
64132 "BE find first recordable address command failed" 71602 "Communication with Analogue Board fails"
64133 "DVD+R disc is full" 71700 "DiagnosticsVersion"
64200 "" 71701 "Can not find segment in FLASH ROM on the Ana-
logue Board"
64201 "BE i2c initialisation failed"
71702 "Communication with Analogue Board fails"
64202 "This nucleus cannot be executed because the
Self-Test failed" 71800 "DownloadVersion"
70000 "Echo test OK" 71801 "Can not find segment in FLASH ROM on the Ana-
logue Board"
70001 "Echo test returned wrong string."
72300 ""
70300 "SoftwareVersion"
72000 ""
70301 "Can not find segment in FLASH ROM on the Ana-
logue Board" 72001 "Adjusting BarGraphLevel failed"
70302 "Communication with Analogue Board fails" 72002 "Communication with Analogue Board fails"
70400 "HardwareVersion" 72100 ""
70401 "Can not find segment in FLASH ROM on the Ana- 72101 "Storing clock correction failed"
logue Board" 72102 "Value out of range : default value stored "
70402 "Communication with Analogue Board fails" 72103 "Invalid input."
70500 "Clock adjusted OK" 72104 "Communication with Analogue Board fails"
70501 "Can not adjust the clock on the Analogue Board." 72200 ""
70502 "Wrong date/time text size." 72201 "Initialising the 1Hz signal on the Clock IC failed"
70503 "Communication with Analogue Board fails" 72202 "Communication with Analogue Board fails"
70600 "Tuner accessibility test OK" 72301 "Clearing the NVRAM on the Analogue Board fails"
70601 "Can not access tuner on the Analogue Board." 72302 "Communication with Analogue Board fails"
70602 "Communication with Analogue Board fails" 72400 "segment checksum is : checksum which is cor-
70700 "Frequency download OK" rect" for every segment
70701 "Wrong frequency table size." 72401 "segment could not be found" or "segment check-
sum is : checksumC ,however it should be : check-
70702 "Can not download the frequency table into the an-
sumE" for every segment
alogue NVRAM."
70703 "Can not download the frequency table into the an-
alogue NVRAM." 72900 "Date received"
70704 "Communication with Analogue Board fails" 72901 "Data returned"
70800 "Data slicer test OK" 72902 "Communication on I2C-bus failed on the Ana-
logue Board fails."
70801 "Test of the Data slicer on the Analogue Board
fails." 72903 "Communication with Analogue Board fails"
70802 "Communication with Analogue Board fails" 73000 ""
70900 "Sound Processor test OK" 73001 "Storing the external presets on the Analogue
Board fails"
70901 "Test of the Sound Processor on the Analogue
Board fails." 73002 "Communication with Analogue Board fails"
70902 "Communication with Analogue Board fails" 73100 "0xslashversion" where slashversion is the slash
version read from the analogue board
71000 "AV Selector test OK"
73101 "Error while reading out slash version."

73102 "I2C Write error." 80311 "We tried to receive a reply for
73103 "I2C Read error." DVIO_MAX_RETRIES_ACKREPLY times !!"
73104 "Communication with Analogue Board fails" 80312 "We tried to receive a reply for
DVIO_MAX_RETRIES_REPLY times !!"
73200 ""
80313 "We tried to receive an Ack for
73201 "Storing the Reference Voltage for the Tuner
DVIO_MAX_RETRIES_ACK times!!"
failed"
80314 "VSM UART error timeout transmitting command"
73202 "Invalid input."
80315 "VSM UART error timeout receiving reply"
80316 "VSM UART frame error occurred receiving from
80000 "The DVIO module is present in the system."
DVIO board"
80001 "The DVIO module is not present in the system."
80317 "VSM UART parity error occurred receiving from
80100 "The DVIO module has been reset OK."
DVIO board"
80101 "The DVIO module is not present in the system."
80318 "The confirmation/indication from the DVIO module
80102 "The DVIO module could not be reset." is invalid."
80103 "Could not initialise I2C before Reset." 80400 "The accessibility of the DVIO module is OK."
80200 "The accessibility of the DVIO module is OK." 80401 "The DVIO board is not present in this DVDR."
80201 "The DVIO board is not present in this DVDR." 80402 "Could not initialise I2C."
80202 "Could not initialise I2C." 80403 "Unable to reset the DVIO module."
80203 "Unable to reset the DVIO module." 80404 "Unable to receive the reset indication from the
80204 "Unable to receive the reset indication from the DVIO module."
DVIO module." 80405 "Unable to send the configuration to the DVIO
80205 "Unable to send the configuration to the DVIO module."
module." 80406 "Unable to download the chip ID to the DVIO mod-
80206 "Unable to download the chip ID to the DVIO module."
ule." 80407 "Unable to set the mode of the DVIO module to
80207 "Unable to set the mode of the DVIO module to IDLE."
IDLE." 80408 "Software Error in function HandleStateAwaitin-
80208 "Software Error in function HandleStateAwaitin- gReply !!"
gReply !!" 80409 "Maximal number of retries reached by HandleS-
80209 "Maximal number of retries reached by HandleS- tateSending !!"
tateSending !!" 80410 "Maximal number of retries (NACKs) reached
80210 "Maximal number of retries (NACKs) reached (HandleStateSending)"
(HandleStateSending)" 80411 "We tried to receive a reply for
80211 "We tried to receive a reply for DVIO_MAX_RETRIES_ACKREPLY times !!"
DVIO_MAX_RETRIES_ACKREPLY times !!" 80412 "We tried to receive a reply for
80212 "We tried to receive a reply for DVIO_MAX_RETRIES_REPLY times !!"
DVIO_MAX_RETRIES_REPLY times !!" 80413 "We tried to receive an Ack for
80213 "We tried to receive an Ack for DVIO_MAX_RETRIES_ACK times!!"
DVIO_MAX_RETRIES_ACK times!!" 80414 "VSM UART error timeout transmitting command"
80214 "VSM UART error timeout transmitting command" 80415 "VSM UART error timeout receiving reply"
80215 "VSM UART error timeout receiving reply" 80416 "VSM UART frame error occurred receiving from
80216 "VSM UART frame error occurred receiving from DVIO board"
DVIO board" 80417 "VSM UART parity error occurred receiving from
80217 "VSM UART parity error occurred receiving from DVIO board"
DVIO board" 80418 "The confirmation/indication from the DVIO module
80218 "The confirmation/indication from the DVIO module is invalid."
is invalid." 80500 ""
80300 "The accessibility of the DVIO module is OK." 80501 "The DVIO board is not present in this DVDR."
80301 "The DVIO board is not present in this DVDR." 80502 "The I2C could not be initialised."
80302 "Could not initialise I2C." 80503 "The DVIO module could not be reset."
80303 "Unable to reset the DVIO module." 80504 "Unable to receive the reset indication from the
80304 "Unable to receive the reset indication from the DVIO module."
DVIO module." 80505 "Unable to send the configuration to the DVIO
80305 "Unable to send the configuration to the DVIO module."
module." 80506 "Unable to download the chip ID to the DVIO mod-
80306 "Unable to download the chip ID to the DVIO module."
ule." 80507 "Unable to set the mode of the DVIO module to
80307 "Unable to set the mode of the DVIO module to IDLE."
IDLE." 80508 "Software Error in HandleStateAwaitingReply func-
80308 "Software Error in function HandleStateAwaitin- tion!"
gReply !!" 80509 "Maximal number of retries reached by HandleS-
80309 "Maximal number of retries reached by HandleS- tateSending!"
tateSending !!" 80510 "Maximal number of retries (NACK's) reached
80310 "Maximal number of retries (NACKs) reached "(HandleStateSending)
(HandleStateSending)" 80511 "We tried to receive a reply for
DVIO_MAX_RETRIES_ACKREPLY times!"

80512 "We tried to receive a reply for 80709 "Maximal number of retries reached by HandleS-
DVIO_MAX_RETRIES_REPLY times!" tateSending!"
80513 "We tried to receive an Acknowledge for 80710 "Maximal number of retries (NACK's) reached
DVIO_MAX_RETRIES_ACK times!" "(HandleStateSending)
80514 "VSM UART error timeout transmitting command" 80711 "We tried to receive a reply for
80515 "VSM UART error timeout receiving reply" DVIO_MAX_RETRIES_ACKREPLY times!"
80516 "VSM UART frame error occurred receiving from 80712 "We tried to receive a reply for
DVIO board" DVIO_MAX_RETRIES_REPLY times!"
80517 "VSM UART parity error occurred receiving from 80713 "We tried to receive an Acknowledge for
DVIO board" DVIO_MAX_RETRIES_ACK times!"
80518 "The confirmation/indication from the DVIO module 80714 "VSM UART error timeout transmitting command"
is invalid." 80715 "VSM UART error timeout receiving reply"
80519 "Setting the DVIO module in/out diagnostics mode 80716 "VSM UART frame error occurred receiving from
failed" DVIO board"
80520 "Invalid input" 80717 "VSM UART parity error occurred receiving from
80521 "Getting the errors of the self-test failed" DVIO board"
80522 "Self-test failed" 80718 "The confirmation/indication from the DVIO module
is invalid."
80600 ""
80719 "Setting the DVIO module in/out diagnostics mode
80601 "The DVIO board is not present in this DVDR."
failed"
80602 "The I2C could not be initialised."
90121 "Error: audio data in host memory contains wrong
80603 "The DVIO module could not be reset." frequency: frequency Hz"
80604 "Unable to receive the reset indication from the 90122 "Error: audio data in host memory contains si-
DVIO module."
lence!"
80605 "Unable to send the configuration to the DVIO
90123 "There is no correct audio frame in the buffer"
module."
90124 "The audio frame has an illegal version bit"
80606 "Unable to download the chip ID to the DVIO mod-
90125 "The audio frame has an illegal bitrate-index"
ule."
90126 "The audio frame has an illegal sampling rate"
80607 "Unable to set the mode of the DVIO module to
IDLE." 90127 "The CRC of the audio frame is wrong"
80608 "Software Error in HandleStateAwaitingReply func- 90128 "The audio frame is not MPEG-I layer II !"
tion!" 90129 "Error cannot de-mute DAC on analogue board"
80609 "Maximal number of retries reached by HandleS- 90200 ""
tateSending!" 90201 "Initialisation of I2C failed"
80610 "Maximal number of retries (NACK's) reached 90202 "Initialisation of VIP and EMPIRE failed"
"(HandleStateSending)
90203 "Initialisation of PLL / Link failed."
80611 "We tried to receive a reply for
90204 "Next descriptor address set wrong."
DVIO_MAX_RETRIES_ACKREPLY times!"
90205 "Turning on the colourbar failed"
80612 "We tried to receive a reply for
DVIO_MAX_RETRIES_REPLY times!" 90206 "No I2C communication possible to start video en-
coder."
80613 "We tried to receive an Acknowledge for
90207 "Starting the video encoder failed."
DVIO_MAX_RETRIES_ACK times!"
90208 "Transfer of data from video encoder to VSM
80614 "VSM UART error timeout transmitting command"
failed."
80615 "VSM UART error timeout receiving reply"
90209 "Stopping the encoder failed."
80616 "VSM UART frame error occurred receiving from
DVIO board" 90210 "Turning off the colourbar failed."
80617 "VSM UART parity error occurred receiving from 90211 "Cannot intialize hostdecoder parallel input"
DVIO board" 90212 "Cannot initialise VSM AV-out DMA port"
80618 "The confirmation/indication from the DVIO module 90213 "Cannot initialise VSM AV-out port"
is invalid." 90214 "Cannot start VSM AV-out DMA port"
80619 "Setting the DVIO module in/out diagnostics mode 90215 "Cannot start VSM AV-out port"
failed" 90216 "Transfer of data from VSM to host decoder failed."
80700 "" 90217 "VSM and Hostdec memory do not match (com-
80701 "The DVIO board is not present in this DVDR." pared after transfer)"
80702 "The I2C could not be initialised." 90218 "Decoding of the video data in the hostdecoder
80703 "The DVIO module could not be reset." memory failed"
80704 "Unable to receive the reset indication from the 90219 "The data in the hostdecoder is not equal to a col-
DVIO module." ourbar"
80705 "Unable to send the configuration to the DVIO 90220 "The video encoder did not return the Group Of
module." Picture count."
80706 "Unable to download the chip ID to the DVIO mod- 90221 "The video encoder did not receive data from the
ule." VIP."
80707 "Unable to set the mode of the DVIO module to 90223 "Initialisation of VIP and EMPRESS failed"
IDLE." 90224 "The video encoder did not return the current sta-
80708 "Software Error in HandleStateAwaitingReply func- tus."
tion!"

90225 "The video encoder timed out in BUSY mode. (no 90429 "The video encoder did not switch from IDLE to
VIP input)" STOP mode."
90226 "The video encoder did not return the current bi- 90500 ""
trate." 90501 "Initialisation of I2C failed"
90227 "The video encoder did not switch to ENCODING 90502 "I2C communication to VIP failed"
mode." 90503 "Initialisation of VIP failed"
90228 "The video encoder could not start from STOP/ 90504 "Generation of Close Caption data failed"
IDLE mode."
90505 "VIP not locked to video signal"
90229 "The video encoder did not switch from IDLE to
90506 "Initialisation of VBI Extractor failed
STOP mode."
90507 "No CC data received"
90300 ""
90508 "Closed Caption data overrun"
90301 "Initialisation of I2C failed"
90509 "Closed Caption data does not match"
90302 "I2C communication to VIP failed"
90510 "Switch off ColourBar failed"
90303 "Initialisation of VIP failed"
90304 "Generation of Close Caption data failed"
failed."
90305 "VIP not locked to video signal"
90600 ""
90306 "Initialisation of VBI Extractor failed
90601 "Initialisation of I2C failed"
90307 "No CC data received"
90602 "Initialisation of VIP and EMPIRE failed"
90308 "Closed Caption data overrun"
90603 "Initialisation of PLL / Link failed."
90604 "Next descriptor address set wrong."
90605 "Turning on the colourbar failed"
90400 ""
90606 "No I2C communication possible to start video en-
90401 "Initialisation of I2C failed" coder."
90402 "Initialisation of VIP and EMPIRE failed" 90607 "Starting the video encoder failed."
90403 "Initialisation of PLL / Link failed." 90608 "Transfer of data from video encoder to VSM
90404 "Next descriptor address set wrong." failed."
90405 "Turning on the colourbar failed" 90609 "Stopping the encoder failed."
90406 "No I2C communication possible to start video en- 90610 "Turning off the colourbar failed."
coder." 90611 "Cannot intialize hostdecoder parallel input"
90407 "Starting the video encoder failed." 90612 "Cannot initialise VSM AV-out DMA port"
90408 "Transfer of data from video encoder to VSM
90613 "Cannot initialise VSM AV-out port"
failed."
90614 "Cannot start VSM AV-out DMA port"
90409 "Stopping the encoder failed."
90615 "Cannot start VSM AV-out port"
90410 "Turning off the colourbar failed."
90616 "Transfer of data from VSM to host decoder failed."
90411 "Cannot intialize hostdecoder parallel input"
90617 "VSM and Hostdec memory do not match (com-
90412 "Cannot initialise VSM AV-out DMA port" pared after transfer)"
90413 "Cannot initialise VSM AV-out port" 90618 "Decoding of the video data in the hostdecoder
90414 "Cannot start VSM AV-out DMA port" memory failed"
90415 "Cannot start VSM AV-out port" 90619 "The data in the hostdecoder is not equal to a col-
90416 "Transfer of data from VSM to host decoder failed." ourbar"
90417 "VSM and Hostdec memory do not match (com- 90620 "The video encoder did not return the Group Of
pared after transfer)" Picture count."
90418 "Decoding of the video data in the hostdecoder 90621 "The video encoder did not receive data from the
memory failed" VIP."
90419 "The data in the hostdecoder is not equal to a col- 90622 "Execution of the command on the analogue board
ourbar" failed."
90420 "The video encoder did not return the Group Of 90623 "Initialisation of VIP and EMPRESS failed"
Picture count." 90624 "The video encoder did not return the current sta-
90421 "The video encoder did not receive data from the tus."
VIP." 90625 "The video encoder timed out in BUSY mode. (no
90422 "Execution of the command on the analogue board VIP input)"
failed." 90626 "The video encoder did not return the current bi-
90423 "Initialisation of VIP and EMPRESS failed" trate."
90424 "The video encoder did not return the current sta- 90627 "The video encoder did not switch to ENCODING
tus." mode."
90425 "The video encoder timed out in BUSY mode. (no 90628 "The video encoder could not start from STOP/
VIP input)" IDLE mode."
90426 "The video encoder did not return the current bi- 90629 "The video encoder did not switch from IDLE to
trate." STOP mode."
90427 "The video encoder did not switch to ENCODING 90700 ""
mode." 90701 "Initialisation of I2C failed"
90428 "The video encoder could not start from STOP/ 90702 "I2C communication to VIP failed"
IDLE mode."
90703 "Initialisation of VIP failed"
90704 "Generation of Close Caption data failed"

90705 "VIP not locked to video signal" 90919 "Error transfer data from VSM to host decoder"
90706 "Initialisation of VBI Extractor failed 90920 "Error: audio data in host memory and VSM mem-
90707 "No CC data received" ory differ"
90708 "Closed Caption data overrun" 90921 "Error: audio data in host memory contains wrong
frequency: frequency Hz"
90922 "Error: audio data in host memory contains si-
lence!"
failed."
90800 ""
90801 "Error routing the audio back to the digital board."
90926 "The audio frame has an illegal sampling rate"
90802 "Error cannot initialise I2C"
90927 "The CRC of the audio frame is wrong"
90803 "Error cannot initialise VIP"
90928 "The audio frame is not MPEG-I layer II !"
90804 "Error cannot set ADC enable pin"
90929 "Error cannot de-mute DAC on analogue board"
90805 "Error cannot set VSM audio clock"
140000 ""
90806 "Error preparing the 12kHz audio-sine"
140001 "I2C to Clock failed" or "I2C initialisation failed"
90807 "Error cannot initialise audio encoder"
140100 ""
90808 "Error cannot initialise VSM audio in port"
140101 "I2C to Clock failed" or "I2C initialisation failed"
90809 "Error cannot initialise VSM audio in DMA port"
141200 ""
90810 "Error cannot initialise VSM audio out DMA port"
141201 "Progressive Scan Board I2C bus busy"
90811 "Error cannot initialise audio VSM out port"
141211 "Progressive Scan Board I2C FLI2200 bus busy"
90812 "Error cannot initialise host decoder audio in"
141212 "Progressive Scan Board I2C FLI2200 read access
90813 "Error loop audio user/dealer cannot start audio en-
time-out"
coder"
141213 "Progressive Scan Board I2C FLI2200 no read ac-
90814 "Error cannot start VSM audio in DMA port"
knowledge"
90815 "Error starting the 12kHz audio-sine"
141214 "Progressive Scan Board I2C FLI2200 read failed"
90816 "Error transfer data from audio encoder to VSM"
141215 "Progressive Scan Board I2C FLI2200 write ac-
90817 "Error cannot start VSM AV out DMA port"
cess time-out"
90818 "Error cannot start VSM AV out port"
141216 "Progressive Scan Board I2C FLI2200 no write ac-
90819 "Error transfer data from VSM to host decoder" knowledge"
90820 "Error: audio data in host memory and VSM mem- 141217 "Progressive Scan Board I2C FLI2200 write failed"
ory differ"
141218 "Progressive Scan Board I2C FLI2200 failed"
90821 "Error: audio data in host memory contains wrong
141221 "Progressive Scan Board I2C AD7196 bus busy"
frequency: frequency Hz"
141222 "Progressive Scan Board I2C AD7196 read access
90822 "Error: audio data in host memory contains si-
time-out"
lence!"
141223 "Progressive Scan Board I2C AD7196 no read ac-
knowledge"
141224 "Progressive Scan Board I2C AD7196 read failed"
141225 "Progressive Scan Board I2C AD7196 write ac-
90826 "The audio frame has an illegal sampling rate" cess time-out"
90827 "The CRC of the audio frame is wrong" 141226 "Progressive Scan Board I2C AD7196 no write ac-
90828 "The audio frame is not MPEG-I layer II !" knowledge"
90829 "Error cannot de-mute DAC on analogue board" 141227 "Progressive Scan Board I2C AD7196 write failed"
90900 "" 141228 "Progressive Scan Board I2C AD7196 failed"
90901 "Error routing the audio back to the digital board." 141300 ""
90902 "Error cannot initialise I2C" 141301 "Progressive Scan Route Enable failed"
90903 "Error cannot initialise VIP" 141302 "Generating test image in Hostdecoder failed"
90904 "Error cannot set ADC enable pin" 141400 ""
90905 "Error cannot set VSM audio clock" 141401 "Progressive Scan Route Disable failed"
90906 "Error preparing the 12kHz audio-sine" 141402 "Turning off test image in Hostdecoder failed"
90907 "Error cannot initialise audio encoder" 141500 ""
90908 "Error cannot initialise VSM audio in port" 141501 "Progressive Scan Board I2C failed"
90909 "Error cannot initialise VSM audio in DMA port" 141600 ""
90910 "Error cannot initialise VSM audio out DMA port" 141601 "Progressive Scan Board I2C failed"
90911 "Error cannot initialise audio VSM out port"
90912 "Error cannot initialise host decoder audio in" 5.5 Loop tests
90913 "Error loop audio user/dealer cannot start audio en-
coder" The following loops can be distinguished:
90914 "Error cannot start VSM audio in DMA port" • Loops performed on the digital board only
90915 "Error starting the 12kHz audio-sine" • User Dealer loops performed on the digital and analogue
90916 "Error transfer data from audio encoder to VSM" board
• System loops performed via an external connection:
90917 "Error cannot start VSM AV out DMA port"
outputs are looped back to the inputs.
90918 "Error cannot start VSM AV out port"
5.5.1 Nucleus 900: Digital Audio Loop
This nucleus tests the audio path through the digital board NUCLEUS 901: AUDIO USER DEALER LOOP
NUCLEUS 900: AUDIO LOOP DIGITAL
ANALOGUE BOARD
ANALOGUE BOARD
7507 7002
STV6410
7004
ADC 7100
DAC
1900 1900
connector connector
1602 1602
connector connector
DIGITAL BOARD
7500 I2S I2S
7200
VIP STI 5508
DIGITAL BOARD
7500
7200
VIP_ICLK: 27MHz
VIP STI 5508
VIP_ICLK: 27MHz
7403 7100
EMPRESS VSM
7403 7100
EMPRESS VSM
GND CL 16532145_037.eps
031201
CL 16532145_036.eps
031201 Figure 5-10
Figure 5-9
5.5.2 Nucleus 901: Audio User Dealer Loop
A PCM audio sine of 12kHz is generated in the Host Decoder

for a while and sent to the analogue board. The signal coming
from the analogue board is encoded again and sent to the
memory of the host decoder for comparison. This nucleus tests
the components on the audio signal path:
• Host decoder
• Flex connection between connector 1602 (digital board)
and connector 1900 (analogue board)
• DAC
• Op-amp
• Scart switch IC
• ADC
• Audio Encoder
• VIP
• VSM
5.5.3 Nucleus 902: Digital Video Loop
A colourbar generated in the host decoder is looped through

the VIP, Empire, and VSM and checked again in the host
decoder. The following components are tested on the video
signal path:
• VIP
• Empire
• VSM
• Host decoder
NUCLEUS 902: DIGITAL VIDEO LOOP
ANALOGUE BOARD
7507
STV6410
DIGITAL BOARD
7500 7200
VIP STI 5508

VIP_ICLK: 27MHz
7403 7100
EMPRESS VSM
CL 16532145_038.eps
031201
Figure 5-11
5.5.4 Nucleus 903: Digital Video VBI Loop 5.5.5 Nucleus 904: System Video Loop
Nucleus for testing the components on the video VBI signal Nucleus for testing the components on the video signal system
path: path:
• The VIP • The VIP
• The VSM • The video encoder
• The Host Decoder • The VSM
This is done by using the internal test signal source (digital • The host decoder
board only) • The analogue board
Remark: this test is only successful if nucleus 121 is carried out On the analogue board the video signal will be routed to the
first. SCART (EUROPE) or CINCH (NAFTA). There it will be looped
back externally by means of the proper cable
NUCLEUS 903: DIGITAL VIDEO VBI LOOP

NUCLEUS 904: SYSTEM VIDEO LOOP
ANALOGUE BOARD
SCART AUX SCART TV

ANALOGUE BOARD
7507
STV6410 7507
STV6410
1954 1954
connector connector
DIGITAL BOARD
1601 1601
7500 7200 connector connector
VIP 7500
VIP_ICLK: 27MHz STI 5508 DIGITAL BOARD 7200
VIP
VIP_ICLK: 27MHz STI 5508
7403 7100
VSM 7403 7100

EMPRESS
EMPRESS VSM
CL 16532145_039.eps
031201
CL 16532145_040.eps
121201
Figure 5-12
Figure 5-13
5.5.6 Nucleus 905: System Video VBI Loop 5.5.7 Nucleus 906: Video User Dealer Loop
This nucleus tests the components on the video signal path: Nucleus for testing the components on the video signal system
• The VIP path:
• The VSM • The VIP
• The Host Decoder • The video encoder
The video CVBS signal is routed to the output of the analogue • The VSM
board where it will be looped back by means of an external • The host decoder
cable • The analogue board
Remark: this test is only successful if nucleus 121 is carried out On the analogue board, the video signal is internally routed
first. back to the digital board.
NUCLEUS 905: SYSTEM VIDEO VBI LOOP NUCLEUS 906: VIDEO USER DEALER LOOP
SCART AUX SCART TV

ANALOGUE BOARD ANALOGUE BOARD
7507
7507
STV6410
STV6410
1954 1954 1954 1954
connector connector connector connector
1601 1601 1601 1601

DIGITAL BOARD
7500 DIGITAL BOARD 7200 7500
7200
VIP VIP STI 5508

VIP_ICLK: 27MHz STI 5508 VIP_ICLK: 27MHz
7403 7100 7403 7100
EMPRESS VSM EMPRESS VSM
CL 16532145_041.eps CL 16532145_042.eps
031201 031201
Figure 5-14 Figure 5-15

5.5.8 Nucleus 907: Video VBI User Dealer Loop 5.5.9 Nucleus 908: System Audio Loop Scart (Europe)
This nucleus tests the components on the video VBI signal Nucleus for testing the components on the audio signal path:
path: • The hostdecoder
• The VIP • The analogue board
• The VSM • The audio encoder
• The Host Decoder • The VSM
The signal is routed back internally on the analogue board On the analogue board, audio is passed to the SCART
Remark: this test is only successful if nucleus 121 is carried out connector, where a SCART cable needs to be used to loop
first. back the audio signal to the digital board
NUCLEUS 907: VIDEO VBI USER DEALER LOOP NUCLEUS 908: SYSTEM AUDIO LOOP SCART
SCART AUX SCART TV

ANALOGUE BOARD ANALOGUE BOARD
7507
7507
STV6410
7002
STV6410 7004 7100
ADC DAC
1954 1954
1900 1900
connector connector
connector connector
1601 1601 1602 1602

DIGITAL BOARD DIGITAL BOARD
7500 7200 7500
7200
VIP VIP
VIP_ICLK: 27MHz STI 5508 VIP_ICLK: 27MHz STI 5508
7403
7100 7100
7403 EMPRESS
VSM VSM
EMPRESS
CL 16532145_043.eps CL 16532145_044.eps
031201 121201
Figure 5-16 Figure 5-17

5.5.10 Nucleus 909: System Audio Loop CINCH (Nafta)
Nucleus for testing the components on the audio signal path:

• The hostdecoder
• The analogue board
• The audio encoder
• The VSM
On the analogue board the audio is passed to the CINCH
connector, where a CINCH cable needs to be used to loop back
the audio signal to the digital board
NUCLEUS 909: SYSTEM AUDIO LOOP CINCH
CINCH IN CINCH OUT

(NAFTA) (NAFTA)
ANALOGUE BOARD
7507
7002
STV6410
7004 7100
ADC DAC
1900 1900
connector connector
1602 1602
connector connector
DIGITAL BOARD
7500
7200
VIP
VIP_ICLK: 27MHz STI 5505
7403
7100
EMPRESS
VSM
CL 16532145_045.eps
031201
Figure 5-18
5.6 Faultfinding Trees
5.6.1 General
PLAYBACK MODE
Plug Recorder
to the mains.
No disc loaded
Standby LED changes Check PSU(see chapter 5.6.2)

NOK
from green to red. Check Analog PCB(see chapter 5.6.4)
Display shows time Check Front PCB(see chapter 5.6.5)
OK
Press "STOP" button
Standby LED changes

from Red to Green. NOK Check Trade Mode(see chapter 5.2.4)
Display shows successively Check Front PCB(see chapter 5.6.5)
"READING" Check Digital PCB(see chapter 5.6.3)
"NO DISC"
OK
Press "OPEN/CLOSE" button
Display shows successively

"OPENING" NOK Check Front PCB(see chapter 5.6.5)
"TRAY OPEN" Check Basic Engine(see chapter 5.6.3)
Tray is open
OK
Insert DVD Disc

Press "OPEN/CLOSE" button
Display shows successively

"CLOSING" NOK Check Digital PCB(see chapter 5.6.3)
"READING"
Check Basic Engine(see chapter 5.6.3)
Recorder starts playback of
DVD-disc
OK
NOK Check Digital PCB(see chapter 5.6.3)
Audio & Video OK ?
Check Analog PCB(see chapter 5.6.4)
OK
Playback DVD OK CL 16532095_243.eps

170801
Figure 5-19
RECORD MODE
Insert DVDR Disc
Display shows:
- Disc content
NOK
- Source - Check Basic Engine(see chapter 5.6.3)
- DVD+RW
- Disc Bar
OK
Press NEXT button to

select empty title
Press "RECORD" button
- Check Analog PCB(see chapter 5.6.4)

NOK - Check Digital PCB(see chapter 5.6.3)
Recording starts - Check Basic Engine(see chapter 5.6.3)
OK - Check DVDR Disc
Press "STOP" button
Menu update
NOK - Check Basic Engine(see chapter 5.6.3)

Check recorded title - Check DVDR Disc
OK
Recording OK CL 16532095_242.eps
170801
Figure 5-20
5.6.2 Power Supply
Remove all the connectors from the PSU

Check DC voltages on connector 0205:
+12Vstby, +5V2stby, -5Nstby, -Vgnstby, +33Vstby
None of the voltages are present +12Vstby and +5V2stby are oke. All voltages are present.
Check +12Vreg circuit: Check +33Vstby circuit: Standby voltages are oke. Check DC
- D6210, C2210, C2212 - D6200, C2200, R3200, D6201, R3201 voltages on connectors 0207 and 0209.
Check +Vreg circuit: Check -5Nstby circuit: Connector 0207:
- D6240, C2240, C2242 - D6220, C2220, IC7220, C2222, C2221 +3V3, +5V, -5V, +12V.
Check Prot_3V3 circuit: Check FLYB circuit: Connector 0209:
- D6215, C2214, C2215, - D6221, T7241, R3220, R3221, R3222, +3V3, +12V, +5V, -5V, STBY_ctrl.
- R3520, R3521, D6520 R3223.
Check -Vgnstby circuit: If not oke, check supply path of failed
Connect PSU to a mains isolated variac. - D6230, C2230, R3230, D6231, R3233, supply voltages.
Turn the input voltage up and measure R3234, C2235.
voltage across C2125. Do not exceed
max. mains voltage indicated on player.
This voltage must be +/- 1.41 x Vin AC.
Check if STBY_ctrl is LOW.
- Check standby control path via digital
board to analog board.
Check primary circuit:
- F1120, D6151, D6152, D6153, D6154,
- R3120, L5120, L5520, C2125.
If fuse 1120 is defective, always check Check +12V circuit:

Q7125, D6145, T7140, Rsense (R3133, must be present for the other voltages
R3134, R3135, R3136 and R3137). - Q7511, T7512, D6511, D6512,
- R3511, R3513, R3514, L551, C2512.
Check with an oscilloscope Vds and Vg Check +3V3 circuit:
of Q7125. - Q7520, Q7521, L5520, C2521, F1520,
- R3522, R3523, R3524, R3525, C2520.
Check +5V circuit:
- Q7501, Q7502, L5501, C2502, R3501
NO - R3502, R3503, R3504, C2540.
Is PSU ticking?
Check +3V3E circuit:
- Q7505, Q7506, D6505, L5505, C2506,
YES - R3505, R3506, R3507, R3508, C2502.
Check -5V circuit:
Check start-up circuit: - Q7515, D6515, L5515, C2515, R3515.
Check power switch circuit:
- Q7125, D6130, D3131, D6132 - R3125, R3126, R3141, R3132
- D6145, D6146, L5125 - Q7125, L5131, R3150, C2146
- C2136
- R3131, R3132, R3133, R3134 If oke, the power supply seems to be ok.
- R3135, R3136, R3137, R3146 Check the other boards in the player
for the cause of the overload.
Check Control circuit
- T7140, D6141, D6142, L5131,
- C2144, C2145, C2147, C2151
- R3151, R3147, R3148, R3150
Check Regulation circuit

- T7251, Q7200, R3250, R3253
- R3254, R3255, R3256, C2251
Check Overvoltage circuit

- T7142, D6143, D6144,
- R3149, R3144, C2152, C2142
Check Overload circuit

- T7141, T7143, R3145, R3143,
- R3142, C2143.
CL 16532095_085.eps
150801
Figure 5-21
Digital board
5.6.3 Digital Board
Start-up DSW
START UP DSW
NOT OK
OK
Check Power Supplies on con. 1900 NOK - Check connection to PSU

(ION should be LOW) - Check Power Supply
OK
Check that Sysclk_5505 on I819 - Check IC 7202

NOK
appears earlier then Resetn_5505 - Check IC 7916-C
is high on I202 - Check IC 7801
OK
Check VDD_STi(+3V3) on I272 - Check IC 7202

NOK
Check VDDA(+3V3) on I275 - Check R 3266
Check VDDA_PCM(+3V3) on I252 - Check L 5200, 5201 and 5202
OK
Check EMI_PROCCLK(50MHz) NOK

- Check IC 7100
on I181
OK
Check if F201 is HIGH and I201 is LOW NOK - Check IC 7202

Check if I208 is LOW and I209 is HIGH - Check L 5200
OK
Check TCK (HIGH) on I247

Check TDI (HIGH) on I248 NOK
- Check IC 7202
Check TMS (HIGH) on I249
Check TRST (LOW) on I250
OK
NOK
Check if service pin is LOW on testpoint I207 - Check Jumper 4206
OK
Check VDD_MEM(+3V3) on I306 NOK - Check L 5300

Check VDD_MEM1(+3V3) on I310 - Check L 5302
OK
Check VCC3_VSM(+3V3) on I100 NOK - Check L 5100

Check VCC3_VSM_MEM(+3V3) on I141 - Check L 5101
OK
Check LOW pulses on EMI_CE3n NOK - Check IC 7202

on pin 126 of IC 7202 - Check IC 7305
OK
Check activity on EMI_CE3n(pin1 of IC 7305) - Check IC 7305

NOK
Check activity on ROMH_CEn(pin6 of IC 7305) - Check IC 7301
Check activity on EMI_OEn(pin29 of IC 7301) - Check IC 7202
OK
- Check IC 7202
Check if FLASH_OEn is LOW on I245 NOK
- Check IC 7302 and IC 7304
Check if EMI_RWn is HIGH(pin133 of IC7202)
- Check IC 7100
OK
Check for short circuits or open circuits on the

IC pins which are connected to the EMI-bus
OK
START UP DSW
CL 16532095_086.eps
OK 150801
Figure 5-22
Power Part Check
POWER PART CHECK DIGITAL BOARD
USE DIGITAL BOARD CIRCUIT DIAGRAMS 1 2, 3, 4, 5, 7 AND 8 AND DIGITAL BOARD BOTTOM VIEW TESTPOINTS
Power On and exit

stand-by mode
OK
Check +3V3 on Testpoints I905

Check +12V on Testpoint I907 NOK - Check connection to PSU
Check +5V on Testpoint I906 - Check PSU
Check -5V on Testpoint I908
OK
NOK
Vcc3_VSM(+3V3) on testpoint I100 check L5100
NOK
Vcc3_VSM_mem(+3V3) on testpoint I141 check L5101
NOK
Vdd_sti(+3V3) on tespoint I244 check L5200
OK
NOK
Vdd_flash_L(+3V3) on testpoint I304 check L5300
NOK
Vdd_flash_H1(+3V3) on testpoint I301 check L5302
OK
NOK
VDD_EMP(+3V3) on tespoint I413 check L5404
NOK
VDD_EMP_CORE(+3V3) on tespoint I412 check IC7404
OK
NOK
VDDA_7118(+3V3) on testpoint I509 check L5507
NOK
VDDA_1A_7118(+3V3) on testpoint I508 check L5500
NOK
NOK
NOK
NOK
VDDX_7118(+3V3) on testpoint I518 check L5508
OK
NOK
VDDE_7118(+3V3) on testpoint I511 check L5506
NOK
VDDI_7118(+3V3) on testpoint I515 check L5505
NOK
VDD_LVC32(+3V3) on testpoint I526 check L5504
OK
NOK
VDD5_OSC(+5V) on tespoint I925 check L5905
NOK
VCC5_4046(+5V) on testpoint I130 check L5103
NOK
VCC3_CLK_BUF(+3V3) on testpoint I930 check L5907
OK
Power Part OK CL 16532145_046.eps

031201
Figure 5-23
Reset and Clock Check
RESET & CLOCK CHECK DIGITAL BOARD

USE DIGITAL BOARD CIRCUIT DIAGRAMS 1,2,7 AND 8 AND DIGITAL BOARD BOTTOM VIEW TESTPOINTS
Power on and exit

stand-by mode
- Check IC7902
NOK
Resetn(+3V3) on testpoint I912 - Check D6900
- Check R3924 and R3925
OK
Resetn_BE(+3V3) on testpoint I126 - Check IC7702

NOK
Resetn_DVIO(+3V3) on testpoint I659 - Check IC7200
Resetn_VE(+3V3) on testpoint I206 - Check IC7403
OK
Sysclk_VSM_5508(27MHz) on testpoint I917 - Check Oscillator 7906

NOK
Sysclk_ProgScan(27MHz) on testpoint I920 - Check IC7904
Sysclk_Empress(27MHz) on testpoint I924 - Check R3906, R3908 and R3917
OK
- Check Oscillator 7906
NOK
ACC_ACLK_PLL(12MHz) on testpoint I902 - Check IC7900
- Check R3901
OK
NOK - Check IC7102

ACC_ACLK_OSC(12MHz) on testpoint I143
- Check R3125
OK
- Check IC7200
NOK
EMI_PROCCLK(60MHz) on testpoint I170 - Check R3208
- Check IC7100
OK
- Check IC7500
NOK
VIP_ICLK(27MHz) on testpoint I101 - Check IC7100
- Check R3505
OK
Reset- & clock signals are OK CL 16532145_047.eps

031201
Figure 5-24
DSW Memory Tests
DSW MEMORY TESTS
Start Diagnostic Software

and select Command mode
Flash Checksum NOK - Check IC 7301

Command: 100 - Check IC 7302
OK
Flash 1 Write Access NOK

- Check IC 7301
Command: 101
OK
Flash 2 Write Access NOK

- Check IC 7302
Command: 102
OK
Flash Write/Read NOK - Check IC 7301

OK
SDRAM Write/Read NOK

- Check IC 7300
Command: 104
OK
SDRAM Write/Read fast NOK

- Check IC 7300
Command: 105
OK
NVRAM I2C Test

Command: 123 NOK - Check I2C-signals
NVRAM Write Read Test - Check 7201
Command: 122
OK
MEMORY PART OK CL 16532145_048.eps

031201
Figure 5-25
DSW VSM Tests
DSW VSM TESTS

VSM Interconnection Test NOK

- Check IC 7100
Command: 304
OK
SDRAM Access Test NOK

- Check IC 7101
Command: 301
OK
SDRAM Write/Read Test NOK - Check IC 7100

OK
VSM Interrupt Test NOK - Check IC 7100

OK
VSM Connection to analog board Test NOK - Check IC 7100

Command: 305 - Check connection to analog
board
OK
VSM PART OK CL 16532145_049.eps

031201
Figure 5-26
DSW Audio Part Check
DSW AUDIO PART CHECK

Audio Clock Test - Check IC 7900

Command: 1400 NOK
- Check IC 7906
Measure ACC_ACLK_PLL on I902
- Check IC 7100
(11.289MHz)
OK
Audio Clock Test - Check IC 7900

Command: 1401 NOK
- Check IC 7906
Measure ACC_ACLK_PLL on I902
- Check IC 7100
(12.288MHz)
OK
Host Pink Noise ON

Command: 115
Check AD_BCLK(3.072MHz) on pin14 of con.1602
NOK - Check IC 7202
Check AD_WCLK(48KHz) on pin12 of con.1602
Check AD_ACLK(12.288MHz) on pin9 of con.1602 - Check IC 7200
Check AD_DATAO(Activity) on pin11 of con.1602
Check AD_SPDIF33(Activity) on pin2 of con.1602
OK
Host Pink Noise OFF

Command: 116
Check AD_BCLK(3.072MHz) on pin14 of con.1602
NOK - Check IC 7202
Check AD_WCLK(48KHz) on pin12 of con.1602
Check AD_ACLK(12.288MHz) on pin9 of con.1602 - Check IC 7200
Check AD_DATAO(No Activity) on pin11 of con.1602
Check AD_SPDIF33(No Activity) on pin2 of con.1602
OK
Audio I2S Encoding Path Test

Command: 900
Check AE_BCLK(3.072MHz) on pin21 of con.1602
NOK - Check IC 7100
Check AE_WCLK(48KHz) on pin20 of con.1602
Check AE_DATAI(Activity) on pin18 of con.1602 - Check IC 7403
Check AE_DATAO(Activity) on testpoint I155
Check AE_ACLK on pin16 of con. 1602
OK
Video Encoding Path Test

Command: 902
Check VIP_ICLK(27MHz) on testpoint I101 - Check IC 7100
NOK
Check VIP_VS(50Hz) on pin1 of IC7502 - Check IC 7500
Check VE_DSn(Activity) on testpoint I104 - Check IC 7502
Check VE_DTACKn(Activity) on testpoint I103
OK
Mute ON Test --> Command: 109

Check Mute level(high) on testpoint I609 NOK - Check IC 7200
Mute OFF Test --> Command: 110 - Check IC 7202
Check Mute Level(low) on testpoint I609
OK
AUDIO PART OK CL 16532145_050.eps

031201
Figure 5-27
DSW Vidoe Part Check
DSW VIDEO PART CHECK

Gateway Test to Analog Board NOK - Check Analog Board

OK
Color Bar ON Test

Command: 120
OK
Check Red Video Out on pin 5 of con.1601

Check Green Video Out on pin 3 of con.1601 - Check T7600, T7601, T7603
Check Blue Video Out on pin 1 of con.1601 NOK
T7604, T7605 and T7606
Check CVBS Video Out on pin 11 of con.1601
Check Y-Video Out on pin 9 of con.1601 - Check IC 7200
Check C-Video Out on pin 7 of con.1601
OK
- Check IC 7200
Check HSYNC on testpoint I221 NOK
- Check IC 7701
Check VSYNC on testpoint I701
- Check IC 7702
OK
Color Bar OFF Test

Command: 121
OK
VBI(Vertical Blanking Interval) Loopback Test - Check IC 7200

NOK
Check the Color Bar on the TV creen - Check IC 7100
OK
VIDEO PART OK CL 16532145_051.eps

031201
Figure 5-28
DSW Video Part Check Progressive Scan
VIDEO PART CHECK PROGRESSIVE SCAN

Generate NTSC Testpicture

Command: 135 10 1
Switch off Macrovision

Command: 137
Route PS to Analog Board

Command: 1415
Route Video on Analog Board

Command: 712
Check activity on Yy_OUT(0:7) of IC7801

NOK - Check IC 7800
Check activity on Cr_OUT(0:7) of IC7801
- Check IC 7801
Check activity on Cb_OUT(0:7) of IC7801
OK
Check HSOUT on testpoint I824 NOK - Check IC 7701 and IC 7702

Check VSOUT on testpoint I825 - Check IC 7200
OK
Check DAC-A/Y on testpoint I808

NOK
Check DAC-B on testpoint I809 - Check IC 7801
Check DAC-C on testpoint I812
OK
Check Y-signal on testpoint I821 NOK

- Check IC 7802
Check Cb-signal on testpoint I822 - Check IC 7803
Check Cr-signal on testpoint I823 - Check R3801, R3812 and R3819
OK
Video Part Progressive Scan OK CL 265362011_023.eps

160102
Figure 5-29
DSW Basic Engine Check
DSW BASIC ENGINE TESTS

Basic Engine S2B Echo Test NOK - Check IC 7202

Command: 601 - Check Basic Engine
OK
Basic Engine Tray Open Test NOK

- Check Basic Engine
Command: 616
OK
Insert a DVDRW video disc
OK
Basic Engine Tray Close Test NOK

- Check Basic Engine
Command: 615
OK
Basic Engine S2B Write Read Test NOK - Check Basic Engine
OK
BASIC ENGINE PART OK CL 16532095_094.eps

150801
Figure 5-30
Waveforms
Waveforms Digital Board

Sysclk_VSM Sysclk_5505
2V / div DC 20ns / div 2V / div DC 20ns / div
27M_clk_PS acc_aclk_pll
EMI_PROCCLK DSP_clk
2V / div DC 10ns / div 2V / div DC 10ms / div
VIP_ICLK VSM_M_CLK

CL 16532145_053.eps
031201
Figure 5-31
AD_WCLK; AE_WCLK AD_BCLK; AE_BCLK AD_ACLK
2V / div AC 10us / div 2V / div AC 200ns / div 2V / div AC 50ns / div
AD_DATAO; AE_DATAO; AE_DATAI AD_SPDIF I401 VIP_VS
2V / div AC 5us / div 2V / div AC 250ns / div 2V / div DC 5ms / div
R_OUT G_OUT B_OUT
200mV / div AC 20us / div 200mV / div AC 20us / div 200mV / div AC 20us / div
CVBS_OUT Y_OUT C_OUT
VSYNC HSYNC
CL 16532145_054.eps
2V / div DC 20ms / div 2V / div DC 20ms / div 031201
Figure 5-32

DAC-B DAC-A/Y Cr-signal
DAC-C HS_IN VSOUT
500mV / div AC 10us / div 2V / div DC 20us / div 2V / div DC 10ms / div
FRAME_IN VS_IN YUV_IN
2V / div DC 10ms / div 2V / div DC 10ms / div 2V / div DC 10ms / div
Y-signal Cb-signal HSOUT
500mV / div AC 10us / div 500mV / div AC 10us / div 2V / div DC 10us / div
Y_OUT; Cr_OUT; Cb_OUT
CL 16532145_055.eps
2V / div DC 20us /div 031201
Figure 5-33
5.6.4
EN 82
Measurement Point Overview for EURO
Signal Signal Signal Schematics Signal Signal Signal Schematics
5.
MP X Y Name Description Type Part Name Coord. MP X Y Name Description Type Part Name Coord.
F800 F_MODE Fact. Mode Condition AIO1 AIO1 C10 F5002 ARIn_SC2 SC2 A R IN NF IN 1950 2B IO4 C9
F3201 12V 12 V Supply PS IN 1932 1 PS C1 F5006 ALIn_SC2 SC2 A L IN NF IN 1950 6B IO4 C9
Analogue Board
F3202 5V 5 V Supply PS IN 1932 2 PS C1 F5020 YCVBSIN_SC2 SC2 Y IN Sin IN 1950 20B IO4 F9
F3203 5NSTBY 5 V Supply PS IN 1932 3 PS C1 F536 BC_SC1 SC1 BC Sin Out* 1950 7A IO1 E13
F3204 VGNSTBY Supply GND PS IN 1932 4 PS C1 F521 8_SC1 SC1 Pin 8 DC Out 1950 8A IO1 F13
F3205 33STBY 33 V Supply PS IN 1932 5 PS D1 F515 P50_SC1 SC1 P50 DC Out 1950 10A IO1 F14
F3206 FLYB Controls PS DC Gen 1932 6 PS D1 F524 Gout_SC1 SC1 G Out Sin Out 1950 11A IO1 F13
F3207 GNDA Ground Analogue GND 1932 7 PS D1 F527 RCOut_SC1 SC1 RC Out Sin Out 1950 15A IO1 G14
Measurement Points Overview
F0017 3VD 3V3 Supply PS IN 1900 17 DAC B1 F530 FBOut_SC1 SC1 FB Out DC Out 1950 16A IO1 H13
F0001 GNDD Ground Digital GND 1900 01 DAC E1 F5007 BC_SC2 SC2 B IN C Out Sin In* 1950 7B IO4 D9
DVDR985 /171
F803 INT Clock Clock Adjust Count Out 7811 7 AIO1 H5 F5008 8_SC2 SC2 Pin 8 DC Out 1950 8B IO4 D9
F900 5STBY2 5V AIO DC Out 7803 12 AIO2 D3 F5011 Gin_SC2 SC2 G In Sin In 1950 11B IO4 D9
F902 IReset Inverse Reset DC Out * 7803 115 AIO2 D2 F5015 RCin_SC2 SC2 RC In Sin In 1950 15B IO4 E9
F8111 5M 5 V Motor DC Out 1987 12 AIO1 F14 F5016 FBin_SC2 SC2 FB In DC In 1950 16B IO4 E9
F303 5SW 5SW DC Out 7703 21 TU B10 F5401 A_V A_V to DIGI Sin Out 1954 01 IO1 I3
F9336 8SW 8SW DC Out 2321 PS B6 F5402 GNDV GNDV to DIGI GND 1954 02 IO1 I4
F8105 SDA IIC1 IIC IO 1981 6 AIO1 E13 F5403 A_U A_U to DIGI Sin Out 1954 03 IO1 I4
F8107 SCL IIC1 IIC IO 1981 8 AIO1 E13 F5405 A_Y A_Y to DIGI V Out 1954 05 IO1 I4
F810 SCL1 IIC2 IIC IO 3804 AIO1 A9 F5407 A_C A_C to DIGI Sin Out 1954 07 IO1 I4
F811 SDA1 IIC2 IIC IO 3805 AIO1 A9 F5409 A_YCVBS AYCVBS to DIGI V Out 1954 09 IO1 I4
F8104 IPOR1 IPOR to DC DC OUT 1981 5 AIO1 E13 F5412 D_CVBS D_CVBS f. DIGI V In 1954 12 IO1 I5
F8101 12STBY 12 V to DC DC Out 1981 2 AIO1 D13 F5414 D_Y D_Y f. DIGI V In 1954 14 IO1 I5
F8110 5STB 5 V to DC DC Out 1981 11 AIO1 F13 F5416 D_C D_C f. DIGI Sin In 1954 16 IO1 I5
Figure 5-34
F5306 8SW 8 SW to FRONT DC Out 1953 6 IO1 I1 F5418 D_R D_T f. DIGI Sin In 1954 18 IO1 I6
F8102 VGNSTBY VGN to DC GND 1981 3 AIO1 E13 F5420 D_G D_G f. DIGI Sin In 1954 20 IO1 I6
F8202 A_DATA To DIGI DC IN 1982 2 AIO1 H13 F5422 D_B D_B f. DIGI Sin In 1954 22 IO1 I6
F8203 D_DATA To DIGI DC IN 1982 3 AIO1 H13 F5301 AFCRI A R from FC NF In 1953 1 IO1 I1
F8204 A_RDY To DIGI DC IN 1982 4 AIO1 H13 F5303 AFCLI A L from FC NF In 1953 3 IO1 I1
F8205 D_RDY To DIGI DC IN 1982 5 AIO1 H13 F5304 CVBSFIN CVBS from FC V In 1953 4 IO1 I1
F8108 INT TO DC DC IN 1981 9 AIO1 F13 F5307 CFIN C from FC Sin In 1953 7 IO1 I2
F8109 RC TO DC DC IN 1981 10 AIO1 F13 F5309 YFIN Y from FC V In 1953 9 IO1 I2
F8201 IRESET_DIG TO DIGI DC IN 1982 1 AIO1 H13 F012 DAINOPT A D Opt to DIGI 1900 20 DAC A1
F513 GNDA SC1 GND A DC IN 1950 4A IO1 E14 F013 DAINCOAX A D Coax to DIGI 1900 21 DAC A1
F517 ARIn_SC1 SC1 A R IN NF IN 1950 2A IO1 E13 F014 DAOUT A D from DIGI 1900 20 DAC A1
F519 ALIn_SC1 SC1 A L IN NF IN 1950 6A IO1 E14 F0002 A_BCLK BCLK from DIGI CLK In 1900 2 DAC E2
F534 YCVBSIN_SC1 SC1 Y IN V IN 1950 20A IO1 I13 F0003 A_WCLK WCLK from DIGI CLK In 1900 3 DAC D2
F525 GNDV SC1 GND V GND 1950 21A IO1 H14 F0005 A_DAT A Data to DIGI Data Out 1900 5 DAC D2
F5001 AROut_SC2 SC2 A R Out NF Out 1950 1B IO4 C9 F0007 A_PCMCLK PCMCLK from DIGI CLK In 1900 7 DAC D2
F5003 ALOutSC2 SC2 A L Out NF Out 1950 3B IO4 C9 F0009 D_BCLK BCLK from DIGI CLK In 1900 9 DAC D2
F5004 GNDA SC2 GND A GND 1950 4B IO4 C9 F0011 D_WCLK WCLK from DIGI CLK In 1900 11 DAC D2
F5019 YCVBSOut_SC2 SC2 Y Out V Out 1950 19B IO4 C9 F0012 D_DATA0 A Data from DIGI Data In 1900 12 DAC C2
F5021 GNDV SC2 GND V GND 1950 21B IO4 C9 F0014 D_PCMCLK PCMCLK from DIGI CLK In 1900 14 DAC C2
F516 AROut_SC1 SC1 A R Out NF Out 1950 1A IO1 E14 F0016 D_KILL A Kill from DIGI DC In 1900 16 DAC C2
F518 ALOutSC1 SC1 A L Out NF Out 1950 3A IO1 E14 F010 ARDAC A R from DAC NF Out 7002 1 DAC C9
F531 YCVBSOut_SC1 SC1 Y Out V Out 1950 19A IO1 G13 F011 ALDAC A L from DAC NF Out 7002 7 DAC E9
F331 RCALOut A L Rear Cinch Out NF Out 1958 4B IO3 E9
150801
CL 16532095_097.eps
F334 RCAROut A R Rear Cinch Out NF Out 1958 5B IO3 E9
F336 RCVBSOut V Rear Cinch Out V Out 1959 1B IO3 C9
Measurement Point Overview for NAFTA
F5101 ARCRI A L Rear Cinch In NF In 1958 1A IO2 D2 F800 F_MODE Fact. Mode Condition AIO1 AIO1 C10
F5103 ARCLI A R Rear Cinch In NF In 1958 2A IO2 E2 F3201 12V 12 V Supply PS IN 1932 1 PS C1
F5202 RCVBSIn V Rear Cinch In V In 1959 2A IO2 C2 F3202 5V 5 V Supply PS IN 1932 2 PS C1
F5503 RSVHSYIn Y Rear SVHS In V In 1955 3B IO2 B2 F3203 5NSTBY 5 V Supply PS IN 1932 3 PS C1
F5504 RSVHSCIn C Rear SVHS In Sin In 1955 4B IO2 B2 F3204 VGNSTBY Supply GND PS IN 1932 4 PS C1
F338 RSVHSYOut Y Rear SVHS Out V Out 1955 3A IO3 A9 F3205 33STBY 33 V Supply PS IN 1932 5 PS D1
F337 RSVHSCOut C Rear SVHS Out Sin Out 1955 4A IO3 A9 F3206 FLYB Controls PS DC Gen 1932 6 PS D1
F6001 DVAR A R from DIGI Sin In 1960 1 AP D1 F3207 GNDA Ground Analogue GND 1932 7 PS D1
F6002 GNDA GNDA GND 1960 2 AP D1 F0017 3VD 3V3 Supply PS IN 1900 17 DAC B1
F6004 DVAL A L from DIGI Sin In 1960 4 AP D1 F0001 GNDD Ground Digital GND 1900 01 DAC E1
F700 IF IF Out DC Out 1705 11 TU C3 F803 INT Clock Clock Adjust Count Out 7811 7 AIO1 H5
F701 IF In IF In Sin In 1705 11 TU C3 F900 5STBY2 5V AIO DC Out 7803 12 AIO2 D3
F702 GNDFV GND FV GND 1705 12 TU C2 F902 IReset Inverse Reset DC Out * 7803 115 AIO2 D2
F703 GNDFV GND FV GND 1700 3 TU B6 F8111 5M 5 V Motor DC Out 1987 12 AIO1 F14
F704 40.4 40.4 Trap Sin Out 1700 1 TU B5 F303 5SW 5SW DC Out 7703 21 TU B10
F705 AGC AGC DC Out 3701 TU A4 F9336 8SW 8SW DC Out 2321 PS B6
F812 SYNC SYNC from Sepa. Freq Out 7803 33 AIO1 F6 F8105 SDA IIC1 IIC IO 1981 6 AIO1 E13
F4202 DIG OUT L Digital Out Low GND 1954 2 DIGI B4 F8107 SCL IIC1 IIC IO 1981 8 AIO1 E13
F4203 DIG OUT H Digital Out High Sin Out 1945 3 DIGI A4 F810 SCL1 IIC2 IIC IO 3804 AIO1 A9
F4204 OPT OUT Optical Out DC Out 1943 1 DIGI D3 F811 SDA1 IIC2 IIC IO 3805 AIO1 A9
F806 FAN OUT FAN Out DC Out 1984 1 FACO C5 F8104 IPOR1 IPOR to DC DC OUT 1981 5 AIO1 E13
F807 FAN IN FAN In DC In 1985 1 FACO F1 F8101 12STBY 12 V to DC DC Out 1981 2 AIO1 D13
F8206 ION ION_FAN DC Out 1982 6 AIO1 H13 F8110 5STB 5 V to DC DC Out 1981 11 AIO1 F13
Figure 5-35
F8208 BE_FAN BE_FAN DC Out 1982 8 AIO1 I13 F5306 8SW 8 SW to FRONT DC Out 1953 6 IO1 I1
F8209 FB FBIN SC2 DC Out 1982 9 AIO1 I13 F8102 VGNSTBY VGN to DC GND 1981 3 AIO1 E13
F8210 GNDD GNDD GNDD 1982 10 AIO1 I13 F8202 A_DATA To DIGI DC_In 1982 2 AIO1 H13
F8203 D_DATA To DIGI DC_In 1982 3 AIO1 H13
Remark: F8204 A_RDY To DIGI DC_In 1982 4 AIO1 H13
Indicator * means more than one signal type F8205 D_RDY To DIGI DC_In 1982 5 AIO1 H13
F8108 INT TO DC DC_In 1981 9 AIO1 F13
F8109 RC TO DC DC_In 1981 10 AIO1 F13
F8201 IRESET_DIG TO DIGI DC_In 1982 1 AIO1 H13
F5103 ARIn_2 A R IN 2 NF IN 1958 3A IO3 E13
F5101 ALIn_2 A L IN 2 NF IN 1958 1A IO3 E14
F5906 GNDV GND V GND 1957 6A IO1 H12
F5806 GNDV GND V GND 1956 6A IO1 I8
F510 ARout_1 A R Out 1 NF Out 1959 5B IO1 E13
F509 ALout_1 A L Out 1 NF Out 1959 4B IO1 D13
DVDR985 /171
F5201 RCVBSOut2 SC1 Y Out V Out 1997 1B IO3 A8

F5105 ARIn_1 A R IN 1 NF IN 1959 1A IO2 E2
F5104 ALIn_1 A L IN 1 NF IN 1959 4A IO2 E2
F5202 RCVBSIn Y IN Sin IN 1997 2A IO2 C2
5.
F5905 Y_OUT Y Out Sin Out* 1957 5A IO1 I12

F5801 U_IN U IN Sin In* 1956 1B IO1 I10
150801
CL 16532095_098.eps
F5805 Y_IN Y IN Sin In 1956 5A IO1 I9
F5802 V_IN V IN Sin In 1956 2B IO1 I10
EN 83
EN 84
F5401 A_V A_V to DIGI Sin Out 1954 01 IO1 I3 F4202 DIG OUT L Digital Out Low GND 1954 2 DIGI B4
F5402 GNDV GNDV to DIGI GND 1954 02 IO1 I4 F4203 DIG OUT H Digital Out High Sin Out 1945 3 DIGI A4
5.
F5403 A_U A_U to DIGI Sin Out 1954 03 IO1 I4 F4204 OPT OUT Optical Out DC Out 1943 1 DIGI D3
F5405 A_Y A_Y to DIGI V Out 1954 05 IO1 I4 F806 FAN OUT FAN Out DC Out 1984 1 FACO C5
F5407 A_C A_C to DIGI Sin Out 1954 07 IO1 I4 F807 FAN IN FAN In DC In 1985 FACO F1
F5409 A_YCVBS AYCVBS to DIGI V Out 1954 09 IO1 I4 F8206 ION ION_FAN DC Out 1982 6 AIO1 H13
F5412 D_CVBS D_CVBS f. DIGI V In 1954 12 IO1 I5 F8208 BE_FAN BE_FAN DC Out 1982 8 AIO1 I13
F5414 D_Y D_Y f. DIGI V In 1954 14 IO1 I5 F8209 FB FBIN SC2 DC Out 1982 9 AIO1 I13
F5416 D_C D_C f. DIGI Sin In 1954 16 IO1 I5 F8210 GNDD GNDD GNDD 1982 10 AIO1 I13
F5418 D_R D_T f. DIGI Sin In 1954 18 IO1 I6
F5420 D_G D_G f. DIGI Sin In 1954 20 IO1 I6 Remark:
F5422 D_B D_B f. DIGI Sin In 1954 22 IO1 I6 Indicator * means more than one signal type
DVDR985 /171
F5301 AFCRI A R from FC NF In 1953 1 IO1 I1

F5303 AFCLI A L from FC NF In 1953 3 IO1 I1
F5304 CVBSFIN CVBS from FC V In 1953 4 IO1 I1
F5307 CFIN C from FC Sin In 1953 7 IO1 I2
F5309 YFIN Y from FC V In 1953 9 IO1 I2
F012 DAINOPT A D Opt to DIGI 1900 20 DAC A1
F013 DAINCOAX A D Coax to DIGI 1900 21 DAC A1
F014 DAOUT A D from DIGI 1900 20 DAC A1
F0002 A_BCLK BCLK from DIGI CLK In 1900 2 DAC E2
F0003 A_WCLK WCLK from DIGI CLK In 1900 3 DAC D2
F0005 A_DAT A Data to DIGI Data Out 1900 5 DAC D2
F0007 A_PCMCLK PCMCLK from DIGI CLK In 1900 7 DAC D2
F0009 D_BCLK BCLK from DIGI CLK In 1900 9 DAC D2
Figure 5-36
F0011 D_WCLK WCLK from DIGI CLK In 1900 11 DAC D2
F0012 D_DATA0 A Data from DIGI Data In 1900 12 DAC C2
F0014 D_PCMCLK PCMCLK from DIGI CLK In 1900 14 DAC C2
F0016 D_KILL A Kill from DIGI DC In 1900 16 DAC C2
F010 ARDAC A R from DAC NF Out 7002 1 DAC C9
F011 ALDAC A L from DAC NF Out 7002 7 DAC E9
F513 ALOut_2 A L Rear Out 2 NF Out 1958 4B IO1 B13
F512 AROut_2 A R Rear Out 2 NF Out 1958 5B IO1 C13
F5205 RCVBSOut1 V Rear Cinch Out1 V Out 1997 5C IO3 A8
F5503 RSVHSYIn Y Rear SVHS In V In 1955 3B IO2 B2
F5504 RSVHSCIn C Rear SVHS In Sin In 1955 4B IO2 B2
F338 RSVHSYOut Y Rear SVHS Out V Out 1955 3A IO3 A9

F337 RSVHSCOut C Rear SVHS Out Sin Out 1955 4A IO3 A9
F6001 DVAR A R from DIGI Sin In 1960 1 AP D1
F6002 GNDA GNDA GND 1960 2 AP D1
F6004 DVAL A L from DIGI Sin In 1960 4 AP D1
F700 IF IF Out DC Out 1705 11 TU C3
F701 IF In IF In Sin In 1705 11 TU C3
F702 GNDFV GND FV GND 1705 12 TU C2
F703 GNDFV GND FV GND 1700 3 TU B6
F705 AGC AGC DC Out 3701 TU A4
F812 SYNC SYNC from Sepa. Freq Out 7803 33 AIO1 F6
150801
CL 16532095_099.eps
F330 RC IN Remote Control In DC Out 1993 2 IO3 E2
Power Part Check
Check internal Power supply voltages

NOK
5M on testpoint F9340 check Fuse 1327
NOK
12STBY on testpoint F810 check Fuse 1326
NOK
8STBY on pin 3 of IC7332 check IC 7332
NOK
8SW on testpoint F9336 check - ISTBY HIGH?
- T7329, T7324, MOSFET7321
NOK
5STBY on testpoint F9333 check Fuse 1325
NOK
5SW on testpoint F303 check - ISTBY HIGH?
- T7329, T7324, MOSFET7323
NOK
5STBY2 on testpoint F900 check L5901, IC7900
NOK
5STBY_uP on IC7803 check L5903, IC7803
OK

031201
Figure 5-37
DSW Check Analoge Board
DSW CHECK ANALOGUE BOARD

- Check Reset signal(+5V) on F902

Echo Test Analogue Board NOK - Check Clock(20MHz) on I915
Command: 700 - Check connection to Digital Board
- Check IC 7803
OK
Boot Code Version Test

Command: 703 NOK
- Check IC 7906
Analogue Flash Checksum Test
Command: 724
OK
Hardware Version Check NOK

- Check IC 7906
Command: 704
OK
Clock Adjust Test NOK - Check IC 7811

Command: 705 2001 07 16 09 15 45 - Check x-tal 1602
(YYYY MM DD HH MM SS)
OK
Tuner Test NOK

- Check tuner 1705
Command: 706
OK
Frequency Download Test

Command: 707 NOK
- Check IC 7815
NVRAM Test
Commdo: 711
OK
Data Slicer Test NOK

- Check IC 7990
Command: 708
OK
Sound Processor Test NOK

- Check IC 7600
Command: 709
OK
Audio Video Selector Test NOK

- Check IC 7507
Command: 710
OK
DCW CHECK ANALOGUE

BOARD OK CL 16532095_101.eps
150801
Figure 5-38
Routing Audio and Video PATH ID DESCRIPTION

04 Input signal is from REAR S-VIDEO(Y/C) IN and
Route Video will be routed to the digital board.
Nucleus Number: 712 05 Input signal is from YUV IN and will be routed to the
Description
digital board.
This nucleus routes the video signals on the analogue board to
06 No routing.
the destination determined by the input parameters
The paths that are available for video routing and their 07 No routing.
description(Europe version) 08 Input signal is VIDEO(CVBS) from ANTENNA IN
and will be routed to VIDEO(CVBS) OUT and .
PATH ID DESCRIPTION 09 Input signal is from YUV IN and will be routed to
00 Input signal is VIDEO(CVBS) from digital board YUV OUT.
and will be re-routed back to the digital board. 10 No routing.
01 Input signal is from FRONT VIDEO(CVBS) IN and 11 No routing.
will be routed to the digital board.
12 Input signal is from REAR VIDEO(CVBS) IN and
02 Input signal is from REAR VIDEO(CVBS) IN and will be routed to REAR VIDEO(CVBS) OUT.
will be routed to the digital board.
13 Input signal is from FRONT VIDEO(CVBS) IN and
03 Input signal is from FRONT S-VIDEO(Y/C) and will will be routed to REAR VIDEO(CVBS) OUT.
be routed to the digital board.
14 Input signal is from REAR S-VIDEO(Y/C) IN and
04 Input signal is from REAR S-VIDEO(Y/C) and will will be routed to REAR S-VIDEO(Y/C) OUT.
be routed to the digital board.
15 Input signal is from FRONT S-VIDEO(Y/C) IN and
05 Input signal is CVBS from SCART1 and will be will be routed to REAR S-VIDEO(Y/C) OUT.
routed to the digital board.
16 No routing.
06 Input signal is CVBS from SCART2 and will be
17 Signal path is routed from digital board RGB to
REAR VIDEO(YUV) OUT and from REAR VID-
07 No routing. EO(YUV) IN to digital board YUV and from digital
08 Input signal is VIDEO(CVBS) from ANTENNA IN board CVBS to digital board CVBS.
and will be routed to SCART1. 18 Signal path is routed from digital board CVBS to
09 Input signal is VIDEO(CVBS) from SCART1 and REAR VIDEO(CVBS) OUT and from REAR VID-
will be routed to SCART2. EO(CVBS) IN to digital board CVBS.
10 Input signal is VIDEO(CVBS) from SCART2 and 19 Signal path is routed from digital board YC to
will be routed to SCART1. REAR S-VIDEO(YC) OUT and from REAR S-VID-
11 No routing. EO(YC) IN to digital board YC.
12 Input signal is from REAR VIDEO(CVBS) IN and
will be routed to SCART1 and SCART2. Example
DD:> 712 01
71200: Video routing on the Analogue Board OK.
will be routed to SCART1.
Test OK @
14 Input signals VIDEO(CVBS and Y/C) from SCART
1 will be routed to SCART2.
Route Audio
15 Input signal is from REAR S-VIDEO(Y/C) IN and Nucleus Number: 713
will be routed to SCART2.
Description
16 Input signal is from FRONT S-VIDEO(Y/C) IN and This nucleus routes the audio on the analogue board to the
will be routed to SCART2. destination determined by the input parameters
17 No routing The paths that are available for audio routing and their
18 No routing description (Europe version)
19 Input signals VIDEO(RGB and FAST BLANKING)
PATH ID DESCRIPTION
from SCART2 will be routed to the corresponding
pins of SCART1. 00 Input signal is VIDEO(CVBS) from digital board
and will be re-routed back to the digital board.
20 Signal path is routed from digital board RGB to
RGB SCART1 and from RGB SCART2 to digital 01 Input signal is from FRONT AUDIO IN and will be
board YUV and from digital board CVBS to digital routed to the digital board.
board CVBS. 02 Input signal is from REAR AUDIO IN and will be
21 Signal path is routed from digital board YC to routed to the digital board.
REAR S-VIDEO(YC) OUT and from REAR S-VID- 03 Input signal is AUDIO from SCART1 and will be
EO(YC) IN to digital board YC. routed to the digital board.
04 Input signal is AUDIO from SCART2 and will be
The paths that are available for video routing and their routed to the digital board.
description (Nafta region) 05 No routing.
06 No routing.
PATH ID DESCRIPTION 07 No routing.
00 Input signal is VIDEO(CVBS) from digital board 08 Input signal is VIDEO(CVBS) and AUDIO from AN-
TENNA IN and will be routed to SCART1.
09 Input signal is VIDEO(CVBS) and AUDIO from
will be routed to the digital board. SCART1 and will be routed to SCART2.
02 Input signal is from REAR VIDEO(CVBS) IN and 10 Input signal is VIDEO(CVBS) and AUDIO from
will be routed to the digital board. SCART2 and will be routed to SCART1.
03 Input signal is from FRONT S-VIDEO(Y/C) IN and 11 Input signal is AUDIO from dvio board and will be
the signal received will be routed to the digital
routed to SCART1.
board.
PATH ID DESCRIPTION
12 No routing.
13 No routing.
14 No routing.
15 No routing.
16 No routing.
17 Input signal is from REAR AUDIO IN and will be
routed to SCART1.
18 Input signal is from FRONT AUDIO IN and will be
routed to SCART1.
The paths that are available for audio routing and their
description (Nafta region)
PATH ID DESCRIPTION
00 Input signal is VIDEO(CVBS) from digital board
02 Input signal is from REAR AUDIO IN 2 and will be
04 No routing.
05 No routing.
06 No routing.
07 No routing.
08 Input signal is VIDEO(CVBS) and AUDIO from AN-
TENNA IN and will be routed to VIDEO(CVBS)
OUT and REAR CINCH OUT 2.
09 No routing.
10 Input signal is from REAR AUDIO CINCH IN 2 and
will be routed to REAR AUDIO CINCH OUT 2.
11 Input signal is from FRONT AUDIO CINCH IN and
will be routed to REAR AUDIO CINCH OUT 2.
12 No routing.
13 No routing.
14 No routing.
15 No routing.
16 Input signal is AUDIO from dvio board and will be
routed to AUDIO CINCH OUT 2.
17 No routing.
18 No routing.
19 No routing.
20 Input signal is from digital board and will be routed
to the REAR AUDIO OUT 1 and input signal is from
REAR AUDIO IN 2 and will be routed to the digital
board.
board.
board.
EXAMPLE
DD:> 713 00
71300: Audio routing on the Analogue Board OK.
Test OK @
5.6.5 Display Board
TROUBLESHOOTING DISPLAY BOARD
• Check supply voltage

NO DISC
POWER ON ⇒ Connector1916-2 12STBY +12V
⇒ Connector1916-3 VGNSTB -32V
⇒ Connector1916-11 5STBY +5V
⇒ Connector1916-12 5M +5.2V
• Check filament voltage

⇒ Testpoint F105 12STBYSI +12V
NO
⇒ AC voltage is created via oscillator circuit (7152-7153).
DISPLAY? ⇒ Check heater voltage on testpoints F102 and F101 3.2VAC, -24,4VDC, 42 kHz.
• Check oscillator frequency of 12MHz at pin 91 of IC7156

YES • Check I2C bus SDA / SCL nucleus 500 of diagnostic software
• Check version of software nucleus 501 of diagnostic software
• Diagnostic software : Player script of Front panel
• Diagnostic software “Player script” : Keyboard test.

NO
Key Function • Check appropriate key and resistor
YES
• Check if voltage at connector 1915-2 is 5V when power on (green light)

NO • Check if voltage at base of Tr 7141 is 2V when power on (green light).
Standby LED ?
• Check if voltage at base of Tr7141 is 0V when switching to standby (red light)
• Diagnostic software “Player script” : LED test.
YES
• Check presence of low pulses at pin 5 of connector 1917 while pressing a key on remote control.
NO • Check IR receiver 7140.
Remote control?
• Diagnostic software “Player script” : Remote control test.
YES
DISPLAY PCB OK. CL 265362011_024.eps

160102
Figure 5-39
DVIO Board
Power Part Check
POWER PART CHECK DVIO
USE DVIO BOARD CIRCUIT DIAGRAMS 1 2, 3, 4 AND 5 AND DVIO TOP VIEW TESTPOINTS
Power On and exit

stand-by mode
OK
+5V on testpoint F536 NOK Check connector 1500

+3V3 on testpoint F531 to Digital board
OK
NOK Check L 5200

+5V_PROC on testpoint F212
Check IC 7203
OK
NOK Check IC 7204

PSEN(+5V) on testpoint F203
Check IC 7208
OK
+3V3_FPGA on testpoint F311

Check L 5302
+3V3_FPGA_CONF on testpoint F312 NOK
Check L 5303
+3V3_SRAM on testpoint F313
Check L 5304
+3V3_PLL on testpoint F325
OK
+3V3_IEEE_PLL on testpoint F138 Check L 5106

+3V3_IEEE_A on testpoint F139 NOK Check L 5109
+3V3_IEEE_D on testpoint F140 Check L 5110
+3V3_LINK on testpoint F141 Check L 5103
OK
+Vcc_DV_RAM(+3V3) on testpoint F417 Check L 5404

+35V_DV_EDO(+3V3) on testpoint F425 NOK
Check L 5403
+3V3_DV on testpoint F416 Check L 5402
OK

031201
Figure 5-40
Reset and Clock check
RESET & CLOCK CHECK DVIO
USE DVIO BOARD CIRCUIT DIAGRAMS 2, 3, 4 AND 5 AND DVIO TOP VIEW TESTPOINTS
Power On and exit

stand-by mode
Enable DVIO board:

- press channel up or down
untill the display shows CAM3
- press tuner key in order to
switch to the DV-source
- Check connection
The red LED above the NOK to Front DVIO
DV-input will light up. - Check IC 7203
- Check T 7207
OK
- Check R 3203
Check Reset signal (LOW) NOK
- Check IC 7203
on testpoint F214
- Check T 7202
OK
Check uP clock - Check x-tal1200

NOK
on testpoint F201 - Check IC 7203
(11,05MHz) - Check R 3201
OK
Check CLOCKAUDTMP - Check IC 7303

NOK
(8,192MHz) - Check R 3315
OK
- Check IC 7308
Check Clock 27MHz NOK
- Check IC 7303
on testpoint F305
- Check R 3317
OK
Check Clock 27M_DV - Check IC 7308

NOK
(27MHz) - Check R 3318
OK
Check Clock 27M_CON - Check IC 7308

NOK
(27MHz) - Check R 3319
OK
Reset- and clock signals

are OK CL 16532145_057.eps
031201
Figure 5-41
DSW DVIO Tests
DSW DVIO TESTS

DVIO Board Presence Test NOK - Check DVIO Board

Command: 800 - Check Connector 1500
OK
Reset DVIO Test NOK - Check IC7303

OK
- Check DVIO Board

DVIO Access Test NOK
- Check Connector 1500
Command: 802 - Check Digital Board
OK
DVIO Module ID's Test NOK - Check IC 7303

OK
DVIO Selftest NOK Check ERROR LIST

Command: 805 in COMPAIR
OK
DVIO DSW CHECK OK

CL 16532145_059.eps
031201
Figure 5-42
Waveforms
Waveforms DVIO
uP_clock Clockaudtmp
Clock 27MHz Clock 27M_DV
Clock 27M_CON
2V / div DC 20ns / div CL 16532145_060.eps

031201
Figure 5-43
Personal Notes:
Block and Wiring Diagram. DVDR985 /171 6. EN 95
6. Block and Wiring Diagram.

Block Diagram DVDR985 /171
ANALOG BOARD
INTELLIGENT FAN
CONTROL 12VDC
AUDIO L
FRONT 1911
1 A1
RC6 IN
AUDIO R
Analog input AFCRI
2
A1
A1 1
1953
P50
3 AFCRI
AFCLI 2
CVBSFIN
4 V1 9 ANALOG AUDIO VIDEO A1 3
5 AFCLI
CVBS 6
V1 4
CVBSFIN
AUDIO DIGITAL
8SW 5
CFIN
7 V2
6 INPUT/OUTPUT
8 1500
V2 7
8SW AUDIO OPTICAL
S-VIDEO
YFIN
9 V3
DVIO DRAM
+3V3
+5V
8
CFIN
CONTROL
V3 9
+12V YFIN uP PROCESSING &
DV_HS_OUT AUDIO L/R
DV_VS SOURCE
8051 DV CODEC DV_CLK
VSM_UART2 4
SELECTION
FRONT 1001 1101 1501
YUV(7:0)
1960 AUDIO L/R
4 4 A2 1
Digital Video input PHY LINK FPGA AUDIO DAC
4 ANALOG AUDIO L/R A2 4
ANA_R
(DATA+CONTROL+PSU)
ANA_L
IEEE 1394 1954

Y
SRAM YUV-YCVBS/C
CVBS_OUT_B V9
Cb PROG. SCAN
CVBS_Y_IN
12
CVBS-RGB-Y/C
Y_OUT_B V10
NOT USED IN DVDR 980 60
C_OUT_B V11
14 OUT
U_IN
C_IN
Y_IN
V_IN
16
R_OUT_B V12 Cr
18
DATA G_OUT_B V13
20
V8
V4
V5
V6
V7
B_OUT_B V14
&CONTROL 22
22 20 18 16 14 Y
DVD & RW ENGINE DIGITAL PCB SDRAM 1501

1601 1600
VSM_UART1 4
1982
Cb COMP.
1402 1902 DIG.VIDEO VIDEO
IRESET_DIG
VIDEO MPEG2 MPEG VIDEO 10 1 Cr
FRONT-END I2S ENCODING VIDEO INPUT 5

ION
6
AUDIO MPEG1
7 I2S EMPRESS PROCESSING
VSM 1602 A3
1900 S-VIDEO
TRAY CONTROL 20
AE_WCLK
AUDIO ENCODER I2S
BE_FAN MPEG ANAL.VIDEO AE_BCLK
Stream FRONT-END I2S or //

AV
21
18 AD_DATAI ADC S-VIDEO
COAX_IN
DECODER 3
SERVO RESETN_BE Manager + HOST
DIGITAL VIDEO DIG. AUDIO 4
OPT_IN
2 SPDIF CVBS
(Sti5508) 7 MUTEN
BE_LOADN AD_ACLK
DISC READ
9
A4 CVBS
11 AD_DATAO AUDIO PCM I2S
LASER 2MB 12 AD_WCLK DAC CVBS
5 S2B S2B SDRAM FLI2200 14 AD_BCLK
WRITE Video
EMI BUS Deinterlacer
Line Doubler
SDRAM Y 1800 1962
Y
Y
U VIDEO Cr
DRAM Cr
+4V6E
DENC CLOCK ANTENNE INPUT

+3V3
+12V
+3V3
+3V3
+3V3
+3V3
+12V
GND
GND
GND
GND
GND
GND
GND
+5V
+5V
ION
-5V
-5V
Cb
V Cb & TUNER
FLASH 4MB
1000 1900 RS232 1903
BACKUP TV OUT
8
8
6
4
2
1
6
4
2
1
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12
1981
SERVICE PSU
+5V2stby
PSU
+12Vstby
-Vgnstby
PSU
+33Vstby
-5Nstby
FLYB
GND
INT/IPOR1
2 I2C
INFRA RED 1932
EYE
+12Vstby
-Vgnstby
1 2 3 4 5 6 7
5STBY
IPOR1
SDA
SCL
INT
1915
5M
2 3 11 12 9 5 6 8
1917 1916
TITLE TRACK CHAPTER TOTAL TRACK TIME REMAIN CHANNEL VPS/PDC DIGITAL PCB
5STBY AM 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7
PM
DVD RW
0209 0205
SAVCD HQ SP L:P EP+ MONITOR SAT TIMER RECORD DECODER
0207
1 +3V3
+3V3
+3V3
+3V3
+3V3
GND
+12V
GND
GND
ION
GND
-5V
+12Vstby
+5V2stby
-5Nstby
-Vgnstby
+33Vstby
FLYB
GND
+5V
2 +5V
ENGINE
-40 -30 -20 -10 0 OVER -40 -30 -20 -10 0 OVER
PROLOGIC MPEG AC-3 DTS PCM MANUAL DIGITAL NICAM STEREO SAP
I II
3 GND
OPEN/CLOSE 4 +4V6E MAINS

GND
PLAY
STOP
5
6 -5V
AC
GND
RECORD 7
FRONT PROCESSOR
REC-LEVEL 8 +12V MULTI-MODE SOPS
RELEASE
CHANNEL
MANUAL
TRACK
DISPLAY & CONTROL SEARCH CL 26532020_003.eps
010202
Block and Wiring Diagram. DVDR985 /171 6. EN 96
Wiring Diagram
8001 8002
1602 1900 1601 1954
1 22 GNDD 1 22 B_OUT_B
2 21 SPDIF 2 21 GNDD
3 20 COAX_IN 3 20 G_OUT_B
4 19 OPT_IN 4 19 GNDD
5 18 +5V 5 18 R_OUT_B
6 17 +3V3 6 17 GNDD
EH
FAN 7 16 MUTEN 7 16 C_OUT_B
8 15 GNDD 8 15 GNDD
9 14 AD_ACLK 9 14 Y_OUT_B
10 13 GNDD 10 13 GNDD
8015 1962
11 12 AD_DATAO 11 12 CVBS_OUT_B
1800 1962 1 7 12 11 AD_WCLK 12 11 GNDD
1 7 GND 13 10 GNDD 13 10 GNDD
2 6 Y 14 9 AD_BCLK 14 9 CVBS_Y_IN
3 5 GND ANALOG 15 8 GNDD 15 8 GNDD
4 4 Cb ONLY FOR NAFTA 16 7 AD_ACLK 16 7 C_IN
5 3 GND 17 6 GNDD 17 6 GNDD
6 2 Cr 18 5 AD_DATAI 18 5 Y_IN
7 1 GND 19 4 GNDD 19 4 GNDD
20 3 AE_WCLK 20 3 U_IN
1984 1900 1982 1954 21 2 AE_BCLK 21 2 GNDD
1 21 22 1 10 1 22 22 1 GNDD 22 1 V_IN
8006
1 ANA_R 1953 1960 1932 8003 8004

2 GNDA
1981
1 4 1 7 PSU
1 12 1 9
8001
8015
8004
8002
3 GNDA 8007 1100 1402 1600 1982
4 ANA_L pH
8006 EH EH
15 1 GNDD 1 10 GNDD
pH-pH LF SHIELDED 8009 14 2 GNDD 2 9 FB
13 3 NC 3 8 BE_FAN
EH 12 4 GNDD 4 7 ANA_WE
22 1 7 1 10 1 22 1 11 5 BE_DATA_WR 5 6 ION
8
1602 1800 1600 1601 10 6 GNDD 6 5 VSM_UART1_RTSn
9 7 BE_SYNC (D_RDY)
1900 12 1 1603 7
1000
pH
SERVICE 8 8 GNDD 7 4 VSM_UART1_CTSn
INTERFACE 7 9 BE_FLAG (A_RDY)
4 1 4 1 2 1 6 10 GNDD 8 3 VSM_UART1_TX
FAN
1
1101 1501 1201 5 11 BE_BCLK (D_DATA)
1
1
ONLY USED FOR DVDR985
4 12 GNDD 9 2 VSM_UART1_RX
1
3 13 BE_DATA_RD (A_DATA)
1500
0207
0209
1501
8008 EH
2
2 14 GNDD 10 1 IRESET_DIG
1
BOARD 1 15 BE_WCLK
1
1
TO DIGITAL
0205
60
60
30
8
BOARD 1101
15 1101 1
8003
12
15 16 GNDD
7
1402
14 17 BE_RXD
DVIO 13 18 GNDD
15 1100
12 19 BE_TXD
11 20 BE_CPR
1
10 21 BE_IRQn
9 22 BE_SUR
8 23 BE_V4
7 24 GNDD
6 25 BE_LOAD
5 26 GNDD
SERVO 4 27 BE_FAN
3 28 RESETn_BE
2 29 GNDD
1 30 GNDD
8005 8007 8008 8009

8013
IEEE WIRE pH-pH LF SHIELDED WIRE WRAP 1 +12Vstby 1 +3V3 1 +3V3
2 +5V2stby 2 +5V 2 +3V3
1
4 12 1 9 1 3 -5Nstby 3 GND 3 +3V3

1915
1917
1001 1002 1911 4 -Vgnstby 4 +4V6E 4 +3V3

1000 1918
5 +33Vstby 5 GND 5 GNDD
8014 1 4 DISPLAY 1 2 6 FLYB 6 -5V 6 +12V
7
8011 7 GND 7 GND 7 GNDD

1200 1100 pH 8 +12V 8 GNDD
FRONT FRONT IR & STBY 1 1916 12 9 +5V
1 24 GND 10 ION(STBY_ctrl
2 23 YUV_IN(7) DV INPUT AV INPUT 11 GNDD
3 22 GND 12 -5V
4 21 YUV_IN(6)
5 20 +3V3
6 19 YUV_IN(5) 8005 8011
7 18 +3V3 8013
8 17 YUV_IN(4) 1 AFCRI 1 TEMP_SENSE
9 16 +5V 1 TPB1-
2 GNDA 2 12VSTBY
10 15 YUV_IN(3) 2 TPB1+
3 AFCLI 3 VGNSTBY
11 14 GND 3 TPA1-
4 VBSFIN 4 -GNDD
12 13 YUV_IN(2) 4 TPA1+
5 GNDV 5 IPOR1
13 12 GND 6 8SW 6 SDA
14 11 YUV_IN(1) 7 CFIN 7 GNDD
15 10 GND 8 GNDV 8 SCL
16 9 YUV_IN(0) 9 YFIN 9 INT
17 8 GND 10 RC
18 7 CLK_27MHZ 11 5STBY
19 6 GND 12 5M
20 5 HS_IN
21 4 FRAME_IN
22 3 SCL
23 2 SDA
CL 26532011_027.eps
24 1 GND
010202
Electrical Diagrams And Print-Layouts DVDR985 /171 7. EN 97
7. Electrical Diagrams And Print-Layouts

Power Supply
1 2 3 4 5 6 7 8 9 10 11 12 0101-1 B1 6130 D7
0101-2 A1 6131 D7
0125 C6 6132 D7
0205 F12 6140 C5
0210 C8 6141 D4
0240 D8 6142 D6
0260 D8 6143 E6
0290 E9 6144 E6
1120 A2 6145 C4
1124 A4 6146 C6
A 2131 +33Vctrl
A 1125 B4 6151 B5
2119 B4 6152 B5
+33V
2120 B3 6153 B5
1124 1n 6200 3200 2125 B6 6154 B5
+33Vstby
2126 B6 6200 A9
BZX79-C33
0101-2 1120 5110 2K7
BYD33J
2127 A4 6201 B10
3201
2200
6201
2201
100n
CU15D3 300V 5131
33K
47u
HSC0528 2 VALUE 2u2 2129 B6 6210 B9
1 2 CT286D8
6151 6153 4 10
2130 B7 6211 B9
3120
220n
680K
3122
2120
V
2131 A7 6215 C9
4 5121 3 1N4006 1N4006 2136 C7 6220 E8
0101-1 5115
220K
220K
2126
220u
2129
3127
3128
10n
6152 6154 2139 D3 6221 E8
HSC0528 1 2u2 2140 C4 6230 F8
B +12Vreg B 2141 D4 6231 F9
2119
1N4006 1N4006
3123
+12V
10M
1n
14 6210 6211 5210 2142 D2 6240 D9
BYD33J
+12Vstby 2143 E3 7125 C6
2130
6125
47p
1125 3126 3125 10u 2144 E4 7140 D4
BYW29EX 1N4004
2145 E4 7141 D3
2210
680u
100u
2211
1M 1M 2
2146 C5 7142 D2
0210 2147 D5 7143 D3
MECHPART
30V 0125 Heatsink 2151 E5 7200 G7
5125
83R
(20V) 15 2152 E7 7220 E9
Vd 2153 D5 7241 D11
3140 6140 3131 2200 B9 7251 G8
C 2K7 BAV21 47R C 2201 B10 9110 A3
BAS216
BAS216
+3.9V 2210 B9 9115 B3
2140
3141
220R
100n
220p
2136
7125
6145
6146
3142
22K
2146 12 6215 2211 B10
STP5NB60FP
Vg +3V9 2212 B9
470p 3132 Vs
STPS745FP 2214 C9
2214
2m2
2215 C9
1N4004 1N4004 1N4004

47R
6130
BAS216 2220 E9
6141
100K
2139
100n
3143
3139
0260
1K
2221 E10
BC847B MECHPART 2222 E10
3135
3134
3133
1R5
1R5
1R5
7142 13
6131
BC857B 2223 E10
3146 Vreg
7141 2230 F9
+5V
100R 17 6240 5240 2235 F10
D -0.07V 2153 3152 +5Vstby 3223 D 2240 D9
6132
220p
2142
3144
7140 1u
1K
(-0.3V) BYW29EX FLYB 2241 D10

BC847B
1000u
68p 22K BC857B 4K7 2242 D9
2240
100u
2241
2147 -13V 6142
7143 3145 3147 3150 7241 3222 2251 G9
BC847B 22K 2K2 68R 8 0240 4K7 3120 B3
10u BAV21 Heatsink 3122 B3
470n
2144
3148
2151
100n
3220
2K2
2K2
16 3123 B2
3125 B5
3149
2K2
6221 3221 3126 B5
7 7220 22K 3127 B7
100K
100n
2143
470n
2145
BAV21
3151
6143 6144 L7905 -5V 3128 B7

11 6220 3129 A5
E BAV21 BZX284-B15
2
IN GND
3
OUT
-5Nstby E 3131 C6
BYV27-200 3132 C6
1
330p
2152
220u
2220
100u
2221
2223
100n
3133 D6
3134 D6
0290 3135 D6
Heatsink
3139 D4
18
0205 EH-B 3140 C5
3230 1
6230 +12Vstby 3141 C4
-Vgnstby 2
3142 C3
BZX79-C33
BYD33J +5Vstby 3143 D3
47R
3234
3144 D2
100u
2230
6231
330u
2235
3233
10K
3
10K
-5Nstby
F -Vgnstby
4 F 3145 D4
3146 D5
5
3147 D5
+33Vstby 3148 E5
6
+4.4V 3149 E7
FLYB
3150 D6
7 (+1.7V) 3151 E4
2251 3253 3255 3254
Vreg 3152 D5
1 22n 47K 4K7 470R 3200 A10
TCET1102 7251 3201 B10
7200 TL431CZ 3220 E11
3 3256
3250 +12Vreg 3221 E11
G 4K7 G 3222 D11
470R 3223 D11
(.....V) MEASURED IN STANDBY 2
3230 F9
Prot_3V3 3233 F9
3234 F10
3250 G8
3253 G9
Vdrain (no disc loaded) Vdrain (standby) Vsource(standby) 3254 G10
Vgate (no disc loaded) Vgate(standby) Vsource (no disc loaded)
3255 G9
3256 G9
5110 A3
5115 B3
H H 5120 B4
5121 B4
5125 C7
5131 B7
50V/div DC 5us/div
5210 B10
50V/div DC 5us/div 10V/div DC 5us/div 10V/div DC 5us/div 500mV/div DC 5us/div 500mV/div DC 5us/div
5240 D9
CL 16532111_020.eps 6125 B7
100901 6128 A4
6129 A5
1 2 3 4 5 6 7 8 9 10 11 12
Power Supply
1 2 3 4 5 6 7 8 9 10
0200 G9
0201 G10
0202 G10
0207 B8
0209 A10
0221 B3
A 0209 A 1520 B4
2501 D4
1 EH-B
+3V3 2502 D5
2 2506 F4
+3V3 2511 E9
3 2512 E10
+3V3
2513 E10
0221 4 2515 E8
0207 +3V3
MECHPART EH-B 2520 B4
1 5
+3V3 2521 B5
5520 1520 2 6
+3V3 +5V +12V 3501 D3
+3V9
2u2 3502 D4
3A15 3 7
B B 3503 D4
510R
MP
3520
7520 4 8 3504 E4
+4V6 3511 E9
6520 STP16NE06 2520
100u
5 9
3525
3512 E9
1K5
+5V
2521
Prot_3V3
3513 F9
BAS216 22n 6 10
-5V STBY_ctrl 3514 E10
680R
3523
3521
3522
1
2K2
1K 7 11 3515 E7
3516 E7
3 8 12 3520 B3
+12V -5V
3521 C3
+12V 3522 C3
3524
4K7
3523 C4
C 2
7521 C 3524 C4
TL431CZ 3525 B4
5501 C4
5505 E4
5511 D10
5501 5515 D7
+5Vstby +5V 5520 B4
2u2
6505 E3
6511 E9
7501 6512 D9
2501 6515 E7
100u
2502
3502
IRLML2502
4K7
D 22n D 6520 B2
7501 D3
680R
3503
3501
1
2K2
7502 E3
7515 7511 E9
3 IRLML2502 5515 6512 5511 7512 E9
-5Nstby -5V +12Vreg +12V
10u 10u 7515 D7
BZX284-C8V2
+12V 1N4004 7520 B3
100u
2515
6511
100u
2512
2513
100n
3504
4K7
7521 C3
2 7502
7511
TL431CZ IRLML2502
3516
10K
E E
3512
4K7
3515 BZX79-C6V8 3511 2511
+12V +33Vctrl
6505 5505 10K 10K 100n
6515
+5V +4V6 7512 10K
BYV10-40 10u STBY_ctrl
BC847B 3514
100u
2506
3513
47K
F F
0200 0201 0202
G G
CL 16532111_021.eps
100901
1 2 3 4 5 6 7 8 9 10
Layout Power Supply (Top View)

0101 A1 0209 B6 1520 B5 2130 A3 2212 A5 2240 A5 2521 B6 3128 A3 3141 B3 3223 A6 5115 A1 5501 A7 6129 B1 6151 B2 6211 A6 6505 A7 7502 A7 9214 A4 9511 A6
0125 B3 0210 A5 2119 A2 2131 A4 2214 A5 2241 A6 3120 B1 3129 B2 3146 B3 3230 A6 5120 A2 5505 A7 6130 A3 6152 A2 6215 A5 6512 A6 7520 A5 9215 A4 9512 A6
0200 A3 0221 A6 2120 B1 2136 A3 2215 A5 2242 A4 3122 B1 3131 B3 3148 B2 3250 A5 5121 A1 5511 A6 6131 A3 6153 A2 6220 B4 6515 B7 7521 A6 9220 B5 9520 A5
0201 A7 0240 A5 2125 B2 2147 B4 2220 B5 2502 B6 3123 A1 3132 B3 3149 A3 3254 A4 5125 A3 5515 B7 6132 A3 6154 A2 6221 A4 7125 A3 9110 B1 9221 A6 9521 A5
0202 A5 0260 A5 2126 B2 2200 A5 2221 A7 2506 B7 3125 B2 3133 A2 3150 B3 3501 B7 5131 A4 5520 B5 6140 B3 6200 B4 6230 A4 7200 B4 9115 A1 9222 A7
0205 A6 0290 B5 2127 B1 2210 A5 2230 A5 2512 A6 3126 B2 3134 A3 3152 B3 3514 A6 5210 A6 6125 A3 6142 B2 6201 A7 6231 A7 7220 B5 9207 B6 9250 B4
0207 B6 1120 B1 2129 A3 2211 A6 2235 A7 2515 B7 3127 A3 3135 A3 3200 A6 5110 A1 5240 A5 6128 B1 6143 B2 6210 A5 6240 A4 7251 B4 9209 B6 9251 B4
CL 16532095_048.eps
100801
Layout Power Supply (Overview Bottom View)

2139 A2 2143 A2 2151 A2 2222 A5 2511 B6 3140 A4 3145 A2 3220 B6 3234 B7 3502 B7 3512 B6 3520 B5 3524 B6 6145 A3 7140 A2 7241 B6 7515 B7
2140 A2 2144 A2 2152 B3 2223 B7 2513 A6 3142 A2 3147 A4 3221 B6 3253 A4 3503 B7 3513 B7 3521 B5 3525 B6 6146 B3 7141 A2 7501 A7
2141 A3 2145 A2 2153 A3 2251 A4 2520 B6 3143 A2 3151 A2 3222 B6 3255 A4 3504 B6 3515 B7 3522 B6 6141 A3 6511 B6 7142 A2 7511 B6
2142 A2 2146 A3 2201 B7 2501 A7 3139 A3 3144 A2 3201 B6 3233 B7 3256 A4 3511 B6 3516 A7 3523 B6 6144 A3 6520 B5 7143 A2 7512 B7
PART 1 PART 2
CL 16532095_49a.eps CL 16532095_49b.eps
CL 16532095_049.eps
100801
Layout Power Supply (Part 1 Bottom View)
CL 16532095_49a.eps
100801
Layout Power Supply (Part 2 Bottom View)
CL 16532095_49b.eps
100801
Display Panel
0201 I1 6177 D4
1 2 3 4 5 6 7 8 9 10 11 12 13 0202 I2 6178 D4
0203 I3 6179 D4
0206
12STBY 12STBYSI 0204 I4 6180 D4
DISPLAY HOLDER
II I SAP STEREO NICAM DIGITAL MANUAL PCM DTS AC-3 MPEG PROLOGIC 0206 A12 6181 D3
7150 1150 A1 6182 D3
VGNSTBY1 OVER 0 10 20 30 40 OVER 0 10 20 30 40
F102 F101 BJ801GNK 1153 F13 6183 B3
F104
VGNSTBY1 1156 I5 6184 A3

F103 6150
1159 I9 6185 B3
1160 I9 6186 A3
BAW56W
250mA
BZX284-C6V8
1150
PSC
1162 I8 6187 B4
A A
3152
22K
6160
BAW56W
BAW56W
DECODER RECORD TIMER SAT MONITOR L:P SP HQ SAVCD DVD+RW 1163 H12 6188 A4
1N4148
1N4148
1N4148
1N4148
1167 H9 6189 B4
6164
6166
6157
6159
6161
6168
PM 1168 H9 6190 A4
1N4148
1N4148
1N4148
1N4148
1N4148
1N4148
1N4148
F105
6184
6186
6188
6190
6192
6194
6196
1169 H9 6191 B4
BAW56W
F106 AM
5153 1170 H8 6192 A4
6155
1171 H8 6193 B4
1N4148
1N4148
1N4148
S16977-03 VPS/PDC CHANNEL REMAIN TIME TRACK TOTAL CHAPTER TRACK TITLE
6165
6167
6158
5151
10u
GNDD 1174 I10 6194 A5
1
3
1N4148
1N4148
1N4148
1N4148
1N4148
1N4148
1N4148
6183
6185
6187
6189
6191
6193
6195
1 2 3 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 67 68 69 1916 E1 6195 B5
F107 1917 H1 6196 A5
BAW56W
6197 2150 H2 6197 B6
2151 H2 6198 H6
2152 B2 7150 A5
3158
3155
1N4148
2154
330u
2155
100n
22K
2K2
VGNSTBY1
2152 6152 2154 B1 7151 C1
B 47n 6169
B 2155 B1
2156 E1
7152 C2
7153 C2
I100
I101
2157 D1 7155 E4
BAW56W
GNDD 2158 E12 7156 D12
2159 E13 7157 G2
F108
GNDD GNDD
2160 E1 7160-A H4
2161 E2 7160-B H4
2162 E13 7160-C H3
STN3NE06
2163 F13 7160-D H3
7152
7153
BC847BW 2165 F13 7164 I6
2167 G2 7165 H6
6151 3153 I102 3160 2168 G1 7166 I6
C 5R6 5R6
F109
C 2169 H4
2170 I8
9100 E3
F101 A3
I103 MCL4148
2180
BAW56W
3157
2171 G3 F102 A2
BAW56W
7151
47K
BC847BW 2173 H8 F103 A2

100n
6172
6174
2174 E2 F104 A1
2175 H11 F105 A1
BAW56W
BAW56W
3150 3159
1N4148
1N4148
1N4148
1N4148
2177 I12 F106 A1
6181
6179
6177
6175
6170
5K6 5K6 {P(37:0),G(15:0),P(77)}
GNDD 2179 H12 F107 B1
2180 C1 F108 B2
2157
10n
BAW56W
GNDD 3145 H13 F109 C3
6171
6173
1N4148
1N4148
1N4148
1N4148
3146 H10 F110 D1
6182
6180
6178
6176
I104
I105
I108
I109
I106
I107
I110
I111
I112
I113
I114
I115
I116
I117
I118
I119
I120
I121
I122
I123
I124
I125
I126
I127
I128
I129
I130
I131
I132
I133
I134
I135
I136
I137
I138
I139
I140
I141
I142
I143
VGNSTBY1
F110 3147 H11 F111 E13
D 7156 D 3148 G9 F112 F1
66 67 68 69 70 71 72 73 58 59 60 61 62 63 64 65 49 50 52 53 54 55 56 57 41 42 43 44 45 46 47 48 33 34 35 36 37 38 39 40 TMP88CU77F 3150 C1 F113 G10
3163
10K
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
P90
P91
P92
P93
P94
P95
P96
P97
P80
P81
P82
P83
P84
P85
P86
P70
P71
P72
P73
P74
P75
P76
P77
P60
P61
P62
P63
P64
P65
P66
P67
3151 I6 F114 G10
P87
VGNSTBY VGNSTBY1 VSS1 29 3152 A1 F115 F1
VGNSTBY 5M 5STBY 12STBY VGNSTBY1 I144 3153 C2 F116 H11
I148 PE7 PD P9 P8 P7 P6
81
VSS2 90 3154 F3 F117 F1
I145 PE6
7155 GNDD F111 3155 B1 F118 F1
VKK 87
GNDD BC847BW I146 80 VFT DRIVE CIRCUIT VGNSTBY1 3156 I7 F119 F1
9100
PE5
2156
100n
2160
100n
2161
100n
2174
100n
VDD1 88 3157 C3 F120 F1

I152 3161 I147 79 5STBY1
PE4 3158 B1 F121 H7
VDD2 32 3159 C1 F122 H7
I154
PE
68K I149 78
BZX384-C2V7
PE3
2158
100n
2159
100n
E E 3160 C2 F123 F1
3162
PROGRAM MEMORY DATA MEMORY TLCS-870/X VDD3 51

68K
I150 77
PE2
3161 E4 F124 G1
6154
GNDD GNDD GNDD GNDD ROM RAM CPU 3162 E4 F125 G1

OPTION
76
I151 PE1 RESET_ 92 3163 D1 F126 G1
I158 2162
PH-B INTERRUPT CONTROLLER GNDD GNDD 3164 F3 F127 G1
GNDD
I153 75 SYSTEM CONTROLLER
PE0 TEST 95 3165 I6 F128 G1
1916 15p
1 F112 temp_sensor 74
STANDBY CONTROLLER 3166 F3 F129 H5
5STBY 5STBY 5STBY I157 TIME BASE 3167 G3 F130 H2
PF4 8-BIT SERIAL EXPANSION 16-BIT
TIMER TIMING GENERATOR I155 12M Hz
2 F115 TIMER/ TIMER/ TIMER/ XIN 89 3168 G3 F131 H1
1153
12STBY I159 86 INTERFACES
PF3 COUNTER COUNTER 1 COUNTERS 3169 F2 F132 I1
I156 CST
3 F117 CLOCK HIGH FR XOUT 91 OPTION 3170 G5 F133 I1
VGNSTBY I160 85 SIO3 WATCHDOG
3169
3193
3154
PF2 TC4 ETC1 TC2 TC1

10K
10K
10K
PF I2C BUS SIO0/1

4 F118
GENERATOR 2163 3171 I8 F134 I1
TIMER LOW FR
F GNDD
I170
I161 84
PF1
2165
GNDD
F 3172 G1 F135 I1
5 F119 IPOR1 3164
10n
15p 3173 G1 F136 I1
I162 83
I171 PF0
GNDD 3174 G3
6 F120 SDA 3166 10K
3177 I9
82
8-BIT
P3 P1 P0 P5 P4 P2 3178 I9
7 F123 270R A/D
VAREF
GNDD
VASS
CONV 3180 I8
P30
P31
P32
P33
P10
P11
P12
P13
P14
P15
P16
P17
P00
P01
P02
P03
P04
P05
P06
P07
P50
P51
P52
P53
P40
P41
P42
P43
P44
P45
P46
P47
P20
P21
P22
I172
8 F124 SCL 3167 3182 H5
I173 13 14 15 16 5 6 7 8 9 10 11 12 97 98 99 100 1 2 3 4 25 26 27 28 17 18 19 20 21 22 23 24 30 31 96 93 94 3183 H8
9 F125 INT 3168 270R NC* NC* NC* NC* 3186 H9
10 F126 RC 3172 7157 100R 3187 H9
BC847BW 3188 H9
I403 I404 I406
11 F127 4K7 I174 3189 H8
G 5STBY
G 3190 H8
5STBY
12 F128 3174
3192 I1
5M I168
3173
2168
100p
2167
470p
10K
4M7 3193 F2
3194 I13
3148
4100
2K2
2171 I199 6156 3170 I402 3197 I10
F113
F114
I164
I165
4100 G10
I166
I167
220n MCL4148 F129 1K
2169
5STBY 4151 H5
F116
GNDD GNDD GNDD GNDD 5STBY 2175 5150 H1
5STBY GNDD
3146
10K 3147
5STBY OPTION 5STBY
10K
I198
5STBY 5STBY1 GNDD 10n 5151 A1

5STBY 4151
7160-B GNDD 7160-A 1u 5153 A2
5150 F130 7160-C 3183
3190
3189
3188
3187
3186
HEF4093BT 14 HEF4093BT 14 6150 A4
2K2
47K
10K
4K7
2K2
5STBY
1K
7160-D HEF4093BT 14 5 1 GNDD
H 10u 5STBY I175 3145 H 6151 C1
F121
F122
CABLE TREE HEF4093BT 14 8 4 3 5STBY

I184 5STBY 6152 B9
12 10 6 2 <
2150
2151
100n
I176
I177
I178
I179
I180
47u
1917
11 9
6198 < 10K 6154 E3
OPEN/CLOSE
REC VOLUME
6155 A13
CHANNEL
temp_sense 13
RECORD
7 7
STOP
PLAY
I400
MCL4148 6156 G3
2173
1171
1170
1169
1168
1167
1163
2179
7
10n
10n
7 F131
3182
1K5
GNDD GNDD GNDD 7 6157 A13

6
GNDD GNDD 7165
F132 3192 GNDD GNDD 6158 A13
IRR PDTC124EU
BC847BW 6159 A13
5 F133 1K I197
Key in 7166 5STBY 6160 A11
GNDD GNDD 3194
6161 A12
4 F134 5STBY
stbyled
1156
3165 2K2
6164 A12
3 F135
5STBY 6165 A12
3171
3180
3178
3177
3197
I I
2K2
10K
2K2
4K7
1K
5STBY 2K2 6166 A12
2177
10n
2 F136 6167 A13
NC 0201 0202 0203 0204 12STBYSI <
3156
6168 A13
I185
I187
I188
I191
10K
1 GNDD <
EARTH SPRING EARTH SPRING EARTH SPRING EARTH SPRING GNDD
REC VOLUME
6169 B9
REC VOLUME
MONITOR
AUTO-MAN
CHANNEL
I401 3151 6170 D12

2170
1162
1160
1159
1174
7164
10n
6171 D13
BC847BW 1K GNDD 6172 C13
GNDD GNDD GND_FC GND_FC 6173 D13
GNDD
6174 C13
GNDD CL 26532011_004.eps
6175 D4
150102 6176 D4
1 2 3 4 5 6 7 8 9 10 11 12 13
1
Layout Display Panel (Top View)

0206 A4 1156 A7 1163 B7 1170 A9 1911 B4 2140 B1 3110 B4 3156 A3 3167 A4 5153 A2 6159 A3 6167 A3 6178 A5 6182 A5 6186 A5 6190 A6 6194 A6 7140 B1 9102 A4 9106 A2 9110 A4 9114 A3
1140 B2 1159 B9 1167 B9 1171 A7 1915 B1 2150 A3 3135 B1 3157 A2 3168 A3 6140 B2 6164 A3 6175 A5 6179 A5 6183 A5 6187 A5 6191 A6 6195 A6 7150 A4 9103 A3 9107 A4 9111 A4 9115 A2
1150 A1 1160 A9 1168 A9 1174 A1 1916 A1 2152 A2 3152 A1 3164 A5 5150 A2 6157 A3 6165 A3 6176 A5 6180 A5 6184 A5 6188 A6 6192 A6 6196 A6 9100 A2 9104 A3 9108 A5 9112 A4 9116 A2
1153 A5 1162 B8 1169 A8 1910 B4 1917 A1 2154 A2 3154 A1 3166 A4 5151 A1 6158 A3 6166 A3 6177 A5 6181 A5 6185 A5 6189 A6 6193 A6 6197 A6 9101 A5 9105 A3 9109 A6 9113 A3 9151 B3
CL 26532011_007.eps
170102
Layout Display Panel (Overview Bottom View)

2100 B6 2151 A7 2161 A9 2170 B2 2180 A8 3106 B7 3136 B8 3143 B8 3150 A8 3161 A7 3172 A8 3183 A9 3193 A8 4103 A9 4110 A8 4117 A9 4300 B9 6151 A8 6168 A7 6198 A7 7145 B8 7160 A7
2101 B7 2155 A8 2162 A5 2171 A8 3100 B7 3107 B7 3137 B8 3144 B8 3151 A9 3162 A7 3173 A8 3186 B1 3194 A9 4104 A9 4111 A8 4118 A9 6100 B7 6152 A8 6169 A7 7100 B7 7151 A8 7164 A9
2102 B7 2156 A9 2163 A5 2173 A3 3101 B7 3108 B7 3138 B8 3145 A9 3153 A8 3163 A8 3174 A8 3187 A1 3197 A9 4105 A9 4112 A7 4119 A9 6101 B6 6154 A8 6170 A5 7101 B6 7152 A8 7165 A7
2103 B7 2157 A8 2165 A5 2174 A9 3102 B7 3109 B7 3139 B8 3146 A7 3155 A9 3165 A7 3177 B1 3188 A2 3999 B9 4106 A9 4113 A7 4120 A9 6102 B6 6155 A6 6171 A6 7141 B8 7153 A8 7166 A7
2104 B7 2158 A5 2167 A8 2175 A7 3103 B7 3111 B6 3140 B9 3147 A7 3158 A8 3169 A8 3178 A1 3189 A1 4100 A7 4107 A9 4114 A6 4121 A9 6103 B6 6156 A8 6172 A6 7142 B8 7155 A7
2105 B7 2159 A5 2168 A8 2177 A9 3104 B7 3112 B6 3141 B8 3148 A7 3159 A8 3170 A7 3180 B2 3190 A3 4101 B7 4108 A8 4115 A5 4122 A9 6104 B6 6160 A8 6173 A6 7143 B8 7156 A6
2106 B5 2160 A8 2169 A7 2179 B3 3105 B7 3113 B5 3142 B8 3149 B9 3160 A8 3171 A9 3182 A4 3192 A9 4102 B7 4109 A8 4116 A7 4151 A7 6150 A8 6161 A7 6174 A6 7144 B8 7157 A8
Part 1
CL 26532011_08a.eps
Part 2
CL 26532011_08b.eps
CL 26532011_008.eps
170102
Layout Display Panel (Part 1 Bottom View)
CL 26532011_08a.eps
170102
Layout Display Panel (Part 2 Bottom View)
CL 26532011_08b.eps
170102
Front AV Part
1910-A D1
1 2 3 4 5 6 7 8 1910-B B1
1910-C C1
1910-D F1
8SW_FC
8SW_FC
OPTION 1911 D8
2100 A6
2101 A5
2102 B3
2103 C6
2104 C5
470K
3100
A A
2100
100n
2105 D3
2106 F2
F200 3101 I300 2101 I301 3100 A5
7100
3101 A3
AR 8 1K 1u BC847BW
GND_FC 3102 B4
6 6100 3103 B5
3104 B6
YKC22-0489 7 3105 C5
2102
330p
680K
3102
4101
3103
3104
4K7
1M
1910-B 3106 C3
3107 D4
F201
3108 D5
DF3A6.8FU
B GND_FC GND_FC GND_FC GND_FC GND_FC GND_FC B 3109 D6
3110 D4
3111 D2
3112 E2
8SW_FC
8SW_FC
OPTION
3113 F2
4101 B4
4102 D4
6100 A3
6101 C3
470K
3105
6102 D3
2103
100n
6103 E3
6104 F3
C F202 3106 I302 2104 I303 7101 C 7100 A6
7101 C6
AL/MONO 11 1K 1u BC847BW
GND_FC F200 A2
8SW_FC
9 6101 F201 B1
F202 C2
YKC22-048910 F203 D7
2105
330p
680K
3107
4102
3108
3109
4K7
1M
1910-C 1911 F204 D7
F203 1 F205 D7
AFCRI_FC
DF3A6.8FU F204 F206 D2
2
GND_FC F207 D7
GND_FC GND_FC GND_FC GND_FC GND_FC GND_FC
F205 3 F208 D7
AFCLI_FC F209 D7
D 12 F206 3110 F207 4
CVBSFIN_FC
D F210 D7
CVBS 6102 150R F208 F211 E1
5
13 GND_FC F212 E7
F209 6 F213 E7
3111
75R
YKC22-0489 8SW_FC I300 A3

1910-A F210 7 I301 A5
F211 CFIN_FC
DF3A6.8FU F212 I302 C3
8
GND_FC I303 C5
GND_FC GND_FC GND_FC
F213 9 I304 F2
YFIN_FC
6103
PH-S
E E
3112
75R
GND_FC
GND_FC
DF3A6.8FU
5 YKC22-0489
GND_FC GND_FC
3 4 6104
1 2
3113
75R
1910-D
GND_FCGND_FC
F I304 DF3A6.8FU F
GND_FC
2106
100n
CL 26532011_006.eps
GND_FC
150102
1 2 3 4 5 6 7 8
Layout Front AV Part
2100 A3 3113 A1
2101 A3 4101 A3
2102 A3 4102 A2
2103 A2 6100 A3
2104 A2 6101 A3
2105 A2 6102 A2
2106 A1 6103 A1
3100 A3 6104 A1
3101 A3 7100 A3
3102 A3 7101 A2
3103 A3
3104 A3
3105 A2
3106 A2
3107 A2
3108 A2
3109 A2
3111 A1
3112 A1
1910 A2
1911 A2
CL 16532095_035.eps
080801
IR and Standby Panel

Layout IR and Standby Panel (Top View)
1140 D2
1 2 3 4 1915 C1
2140 E2
5VSTBY 3135 D1
IR and Standby Panel 5VSTBY 3136 A3
3137 B3
3138 C3
390R
3144
3139 C4
3143
10K
3140 D2
I310 3141 D3
3999
3142 D2
A A
I311
3136 I312 7143 3143 A3
BC857BW 3144 A4
4K7 3149 C3
I314 3999 A2
7141 6140 B4
PDTC124EU 7140 D4
Layout IR and Standby Panel (Bottom View)
7141 A2
3137 I313 7142 7142 B4
BC847BW 7143 A4
4K7
7144 C4 3142
7145 D4
B B F300 C1 3140
3137
3144
6140
3136
3143
F301 C1
GND LTL-14CHJ
3141
3139
3138
3149
GND 2 F302 C1
F303 D1
F304 D1
5VSTBY
F305 D1
1 F306 D1
5VSTBY I310 A4
390R
3139
I311 A2
I312 A3
I313 B3
3138
10K
I316 I314 A4
C 1915 3149 I317
C I315 D4
F300 7144 I316 C4
1 NC BC857BW I317 C3
4K7
2
F301 I318 D3
5VSTBY I319 D2
F302 stbyled
3 I320 D3
1140 I315
4
F303 key in 3142 I319
3141 I318 7145
F304 IRR 47K STBY
5
4K7 BC847BW
6
F305 GND
5VSTBY
D 7
F306 temp_sense
D
GND GND
2322640
CABLE TREE
220R
3140
3135
7140
TSOP2236
I320
2 VS CTRL
INP
CIRCUIT
GND
1 OUT
BAND
DEM PASS AGC PIN
E E
2140
22u
3 GND
GND GND
1 2 3 4 CL 26532011_005.eps
170102
Analog Board: All in One 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14
1802 H5 7805 D3 I975 D4
1980 A10 7806 E2 I976 D7
12STBY
All In One 1 AIO1 1981 D13 7807 F5 I977 C7
AGC_MUTE
to TU, AP
IPOR_EPG
SDA1
to EPG
SCL1
to TU, AP
5SW 5SW
A_YCVBS
A_YCVBS
1982 H14 7809 F4 I978 C7
INT_EPG
WSRO
1987 D14 7810 H1 I979 C7
SCL1
GNDD
GNDD
SDA1
GNDD
WSRI
WSFI
5SW
AFC
WU
2800 A1 7811 H7 I980 C7
VD
IS2
IS1
100n
2832
2831
47u
2802 A4 7812 I3 I981 C7
PH-B
7800-A 2804 A9 7813 I5 I983 F11
1980
3 4
TL074 2805 A10 7815 C13
3805
3804
100K
3802
2819 I803
2K2
2K2
1 I802 12 7800-D 2806 B1 7816 A3
1
2
3
4
5
6
7
8
4 2807 B4 7817 B3
TL074 F8002
470n 14 6802 GNDD 2808 D12 F800 C10
A 2
A
F8005
F8006
F8007
F8008
VGNSTBY
2809 D13 F8001 A10
5NSTBY
3807
100K
5STBY2
3810
12STBY
F801 2800 11
5STBY
F810 3826
GNDD
F811 2810 F3 F8002 A10
680K
F8004
3813
2802
3811
470n
13 MCL4148
4K7
8SW
5SW
ALADC
12STBY 2811 G6 F8003 A11
470n 11 100R
7816 2812 G1 F8004 A11
F8001
F8003
I800
1K 1%
not used
not used
not used
2805
100p
2804
100p
2813 G6 F8005 A11
I836
I837
I816
I817
I815
I821
I820
I819
I818
BC847BW
100K
3815
3822
2814 H4 F8006 A11

I801 2815 H5 F8007 A11
5NSTBY GNDD GNDD
5SW 2816 H3 F8008 A11
5NSTBY 8SW 5SW 5STBY2 5STBY 12STBY VGNSTBY GNDD 2817 H3 F801 A1
I804 3809 GNDD GNDD 3828 GNDD GNDD
GNDD GNDD GNDD 2818 I6 F802 B1
2819 A2 F803 H5
GNDD
10K 3800 100R
2820 B2 F804 G6
F802 2806 I806 5 7800-B 8K2 2821 B4 F808 I10
4 2822 C4 F810 A9
ARADC TL074 5STBY2 5STBY2 5STBY2
2820 I809
B B 2823 D14 F8101 D13
GNDD
470n 7 I808 10 7800-C 2821
4
not used
2827 F2 F8102 E13
100R
100R
100R
100R
TL074
I830 3816
I832 3818
I833 3819
3871
5STBY2
3820
3835
4K7
10K
6 470n 8 6803 4u7 5,2V 2831 A3 F8103 E13
2832 A4 F8104 E13
100K
3829
3837
11 8
3800 B4 F8105 E13
680K
3838
3842
0V
2807
470n
9 MCL4148
3821
I829
I831
not used
4K7
10K
12STBY VCC E0 3802 A8 F8106 E13
100R
3823
3833
3836
3834
10K
2K2
2K2
11 7817 1 3804 A9 F8107 E13
ST24E16 0V
1K 1%
BC847BW 6 5 4 3 2 1 7815 E1 3805 A10 F8108 E13
3825
3839
10K
10K
3915 2 0V
100K
3807 A2 F8109 F13

3832
3854
I945
PB4|SDA1
PB5|SCL1
P53|INT1
P52|INT2|TI1
P51|INT3|TI2
I807 120 F800
P50|INT4|TI3
SDA E2 3809 B4 F811 A9
7 F_MODE 3
GNDD GNDD P54|INT0 PB3|SCK1 100R 5,2V 5 5,2V 3810 A2 F8110 F13
I981 8 119 I841 SCL 3811 A4 F8111 F13
100R I946
I810 3831 P55|TI5|AIN0 PB2|SO1|SI1 6 0V 3813 A4 F8112 D13
GNDD GNDD GNDD I980 110 I842 VSS WC_
9 3815 A2 F812 F7
C 10K P56|TI4|AIN1 P77|SCK0 7
C
3914
3816 B8 F8201 H14
GNDD
3824 I979 10 109 I843 4 0V
P76|SI0 3818 B9 F8202 H14
P57|TI0|AIN2
8K2 I978 3819 B9 F8203 H14
14 108 I844 3820 B6 F8204 H14
P40|AIN3 P75|SO0
3821 B5 F8205 H14
GNDD
2822 I977 3840 GNDD
5STBY 5STBY2 15 107 I845 SCL 3822 A1 F8206 H14
P41|AIN4 P74|SCL0
I972 100R 3841 3823 B10 F8207 H14
4u7 16 106 I846 SDA 3824 C4 F8208 I14
P42|AIN5 P73|SDA0
I971 3844 100R 3825 C6 F8209 I14
102 I948
3848
17
47K
not used
not used
P43|AIN6 P72|CTS_ F8112 4801 3826 A10 F8210 I14
2808
100p
2809
100p
3843 I976 1K 3846 TEMP_SENSE 3828 B10 I800 A1
I891 18 101 I848
3850 P44|AIN7 P71|RXD 3829 B2 I801 A3
2823
100n
BC857BW
10K 3892 I838 19 100 I849 3847 1K 3830 E6 I802 A2
I890 7804 I975 3851
D KIL
4K7 5STBY2
3893 10K I839 20
P45|AIN8
7803-B
P70|TXD
99 I862 3K3
D 3831 C4
3832 C1
I803 A2
I804 B3
10K P46|AIN9 P67|PWM11 GNDD GNDD 3833 B12 I806 B1
5STBY 7805 10K 3891 not used I866 21 98 I863 3889 1981 GNDD 1987 3834 B13 I807 C3
3852
TMP93C071
22K
P47|AIN10 P66|PWM10
100K
BC847BW 1 1 3835 B6 I808 B2

3853
3845 100K I974 97 I864 1K TEMP_SENSE

3849
22 3836 B11 I809 B2

10K
PC0|AIN11 P65|PWM9 F8101 2 2 3837 B2 I810 C3

GNDD 4K7 I859 I865 12STBY 12STBY
3899
23 96
10K
3838 B4 I813 I11
PC1|AIN12 P64|PWM8 F8102 3 3
I894 3855 I973 3865 3839 C6 I815 A5
95 I867 VGNSTBY VGNSTBY
GNDA 5NSTBY BC857BW 24
P63|PMW7 3840 C10 I816 A5
PC2|AIN13 F8103 4 4
I893 7806 4K7 100R GNDD GNDD 3841 D11 I817 A6
25 91 GNDD 3842 B4 I818 A6
KIR PC3|AIN14 PA5|PWM3|HWR_ F8104 5 5
IPOR1 3843 D6 I819 A6
26 89
E E 3844 D10 I820 A5
3859
PC4|AIN15 PA3|PWM2 F8105 6

100K
3858
6
22K
3860 SDA SDA 3845 D6 I821 A6

27 88 3846 D11 I822 I9
8SW P80|CTLIN PWM1 F8106 7 7
6K8 3830 GNDD GNDD 3847 D10 I829 B8
3896 28 87
10K
5SW P81|DFGIN PWM0 F8107 8 8 3848 D3 I830 B8
4K7 SCL SCL 3849 D4 I831 B9
GNDA 5NSTBY 29 86
P82|RMTIN PA2|CR|TPG00 F8108 9 9 3850 D3 I832 B9
IPFAIL 5SW 5SW I970 30 85 INT 3851 D4 I833 B9
GNDD P83|EXT PA1|HA|TPG05 F8109 10 10 3852 D2 I836 A5
3894 RC 3853 D1 I837 A5
I898
PWR 31 84
5STBY
FLYB P84|DPGIN PA0|PV|PH F8110 11 11 3854 C2 I838 D7
100K 42 I852 5STBY
3857
3855 E3 I839 D7
2K2
32
P85|CFGIN P97|TPG11
220K
3895
2827
100n
12 3857 F4 I841 C10

F812 PH-B
P90|TPG12
P91|TPG01
P92|TPG02
P93|TPG03
P94|TPG04
P95|TPG13
5M
33 41 I853 3858 E2 I842 C10
F I897 PDTA124EU P86|CSYNCIN P96|TPG10 not used
F
I983
I903
3859 E2 I843 C10
7807 34 PH-B
3862 I896 3860 E5 I844 C10
not used 7809 5STBY2 P87|COMPIN 3861 F4 I845 C10
GNDA GNDA F8111 5M
22K BC847BW 3879 3862 F3 I846 D10
from PS 3865 E10 I848 D10
35 36 37 38 39 40
2810
BAS385
3867 G8 I849 D10

1n
10K 6807 I892

3861
6805
10K
IPOR 3868 G9 I852 F10
100R
only for SW fan control 3917
only for SW fan control3916
3890
10K
10K
I858
I861
I857
I856
I855
I854
MCL4148 3869 G9 I853 F10
for SATCONTROL only

GNDD 3870 G9 I854 G9
I899 F804 3871 B8 I855 G9
3885
2K2
not used
not used GNDD GNDD GNDD 3872 G5 I856 G9
100R
100R
100R
3884
3867
3923
3868
3869
3870
10K
3K3
1K
4906 3873 G6 I857 G8
not used
3874 G7 I858 G8
220m
3872
3873
2811
2813
470u
10K
10K
not used
G 5SW G 3875 H12
3876 H3
I859 D7
I861 G8
I886 3898 GNDD 3877 H5 I862 D10
3878 I5 I863 D10
10K 3879 F6 I864 D10
I870 GNDD GNDD 3874
2812
100n
3880 I9 I865 E10

3881 I5 I866 D7
12K 1982 3882 I1 I867 E10
5SW 5,1V 7811 F8201
2814
2815
1
3883 H3 I870 G5
10n
18p
GNDA 8 PCF8593T IRESET_DIG

3884 G7 I871 H5
7810 F8202 2
3885 G10 I872 H5
I871 VDD A_DATA
BA7046F 7 1 OSCI 3886 I4 I874 H5
VCC 2,5V F8203 3
3887 I3 I875 H5
I872 2 OSCO OSCILLATOR DIVIDER D_DATA
32K768
330R
3876
1 8 PHASE
DT-38
GNDD
H H.OSC F8204 H 3888 I1 I876 I5
1802
COMP 4,8V 4
3889 D11 I877 I6
F803 7 INT_ A_RDY
2 HD I885 2816 I882 3883 3890 G11 I878 I5
SYNC 6 0V CONTROL F8205 5
4 SEPA 3 RESET D_RDY 3891 D6 I880 I4
V.SEPA 330R I874 RESET LOGIC 3875 3892 D6 I881 I4
SYNC 3 1u 5,1V CLOCK / F8206 6
ION 3893 D6 I882 H3
3877 I875 CALENDAR 1K F8207 3894 F1 I885 H3
2817
GND 6 SCL 7
1n
5 5,1V I 2 C-BUS ADDRESS WE 3895 F2 I886 G2

100R 3878 I876 5 SDA F8208 8 3896 E6 I887 I1
I887 INTERFACE REGISTER BE_FAN
3880
3898 G2 I888 I1
10K
100R 5,1V
GNDA GNDA F8209 9 3899 E11 I890 D1
5STBY2 FB
I881 I880 3914 C14 I891 D2
3886
100K
F8210
I888 3882
BC857BW VSS 10 3915 C13 I892 F14

GNDD GNDD
7812 4 3916 G11 I893 E2
I 47R I
F808
3881
5,1V
I822
I813
10K
I877 FMN 3917 G11 I894 E2

3923 G8 I896 F3
470K
3887
GNDD 4801 D13 I897 F4

7813 4906 G2 I898 F4
I878
2818
3888
10n
22K
BC847BW WE 6802 A3 I899 G2

0,1V 6803 B3 I903 F11
to AIO2
from FACO
6805 F6 I945 C13
from FACO
ISTBY
ION_FAN
to FACO
SW_BE_FAN
SW_CAB_FAN
FL_READY
YUV_ON
VMUTE
SATCO
SCL
5STBY2 6807 F14 I946 C14

TEMP
BE_FAN
A_YCVBS
SDA
to FACO
GNDA GNDA GNDA
to FACO
7800-A A2 I948 D10
GNDD GNDD
RC
CL16532111_002.eps 7800-B B2 I970 E7
7800-C B3 I971 D7
070901 7800-D A3 I972 C7
7803-B D8 I973 E7
7804 D2 I974 D7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Analog Board: All in One 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14
1994 I3
2900 A2
All In One 2 Pos. 3920, 3921,3922, 7902,7903, 7904 are for "ON-BOARD-PROGRAMMING" AIO2 2901 B14
FL_READY
5STBY2 2902 B13
2903 B14
SAWS
5STBY2 2904 H14
IPOR
PSS
SB1
TS
5STBY2 2905 H14
2906 H14
7900 2907 D14
TL7705 2908 F1
3918 2909 H6
A 6 8
A
3901
3900
3911
47K
10K
4K7
RESET VS 2910 I3
10K 2911 I3
2900 3902 2913 C7
5 7 2914 H12
GNDD RESETQ_ SENSE
10n 4K7 2915 H13
2 2916 H13
RESIN_ 2917 H13
2901
3 2918 I6
I942 1 REF
47u
CT I943 3900 A13
GND 3901 A12
I902 3902 A3
4 3903 B4
2902
100n
2903
220n
12STBY
12STBY 5STBY2 3904 B5
3905 B5
B B 3906 E9
not used
not used
220K
4901
3920
3904
3907 D1
3905
3903
1K
1K
1K
GNDD GNDD GNDD GNDD
3919
3908 D1
10K
F937
3909 E1
not used 3910 D1
I905
PDTA124EU 3911 A12
BSH111 7908 3912 C13
7902 3913 D13
F943
F942
3918 A6
2913
7909
10n
3919 B8
PDTC124EU 3920 B3
3921 D11
3924 I7
C C
F926
3925 H3
7901 4901 B3
GNDD PMBT2369 4902 D10
GNDD 5,1V I847 3912 4903 I8
WE 5901 H14
F902 0V 10K 5902 F1
5903 H13
5,1V 5904 I6
7803-A F3
F938
100K
3913
2907
7900 A14
10n
7901 C13
7902 C3
7903 12STBY 7903 D11
D 5STBY_uP GNDD GNDD GNDD
BSH111
F939 3921 GNDD GNDD
D 7904 I7
7905 H9
4902
not used
7906 H7
GNDD
100R
100R
5,1V
3907
3908
3910
7907 H11
1K
220K
5,1V 46 27 not used not used 7908 B7
47 7909 C7
118 115 111 105 104 12 11
VSS2
VSS1
BYTE_ C900 I14
F900 H14
EA_
RESET_
DVCC1
DVCC3
AM8|16_
ADREF
DVCC2
I938 12
100R
3909
83 5,1V F901 H2
P27|A23 RP_
I900 94 82 0,1V I935 10 11 F924 F902 C2
P62|PWM6|CS2_ P26|A22 W_ F903 E4
5,1V I934 9 28 F904 E4
81 0V
I901 93 P25|A21 G_ F905 E4
5,1V
NC
P61|PWM5|CS1_ I936 26 F906 F4
E P24|A20
80
0V
14
E_
F925
GNDD E F908 F4
F927 F903 13 16
3906
92 79 F909 F4
33K
A19 A19
P60|PWM4|CS0_ A19 A18 F910 F4
F904 17 F911 F4
I984 78 A18 A18
90 A18 A17 16 F912 F4
PA4|WR_ F905 15 48 F913 F4
77 A17 A17 GND
A17 RB_ A16 NC F914 G4
F928 5902 I904 F906 45 1 GNDD 1
103 76 A16 A16 F915 G4
RD_ A16 DQ15|A-1 A15 GNDD A16
Bead F908 2 F916 G4
43 2
58
D15 7803-A A15
75
F909
A15
41
DQ14 A14
3
A15
10
14 31
A15 F917 G4
F918 G4
2908
57 74 A14
27p
A14 A0 F919 G4
D14 A14 DQ13 A13 A14 GND A14 WE_
TMP93C071 F910 4 3 29 F920 G4

F 56
D13 A13
73 A13 39
DQ12 A12
A13 A1 9
A13
28
A13 OE_
24
F F921 H4
F922 H4
F911 36 5 8 27
55 72 A12 A12 A2
F923 H4
D12 A12 DQ11 A11 A12 WE_ A12 CE1_
GNDD F912 34 6 7 22 4 22 F924 E8
54 71 A11 A11 A3
5STBY_uP
D11 A11 DQ10 A10 A11 OE_ A11 CE2 F925 E11
GNDD F913 32 7 6 20 25 30 F926 C3
53 70 A10 A4
D10 A10 DQ9 A9 A10 CE_ A10 F927 E1
F914 30 8 5 23 F928 F1
52 69 A9 A9 A5
D9 A9 DQ8 A8 A9 A9 F929 G1
F915 44 18 4 26 F930 G1
51 68 A8 D7 A8 A6
D8 A8 DQ7 A7 A8 A8 F931 G1
F929 F916 42 19 3 27
D7 50 67 A7 D6 A7 A7 D7 F932 G1
M29F800AT
D7 A7 DQ6 A6 A7 I|O7 A7 I|O7 D7 F933 G1

F930 F917 20 5 21
G D6 49
D6 A6
66 A6 D5 40
DQ5 A5
A6 A12 2
A6 I|O6
19 D6
A6 I|O6 D6
G F934 H1
F935 H1
CY62128
F931 F918 38 21 1 18 6 20
D5 48 65 A5 D4 A5 A14 D5 F936 H1
D5 A5 DQ4 A4 A5 I|O5 A5 I|O5
CY62256
F932 F919 22 26 7 19 D5 F937 B3
D4 47 64 A4 D3 35 A4 A13 17 D4 F938 D10
D4 A4 DQ3 A3 A4 I|O4 A4 I|O4 5STBY_uP 5STBY2 5STBY
8 18 D4 F939 D11
D3
F933 46 63 F920 A3 D2 33 23 A8 25 16 D3
A3 F940 I7
D3 A3 DQ2 A2 A3 I|O3 A3 I|O3 D3
9 17 F941 H8
DGND2|ADGND
F934 F921 31 24 24 15
D2 45 62 A2 D1 A2 A9 D2
F900 F942 C13
D2 A2 DQ1 A1 A2 I|O2 A2 I|O2 D2
F935 F922 D0 29 25 23 13 10 15 F943 C12
D1 44 61 A1 A1 A11 D1
I947
A1 DQ0 VCC A0 A1 I|O1 A1 I|O1 I847 C13
PB1|XT2
PB0|XT1
D1
DGND1
DGND3
11 14 D1
D0
F936 43 60 F923 A0 A10 21 12 D0 I900 E1
D0 A0 7906 37 A0 VCC I|O0 A0 VCC I|O0 5903 5901 I901 E1
D0
X2
X1
12 13 I902 B2
H 59 13 114 113 2,2V 112 117 116
5STBY_F 7905 28
11
5STBY_uP 32 100MHZ 100MHZ H I904 F1
not used 7907 I905 B7
2914
100n
2915
100n
2916
100n
2917
100n
2904
2905
2906
100n
47u
5,1V
1u
F901 2,1V 0,2V 0,1V F941 I914 I3
I915 I3
3925
22R
I934 E4
GNDD
2909
I935 E4
I914 I915 GNDD GNDD GNDD GNDD GNDD GNDD GNDD I936 E4
100n I938 E4
1994 I942 B13
5STBY2
5STBY
I943 B14
GNDD
GNDD
2918
I947 H14
AT-49 12STBY 7904 I984 E1
GNDD 100n
4903
BSH111
100MHZ
20M00
I I
5904
3924 F940
2911
2910
33p
27p
220K
C900
not used not used
GNDD GNDD 5STBY2 5STBY 5STBY2

GNDD
CL 16532111_003.eps
070901
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Analog Board: Tuner / Demodulator

1700 A5 2700 A2 2705 A9 2710 A8 2715 D7 3701 A3 3706 A8 3711 A1 3716 B1 3721 E10 3727 E8 4702 E5 5704 C2 6701 C4 7702 C4 7707 E3 F702 C1 I704 B4 I709 A7 I714 B8 I730 E10 I735 E9 I751 E5 I758 B1 I763 A3
1701 C5 2701 A4 2706 A7 2711 C3 2716 A3 3702 A10 3707 A7 3712 C4 3717 E9 3722 E10 3728 E9 5700 A2 5705 A1 6702 E3 7703 B7 7708 E2 F703 B6 I705 B5 I710 B7 I715 A4 I731 E10 I736 D9 I752 D5 I759 A1 I764 E1
1702 D5 2702 A4 2707 A9 2712 C3 2717 A1 3703 A2 3708 A4 3713 C5 3718 E3 3723 E7 3729 E4 5701 A9 5706 A3 6703 E6 7704 E10 F303 B10 F705 A3 I706 C5 I711 B7 I717 A10 I732 E10 I737 D10 I753 E3 I760 A1
1703 E10 2703 A7 2708 A10 2713 A1 2718 E8 3704 A3 3709 A9 3714 C4 3719 E2 3724 D7 3730 E4 5702 A5 5707 E10 7700 A10 7705 E7 F700 C2 I701 A4 I707 C6 I712 B8 I718 A10 I733 E9 I739 D7 I756 B1 I761 A1
1705 A1 2704 A7 2709 A8 2714 D7 3700 A3 3705 A9 3710 D10 3715 E9 3720 B1 3726 D9 4701 D4 5703 A8 6700 B3 7701 B5 7706 E9 F701 C2 I703 A4 I708 C6 I713 A8 I719 E7 I734 D10 I741 D7 I757 B1 I762 A3
1 2 3 4 5 6 7 8 9 10
F705 3701 I701 TU
Tuner/Demod. 680R
3702 I717
5SW not used
5K6
I718
3700
GNDFV GNDFV GNDFV
5706 I762
33K
not used 0V
Bead
150K
3703
5700
2700
5SW 5SW
22u
33STBY 40,4-ADJUST SB1
7KMY 5702
2u2 low leakage

6u8
I703 2701 I715
I761 4 3
A AGC-ADJUST 7700 A
3705
5701
18K
6u8
5705
10u
GNDFV GNDFV 5SW 120p 2 AFC-ADJUST PDTC124EU
330R
I712 2709 I713 3706
2702 GNDFV
3711 I759 5703
22K
6 1
I760 6 3 AFC
100n 2703
I763
3707
220p
3704
2704
470p
4K7
8 7
100R
3708
3709
2
2717
I758 2713
2705
100n
18K
2u2
47n
1700
2716
100u
2706
2707
2708
10n
10u
OFWK3953M I709 2710 4 1
220n
GNDFV
1705
I711
UV1336K 1 7 9 I704 I705 1 4 3,3V 10p
7 8
I710
I714
AGC VCC +33V GNDFV GNDFV
GNDFV
GNDFV
GNDFV GNDFV GNDFV
2 11 F303 GNDFV
GNDFV
3
0,7V
0,9V
3,1V
2,5V
3,5V
2,7V
2,7V
TU IF 2 5 3,3V
3V
5V
1SS356
B GNDFV 4 AS 7703 B
6700
7701 22 15 4 6 7 19 18 17 21 20
3720 I756 3
10 PDTC124EU
SCL1 5 SCL F703
100R 8 TDA9817
SDA NC 14 VOLTAGE
3716 I757 GNDFV TUNER VIF
SDA1
6 GNDFV REFERENCE
GND AGC AGC
100R
12 13 14 15 7702 AFC
PDTC124EU 1701 DETECTOR
2711 OFWM3953M
F702 F700 I706 1 4 I707 3,3V 1 VCO 16
1n VIF FPLL 2V
I708 3,3V 2 TWD
3714
2 5
4K7
AMPLIFIER VIDEO DEMODULATOR
C GNDFV
GNDFV 5SW 5SW
AND AMPLIFIER
8 C
F701 3,2V 23
3 QSS MIXER
GNDFV 6701 SIF INTERCARRIER MIXER
3,2V 24 AMPLIFIER AM DEMODULATOR
3712
3713
2K2
6K8
GNDFV
not used
5704
2712
1SS356
1u
1n
FM-PLL DEMODULATOR
4701 SIF INTERCARRIER
AGC MODE SWITCH
GNDFV
1702 2,8V 5 5,2V 3 2V 12 13 9 10 11
OFWM9370M I736
D 1 4 I741 I739 not used D
I734 3710 I737
I752 TS
3726
2 5
5K6
100R
680R
3724
2714
2715
2u2
1n
3
5SW BC857BW
GNDFV GNDFV I733 I730
not used
6702 I751 7704
not used 5SW
GNDFV GNDFV
2718
1SS356
4702
47u
5707
100R
3715
3717
5SW
1K
I753
3719
4K7
15u
GNDFV 1703
GNDFV
E 3729
7705 I735
I732
EFC 4,5MHz E
3718
33STBY 5SW
I719
4K7
I764 7707 BC847C

1 3 3721
SAWS 7708 BC847BW 5K6
3727
2K7
PDTC124EU
7706 I731 270R
3722
3730
3K3
5K6
6703
100K
3723
BC857BW
2
330R
3728
AGC_MUTE
MCL4148
SIF1
VFV
PSS
GNDFV GNDFV GNDFV GNDFV GNDFV
SB1
GNDFV GNDFV 33STBY 5SW CL 16532111_004.eps

GNDFV GNDFV 070901
1 2 3 4 5 6 7 8 9 10
Analog Board: In / Out 1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 1951 A14 6512 H9 I576 C4
I/O 11953 I1 6900 D13 I580 D12
to ADC, AIO1
to ADC, AIO1
5STBY 5STBY 1954 I3 6901 E13 I581 E12
from DAC
from AIO1
from DAC
from AIO1
2500 2501
A_YCVBS
YS_OUT
ARADC
ALADC
ARDAC
C_OUT
ALDAC
1956-A I8 6902 B13 I585 D7
In / Out 1
to AIO1
from IO2
from IO2
from IO2
from IO2
to IO3
to IO3
AR1_IN
AR2_IN
AL1_IN
AL2_IN
8STBY 1956-B I9 6903 C13 I586 E7
KIR
KIL
100n 100n
GNDV GNDV 2555 1957-A I12 7500 A5 I588 D7
220R
220R
3503
3506
1957-B I13 7501 A6 I589 D7
3 8
7513-A 100n not used 1958-B C14 7502 D12 I590 C5
MC33078 GNDA 1951 1959-B D14 7503 E12 I591 C5
8STBY 8SW 5NSTBY 5STBY 12STBY 1 F340 1
HPR 2423 F8 7504 B12 I592 F5
A 7513-B A 2500 A5 7505 C12
from PS
from PS
from PS
from PS
2 5
from PS
I564 I566 8 GNDA
2
MC33078 GNDA 2501 A6 7507 C4
BC857BW 7501 4 2553
7 F341 3 2502 C8 7513-A A12
7500 BC857BW
to headphone
HPL
2503 C8 7513-B A13
100n 6 not used 4405 I458 4
8STBY VCC_HA 2505 C4 7514 B2
GNDV GNDA 4
8STBY 8SW 5NSTBY 5STBY 12STBY 4406 5 2506 C5 7515 B2
GNDV 5NSTBY 5STBY NC 2507 E9 7516 F11
6 2508 E10 7517 B3
5STBY 5STBY 5STBY GNDA GNDA
2509 B10 C570 I3
I561 3556 7
5NSTBY 5NSTBY 2510 D10 F340 A14
3500
3504
3505
3501
2K7
2K2
2K2
2K7
47K 2511 E2 F341 A14
7514 EH-B
BC857BW 3557 2512 E2 F509 D13
2513 E3 F510 E14
BC857BW I563 2542 I560 47K
B 7515
7517 GNDV GNDV REAR_OUT 2 B 2515 G4 F512 C13
100n BC847BW 2509 3511 I502 3564 F513 4 2516 E2 F513 B13
I559 2517 E2 F5301 I1
8STBY 8STBY 47u 470R 100R AL 2518 C10 F5303 I1
3512
DF3A6.8FU
5
2546
470p
25 7504 2519 G5 F5304 I1
470K
100K
3990
3558
3560
3528
I558
GNDV 2520 F7 F5306 I1

22K
3K3
4K7 I503 BC817-25W(COL) AR 2521 F8 F5307 I1
6902
6
2522 F2 F5309 I2
2505
100n
GNDV GNDA GNDA YKC21-3620 2523 F9 F5401 I3
2506
100n
I591
I573
I571
I569
1958-B 2524 G7 F5402 I3
GNDA
I576
I575
I590
I574
I572
I570
I568
WU GNDV GNDV 5NSTBY GNDA 2525 F3 F5403 I3
to AIO1 2518 3513 I504 3565 2526 F4 F5405 I4
F512 GNDA
C GNDV
C 2528 G2 F5407 I4
2541
100n
3559
3K9
GNDV 470R 100R

7507 47u 2529 G6 F5409 I4
3514
2547
470p
STV6410A 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 7505 2530 H5 F5410 I4
DF3A6.8FU
100K
2502
2503
3529
2531 G1 F5412 I5
4u7
4u7
BC817-25W(COL)
VCCV2
YCVBSOUT-AUX
GNDV2
COUT-AUX
VCCV3
FILTER
GNDV3
VOUT-RF
AOUT-RF
YCVBSOUT-VCR
LOUT-AUX
COUT-VCR
ROUT-AUX
YCVBSOUT-TV
LOUT-TV
RCOUT-TV
4K7 I505
50
50
2532 H2 F5414 I5
6903
GNDV GNDV 2533 H3 F5416 I5
GNDA GNDA
I554 17 64 I546 2534 F9 F5418 I5
FBOUT-TV ROUT-TV
I555 18 63 I545
GNDA GNDA REAR_OUT 1 2535 H7 F5420 I6
2510 3502 3562 F509 2536 G5 F5421 I6
FBIN-AUX GOUT-TV I580 4
I556 2538 G6 F5422 I6
12STBY 19 62 I588
FBIN-ENC LOUT-VCR 47u 470R 100R AL 2539 H8 F5801 I10
GNDV
I585 3507 I500 5 2540 I11 F5802 I10
2544
470p
20 61 25 7502
DF3A6.8FU
D ADD BOUT-TV D
100K
2541 C1 F5805 I9
3526
I514 BC817-25W(COL) AR
3524 21 60 I589 4K7 2542 B3 F5806 I9
SCL ROUT-VCR 6
6900
SCL
from AIO1 100R 3525 I515 2544 D13 F5901 H14
22 59
SDA SDA LOUT-CINCH YKC21-3620 2545 E13 F5902 H13
from/to AIO1 100R 23 58 8STBY 1959-B 2546 B13 F5905 I13
VCC12 ROUT-CINCH
GNDA GNDA GNDA GNDA GNDA
2547 C13 F5906 I12
2548
GNDA
I542
2512
2511
100n
24 57
2513
2548 E3 I458 A14

47p
47p
YCVBSIN-AUX GNDA 2508 3509 I581 3563

YR_IN 1u I543 I586 F510 2549 G6 I500 D12
25 56
from IO2 SLB-TV RIN-TV 47u 470R 100R 2550 H7 I501 E12
I525 3510 I501 2551 F12 I502 B12
2545
470p
26 55 25 7503
DF3A6.8FU
GNDV GNDV YIN-AUX VCCA
100K
2552 F12 I503 B12
3527
GNDV I547 4K7 BC817-25W(COL)
27 54 2553 A12 I504 C12
E SLB-VCR CIN-TV E
6901
CVBSR_IN
2507
100n
from IO2 2517 I526 I539 2554 G14 I505 C12
28 53
RCIN-AUX LIN-TV 2555 A12 I506 G13
GNDV
1u 10 29 52 I540 2557 G13 I509 I7

GNDV1 YCVBSIN-TV
GNDA GNDA GNDA GNDA
2558 H10 I510 G8
2516 I527 30 51 I548
GIN-AUX VREF
GNDA YCVBS_OUT 2559 H11 I511 H7
5STBY to IO3 2560 G12 I512 I8
1u 10 I528 31 50 I549
YCVBSIN-ENC
SLB-AUX YCVBSIN-VCR 3500 B5 I513 I7

CVBSIN-STB
2522 I529 32 49 I550 3501 B6 I514 D3

RCIN-ENC
GIN-ENC
BIN-AUX LIN-VCR
CIN-ENC
RIN-ENC
RIN-VCR
CIN-VCR
RIN-AUX
YIN-ENC
BIN-ENC
RIN-STB
LIN-ENC
5501
LIN-AUX
3502 D11 I515 D3

LIN-STB
10u
VCCV1
1u 10 3503 A5 I517 G14
2423
3504 B5 I518 G14
1u
2520
100u
100n
2521
F F
10
3505 B6 I520 G13
2551
2552
47u
22n
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 3506 A6 I521 G13
7516
2525
470K
470K
3570
3572
8STBY
1u
BA7623F 5 3507 D11 I525 E3

I530
I532
I592
I533
I534
I535
I536
I537
I557
I538
10
GNDA GNDA VCC 3509 E11 I526 E3

2526
100n
I531
I541
4u7
4u7
GNDV GNDV
2523
2534
3510 E11 I527 E3
2 IN1 OUT1 8
75E 3511 B12 I528 F3
3 IN2 OUT2 7 3512 B11 I529 F3
4u7
4u7
75E
3513 C11 I530 F4
2515
2519
2528 GNDV
4 IN3 OUT3 6 3514 C11 I531 F5
VFV 75E
from TU
1u 10 3524 D1 I532 F5
GND
I544
I520
I517
1u 10
3525 D2 I533 F5
2536
2549
2538
2529
100n
2524
1
1u
1u
1u
3526 D10 I534 F6

G G
2560
2557
2554
3527 E10 I535 F6
1m0
1m0
1m0
3528 B10 I536 F6
GNDV 3529 C10 I537 F6
I506
I521
I518
3537 H14 I538 F6
GNDV
GNDV
GNDV
3574 3575 3576
3545 H13 I539 E7
3569
3571
82K
82K
2531 100K 100K 100K
I510
3552 H12 I540 E7
I511
C_IN
from IO2 GNDV GNDV 3555 I11 I541 F5
100n
3556 B4 I542 E3
3552
3545
3537
75R
75R
75R
3557 B4 I543 E3
GNDV
GNDV
GNDV
2532 3566 3568 3567
GNDV GNDV
3558 B2 I544 G12
10u 16 2533 75R 75R 75R 3559 C2 I545 D7
2535
3560 B3 I546 D7
16 10u
H H
GNDV
GNDV
GNDV
GNDV
GNDV
GNDV
10u 16
2558
2559
10u
10u
3562 D13 I547 E7
3563 E13 I548 E7
1u 10
3564 B13 I549 F7

2530
8SW
F5902
F5901
2550
2539
3565 C13 I550 F7

16 10u
1u
3566 H8 I554 D3
6510 6512 6511 6508 6504 6509 3567 H10 I555 D3
F5905
DF3A6.8FU DF3A6.8FU DF3A6.8FU DF3A6.8FU DF3A6.8FU DF3A6.8FU 3568 H9 I556 D3
GNDV
GNDV
F5806
F5805
F5802
F5801
GNDA GNDV GNDV GNDV GNDV GNDV GNDV GNDV GNDV GNDV GNDV GNDV GNDV GNDV 3569 G11 I557 F6
F5906
GNDV
GNDV
3570 F10 I558 B2
3555
3K3
F5301
F5303
F5304
F5306
F5307
F5309
12 F5412
14 F5414
16 F5416
1 F5401
2 F5402
3 F5403
5 F5405
7 F5407
9 F5409
10 F5410
18 F5418
20 F5420
21 F5421
22 F5422
3571 G11 I559 B2
YKC21-4010 3
YKC21-4010 3
YKC21-4010 6
YKC21-4010 6
1
I509
I512
I513
3572 F11 I560 B3

I I 3574 G12 I561 B4
1957-B
1956-B
C570
11
13
15
17
19
1957-A
1956-A
1
2
3
4
5
6
7
8
9
3575 G13 I563 B2

1953
1954
PH-B
FMN
2540 3576 G14 I564 A6
GNDV
to YUV_CON
to YUV_CON
to YUV_CON
GNDA GNDV 3990 B2 I566 A6
from YUV_CON
from YUV_CON
AFCRI
GNDV
CVBSFIN
4405 A14 I568 C6

AFCLI
YF_IN
A_YCVBS
GNDA
GNDV
CF_IN
GNDV
GNDV
GNDV
GNDV
GNDV
GNDV
GNDV
GNDV
GNDV
GNDV
GNDV
U_IN
D_CVBS
V_IN
Y_IN
A_C
D_G
Y_OUT
D_B
8SW
V_OUT
U_OUT
10n
D_R
D_Y
Y_IN
to AIO1
D_C
V_IN
U_IN
from IO2
from AP
D_R
Y_IN
from AP
YS_IN
D_B
D_G
4406 A14 I569 C6

AFER
AFEL
to IO2
to IO2
to IO2
VD
U_CON
V_CON
CF_IN
YF_IN
5501 F12 I570 C6

from Front A/V Board 6504 H13 I571 C6
from / to Digital Board CL16532111_005.eps 6508 H12 I572 C6
6509 H14 I573 C6
070901 6510 H8 I574 C5
6511 H10 I575 C5
1 2 3 4 5 6 7 8 9 10 11 12 13 14

1952-A C1
1 2 3 4 5 6 7 8 9 10 1955-B A1
1958-A F1
CVBSR_IN
from AIO1
from AIO1
1959-A D1
from IO2
from AIO2
In / Out 2 I/O 2
5STBY2
to IO1
from PS
5STBY
2400 B5
to IO1
to AIO1
YR_IN
WSRI
Y_IN
IS1
IS2
5STBY2 5STBY2 5STBY 2401 B2
2402 C9
2403 C9
2405 C9
2406 E4
REAR_IN
A A 2407 E8
100K
100K
3401
3400
S-CONN 2408 E9
2409 A6
2409
100K
3402
GNDV
10n
1955-B 3400 A5
5400
TCX0310 3401 A5
10u
1B 3402 A3
3B
F5503 3403 I402 2400 I404 7400 5STBY 5STBY2 3403 B4
Y/C IN Y BA7652AF 3404 B4
4B
F5504 3404 100R 10n 3405 B2
C 100R 3406 B2
2B 1 IN1 GND 8 3407 C4
3405 6403 6402
3406
75R
75R
DF3A6.8FU DF3A6.8FU 3408 C2
B GNDV
GNDV I417
B 3409 E5
2 CTLA OUT 7 3410 E2
YS_IN
2401 to IO1 3411 E2
100n
3412 E5
3 IN2 VCC 6 3413 E9
3414 F9
GNDV LOGIC 3415 F9
2402
100n
2403
GNDV GNDV GNDV 3416 F2
47u
I416
4 CTLB IN3 5
REAR_IN 3417 F2
F5202 3407 I406 3418 D2
3419 D2
2 6405 100R
C CVBS DF3A6.8FU
GNDV GNDV C 3420 E2
3421 E2
YKC21-4157 4 2405 5400 A8
3408
75R
1997-A YF_IN 6402 B4

10n from IO1 6403 B3
GNDV 6405 C3
7400 B6
GNDV GNDV 7401 D6
REAR1_IN
F5104 F5101 E2
AL / 1
F5103 E2
MONO F5104 D2
F5105
100K
3419
3418
F5105 D2
7401
D D
V
AR 3 5STBY BA7652AF
F5202 C2
F5503 A2
5STBY F5504 B2
YKC21-3620 2 GNDA GNDA 1 IN1 GND 8 I402 B5
1959-A I404 B5
GNDA I406 C5
GNDV I409 E4
I414
100K
2 CTLA OUT 7
3420
3421
3409
10K
C_IN I410 E5
V
to IO1 I411 E8
2406 I411 I412 E8
I409 I410 3 IN2 VCC 6 5STBY
I414 E9
GNDA GNDA
REAR2_IN 1n I416 C8
E F5101
LOGIC
E I417 B10
2407
100n
AL / 4 CTLB IN3 5 I412
3412
10K
3413
MONO
10K
F5103
100K
3410
3411
V
AR 3
GNDV 2408
GNDV CF_IN
YKC21-3620 2 GNDA GNDA 1n from IO1
1958-A CTLA CTLB OUT
100K
3414
3415
GNDA
10K
L L IN1
100K
3416
3417
H L IN2
F
V
L H IN3
F
GNDV
H H MUTE
GNDA GNDA
to AIO1
WSFI
to IO1
to IO1
to IO1
to IO1
AR2_IN
AR1_IN
AL2_IN
AL1_IN
CL 16532111_006.eps
070901
1 2 3 4 5 6 7 8 9 10

1 2 3 4 5 6 7 8 9 1955-A B9
1955-C C9
from AIO2
5STBY2
1961-A F9
5STBY
from PS
from PS
5SW
5STBY
In / Out 3 I/O 3 1961-B E9
1962 F6
1992 E1
3439 F5205 REAR_OUT 1 1993 F1
5430
10u
75R 6432 5 1997-B B9
CVBS 1997-C A9
2334 B5
A 6 YKC21-4157 A 2430 D6
2431
2432
47u
22n
7430 GNDV 1997-C 2431 A4
BA7623F 5 2432 A5
5STBY2 5STBY 5SW DF3A6.8FU 2433 E8
VCC 2440 2434 E8
I436 GNDV GNDV GNDV
I430
2 IN1 OUT1 8 I439 3440 F5201 REAR_OUT 2 2435 F8
YCVBS_OUT 75E
I434 75R 6434 1 2438 C5

from IO1 3 IN2 OUT2 7 1m0 CVBS
75E F511 2440 A5
I431 I438 2444 E4
100K
4 IN3 OUT3 6
3436
YS_OUT 75E 3 YKC21-4157 2445 F2
from IO1 GND 1997-B 3431 C6
GNDV
3432 B7
I432 1 REAR_OUT
B C_OUT
GNDV
DF3A6.8FU
GNDV
1955-A
TCX0310
B 3433 C7
3436 B6
from IO1 GNDV 1A S_CONN 3439 A7
2334 3440 A7
I441 3432 F338
GNDV 3A 3441 D7
Y 3442 E7
1m0 75R F337 4A
Y/C OUT
6430 3443 F7
C 3444 D4
100K
3992
2A
3447 D2
GNDV 3448 D3
3452 E5
1955-C 3453 E3
DF3A6.8FU 3454 D4
GNDV TCX0310
C 2438 I442 3433 GNDV
5 6 7
C 3992 C6
5430 A4
100n 68R 6430 B8
6431 6431 C8
6432 A7
GNDV
5SW 5SW 6434 B7
3431
4K7
for SATCONTROL only I452
6436 D5
6437 D2
6436 6438 F2
BAV99W DF3A6.8FU 6439 E8
I451 3444
3454
10R
10R
GNDD GNDV 6440 F8
WSRO 6441 F8
6437 7430 A3
D SATCONTROL
BAV99W
for PROGRESSIVE SCAN only
from AIO1
D 7432 D4
2430
10n
F330 E2
F339 3447 I449 3448 I450 BC327-40 F6204 3441 F6101 F337 B8
I453
7432 F338 B8
2 F342 1K5 47K F339 D1
GNDV F342 D1
3 F511 B8
2433
560p
1 F5201 A8
3452
2444
100u
2K2
1992 F5205 A8
6439 F6101 D9
YKB21-5130 GNDD
F6102 E9
GNDV DF3A6.8FU
GNDV
1 U_OUT F6105 F9
F6202 F6102 F6106 F9
E GNDD GNDD 3442
E F6202 E7
2 V_OUT F6204 D7
F6206 F7
2434
560p
3 YKC21-4010 I430 A2
F330 3453 I459 I431 B2
1961-B I432 B2
2 I434 B5
1K 6440
RC IN
BZM55-C6V8
GNDV I436 A4
F6206 3443 GNDV GNDV DF3A6.8FU F6105 I438 B4
2445
6438
3
1n
I439 A6
YKC21-3478 5 Y_OUT I441 B6
1993 F6106 I442 C6
no used
F F
2435
I449 D3
10n
6 YKC21-4010
I450 D4
7
1961-A
I451 D4
1962
FMN
I452 D4
6441
from AIO1
GNDV I453 D5
GNDD GNDD GNDD GNDV GNDV DF3A6.8FU
to AIO1
SATCO
GNDV I459 E3
RC
CL 16532111_007.eps
070901
1 2 3 4 5 6 7 8 9
Analog Board: Sound Processing

1 2 3 4 5 6 7 8 9
1600 F6
Sound Processing GNDA 8SW AP 1960 D1
2600 A5
I602 2601 A6
2602 A6
GNDD GNDD
5SW
8SW
2603 A7
5SW 2604 A8
2600
2601
2602
2603
100n
10u
10n
10u
2605 B8
A A
4601
I604 3600 2606 B8
C670
I600
I601 2607 C1
I603 10K 2608 C9
2609 C2
2604
5600
10n
10u
GNDA GNDD GNDA
2610 C8
8SW 5SW 18 10 8 9 4 42 33 34 2612 D8
2616 E7
D_CTR_IO1
D_CTR_IO0
TESTEN
VREFTOP
AHVSUP
CAPL_M
ADR_CL
ADR_SEL
I624 2617 E8
3601 12 I2C_CL 2620 F6
SCL1 GNDD
I623 2621 F7
100R 3603 13 I2C_DA 2622 F5
SDA1
2605
2606
11
10u
10n
100R STBYQ 2623 F5
14 I2S_CL
MCL4148
2624 D1
B B
6600
3602
4K7
I605 2625 D1
15 I2S_WS 7600 19 2626 D1
DVSUP
16 I2S_DA_OUT MSP3445G GNDD
2627 E1
I606 3600 A8
22
17 I2S_DA_IN1 RESETQ 3601 B1
3602 B9
21 I2S_DA_IN2 3603 B1
2608
3606 D2
10u
S1...4 I2SL/R I2SL/R
DACM_R 26 3607 D2
2607 I622 FM1 D/A
GNDA
3 ANA_IN- LOUDSPEAKER R 4601 A5

FM2 LOUDSPEAKER 5600 A8
56p DEMODULATOR NICAM A DACM_L 27 5601 F5
I620 2609 I619 LOUDSPEAKER L
2 ANA_IN+ NICAM B D/A GNDD 5602 F5
C SIF1
56p C 6600 B8
7600 B6
C670 A2
F6001 D1
2610 F6002 D1
F6004 D1
10n I600 A4
43 MONO_IN IDENT IDENT DFP I601 A6
2612 I602 A6
I607 I603 A7
AGNDC 36
I604 A7
4u7 I605 B7
1960 A/D SCART-L HEADPHONE R I606 B7
2624 I607 D7
D DVAR
1 F6001
GNDA
D I609 F7
from DV - Board
GNDA
2 F6002 2u2 3606 41 SC1_IN_R HEADPHONE L I611 F6

GND A/D SCART-R
I612 F5
3
1K I613 F5
GND
2625 3607 40 SC1_IN_L SC1_OUT_R 30 I619 C2
F6004 SCART-R AFER I620 C1
4 D/A
DVAL 1K I622 C2
2u2 38 SC2_IN_R SC1_OUT_L 31 I623 B2
EH-B SCART-L AFEL
I624 B2
D/A
2617
2616
37 SC2_IN_L
1n
1n
SCART Switching Facilities
XTAL_OUT
E E
XTAL_IN
AHVSS
AVSUP
GNDA GNDA
VREF2
VREF1
DVSS
AVSS
ASG
NC
TP
25 29 35 39 44 20 23 24 28 32 1 7 5 6
1600 I609
I611
5SW HC-49/U
GNDA GNDD
5601 I613 5602 I612 18M432
F 100u 10u F
2620
2621
3p3
3p3
10u
10n
2622
2623
GNDD GNDD CL 16532111_008.eps

GNDA GNDA 070901
1 2 3 4 5 6 7 8 9
Analog Board: Power Supply

1 2 3 4 5 6 7 8 9 1324 E8
1325 C8
1326 B2
1327 B2
Power Supply PS 1932 C1
5M
1996 D4
12STBY 2321 C6
2322 D6
2323 D6
2324 B3
A A 2325 B4
7332
2328 C8
2329 E2
I345
F9349
F9344
1 3 2330 B3
IN OUT
8STBY 2331 B4
GND
2332 B8
not used
2
2330
2324
330n
2325
100n
2331
220u
47u
3321 C7
F9350
F9345
3322 E6
3323 F6
3325 D6
GNDA GNDA GNDA GNDA GNDA 3326 D7
B F9336
8SW
B 3335 F9
3336 F8
3337 D6
500mA
33STBY
1327
1326
2332
100u
3338 D3
PSC
PSC
1A
3339 D2
3340 E2
2321
100n
2SK2839
4320 D4
220K
3321
7321
GNDA
7321 C5
7322 F6
1932 I324 7323 D5
F3201 F9346 7324 D7
1
12V 17.9V / 0V 7329 F8
C 5V
2
F3202
F9343 F9338 1325 F9342 F9341
C 7330 E2
5.3V / 0V 7331 E3
3
F3203 5SW
5NSTBY 7332 A4
500mA
F3204 F9347 F3201 C1
PSC
2328
100u
4
VGNSTBY F3202 C1
2SK2839
F3205 F3203 C1
100K
2322
100n
3337
3326
7323
5
10K
33STBY
F3204 C1
6
F3206
FLYB GNDA F3205 C1
F3206 D1
1996 not used

7
F3207
GNDA I339 F3207 D1
F9330 E8
250mA
EH-B
4320
5STBY 12.3V / 0V F9332 E9
D D
220K
3325
2323
F9333 E9
47n
220K
3339
GNDA 7324 F9336 B6

PDTC124EU F9338 C8
220K
3338
F9341 C9
I341 GNDA
GNDA GNDA F9342 C8
I340 F9343 C8
7330 F9344 A2
7331
BC847BW F9345 B2
BC847BW
F9346 C2
F9330 1324 F9332 F9333 F9347 C2
5STBY
220K
3340
2329
470n
F9349 A2
1A
E PSC E F9350 B2
I324 C6
5SW not used 5STBY I325 F5
I326 F6
GNDA GNDA GNDA GNDA I337 F8
I325 3322
47R
I338 F8
3336
10K
I339 D6
I340 E2
5.2V / 0V
I341 D3
I326 3323 I337 0V / 5.3V I345 A4
7322
BC847BW 0V / 5.3V 10K I338 3335
F 7329 ISTBY F
to DAC_ADC,AIO1
to DAC_ADC,YUV,
BC847BW 4K7
to AIO1
AIO1, IO1
IPFAIL
FLYB
33STBY
VGNSTBY
5NSTBY
to TU
to AIO1
GNDA GNDA
CL 16532111_009.eps
070901
1 2 3 4 5 6 7 8 9
Analog Board: Audio Converter

1 2 3 4 5 6 7 8 9
Audio Converter DAC_ADC 1900 B1 F0002 E2
2000 A4 F0003 D2
2001 E1 F0005 D2
5NSTBY
3000
from PS
from PS
8STBY
2002 C7 F0007 D2
3V3DD
4K7 I028 3001 2003 C4 F0009 D2
GNDD GNDD GNDD GNDD
I001 6000 2004 C4 F0011 C2
100K
2000
BC857BW
not used
2005 D5 F0012 C2
22n
not used
IPFAIL
7001 I032
2025
2026
2024
3004
47p
47p
10K
47p
from AIO1 F012 MCL4148 GNDD 7000 2006 D5 F0014 C2
UDA1328T 21 20
A DAINOPT
from DIGIO
F013 I033 GNDD 10 BCK
VDDD VSSD
STATIC 9
A 2007 D8
2008 D7
F0016 C2
F0017 B1
DAINCOAX
from DIGIO 2009 D4 F010 C9
F014 I034 11 WS MUTE 23 I031 2010 E8 F011 E9
INTERFACE
DAOUT
DIGITAL
to DIGIO
I035 2011 E6 F012 A1
12 DI12 DEEM1 24
3026
22R
INTERFACE
2012 E6 F013 A1
3002
CONTROL
10K
3V3DD
GNDD
to DIGIO
2013 E1 F014 A1
5VDD
13 DI34 DEEM0 25 5NSTBY
GNDD 8STBY 2014 E8 I001 A1
1900 3025 14 DI56 L3CLK 18
3027
2015 F1 I009 B6
22R
22R
FMN GNDD 2016 F5 I010 C6
GNDD 27 TST1 L3DATA 19
GNDD GNDD 2017 F6 I011 D6
22 5000 I036 2018 F8 I012 D6
16 SYSCLK L3MODE 17
DAOUT 2019 E5 I013 D5
21
B DAINCOAX
Bead 7 TST2 22 B 2020 F2 I014 F6
3003
GNDD
10K
20 VOL/MUTE/DEEMPH 2021 F2 I015 E3
8 DS 26
DAINOPT NC INTERPOL FILTER 2022 E3 I016 E3
19 5003 5002 2023 D3 I017 F3
15 NOISE SHAPER
5VD 2024 A2 I018 F3
18 F0017 5004 10u GNDD I024 7002-A
28 VO1P VO2P 32 I009 3005 3 MC33078 2025 A3 I019 F3
3VD
2030
100u
17 F0016 I010 2026 A3 I020 F3
29 VO1N VO2N 31 4K7 1%
1 F010
D_IKILL ARDAC 2027 D3 I022 E8
16 I025 to IO1, IO3
GNDD
1 VO3 DAC'S VO4 2 3006 2 2028 D3 I023 F5

GNDD 2029 C3 I024 B8
15 F0014 3030 GNDD 4 VO5 VO6 5 4K7 1%
2030 C3 I025 C8
1%
D_PCMCLK 3V3DD
14 3000 A2 I026 D8
C C
not used
GNDD
22R
3007
2029
2002
330p
VDDA VSSA VREFA
4K7
47p
GNDD 3001 A7 I027 E8

13 F0012 6 3 30 3002 A6 I028 A4
D_DATA0 I029 I030 3008 3009 3029 3003 B4 I029 C4
12 F0011 7005
D_WCLK 1% 3004 A3 I030 C5
LF33CV 1R5 5K1
11 GNDD 3005 B7 I031 A6
GNDD
3010
2003
2004
22n
47u
GNDD GNDA GNDA 3006 C7 I032 A7
2005
100n
2006
47u
IN OUT
10 F0009 GND
1R5 2007 3007 C7 I033 A4
D_BCLK 3008 C6 I034 A4
2027
2028
100n
10u
9
GNDD
220p 3009 C8 I035 A4

GNDD
8 F0007 3016 GNDA GNDA GNDA GNDA GNDA I011 3011 I026 3010 C6 I036 B4
A_PCMCLK 3011 D6 I037 E3
7 GNDD GNDD GNDD
D D
GNDD
not used
22R 4K7 1% 3012 D6 I038 F1

2023
47p
GNDD not used 3013 F2 I039 F1

6 F0005 I012 3012 8STBY 3014 D2
A_DAT
1%
5 3015 E2
GNDD
3V3DD 3V3DD 3V3DD 4K7 1%

3016 D2
3017
GNDD
2008
330p
4K7
4 F0003 3014 GNDD 2009 I013 3017 D7
A_WCLK 3018 E6
100n
2010
not used
3 F0002 3015 22R 100n 2019

2022
3023
3019 E6
47K
47p
A_BCLK 7004 GNDA 3020 F1

2 F0001
GNDD
22R 9 100n
3018
3019
UDA1360TS 16
1R5
1R5
GNDD 3021 F1
1 I015 I037 VDDA VDDD GNDD GNDA 3022 F8
8 SYSCLK GNDA GNDA
5 8 7002-B 3023 E3
GNDD
E 14 FSEL CLOCK VREFP 5 MC33078 E 3024 E3
DECIMATION
not used
GNDD F011
Bead
5001
2001
CONTROL 7 3025 B2
1n
3024 ALDAC
FILTER
7 PWON VREFN 4 I027

GNDD to IO1, IO3 3026 A2
2011
2012
100n
6
47u
I016 47K 3027 B2
GNDA
1 VINL VREF 2 4
ADC 3028 F5
2013 2014 3029 C8
ALADC I038 3020 I022
I017 100n 3030 C2
3 VINR
from IO1
47u 12K 1% ADC GNDA GNDA GNDA 3032 F8
DC-CANCEL
2015 GNDA 5000 B3
3021 I019 FILTER 5NSTBY
ARADC I039 11 BCK 5001 E1
I018 DIGITAL DATAO 13 5002 B2
from IO1 47u 12K 1% 12 WS INTERFACE I014 3022 3032 5003 B1
not used
F F
not used
5K1 1% 5004 B1
2020
2021
2016
100n
2017
6 SFOR
3013
3028
22R
4R7
47p
47p
47u
VSSD VSSA 6000 A1

7000 A6
10 15 2018 7001 A4
I023
7002-A B8
GNDD GNDD 220p
GNDA GNDA 7002-B E8
I020 GNDD GNDD GNDA CL 16532111_010.eps 7004 E4
070901 7005 C3
F0001 E1
1 2 3 4 5 6 7 8 9
Analog Board: RGB-YUV Converter Analog Board: Digital In / Out

2200 A1 3200 A4 3210 C2 3214 E2 3220 E3 7200-B D3 I201 A2 I207 B1 I212 C2 I216 D4
2201 A1 3207 B2 3211 D2 3215 C3 3221 E1 7200-C A2 I202 A3 I208 B4 I213 D1 I224 E3 1941-A A4 2472 A3 2479 C3 3472 A2 3479 C1 4971 C2 7470-D A1 F4204 D2 I490 C2
2202 A3 3208 C1 3212 C2 3218 D2 3222 E2 7200-D A2 I203 A4 I210 B2 I214 D2 I225 D2 1941-B C4 2473 B3 2481 E2 3473 A3 3480 C2 5470 B2 7470-E D2 F4205 E4 I492 C3
2203 A3 3209 C2 3213 D2 3219 D2 7200-A B3 7201 B4 I204 A4 I211 C2 I215 C1 I226 E2 1942 E4 2474 B3 2485 C4 3474 A2 3481 D2 6470 A3 7470-F D2 F488 D3 I495 A1
1943 D4 2475 B1 2486 B1 3475 A1 3482 E3 6471 C3 F4102 A4 I485 A2 I496 D3
1945 A4 2476 C3 2912 D3 3476 B3 3483 D3 7470-A C2 F4103 A4 I486 B1 I497 A2
1 2 3 4 1948 B4
2471 A3
2477 A1
2478 D3
3470 A1
3471 A2
3477 B1
3478 C1
3484 D4
4970 C1
7470-B C2
7470-C C2
F4202 B4
F4203 B4
I487 B3
I489 C1
5STBY 5NSTBY 5STBY 1 2 3 4

RGB-YUV-Conv. YUV_CON
I201 I202 5VD1
Digital In / Out not used GNDD DIGIO
14 7200-D 5VDD 1941-A
4
3200
TSH95
2200
2201
2202
2203
YKC21-3600
22K
22n
47u
22n
47u
330R
100K
F4103
3471
3470
16 3
5NSTBY
DIGITAL
from PS
from PS
5STBY
A GNDV 15
13
A 7470-D
14 PC74HCU04D
3472
2471 F4102 1
IN
8 Vcc 9
BZX284-C6V8
5VD1
from DAC_ADC
GNDV GNDV GNDV GNDV
I203 A Y A I497 100n
A
2477
Vss 5
1u
100R
100K
3473
3474
7
2472
150p
6470
75R
GNDD
5VDD
I204 GNDD
12 7200-C YUV_ON I495
TSH95 from AIO1
GNDD GNDD GNDD GNDD Ground not connected
10 7201 3475 1945 to the rear plane
PDTC124EU F4203 3 YKC21-3479
5STBY 5NSTBY GNDV 11 9 10K I485
2486
GNDV
10n
5VDD DIGITAL
2474
100n
5470 F4202 2
3 4
DAINCOAX
OUT
not used
B B
2473
150p
to DAC_ADC 2
1
5VD1 GNDD
B not used GNDD 1 6 I487 3476
GNDD B
I207 I210 7200-A 75R
100K
3477
3207 3 6RG 1948
D_R TSH95
1K 1% YKC21-3416
from IO1 1 I208 3
2475 I486 GNDD GNDD
3208 I211 3209 I212
not used
2 8 100n
2485
100n
D_B 2
100K
560R 5K62 1%
3479
from IO1 not used
1K 1%
not used
2479 1
4971
3210
not used
GNDD GNDD
7470-B 10u
C C GNDD 7470-A
PC74HCU04D I490 PC74HCU04D 1941-B
GNDV
C DAOUT
4970 3478 1
A Y
2 3
A Y
4 I492 2476 YKC21-3600 C
BZX284-C6V8
4
from DAC_ADC 470R 100n
I215
not used
3212 3215 7470-C
6471
D_G V_CON PC74HCU04D
3480 2
from IO1 5K62 1% 1K 1% to I/O 1
I489
5
A Y
6
2K2 5VDD
3213 7470-E 5
PC74HCU04D
11 10 3483 I496
1K5 1% A Y GNDD GNDD
3484
47R
560R
7470-F
PC74HCU04D F488
2478
I213 13 12
1n
I214 7200-B
D 3211 5 D A Y
100n
2912
1K 1%
TSH95
7 I216
D 1943
GP1FA550TZ
D
2
3218 I225 3219 VCC
6 F4204 GNDD GNDD
3481 1
10R 1K5 1% DAOUT VIN OPTICAL
1K 1%
100R
from DAC_ADC 3
GND OUT
2481
3214
33p
GNDD
not used 5VDD

GNDV GNDD
I226
E 3221 3222 3220
U_CON E E DAINOPT 1942 E
750R 1% 2K2 1% I224 1K 1% to I/O 1
to DAC_ADC 1 VCC GP1FA550RZ
3482 F4205 3
OPTICAL
1K OUT
2 GND
IN
U = B/2 - 0,169R - 0,331G
V = R/2 - 0,419G - 0,081B
CL 16532111_011.eps GNDD CL 1653111_012.eps
070901 070901
1 2 3 4 1 2 3 4
Analog Board: Fan Control

1983 B5 2985 A3 3948 C3 3974 E1 3982 E3 3996 A4 7970-C E3 F806 C5 I924 E3 I932 A1 Personal Notes:
1984 C5 3940 C4 3967 A3 3975 E2 3983 E3 3997 A5 7970-D D2 F807 E1 I925 C3 I933 E3
2970 C2 3941 D4 3968 A3 3976 E2 3984 E5 4905 B4 7971 B5 F813 B5 I926 E2
2980 A2 3942 A1 3969 A4 3977 A2 3985 C1 6970 B3 7972 C5 F814 C4 I927 D1
2981 A2 3943 C1 3970 D2 3978 A5 3987 C4 6971 B4 7973 B1 I920 A2 I928 D1
2982 B3 3944 B1 3971 E1 3979 B4 3988 E1 6972 C3 7974 C1 I921 A3 I929 C3
2983 D4 3946 A1 3972 C3 3980 D3 3989 D5 7970-A E4 7975 B2 I922 A4 I930 E4
2984 D1 3947 A4 3973 E2 3981 E4 3991 D1 7970-B B3 F805 B5 I923 D2 I931 D5
1 2 3 4 5
Fan Control FACO

3967 3968 3969 3996
from PS
from PS
12STBY
12STBY
5SW
10R 10R 10R 10R
3997
10R
12STBY
22K 2980
100u
2981
100n
A for SW contr. only A
2985 I921
3977
3947
3978
10R
10K
12STBY
3946 I932 10n
GNDD GNDD
2K2 3942 11 5SW 12STBY
SW_CAB_FAN
from AIO1 22K I920 6 3979 I922
BC636
7 1K 7971
MCL4148
7973 5SW 7970-B
6971
BC847BW 5 4
LM324D
B for SW contr. only GNDD F805 F813 B

7975 6970
not used
125mA
BSH111
MP13
3944
4905
1983
12STBY 12STBY
2982
MCL4148 100u
220K
6972 I925 1984
ION_FAN 3943 1
to FAN
from AIO1 MCL4148 MOT
F814 F806
for SW contr. only

10K 7974
470R
2970
3972
3987
3940
4K7
2
10u
GNDD 1K GNDD
BC847BW
C 12STBY
3948 GNDD EH-B
C
delete for SW contr. GNDD
3985
5K6
for SW contr. only 7972

3980 I929 3941 BC847BW
I927 12 LM324D
4 I931 3989 from AIO1
7970-D 33K 22K ION_FAN
14 delete for
SW contr. 10K
2983
10n
I928
13
D from AIO1
D
3991
10K
11 SW_BE_FAN
12STBY
2984
GNDD GNDD
1n
3970 I923 12STBY 12STBY
GNDD GNDD 220K

7970-A
3988
3971
3
27K
33K
LM324D 4
LM324D I930
3982
10
18K
4 7970-C
1 3984
8 BE_FAN
I933 2 1K to AIO1
3973 I926
TEMP_SENSE
9 11
11
E F807 1K
E
3983
from AIO1
56K
not used
GNDD
3975
3974
56K
t
3981
GNDD
3976 15K
TEMP CL 16532111_026.eps
GNDA GNDD 82K I924 to AIO1
100901
1 2 3 4 5
Layout Analog Board (Overview Top View)

1324 C9 1953 C7 2000 B5 2030 A3 2475 A2 2523 A5 2558 A7 2810 B4 3006 A5 3403 A8 3500 B7 3819 C6 3862 B4 3888 B4 3924 A1 3981 A1 4971 A2 6805 A3 7507 B6 7901 B1
1325 C8 1954 B4 2003 A4 2201 A5 2476 A3 2525 C6 2559 A7 2811 A3 3008 A4 3404 A8 3501 B7 3821 B3 3865 B2 3890 B2 3940 A2 3982 A1 5000 A4 6807 B2 7513 B4 7902 A2
1326 C9 1955 A8 2004 A4 2203 B5 2477 A3 2528 B6 2560 A8 2812 B4 3009 A5 3409 A8 3503 B7 3822 A3 3867 A2 3891 A3 3941 A2 3983 A1 5002 A3 6970 A1 7514 B7 7903 A1
1327 C6 1956 A8 2006 A4 2328 C8 2478 A2 2529 B6 2600 B7 2813 A3 3010 A4 3412 A8 3504 B7 3829 A3 3868 A2 3892 A3 3942 A1 3984 A2 5003 B2 6971 A1 7515 B7 7904 A1
1600 C7 1957 A7 2007 A5 2330 A4 2479 A3 2530 B6 2602 B7 2816 B3 3011 A5 3413 A8 3505 B7 3830 A3 3869 A2 3896 B3 3943 A1 3985 A2 5400 A8 6972 A1 7516 A7 7906 A1
1700 C9 1958 A5 2010 A5 2331 A5 2486 A3 2532 C6 2605 B8 2817 B3 3012 A5 3414 A8 3506 B7 3832 A4 3870 A2 3898 B4 3944 A1 3987 A2 5430 A8 7000 A5 7517 B7 7970 A1
1701 B9 1959 A6 2011 A5 2332 C8 2500 B7 2533 C6 2608 B8 2818 A3 3018 A5 3415 A8 3525 B6 3837 A3 3872 A3 3901 B1 3946 A1 3988 A2 5470 A3 7001 A4 7600 B7 7971 A1
1702 B9 1960 C7 2012 A5 2334 A8 2501 B7 2534 A5 2612 B7 2820 A3 3021 A5 3431 A9 3556 B7 3839 B3 3874 A3 3903 B2 3947 A1 3989 A2 5501 A7 7002 A5 7705 C9 7972 A2
1703 B8 1961 A7 2013 A5 2400 A8 2502 A6 2535 B7 2622 C8 2831 A4 3022 A5 3432 A8 3557 B7 3840 B2 3875 B3 3904 B2 3948 A2 3990 B7 5600 B8 7004 A4 7800 A4 7973 A1
1705 A9 1962 A7 2015 A4 2403 A8 2503 A5 2536 B6 2624 C7 2901 B1 3028 A4 3433 A9 3558 B7 3841 B2 3876 B4 3905 B2 3967 A2 3991 A2 5601 C8 7005 A4 7803 B2 7974 A1
1802 A3 1980 B3 2017 A5 2405 A8 2508 A6 2538 B6 2625 C7 2905 B5 3029 A5 3441 A7 3559 B7 3844 B2 3877 A3 3906 A1 3968 A2 3992 A8 5602 C7 7200 B5 7804 A5 7975 A1
1900 B1 1981 C5 2018 A5 2406 A8 2509 A5 2539 B7 2700 A9 2918 A1 3032 A5 3470 A3 3560 B7 3847 B2 3878 A3 3908 B2 3969 A2 3996 A2 5701 B9 7321 C8 7805 B3
1910 C3 1982 B3 2020 B1 2407 A8 2510 A6 2541 B7 2703 C9 2970 A1 3110 C4 3471 A3 3600 C8 3848 B3 3879 A3 3910 B2 3970 A2 3997 A2 5702 C9 7323 C8 7806 A5
1911 C3 1983 A1 2021 B1 2408 A8 2512 B6 2542 B7 2708 A8 2980 A4 3207 B5 3472 A3 3601 C8 3850 A5 3880 A2 3911 B1 3971 A2 4405 B4 5703 B9 7332 A4 7807 B4
1932 C9 1984 B1 2022 B1 2423 B6 2515 A6 2549 B6 2714 B8 2982 A1 3208 B5 3474 A3 3603 C8 3852 A5 3881 A3 3912 B1 3972 A2 4406 B4 5704 B9 7400 A8 7809 B4
1941 A2 1987 C6 2023 B1 2430 A9 2517 B6 2550 B6 2716 B9 2983 A2 3210 B5 3475 A3 3707 A9 3854 A3 3882 B4 3916 B2 3973 A2 4801 C5 5705 C9 7401 A8 7810 B4
1942 A3 1992 A2 2024 B1 2431 A9 2518 A6 2551 A7 2717 B9 2984 A2 3211 B5 3477 A2 3802 B3 3855 A5 3883 B3 3917 B2 3975 A2 4901 A1 5706 B9 7430 A9 7811 A3
1943 A4 1993 A1 2025 B1 2438 A9 2519 A6 2553 B4 2718 B8 2985 A1 3214 B5 3478 A2 3804 B3 3857 B4 3884 A3 3918 B1 3976 A2 4902 A1 5707 A8 7432 A2 7812 B3
1945 A3 1994 B2 2026 B1 2440 A9 2520 B7 2554 A7 2800 A4 3000 A5 3400 B3 3479 A2 3807 A4 3859 A5 3885 A2 3920 A2 3977 A1 4903 A1 5902 B2 7470 A2 7813 A3
1948 A3 1996 C9 2028 A4 2444 A2 2521 B6 2555 B4 2804 B3 3001 A5 3401 B3 3480 A2 3815 A4 3860 B3 3886 B3 3921 A1 3979 A1 4906 B4 6000 A5 7500 B7 7815 B2
1951 B4 1997 A9 2029 B1 2471 A3 2522 B6 2557 A8 2806 A4 3005 A5 3402 A8 3483 A2 3818 B3 3861 B4 3887 B4 3923 A2 3980 A2 4970 A2 6471 A3 7501 B7 7900 B1
Part 1 Part 2
CL 16532111_13a.eps CL 16532111_13b.eps
CL 16532111_013.eps
100901
Layout Analog Board (Part 1 Top View)
CL 16532111_13a.eps
100901
Layout Analog Board (Part 2 Top View)
CL 16532111_13b.eps
100901
Layout Analog Board (Overview Bottom View)

2001 A6 2321 C2 2472 A8 2607 B2 2715 B1 2907 B9 3016 B9 3109 C6 3329 A4 3416 A5 3481 A6 3564 A5 3709 B2 3729 B1 3836 B7 3907 B8 5700 A1 6439 A3 6902 A5 7706 B2
2002 A3 2322 C2 2473 A7 2609 C3 2802 B6 2908 B8 3017 A5 3111 C6 3335 C2 3417 A5 3482 A7 3568 A2 3710 C2 3730 B1 3838 A7 3909 B8 5901 B5 6440 A3 6903 A5 7707 B1
2005 A6 2323 C2 2474 A7 2610 B3 2805 B7 2909 A9 3019 A6 3112 C6 3336 C1 3418 A4 3484 A7 3569 A3 3711 A1 3800 B6 3842 A7 3913 B9 5903 B8 6441 A3 7100 C7 7708 B1
2008 A3 2324 A6 2481 A6 2616 B3 2807 A7 2910 B8 3020 A5 3113 C6 3337 A3 3419 A4 3502 A4 3570 A3 3712 B1 3805 B7 3843 A7 3914 B8 5904 A9 6470 A8 7101 C7 7816 A6
2009 A6 2324 B4 2485 A7 2617 B3 2808 B8 2911 B8 3023 A6 3200 B5 3337 C2 3420 A4 3507 A4 3571 A3 3713 B1 3809 A6 3843 A7 3915 B8 6100 C7 6504 A3 7201 B5 7817 A7
2014 A3 2325 A6 2505 B4 2620 B3 2809 B8 2912 A7 3024 A6 3209 B5 3338 C1 3421 A4 3509 A4 3572 A3 3714 C1 3810 A6 3846 B8 3919 B9 6101 C7 6508 A3 7322 C2 7905 B8
2016 A3 2326 B4 2506 A4 2621 B3 2814 A7 2913 B9 3025 B9 3212 B5 3339 C1 3436 A1 3510 A4 3575 A3 3715 B2 3811 A6 3849 A7 3925 B8 6102 C6 6509 A3 7324 C2 7907 B8
2019 A6 2329 C1 2507 B4 2623 C3 2815 A7 2914 B8 3026 B9 3213 B5 3340 C1 3439 A1 3511 A5 3576 A3 3716 A1 3813 B6 3851 A7 3974 A5 6103 C6 6510 A2 7329 C2 7908 B9
2027 A7 2340 A3 2511 B5 2701 C1 2819 A6 2915 B8 3027 B9 3215 B5 3343 A3 3440 A1 3512 A5 3602 B2 3717 B2 3816 B7 3853 A5 3978 A9 6104 C6 6511 A3 7330 C1 7909 B9
2100 C7 2347 A4 2513 B4 2702 C1 2821 A7 2916 B7 3030 B9 3218 B5 3365 A4 3442 A3 3513 A4 3606 B3 3718 B1 3820 B7 3858 A4 4101 C7 6402 A2 6512 A2 7331 C1
2101 C7 2348 B4 2531 B4 2704 A1 2822 B7 2917 B8 3100 C7 3219 B5 3366 A2 3443 A3 3514 A4 3607 B3 3719 B1 3823 B7 3871 B7 4102 C7 6403 A2 6600 B2 7502 A4
2102 C7 2401 A1 2544 A4 2705 B2 2823 A7 2981 A8 3101 C7 3220 B5 3367 A2 3444 A8 3524 B4 3700 BI 3720 A1 3823 B7 3873 A7 4320 C1 6405 A1 6700 C1 7503 A4
2103 C7 2402 A2 2545 A4 2706 B2 2827 C1 3002 A6 3102 C7 3221 B5 3374 A3 3447 A8 3526 A4 3701 A1 3721 B2 3824 B7 3889 B8 4601 B3 6430 A2 6701 C1 7504 A5
2103 C7 2409 A2 2546 A3 2707 B1 2832 A6 3003 A6 3103 C7 3222 B5 3405 A2 3448 A8 3527 A3 3702 B1 3722 B2 3826 B7 3893 A7 4701 C1 6431 A2 6702 B1 7505 A4
2104 C7 2432 A1 2552 A3 2709 B2 2900 B8 3004 A6 3104 C7 3321 C1 3406 A1 3452 A9 3528 A3 3703 A1 3723 C2 3828 B7 3894 C1 4702 B1 6432 A1 6703 C1 7700 B1
2106 C6 2433 A3 2601 C3 2710 B1 2902 B9 3007 A5 3105 C7 3322 C1 3407 A1 3453 A9 3552 A3 3704 C1 3724 B1 3831 B7 3895 C1 4905 A9 6434 A1 6802 A6 7701 B1
2200 A3 2434 A3 2603 B3 2711 C1 2903 B9 3013 B9 3106 C7 3323 C1 3408 A1 3454 A8 3555 A3 3705 B2 3726 B2 3833 B8 3899 B8 4999 A9 6436 A9 6803 A7 7702 C1
2202 B5 2435 A3 2604 B2 2712 B1 2904 A9 3014 B9 3107 C7 3325 C2 3410 A5 3473 A8 3562 A4 3706 B2 3727 B2 3833 B7 3900 B8 5001 A6 6437 A8 6900 A4 7703 B1
2316 B4 2445 A9 2606 B2 2713 A1 2906 B5 3015 B9 3108 C7 3326 C2 3411 A5 3476 A7 3563 A4 3708 C1 3728 B2 3834 B8 3902 B8 5004 B9 6438 A9 6901 A4 7704 B2
PART 1 PART 2
CL 16532111_14a.eps CL 16532111_14b.eps
CL 16532111_014.eps
100901
Layout Analog Board (Part 1 Bottom View)
CL 16532111_14a.eps
070901
Layout Analog Board (Part 2 Bottom View)
CL 16532111_14b.eps
070901
Layout Analog Board (Testlands Top View)
CL 16532111_015.eps
100901
Layout Analog Board (Testlands Bottom View)
RSVHSCIn AROut_1 ALOut_1 ALOut_2

RCVBSIn AROut_2
V_IN GNDV DIG OUT H
RSVHSYIn FAN_IN
RCVBSOut1 Y_IN
AGC RSVHSCOut RSVHSYOut ARIn_1 ALIn_1 OPT OUT RC IN
RCVBSOut2 Y_OUT
U_IN DIG OUT L
GNDFV
ARIn_2 FAN_OUT
ALIn_2
ALDAC DAINCOAX
ARDAC INT Clock SYNC
IF
5SW
8SW 5STBY2
SDA1 GNDD
SCL1
D_PCMCLK
A_WCKL
DAOUT
GNDFV
IF-In
ADATA D_RDY
GNDV SCL D_BCLK
IReset A_PCMCLK
A_V FB D_DATAO D_WCLK
A_U BE_FAN
ION A_DAT
IRESET_DIG D_DATA 3VD
A_Y A_RDY
A_C GNDD
GNDA D_KILL A_BCLK
12STBY A_YCVBS
D_CVBS DAINOPT
D_Y
D_C
D_R
D_G
DVAR D_B
FLYB GNDV AFCRI
AFCLI SDA
33STBY CVBSFIN 5M INT
GNDA
VGNSTBY DVAL 8SW 5STB
5NSTBY CFIN RC IPOR1
5V SCL CL 16532111_016.eps
YFIN
12V VGNSTBY 070901
DVIO Front Board Layout DVIO Front Board

0002 C3 1000 B1 1002 A1 2001 A1 2003 D2 5000 B2 6000 A2
0003 D3 1001 B2 2000 A2 2002 D2 3000 D2 5001 C2 6001 C2
1 2 3 0002 C1
DVIO FRONT BOARD 0003 A2
1000 C1
5V
1001 B2
1002 C2
TLMH3100
1002
2000 B1
6000
2000
2005
PH-S
4n7
A A
1n
1
2001 B1
2
2002 B2
2003 A1
2001
2004
4n7
1n
2004 C1
2005 C2
GND GND1394 GND GND1394 3000 B2
5000 B2
B B 5001 B2
1000
54030 1001 6000 B1
1 1318141 5 6 7 8
5000 6001 A1
2 DLW31S GND1394
4
3
3
4 5001
2
1
6 5
C DLW31S
C
GND1394 6001
310412124452
0002
SM6T
4n7 CL 16532095_033.eps
080801
2003
4n7
GND1394
2002 EARTH SPRING
D 1M
0003 D
3000
GND1394 GND
GND
CL 16532095_032.eps
080801
1 2 3
DVIO Board: 1394 Interface

1 2 3 4 5 6 7 8 9 10 11 12 13 14
1101 B1 3180 B7 F184 D12
1102 D1 3188 D7 F185 D2
2104 D3 3189 B7 F186 D12
1394 INTERFACE +3V3_IEEE_A +3V3_IEEE_D +3V3_IEEE_PLL
+3V3_IEEE_D +3V3_IEEE_D
+3V3_LINK
{LINK_AVCLK,LINK_AVSYNC,LINK_AVVALID,LINK_AVFSYNC,LINK_CSn,LINK_INTn,LINK_AVREADY}
LINKFIFO_DQ(7:0) 2105
2146
D3
I5
3190
3191
D7
C7
F187
F188
D12
D12
2147 I5 3192 C13 F189 D12
2148 I6 3193 B7 F190 D12
3140
10K
OPTION 7101 2149 I6 3197 C13 F191 D12
3179
3138
10K
10K
A 3147
52 51 42 31 30 27 62 61 26 25 56 PDI1394 LINK A 2150 I6 3198 C13 F192 E3
TESTM
AVDD DVDD PLLVDD 3137 F195 2151 I6 3199 C13 F193 E3
10K CPS 24 +3V3_IEEE_D 1R 2152 I6 4100 H12 F194 B6
+3V3_LINK
+3V3_LINK
3148 F148 F601 OPTION
3141
40 R0 LPS 15 2153 I7 4101 D7 F195 A8
3139
9K1
10K
OPTION
OPTION
RECEIVED 7103
6K34 F150 41 R1 BIAS DATA ISO_ 23 2154 I7 4102 H12 F197 B13
+3V3_IEEE_D PDI1394
138
132
120
113
107
OPTION
3180
95
90
84
78
70
61
54
44
35
24
18
12
2155 I7 4103 B13 F198 G12
10K
VOLTAGE
6
38 TPBIAS0 DECODER/ C|LKON 19 F194
AND TIMER VDD 2156 I7 5103 I5 F199 B1
3102 10K
F199 2158 F122 CURRENT F110
AV1D0 108 F124 LINKFIFO_DQ(0)
SYSCLK 2 AV1D1 109 F125 LINKFIFO_DQ(1) 2157 I8 5106 G2 F601 A6
OPTION
GENERATOR AV1D2 110 F127 LINKFIFO_DQ(2)
F111 3193 F602 2158 B2 5109 G2 F602 B9
TRANSMITTER/RECEIVER
1u LREQ 1
B F126 57 CYCLEOUT AV1D3 111 F128 LINKFIFO_DQ(3)
B
3164
3165
56R
56R
F112 3189 1R F105
91 LPS AV1D4 114 F129 LINKFIFO_DQ(4) 2163 C2 5110 H2
8 7 6 5 37 TPA0+ LINK CTL0 4 56 CYCLEIN AV1D5 115 F130 LINKFIFO_DQ(5)
ISOCHRONOUS
1101 F197 2170 D1 7101 A5
82 PHYD0 AV1D6 116 F131 LINK_AVREADY
3171 10R
INTERFACE LINKFIFO_DQ(6)
AV1 LAYER
4 F118 36 TPA0- CTL1 5 F113 F100 81 PHYD1 AV1D7 117 F132 LINKFIFO_DQ(7)
2171 D1 7103 B12
DV INPUT PCB
4103
3172 10R
FROM FRONT
80 PHYD2 AV1READY 118

3 F119 D0 6 F114 F101 79 PHYD3 AV1CLK 99 F133 LINK_AVCLK 2173 G3 F100 B8
12KB BUFFER F134 LINK_AVSYNC
3174 10R
76 PHYD4 AV1SYNC 103
2
F120 35 TPB0+ D1 7 F115 F102 75 PHYD5 MEMORY AV1VALID 102 F135 LINK_AVVALID 2174 G4 F101 B8
74 PHYD6 AV1FSYNC 100 F136 LINK_AVFSYNC 2175 H3 F102 C8
1 F121 34 TPB0- D2 8 F116 3176 10R F103
ARBITR’N 73 PHYD7 AV1ENDPCK 98 3103
LINK AV1ERR0 96 F143 10K 2176 H3 F103 C8
AND D3 9 F142 3105 10R F153 CORE
86 PHYCTL0 AV1ERR1 97 F144 2177 H3 F104 D8
CONTROL
3173
3178
56R
56R
3107 10R 3106

85 PHYCTL1 AV1SY 101
D4 10 F149 F154 2178 H4 F105 B8
C STATE
MACHINE F152 3108 10R F156
87 LREQ
10K
C 2181 I2 F106 D8
59 XI D5 11 92 LINKON AV2D0 133 F163 3192
LOGIC
XTAL OSC. F157 3117 10R F158 +3V3_LINK
93 ISON AV2D1 134 F165 3197 47K 2182 I3 F107 C8
TRANSMITTER/RECEIVER
F123 60 XO D6 12 48 PD AV2D2 135 F166 3198 47K
PLL 2183 I3 F108 D7
2163
270p
3177
5K1
AV2D3 136
3191 10R F167 3199 47K
88 SCLK
16 CLOCK D7 13 F109 F107 55 CLK50 AV2D4 139 F168 3100 47K 2184 I3 F109 C6
ISOCHRONOUS
10R 47 1394MODE AV2D5 140 F169 3101 47K
AV1 LAYER
43 PC0 20 3188 F104 AV2D6 141 2187 I4 F110 B6
F170 3104 47K
AV2D7 142 F171 3109 47K
F162 44 TRANSMIT PC1 21 3190 47R F106 AV2READY 143
2192 I8 F111 B6
F172 3110 47K
DATA AV2CLK 124 F161 3118 47K 2193 I8 F112 B6
1102 F146 3116 F185 47R
45 ENCODER PC2 22 AV2SYNC 128 F184 3119 47K
NC AV2VALID 127 F186 3120 47K
2194 I8 F113 B6
1R 46 CNA 3 4101
D CX-11F F108 PHY_CNA
AV2FSYNC 125 F187 3121 47K
D 2195 I8 F114 B6
24M576 AV2ENDPCK 123 F188 3122 47K
F175 2196 I9 F115 C6
2170
2171
47 AV2ERR0|LTLEND 121
12p
12p
F190 3133 47K
3166
RESET_ 53
2K2
AV2ERR1|DATAINV 122 F191 3134 22K 2197 I9 F116 C6
OPTION
2104 54 AV2SY 126 F189 3123 22K
100n PD 14 47K 3100 C13 F117 E7
2105 55
HIFA0 33 PA(0)
3101 D13 F118 B2
100n
TEST1
TEST0
OPTION
HIFA1 32 PA(1) 3102 B13 F119 B2
HIFA2 31 PA(2)
AGND DGND PLLGND HIFA3 30 PA(3) 3103 C12 F120 C2
28 29 50 49 48 39 33 32 64 63 18 17 58 57 HIFA4 29 PA(4) 3104 D13 F121 C2
+3V3 HIFA5 28 PA(5)
HIFA6 27 PA(6) 3105 C7 F122 B2
PA(7)
E 3136 F193 62
HIFA7 26
HIFA8 25 PA(8) E 3106 C12 F123 C2
3107 C7 F124 B12
F137
63 TESTPIN1
3111
2K2
OPTION
1R
64 TESTPIN2 HIFD8 10 3124
F192 PHY TESTPIN3 HIFD9 9
+3V3_LINK 3108 C7 F125 B12
F117 3125 47K
HIFD10 8 3126 47K 3109 D13 F126 B9
49 HIFD11 7 3127 47K 3110 D13 F127 B12
INTERFACE
50 RESERVED1 HIFD12 4 3128 47K
51 RESERVED2 HIFD13 3 3130 47K 3111 E8 F128 B12
8-BIT
52 RESERVED3 HIFD14 2 3131 47K
58 RESERVED4 HIFD15 1 3132 47K 3113 G9 F129 B12
59 RESERVED5 47K 3115 G14 F130 B12
65 RESERVED6 HIFAD0 22 PAD(0)
66 RESERVED7 HIFAD1 21 PAD(1) 3116 D2 F131 B12
67 RESERVED8 PAD(2)
F 68 RESERVED9
HIFAD2 20
HIFAD3 19 PAD(3) F 3117 C7 F132 B12
71 RESERVED10 HIFAD4 16 PAD(4) 3118 D13 F133 B12
72 RESERVED11 HIFAD5 15 PAD(5)
104 RESERVED12 HIFAD6 14 PAD(6) 3119 D13 F134 C12
105 RESERVED13 HIFAD7 13 PAD(7) 3120 D13 F135 C12
129 RESERVED14
130 RESERVED15 HIF16BIT 45 3121 D13 F136 C12
144 RESERVED16 ASYNC HIFWRN 37 PWRn 3122 D13 F137 E4
5106 F138 RESERVED17 HIFALE 39 PALE
+3V3_IEEE_PLL TRANSMITTER HIFRDN 40 PRDn 3123 D13 F138 G4
100MHZ AND HIFMUX 46
LINK_CSn 3124 E12 F139 G4
2173
2174
100n
RECEIVER HIFCSN 36
10u
CONTROL 3125 E12 F140 H4

G 1394_RSTn 42 RESET_ AND
STATUS
HIFWAIT 41
HIFINTN 38 F174 LINK_INTn G 3126 E12 F141 I9
REGISTERS 3127 E12 F142 C6
F198
3113
10K
3128 F12 F143 C12
GND 3115
5109 F139 +3V3_LINK 3130 F12 F144 C12
89
83
77
69
60
53
43
34
23
17
11
137
131
119
112
106
94
+3V3_IEEE_A
5
1K 3131 F12 F146 D1
100MHZ 4100
+3V3_LINK 3132 F12 F148 A3
2175
2176
100n
2177
100n
2178
100n
10u
3133 D13 F149 C6

4102
3134 D13 F150 B3
OPTION
3136 E3 F152 C6
H H 3137 A8 F153 C8
3138 A7 F154 C8
5110 F140 3139 A7 F156 C8
+3V3 +3V3_IEEE_D
100MHZ 3140 A8 F157 C6
3141 A8 F158 C8
2181
100u
2182
2183
100n
2184
100n
2187
100n
10u
3147 A3 F161 D12

3148 A3 F162 D1
3164 B2 F163 C12
PA(0:15)
3165 B2 F165 C12
I 5103 F141
I 3166 D8 F166 C12
+3V3 PAD(7:0) 3171 B7 F167 C12
+3V3_LINK
100MHZ
3172 B7 F168 C12
2146
100n
2147
100n
2148
100n
2149
100n
2150
100n
2151
100n
2152
100n
2153
100n
2154
100n
2155
100n
2156
100n
2157
100n
2192
100n
2193
100n
2194
100n
2195
100n
2196
100n
2197
100n
{SRAMCE0n,SRAMRDn,PINT0n,PINT1n,PALE,PWRn,PRDn,PRSTn} 3173 C2 F169 D12

3174 C7 F170 D12
3176 C7 F171 D12
CL 16532145_014.eps 3177 C2 F172 D12
221101 3178 C2 F174 G12
3179 A7 F175 D8
1 2 3 4 5 6 7 8 9 10 11 12 13 14
DVIO Board: Microprocessor

1 2 3 4 5 6 7 8 9 10 11 12 13 14
1200 B4
MICROPROCESSOR 1201
2200
G10
B4
PAD(0:7) PAD(0:7) 2202 G2
2203 G2
2204 G3
2205 B4
A SRAM A 2206 C3
2207 G10
+5V_PROC 3201 B5
Micro processor
7201 3202 B2
+5V_PROC CY62256 28 3203 B3
2200 PA(0) 21 11 PAD(0)
A0 VCC I|O0
7203 3204 C1
DSX840GA
12p P89C51 44 PA(1) 23 12 PAD(1)
3205 B2
11M05
A1 I|O1
1200
+5V_PROC VCC
F200 21 43 PAD(0) PA(2) 24 13 PAD(2) 3206 C2
XTAL1 AD0 A2 I|O2
2205 F201 3201 F232 20 3214 C8
B XTAL2 AD1
42 PAD(1) PA(3) 25
A3 I|O3
15 PAD(3)
B
3202
3215 C8
10K
12p 47R 41 PAD(2) PA(4) 26 16 PAD(4)
AD2 A4 I|O4 3216 D8
F202 3203 F214 10 40 PAD(3) PA(5) 1 17 PAD(5) 3217 D8
PORT0
RST AD3 A5 I|O5
PRSTn 3205 F223 7202 1K 35 39 PAD(4) PA(6) 2 18 PAD(6) 3223 G8
+5V_PROC EA_VPP AD4 A6 I|O6
2206
100p
47K BC847B 3224 G9
32 38 PAD(5) PA(7) 3 19 PAD(7)
PSEN_ AD5 A7 I|O7
3204
3206
3225 C4
10K
47K
PALE F204 3225 F209 33 37 PAD(6) PA(8) 4

ALE AD6 A8 3226 E2
10R 36 PAD(7) PA(9) 5
AD7 A9 4206 D4
5200 F2
C RXD
11
RXD T2
2 PA(10) 6
A10 CE_
20 SRAMCE0n
C 6200 H9
+5V_PROC 13 3 PA(11) 7 22 SRAMRDn
TXD TXD T2EX PORT1_1 A11 OE_
PINT0n F211
OPTION 7201 A10
14 4 F205 3214 PA(12) 8 27 PWRn
7208 INT0_ ECI
1K
A12 WE_ 7202 B2
74HCT1G04 5 7204 PINT1n 15 5 F206 3215 PA(13) 9 7203 B5
PORT3
PORT1
BST82 INT1_ CEX0 A13
F203 1K Board ID 7204 C3
F213 16 6 F207 3216 PA(14) 10
2 4 T0 CEX1 A14 GND
ISPn 4206 F230 17 7 F208
1K 7207 G9
RTSn 3217 14
T1 CEX2
1K 7208 C2
NC PWRn Option 18 8
WR_ CEX3 7209 E2
3 1
D PRDn 19 9
D F200 B4
RD_ CEX4 CTSn
24 PA(8) F201 B4
A8 F202 B3
+5V_PROC 25 PA(9)
A9 F203 D3
26 PA(10)
A10 F204 C4
PA(11) F205 C6
3226
F220
1 27
10K
A11
PORT2
12 28 PA(12) F206 C6
A12 F207 D6
NC
23 29 PA(13)
7209 A13 F208 D6
PA(14)
E PDTC144EU 34
A14
30
E F209 C5
31 PA(15) F210 G9
VSS A15
F211 C5
OPTION
22 F212 F3
F213 D3
F214 B4
F216 G9
F219 F8
{SRAMCE0n,SRAMRDn,PINT0n,PINT1n,PALE,PWRn,PRDn,PRSTn} F220 E2
F PA(0:15) PA(0:15) F F221 G9
F222 G9
+5V F223 B2
F219
F230 D5
5200 F212 F232 B5
+5V +5V_PROC
330R
3224
100MHZ
2202
100n
2203
100n
2204
100n
F221
G 2207 G
3223 F222
7207
100n
4K7 BC847B
1201
F216 PH-S
1
TLMH3100
F210 2 To front DV input PCB
6200
Option
H H
I I
CL 16532145_015.eps
221101
1 2 3 4 5 6 7 8 9 10 11 12 13 14
DVIO Board: Fifo & Control

1 2 3 4 5 6 7 8 9 10 11 12 13 14
2301 I3 F330 D7
{TDI,TCK,TDO,TDO_CONF,TMS}
2302 I4 F331 C8
FIFO & CONTROL 2303 F4 F332 C8
TDO_CONF
4302 2304 C8 F333 E12
2305 F3 F335 B10
+3V3_FPGA_CONF
+3V3_FPGA_CONF
+3V3_FPGA_CONF
HAD(7:0) 2306 I9 F336 B8
2307 I9
HAD(7)
HAD(6)
HAD(5)
HAD(4)
HAD(3)
HAD(2)
HAD(1)
HAD(0)
A A 2308 I9
5303 F312 2309 I9
+3V3 +3V3_FPGA_CONF {DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn}
100MHZ 2310 I9
DV_HS_IN
2311 I10
DV_LCn
DV_ERRn
DV_DRQn
DV_DTACKn
DV_RSTn
DV_RWn
DV_DSUn
DV_DSLn
+3V3_FPGA_CONF 2330 2312 I10
DV_HS_OUT
DV_ASn
7309 100n 2313 I10
XC18V01 2331
F324 1 20
2314 I8
1 20 100n 2318 D3
1K
1K
2 19 2332
2 19 2319 D3
4300
3306
3305
PROGRAMn
F336 CCLK
DATA
100n
3
3 18
18
3301 2324 I12
B TDI
F316 4 17 F326 +3V3_FPGA
B 2325 I12
CLOCKGENVID
4 17 1K
F319 2330 A4
TMS 5 16
5 16 2331 B4
F335
F322 6 15
AUD_SDO_CON
2332 B4
AUD_MUTE
AUD_SDI
AUD_WS_701
TCK 6 15
7 14 3300 G9
7 14
5300 F314 2304 3301 B11
47R
3307
8 13
1K
8 13 CONFIG FLASH +3V3_PLL 3303 E12
F331
9 12 100MHZ 100n
F306 3322
F301
9 12 7307 3305 B1
DOUT
10 11 CY2071AS 7 3306 B1
47R
10 11
C VDD
C
3330
CLOCKGENAUD XTI OSC PLL 3307 C1
F332 3327
OPTION BLOCK
+3V3_FPGA
+3V3_FPGA
+3V3_FPGA
3 3312 F5
PROGRAMn
4 XTO EPROM CLKA 1 F315

3313 H9
CLK27M
CONFIGURABLE
MULTIPLEXER
RESETn
AND DIVIDE
CLKB 5
DONE
3314 H9
47R
DATA
CCLK
INITn
LOGIC
8 OE|FS
F302
CLKC 6 3315 D7
{DATA,CCLK,DONE,INITn,PROGRAMn}
GND 3317 G3
3318 G3
DONE
DATA
7303
CCLK
2
INITn
108
107
106
105
104
103
102
101
100
+3V3_FPGA_CONF PLL AUDIO
99
98
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
97
96
XCS30XL
2319
3319 G3
VCC6
CCLK
I|O84-GCK6-DOUT
I|O83-D0-DIN
I|O82
I|O81
I|O80
I|O79-D1
GND12
I|O78
I|O77
I|O76
I|O75-D2
I|O74
I|O73
I|O72
I|O71-D3
GND11
VCC5
I|O70
I|O69-D4
I|O68
I|O67
I|O66
I|O65-D5
I|O64
I|O63
GND10
I|O62
I|O61-D6
I|O60
I|O59
I|O58-GCK5
I|O57-D7
PROGRAM_
VCC4
F303 3315
3320 D7
D 100n
2318
TDO 33R 109
O-TDO DONE
72 DONE D 3321 D7
F309 3331 F310
110
GND13 GND9
71
FIFOA_A(0) 3322 C10
100n AUD_SDO_DAC 111 70
7300 47R 112
I|O85 I|O56-GCK4
69 FIFOA_A(16) +3V3_FPGA 3325 D7
XC17S30XL 8 7 I|O86-GCK7 I|O55
AUD_BCLK 3321 113 68 FIFOA_A(1)
AUD_WS_OUT 3325 47R F330 114
I|O87 I|O54
67 FIFOA_A(15) 3327 C9
4 CE_ VCC 47R
I|O88 I|O53
FIFOA_A(2) 3328 G10
CLOCKGENAUD 3320 F304 115
I|O89-CS1 I|O52
66
3303
SRAMCE0n 47R 116 65 FIFOA_A(14)
1K
3 RESET|OE_ SRAMRDn 117
I|O90 I|O51
64 3329 G11
I|O91 GND8
118 63 FIFOA_A(3) 3330 C8
GND14 I|O50
F333
PWRn 119 62 FIFOA_A(13)
PRDn 120
I|O92 I|O49
61
FIFOA_OEn
3331 D7
I|O93 I|O48
2 CLK PA(15) FIFOA_D(0)
ADDR PA(14)
121
I|O94 I|O47
60
FIFOA_D(7) 4300 B1
E COUNTER PA(13)
122
123
I|O95
I|O96
I|O46
I|O45
59
58 FIFOA_D(1)
FIFOA_D(6)
E 4301 E4
PA(12) 124 57
PA(11) 125
I|O97 I|O44
56 FIFOA_D(2) 4302 A2
EPROM DATA 1 F328 4301 PA(10) 126
I|O98 FPGA / EPLD I|O43
55 5300 C7
CONFIG ROM CELL
127
I|O99 GND7
54 INITn
GND NC MATRIX +3V3_FPGA 128
GND15 VCC3
53
+3V3_FPGA FIFOA_D(7:0) 5301 F2
VCC7 I|O42-INIT_
5 6 PA(9) 129 52 FIFOA_D(5) 5302 I8
I|O100 I|O41
PA(8) 130 51 FIFOA_D(3)
+5V_PROC 131
I|O101 I|O40
50 FIFOA_D(4) +3V3_SRAM 5303 A1
I|O102 I|O39
PRSTn PAD(7) FIFOA_WEn 8 24
100n PAD(6)
132
133
I|O103 I|O38
49
48 FIFOA_A(12) 7301 5304 I12
I|O104 I|O37 CY7C1019BV33-10VC VCC
7304 PAD(5) 134 47 FIFOA_A(4) 6300 I3
FXO-31FT 4 2303 PAD(4) 135
I|O105 I|O36
46 FIFOA_A(11) 5 12
PAD(3) 136
I|O106 I|O35
45
CE_ WE_ FIFOA_WEn 7300 D2
F +3V3_PLL
5301 F317 2305 1
TS
VDD
OUT
3 3312 F300
CLK27M_OSC
137
I|O107
GND16
GND6
I|O34-LDC_
44 FIFOA_A(5)
FIFOA_A(10)
SRAM OE_
28
FIFOA_OEn
F 7301 F13
100MHZ OSC PAD(2) 138 43
100n 10R PAD(1) 139
I|O108 I|O33
42 FIFOA_A(6) 7303 D10
7308 I|O109 I|O32
GND PAD(0) 140 41 FIFOA_A(9) 7304 F4
I|O110 I|O31
CY2071AS 7 2 141 40 FIFOA_A(7)
VDD PINT0n 142
I|O111 I|O30-HDC
39 FIFOA_A(8) FIFOA_A(0) 1 7307 C7
3 XTI
OSC PLL
PINT1n I|O112 I|O29-GCK3 A0
CLOCKGENVID BLOCK
PALE
143
144
I|O113-GCK8 PWRDWN_
38
37
FIFOA_A(1) 2
7308 F2
F329 3317 F305 VCC8 VCC2 +3V3_FPGA A1
I|O28-GCK2
4 XTO CLKA 1 7309 A2
I|O1-GCK1
EPROM +3V3_FPGA
I|O9-TMS
CLK27M
I|O6-TCK
FIFOA_A(2)
I|O5-TDI
3
CONFIGURABLE
MULTIPLEXER
F321 3318 F307 A2 F300 F5
GND1
GND2
GND3
GND4
GND5
VCC1
AND DIVIDE
CLKB 5
I|O10
I|O11
I|O12
I|O13
I|O14
I|O15
I|O16
I|O17
I|O18
I|O19
I|O20
I|O21
I|O22
I|O23
I|O24
I|O25
I|O26
I|O27
I|O2
I|O3
I|O4
I|O7
I|O8
CLK27M_DV
M1
M0
FIFOA_A(3)
LOGIC
8 OE|FS FIFOA_A(16:0) 4 27 FIFOA_D(7) F301 C8

+3V3 CLKC 6 F323 3319 F308 A3 I|O7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CLK27M_CON FIFOA_A(4) 13 26 FIFOA_D(6) F302 C8
G 33R A4 I|O6 G
3300
GND
F303 D7
TDO_CONF
FIFOA_A(5) 14 23 FIFOA_D(5)
2 A5 I|O5 F304 D7
10R
10K
10K
+3V3_FPGA
IO1
IO3
IO4
IO10
PLL VIDEO FIFOA_A(6) 15
A6 I|O4
22 FIFOA_D(4)
F305 G3
TMS
TCK
LINK_AVREADY
LINK_AVFSYNC
FIFOA_A(7)
3328
3329
16 FIFOA_D(3) F306 C10
LINK_AVVALID
11
LINK_AVSYNC
A7 I|O3
LINK_AVCLK
LINKFIFO_DQ(7)
LINKFIFO_DQ(6)
LINKFIFO_DQ(5)
LINKFIFO_DQ(4)
LINKFIFO_DQ(3)
LINKFIFO_DQ(2)
LINKFIFO_DQ(1)
LINKFIFO_DQ(0)
FIFOA_A(8) 17 10 FIFOA_D(2) F307 G3
LINK_INTn
LINK_CSn
A8 I|O2
F308 G3
+3V3_FPGA
PHY_CNA
CLK27M_OSC
1394_RSTn
FIFOA_A(9) 18 FIFOA_D(1)
A9 I|O1 7 F309 D7
FIFOA_A(10) 19 6 FIFOA_D(0)
{LINK_CYCLEOUT,LINK_AVCLK,LINK_AVSYNC,LINK_AVVALID,LINK_AVFSYNC,LINK_AVERR1,LINK_AVERR0,LINK_CSn,LINK_INTn,LINK_AVREADY} A10 I|O0 F310 D7
FIFOA_A(11) 20 F311 I10
H LINKFIFO_DQ(0:7)
FIFOA_A(12)
A11 H F312 A2
21
{SRAMCE0n,SRAMRDn,PINT0n,PINT1n,PALE,PWRn,PRDn,PRSTn} A12
F318 3313
+3V3 F313 I12
FIFOA_A(13) 29
PA(8:15) A13 F314 C7
F320 3314 10K FIFOA_A(14) 30
A14 F315 C8
PAD(7:0) 10K
FIFOA_A(15) 31 F316 B2
A15
F317 F2
BUFENn_VID
BUFENn_AUD
FIFOA_A(16) 32
A16 F318 H9
GND F319 B2
9 25
F320 H9
6300
LD1117 F321 G3
F325
I +5V
3
IN OUT
2
+3V3_PLL I F322 B2
GND {AUD_BCLK,AUD_WS_OUT,AUD_WS_701,AUD_MUTE,AUD_SDI,AUD_SDO_DAC,AUD_SDO_CON} F323 G3
2301
100n
2302
F324 B2
47u
1 5302 F311 5304 F313

+3V3 +3V3_FPGA +3V3 +3V3_SRAM F325 I4
100MHZ 100MHZ
2306
2324
100n
2325
100n
100n
2307
100n
2308
100n
2309
100n
2310
100n
2311
100n
2312
100n
2313
100n
F326 B3
OPTION
2314
47u
CL 16532145_016.eps F328 E4
221101 F329 G3
1 2 3 4 5 6 7 8 9 10 11 12 13 14
DVIO Board: DVCODEC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2400 I6
2401 I6
2402 I6
2403 I7
A DVCODEC A 2404
2405
I7
I7
2406 I8
IO(31:0) 2407 I8
A(0:8) 2408 I8
DV_RSTn
DV_RWn
DV_DSUn
DV_DSLn
DV_PDn
DV_ASn
IO(31)
IO(30)
IO(29)
IO(28)
IO(27)
IO(26)
IO(25)
IO(24)
IO(23)
IO(22)
IO(21)
IO(20)
IO(19)
IO(18)
IO(17)
IO(16)
IO(15)
IO(14)
IO(13)
IO(12)
IO(11)
2409 I8
2410 I10
2411 I10
+35V_DV_EDO
+35V_DV_EDO
+35V_DV_EDO
2412 I11
F400 2413 I11
+3V3_DV
+3V3_DV
B B 2414 I11
3400
10K
2415 I12
2416 I13
2417 I13
7404
2418 I14
2419 I14
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
NW700LQ
2420 I14
VSS26
HOST-RST_
HOST-CS_
HOST-R|W_
HOST-DSU_
HOST-DSL_
HOST-PD_
HOST-AS_
VSS25
DRAM-D31
VCC3.3-25
DRAM-D30
DRAM-D29
DRAM-D28
VSS24
DRAM-D27
VCC3.3-24
DRAM-D26
DRAM-D25
DRAM-D24
VSS23
DRAM-D23
VCC3.3-23
DRAM-D22
DRAM-D21
DRAM-D20
VSS22
DRAM-D19
VCC3.3-22
DRAM-D18
DRAM-D17
DRAM-D16
VSS21
DRAM-D15
VCC3.3-21
DRAM-D14
DRAM-D13
DRAM-D12
VSS20
DRAM-D11
2421 I15
C +3V3_DV
1
2
VCC3.3-1 VCC3.3-20
120
119
+35V_DV_EDO
IO(10) C 3400 B4
HOST-16|8_ DRAM-D10
3
GPIO0 DRAM-D9
118 IO(9) 3401-A H5
4 117 IO(8) +VCC_DV_RAM +VCC_DV_RAM
GPIO1 DRAM-D8 3401-B G5
PURPOSE I/O
5 116
GPIO2 DRAM DATA [ 0...31] BUS VSS19
GENERAL
6
GPIO3 DRAM-D7
115 IO(7) 7402 7403 3401-C H5
7 114
+35V_DV_EDO MT4LC1M16E5 MT4LC1M16E5
VSS1 VCC3.3-19 3401-D G5
21
21
DV_DTACKn 8 113 IO(6)
6
HOST-DTAC_ DRAM-D6
DV_DRQn
DV_ERRn
9
10
HOST-DRQ_ DRAM-D5
112
111
IO(5)
IO(4) Φ Φ 3402-A H6
DV_LCn 11
HOST-ERR_ DRAM-D4
110 A(0) 17 EDO RAM 2 IO(0) A(0) 17 EDO RAM 2 IO(16) 3402-B G6
HOST-LC_ VSS18 0 1Mx16 0 0 1Mx16 0
12 109 IO(3) A(1) 18 3 IO(1) A(1) 18 3 IO(17) 3402-C H6
+3V3_DV VCC3.3-2 DRAM-D3 1 1 1 1
HAD(0) 13 108
+35V_DV_EDO A(2) 19 4 IO(2) A(2) 19 4 IO(18)
HOST-AD0 VCC3.3-18 2 2 2 2
14
VSS2 DRAM-D2
107 IO(2) A(3) 20
3 3
5 IO(3) A(3) 20
3 3
5 IO(19) 3402-D G6
HAD(1) 15 106 IO(1) A(4) 23 7 IO(4) A(4) 23 7
D HAD(2) 16
HOST-AD1
HOST-AD2
DRAM-D1
DRAM-D0
105 IO(0) A(5) 24
4
5
ADR 4
5
8 IO(5) A(5) 24
4
5
ADR 4
5
8
IO(20)
IO(21) D 3403 G6
HAD(3) 17
HOST-AD3 VSS17
104 A(6) 25
6 6
9 IO(6) A(6) 25
6 6
9 IO(22) 3404 G7
18 103 A(8) A(7) 26 10 IO(7) A(7) 26 10 IO(23) 3405 F3
HOST AD BUS [ 0....15 ]

+3V3_DV VCC3.3-3 DRAM-A8 7 7 7 7
HAD(4) 19 102
+3V3_DV A(8) 27 DATA 33 IO(8) A(8) 27 DATA 33 IO(24)
HOST-AD4 VCC3.3-17 8 8 8 8
DRAM ADDRESS BUS

20 101 A(7) 28 34 IO(9) 28 34 IO(25) 5400 H10
VSS3 DRAM-A7 9 9 9 9
HAD(5)
HAD(6)
21
22
HOST-AD5
HOST-AD6
DV Decoder DRAM-A6
DRAM-A5
100
99
A(6)
A(5) RASn 14
RAS
10
11
35
36
IO(10)
IO(11) RASn 14
RAS
10
11
35
36
IO(26)
IO(27) 5401 H13
HAD(7) 23 98 LCASn 31 38 IO(12) LCASn 31 38
HOST-AD7 VSS16
UCASn LCAS 12
IO(13) UCASn LCAS 12 IO(28) 5402 I5
24
VCC3.3-4 DRAM-A4
97 A(4) 30
HCAS 13
39 30
HCAS 13
39 IO(29)
+3V3_DV 25
HOST-AD8 VCC3.3-16
96
+3V3_DV WEn 13
WE 14
40 IO(14) WEn 13
WE 14
40 IO(30) 5403 I10
26 95 A(3) 29 41 IO(15) 29 41 IO(31) 5404 I13
VIDEO BUS CLOCK INPUTS

VSS4 DRAM-A3 OE 15 OE 15
27
HOST-AD9 DRAM-A2
94 A(2)
28
HOST-AD10 DRAM-A1
93 A(1) 15 11 15 11 7402 C9
29 92 16 NC 12 16 NC 12
E 30
HOST-AD11 VSS15
91 A(0)
NC
32
NC
32 E 7403 C11
VIDEO INTERFACE
+3V3_DV VCC3.3-5 DRAM-A0
31 90
+3V3_DV 7404 C4
DRAM CTRL
HOST-AD12 VCC3.3-15
SYNCHRONOUS
WEn
22
37
42
22
37
42
32 89
33
VSS5
HOST-AD13
DRAM-WE_
DRAM-LCAS_
88 LCASn F400 B4
34 87 UCASn
35
HOST-AD14 DRAM-UCAS_
86
F401 F3
+3V3_DV 36
HOST-AD15 VSS14
85 RASn F402 F4
AUD_WS_701 VCC3.3-6 DRAM-RAS_
37 84
F402 38
AUD-WS
AUDIO VCC3.3-14
83
+3V3_DV F403 F3
F401 VSS6 VIDEO BUS VID-RDY CRTL{RASn,LCASn,UCASn,WEn}
AUD_BCLK 39
AUD-BCLK INTERFACE VID-DTACK_
82 F404 G6
AUD_SDI 3405 40 81
AUD-SDO
VCC3.3-10
VID-OE_ F405 G7
VCC3.3-11
VCC3.3-12
VCC3.3-13
VID-CLK1
VID-CLK0
F403
VCC3.3-7
VCC3.3-8
VCC3.3-9
47R F426
AUD-SDI
VID-FLD
F406 F5
VID-HS
VID-VS
VID-D0
VID-D1
VID-D2
VID-D3
VID-D4
VID-D5
VID-D6
VID-D7
RES10
RES11
VSS10
VSS11
VSS12
VSS13
RES1
RES2
RES3
RES4
RES5
RES6
RES7
RES8
RES9
VSS7
VSS8
VSS9
TEST
F F F407 F5
F408 F5
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
F409 H6
F407
F408
F419
F412
F413
F414
F411
F410 G6
F406
F411 F6
+3V3_DV
+3V3_DV
+3V3_DV
+3V3_DV
+3V3_DV
F404 +3V3_DV
+3V3_DV
1Mx16 devices are used as 256kx16 F412 F6
F410
F413 F6
F405
F418
3402-B
3401-B
47R
F414 F6
47R
47R
47R
F416 I9
3401-D
47R 3402-D
CLK27M_DV
G G F417 I15
F418 G7
47R
47R
47R
3403
47R
F419 F6
F420 H6
3404
F422 47R
F421 H6
3401-C
YUV(5) 3402-C
3401-A
YUV(7) 3402-A
F422 H7
F421
F425 I12
F409
F420
DV_HS_IN
F426 F4
YUV(0)
YUV(1)
YUV(2)
YUV(3)
YUV(4)
YUV(6)
DV_VS
H YUV(7:0)
H
HAD(7:0)
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn}
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn} OPTION OPTION

5400 5401
{AUD_BCLK,AUD_WS_OUT,AUD_WS_701,AUD_MUTE,AUD_SDI,AUD_SDO_DAC,AUD_SDO_CON} +5V +5V
100MHZ 100MHZ
5402 F416 5403 F425 5404 F417

+3V3 +3V3_DV +3V3 +35V_DV_EDO +3V3 +VCC_DV_RAM
100MHZ 100MHZ 100MHZ
2400
100n
2401
100n
2402
100n
2403
100n
2404
100n
2405
100n
2406
100n
2407
100n
2408
100n
2409
100n
2410
100n
2411
100n
2412
100n
2413
100n
2414
100n
2415
100n
2416
100n
2417
100n
2418
100n
2419
100n
2420
100n
2421
100n
I I
CL 16532145_017.eps
221101
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DVIO Board: Audio & Video Output

1 2 3 4 5 6 7 8 9 10 11 12 13 14
0001 I4 F509 C6
AUDIO & VIDEO OUTPUT 0002

0003
0004
I5
I6
I6
F510
F511
F512
C5
D6
D6
{SRAMCE0n,SRAMRDn,PINT0n,PINT1n,PALE,PWRn,PRDn,PRSTn} 0005 I7 F513 D7
{LINK_AVCLK,LINK_AVSYNC,LINK_AVVALID,LINK_AVFSYNC,LINK_CSn,LINK_INTn,LINK_AVREADY} 0006 I8 F514 D6
1508
0007 I8 F515 D6
PINT0n 4506 1 PH-S 1500 C7 F516 D6
A PINT1n 4507 2
A 1501 G14 F517 D6
1502 I2 F518 D7
Clock delay LINK_AVVALID 4508 3
1503 I2 F519 D5
+3V3_dly +3V3_dly +3V3_dly +3V3_dly +3V3_dly LINK_AVFSYNC 4509 4 1504 I2 F520 D5
5 1505 I2 F521 E7
7500-A 7500-B 7500-C 7500-E 7500-D
74LVC04A 74LVC04A 74LVC04A 74LVC04A 74LVC04A 4510 6
1506 I3 F522 D5
14 14 14 14 14 DOUT 1507 I3 F523 E6
1 2 3 4 5 6 4500 F500 11 10 9 8 F501 4511 7
CLK27M_CON IO1 1508 A14 F524 D5
2500 C1 F525 E12
3510 F502
7 7 7 OPTION
7 7 4512 8
B IO3
B
4501
2501 C3 F526 E12
3512
9
47R
OPTION
2502 C3 F527 E2
47R
4513 10
IO4 2503 C3 F528 E6
4514 11 2504 C3 F529 D5
IO10
5500 +3V3 12 2505 E12 F530 E4
+3V3 +3V3_dly F510 3504-B 2 F509
100MHZ 7 2506 E12 F531 E7
F508 33R 5 3504-D F507 2507 E11 F532 E8
2500
100n
100MHZ
4 OPTION
5501
F506 7
3505-B 2 33R F505 2508 E11 F533 E4
2501 33R 3505-D F503 2509 E6 F534 F7
C F504 5 4 C 2510 F8 F535 F7
2502 100n 33R
2511 F8 F536 F7
100n 2503 2512 G8 F537 G7
2504 100n 1500 2514 G11 F538 G7
179161 2515 G13 F539 G8
100n 1 2
7505
7 18 31 42
2516 G10 F540 G10
74LVC16244AD F519 3505-C 3 F511
VC
4 6 3 4 2517 G13 F541 G13
10
1 15 F520 8
3505-A
1
33R F512 F513 5 6 2518 H12 F542 G13
BUFENn_VID EN1
48 21
2519 H12 F543 G14
GND
F514
D 25
24
EN2
EN3
28
34
F522 33R 3504-C 3
6 7 8 D 3502 D5 F544 G12
BUFENn_AUD EN4 39 F524 3504-A 33R F515 9 10
8 1 3504-A D5 F545 G11
45
33R 3524 2 F516 11 12 3504-B C5 F546 G7
1
YUV(0) 47 2
F529 3502 33R F517 F518 13 14 +3V3 +3V3 3504-C D5 F547 G8
1 1
YUV(1) 46 3
33R 3504-D C5 F548 G12
YUV(2) 44 5 15 16
YUV(3) 43 6
F559 3505-A D5 F549 H7
F521 17
5503
5502
YUV(4) 41 8 18 DAC 3505-B C5 F550 H8
1 2
YUV(5) 40 9
F523
YUV(6) 38 11
3506 19 20 3505-C D5 F551 H7
YUV(7) 37 12 2507 2505 3505-D C5 F552 H8
E 33R
E
F526
F525
36 13 21 22
F527 35
1 3
14 3506 E5 F553 H13
F530 F528 23 24 47u 47u
33 16
DV_HS_OUT 32 17
RTSN 3510 B3 F554 E4
F531 F532 2508 2506
4505
DV_VS 30
1 4
19
F533 3525 +3V3
25 26 +3V3 3511 B4 F555 F4
AUD_BCLK 29 20
100n 100n 3512 B5 F556 F4
2509
100n
AUD_SDO_CON 27 22 27 28
F554 33R 7506
2510
100n
2511
AUD_WS_OUT 3518 G10 F557 F6
47u
26 23
F534 29 30 UDA1334ATS 13 4
VDDA VDDD
3519 G13 F558 F6
F555 F558
Buffer 3526 31 32 AUD_BCLK 1 BCK
3520 G10 F559 E6
33R F535 33 34 AUD_WS_OUT 2 WS PLL0 10 3521 G13
DIGITAL PLL
F556 F557 INTERFACE 3524 D5
F 3527 35 36 AUD_SDO_DAC 3 DATAI
SFOR0 11
F 3525 E5
33R 37 38 DE-EMPHASIS 3526 F5
SFOR1 7
F536 39 40 6 SYSCLK|PLL1
+5V +5V 3527 F5
41 42 INTERPOLATION FILTER 4500 B4
2512
AUD_MUTE 8 MUTE
47u
F537 43 44 4505 E6
RESETn NOISE SHAPER 4506 A13
45 46 9 DEEM|CLKO
4507 A13
DAC
DAC
PH-S
To analog PCB
F538 47 48 F539
ISPN CTSN 3518 F540
2514 2515 F541
3519 F542
1501 4508 A13
14 VOL VOR 16 1
G 49 50 G 4509 A13
100R 47u F545 F544 47u 100R F543 2
F546 F547 4510 B13
220K
3521
2517
51 52 VSSA VSSD VREF-DAC
2516
3520
220K
10n
10n
TXD RXD 3 4511 B13
15 5 12 F548
53 54
4
4512 B13
55 56 4513 B13
2519
100n
2518
F549 F550 4514 B13
47u
TDI 57 58 TDO
F551 F552 5500 B1
TCK 59 60 TMS
5501 C3
5502 E12
F553 5503 E12
H YUV(7:0)
To digital PCB H
{DV_LCn,DV_ERRn,DV_DRQn,DV_DTACKn,DV_ASn,DV_PDn,DV_DSUn,DV_RWn,DV_VS,DV_HS_IN,DV_RSTn,DV_HS_OUT,DV_DSLn} 7500-A B2
7500-B B2
{TDI,TCK,TDO,TDO_CONF,TMS}
7500-C B3
{AUD_BCLK,AUD_WS_OUT,AUDIO_WS_701,AUD_MUTE,AUD_SDI,AUD_SDO_DAC,AUD_SDO_CON} 7500-D B4
7500-E B4
7500-F I1
7505 D3
Shielding connection on mounting holes
+3V3_dly 7506 F11
I 7500-F
74LVC04A
Hole 4.0 mm with Cu Hole 4.0 mm with Cu Hole 4.9mm Hole 3.6 mm
I F500 B4
0001 0002 0003 0004 0005 0006 0007 F501 B5
1504
1502
1503
1505
1506
1507
14
13 12 F502 B3
7
F503 C6
F504 C5
OPTION
F505 C6
CL 16532145_018.eps F506 C5
221101 F507 C6
F508 C5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Layout DVIO Board (Overview Top View)

1101 A2 2332 F4 3130 D2 3331 D4 7403 F5
1102 B1 2400 D6 3131 E2 3400 D6 7404 D5
1200 B5 2401 D5 3132 E2 3401 D5 7500 B5
PART 1 1201 A6 2402 D5 3133 E1 3402 D5 7505 B5
1500 C6 2403 D5 3134 E1 3403 E5 7506 B4
CL 16532145_19a.eps 1501 A4 2404 D5 3136 B2 3404 E4
1508 G2 2405 D5 3137 C2 3405 D4
2104 B1 2406 D5 3138 B2 3502 B6
2105 C1 2407 D5 3139 C2 3504 B6
2146 D2 2408 E5 3140 D1 3505 B6
2147 D2 2409 E5 3141 D1 3506 B6
2148 D2 2410 E5 3147 B1 3510 B5
2149 D2 2411 E5 3148 B1 3512 B5
2150 D2 2412 E6 3164 B2 3518 A4
2151 C2 2413 E6 3165 B2 3519 A4
2152 C2 2414 D6 3166 C3 3520 A4
2153 C1 2415 D6 3171 C1 3521 A4
2154 C1 2416 F4 3172 C1 3524 B6
2155 D1 2417 F5 3173 B2 3525 C5
2156 D1 2418 F6 3174 C1 3526 B6
2157 D1 2419 E4 3176 C1 3527 B6
2158 A1 2420 E5 3177 B2 4100 C2
2163 B2 2421 E6 3178 B2 4101 C2
2170 B1 2500 A5 3179 C2 4102 C2
2171 B1 2501 B5 3180 C2 4103 E1
2173 C1 2502 B5 3188 C1 4206 B5
2174 B1 2503 B6 3189 C1 4300 E4
2175 B1 2504 C5 3190 C1 4301 E4
2176 B1 2505 B4 3191 C2 4302 E4
2177 B1 2506 B4 3192 E2 4500 B5
2178 B2 2507 B5 3193 D1 4501 B5
2181 A1 2508 B4 3197 E2 4505 B5
2182 B2 2509 C6 3198 E2 5103 C2
2183 B2 2510 B6 3199 E2 5106 C1
2184 B2 2511 C5 3201 B5 5109 B1
2187 B1 2512 C5 3202 C5 5110 B2
2192 D1 2514 A4 3203 C5 5200 C5
2193 D1 2515 A5 3204 C5 5300 D4
2194 E1 2516 A4 3205 C5 5301 D4
2195 E1 2517 A4 3206 C5 5302 E2
2196 E2 2518 B4 3214 C5 5303 F4
2197 E2 2519 B4 3215 C5 5304 F3
2200 B4 3100 E2 3216 C5 5400 E6
2202 C4 3101 E2 3217 C5 5401 F6
2203 C4 3102 E1 3223 A6 5402 E5
2204 C3 3103 D1 3224 B6 5403 E6
2205 B5 3104 E2 3225 C4 5404 F6
2206 C5 3105 C1 3226 C4 5500 A5
2207 A6 3106 D1 3300 E3 5501 A5
2301 G4 3107 C2 3301 E4 5502 B4
2302 G4 3108 C2 3303 E3 5503 B4
2303 E2 3109 E2 3305 F4 6300 G4
2304 D4 3110 E2 3306 F4 7101 B1
2305 D4 3111 C2 3307 F4 7103 D2
2306 E3 3113 C2 3312 E3 7201 C3
2307 E3 3115 C2 3313 E3 7202 C5
2308 E4 3116 B1 3314 E3 7203 C4
2309 E4 3117 C2 3315 D4 7204 C4
2310 D4 3118 E2 3317 E4 7207 A6
2311 D3 3119 E2 3318 D4 7208 C4
2312 D3 3120 E2 3319 D4 7209 C4
2313 E3 3121 E2 3320 D3 7300 E4
PART 2 2314 F2 3122 E2 3321 D4 7301 F3
2318 E4 3123 E2 3322 E4 7303 E3
CL 16532145_19b.eps 2319 E4 3124 D2 3325 D4 7304 E2
2324 E3 3125 D2 3327 E4 7307 D4
2325 F3 3126 D2 3328 E3 7308 D4
CL 16532145_019.eps
201101 2330 E4 3127 D2 3329 E3 7309 F4
2331 F4 3128 D2 3330 D4 7402 F5
Layout DVIO Board (Part 1 Top View)
PART 1
CL 16532145_19a.eps
211101
Layout DVIO Board (Part 2 Top View)
CL 16532145_019b.eps
PART 2 211101
Layout DVIO Board (Testlands Bottom View)

CLK27M_con
+3V3 uP_CLK PSEN
F100 C6 F144 D6 F206 C2 F328 E3 F513 B1

F100 C6 F146 B6 F206 C2 F329 D3 F513 B1
F101 C6 F146 B6 F207 C2 F329 D3 F514 B1
F101 C6 F148 B6 F207 C2 F330 D4 F514 B1
F102 C6 F148 B6 F208 C2 F330 D4 F515 B1
F102 C6 F149 C5 F208 C2 F331 E3 F515 B1
F103 C5 F149 C5 F209 C3 F331 E3 F516 B1
F103 C5 F150 B6 F209 C3 F332 E3 F516 B1
F104 C6 F150 B6 F210 A1 F332 E3 F517 B1
F104 C6 F152 C5 F210 A1 F333 E4 F517 B1
F105 C6 F152 C5 F211 C2 F333 E4 F518 B3
F105 C6 F153 C5 F211 C2 F335 E3 F518 B3
F106 C6 F153 C5 F212 C3 F335 E3 F519 B2
F106 C6 F154 C5 F212 C3 F336 D3 F519 B2
F107 C5 F154 C5 F213 C3 F336 D3 F520 B2
F107 C5 F156 C5 F213 C3 F400 E3 F520 B2
F108 B5 F156 C5 F214 C2 F400 E3 F521 C1
F108 B5 F157 C5 F214 C2 F401 D2 F521 C1
F109 C5 F157 C5 F216 A2 F401 D2 F522 B2
+3V3_IEEE_A F109 C5 F158 C5 F216 A2 F402 E5 F522 B2
F110 C6 F158 C5 F219 B2 F402 E5 F523 B1
+3V3_IEEE_D F110 C6 F161 D6 F219 B2 F403 E4 F523 B1
F111 C6 F161 D6 F220 C1 F403 E4 F524 C2
F111 C6 F162 B6 F220 C1 F404 E2 F524 C2
F112 C6 F162 B6 F221 B1 F404 E2 F525 B3
F112 C6 F163 D5 F221 B1 F405 E3 F525 B3
F113 C6 F163 D5 F222 A1 F405 E3 F526 B3
+3V3_IEEE_PLL F113 C6 F165 E5 F222 A1 F406 D2 F526 B3
F114 C6 F165 E5 F223 C2 F406 D2 F527 B2
F114 C6 F166 D5 F223 C2 F407 D3 F527 B2
F115 C6 F166 D5 F230 B2 F407 D3 F528 B1
F115 C6 F167 D5 F230 B2 F408 D2 F528 B1
+5V F116 C6 F167 D5 F232 B2 F408 D2 F529 B2
F116 C6 F168 E5 F232 B2 F409 B2 F529 B2
F117 C5 F168 E5 F300 E4 F409 B2 F530 B2
F117 C5 F169 E5 F300 E4 F410 D2 F530 B2
RESET F118 B5 F169 E5 F301 D3 F410 D2 F531 A2
F118 B5 F170 D5 F301 D3 F411 D2 F531 B2
F119 B5 F170 D5 F302 E4 F411 D2 F532 C1
F119 B5 F171 D5 F302 E4 F412 D2 F532 C1
+3V3_LINK F120 B5 F171 D5 F303 D3 F412 D2 F533 B1
+5V_PROC F120 B5 F172 E5 F303 D3 F413 D2 F533 B1
F121 B5 F172 E5 F304 D4 F413 D2 F534 C1
+3V3_FPGA F121 B5 F174 D5 F304 D4 F414 D2 F534 C1
F122 B5 F174 D5 F305 E3 F414 D2 F535 C1
F122 B5 F175 C4 F305 E3 F416 E1 F535 C1
F123 B5 F175 C4 F306 E3 F416 E1 F536 C1
CLK27M_DV F123 B5 F184 D5 F306 E3 F417 E2 F536 C1
F124 E4 F184 D5 F307 D3 F417 E2 F537 C1
+3V3_DV F124 E4 F185 B6 F307 D3 F418 E2 F537 C1
F125 E4 F185 B6 F308 B2 F418 E2 F538 C3
F125 E4 F186 D5 F308 B2 F419 D2 F538 C3
F126 D5 F186 D5 F309 B3 F419 D2 F539 C1
+35V_DV_EDO F126 D5 F187 D5 F309 B3 F420 B2 F539 C1
F127 E6 F187 D5 F310 D3 F420 B2 F540 A3
F127 E6 F188 D6 F310 D3 F421 E2 F540 A3
F128 E4 F188 D6 F311 D4 F421 E2 F541 A3
F128 E4 F189 D5 F311 D4 F422 E4 F541 A3
CLOCKAUDTMP F129 E6 F189 D5 F312 F3 F422 E4 F542 A3
F129 E6 F190 E6 F312 F3 F425 E2 F542 A3
+Vcc_DV_RAM F130 E4 F190 E6 F313 E4 F425 E2 F543 A3
F130 E4 F191 D6 F313 E4 F426 D2 F543 A3
F131 E6 F191 D6 F314 D3 F426 D2 F544 B3
F131 E6 F192 B5 F314 D3 F500 B2 F544 B3
F132 E6 F192 B5 F315 D3 F500 B2 F545 B3
F132 E6 F193 B5 F315 D3 F501 B2 F545 B3
F133 E5 F193 B5 F316 F3 F501 B2 F546 C1
F133 E5 F194 C5 F316 F3 F502 B2 F546 C1
F134 E5 F194 C5 F317 D3 F502 B2 F547 C1
F134 E5 F195 C5 F317 D3 F503 B1 F547 C1
F135 D6 F195 C5 F318 E4 F503 B1 F548 B3
F135 D6 F197 E6 F318 E4 F504 B2 F548 B3
F136 D6 F197 E6 F319 F3 F504 B2 F549 C1
F136 D6 F198 D5 F319 F3 F505 B1 F549 C1
F137 A6 F198 D5 F320 D4 F505 B1 F550 C1
F137 A6 F199 B5 F320 D4 F506 B2 F550 C1
F138 C6 F199 B5 F321 D3 F506 B2 F551 C1
F138 C6 F200 B3 F321 D3 F507 B1 F551 C1
F139 B6 F200 B3 F322 F3 F507 B1 F552 C1
F139 B6 F201 B2 F322 F3 F508 B2 F552 C1
F140 B5 F201 B2 F323 D3 F508 B2 F553 A3
F140 B5 F202 C2 F323 D3 F509 B1 F553 A3
F141 C5 F202 C2 F324 E3 F509 B1 F554 B2
F141 C5 F203 C3 F324 E3 F510 B2 F554 B2
F142 C6 F203 C3 F325 G3 F510 B2 F555 B2
F142 C6 F204 D4 F325 G3 F511 B1 F555 B2
F143 D6 F204 D4 F326 E3 F511 B1 F556 B1
CL 16532145_021.eps
F143 D6 F205 C2 F326 E3 F512 B1 F556 B1
221101
F144 D6 F205 C2 F328 E3 F512 B1 F557 C1
CLK27M +3V3_PLL +3V3_SRAM
+3V3_FPGA_CONF
Digital Board: VSM, Buffer Memory and Bit Engine Interface

1100 C1 2106 A5 2114 A5 2122 B14 2130 G15 2139 G13 2147 D1 3102 E3 3110 F3 3118 D11 3126 H12 3134 E2 4103 F7 7101 B14
1101 H1 2107 A5 2115 A6 2123 B14 2131 H15 2140 G2 2148 E1 3103 D11 3111 B3 3119 F10 3127 G3 3135 E2 4104 G6 7102 G13
2100 A4 2108 A5 2116 A6 2124 B13 2132 B1 2141 G2 2149 E1 3104 C2 3112 B3 3120 G15 3128 G2 3136 G1 4105 G7 7103 C1
2101 A5 2109 A5 2117 A6 2125 B13 2134 D1 2142 G2 2150 E1 3105 D2 3113 B3 3121 G12 3129 H2 3137 B2 5100 A4 7104 H4
2102 A5 2110 A5 2118 A6 2126 B12 2135 G13 2143 H1 2151 F1 3106 F2 3114 B2 3122 H12 3130 H12 3138 B2 5101 A12
2103 A5 2111 A5 2119 A4 2127 B12 2136 F1 2144 H1 2152 G1 3107 C3 3115 E3 3123 H12 3131 D2 4100 C15 5102 B1
2104 A5 2112 A5 2120 B15 2128 B3 2137 G4 2145 H1 3100 D11 3108 F3 3116 E3 3124 H12 3132 E2 4101 H4 5103 F13
2105 A5 2113 A5 2121 B15 2129 G13 2138 G1 2146 A4 3101 F10 3109 F3 3117 D11 3125 G14 3133 E2 4102 F6 7100 B4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VERSATILE STREAM MANAGER (VSM), BUFFER MEMORY & BITENGINE INTERFACE DIGITAL VIDEO(CCIR656)
MPEG2 VIDEO
{VSM_M_LDQM,VSM_M_UDQM,VSM_M_WEn,VSM_M_RASn,VSM_M_CASn,VSM_M_CLKEN,VSM_M_CLKOUT}
GNDD
2146 100n
2100 100n
2101 100n
2102 100n
2103 100n
2104 100n
2105 100n
2106 100n
2107 100n
2108 100n
2109 100n
2110 100n
2111 100n
2112 100n
2113 100n
2114 100n
100n
100n
100n
100n
VSM_M_A(13:0)
2119
A A
4u7
VSM_M_D(15:0)
2115
2116
2117
2118
VCC3_VSM_MEM
5101 I141
5100 +3V3
VCC3_VSM 100MHZ
+3V3
+5V +5V +5V +5V +5V +5V 100MHZ I100
2127
2126
100n
2125
100n
2124
100n
2123
100n
2122
100n
2121
100n
2120
100n
4u7
7100
201
183
169
156
144
126
108
181
129
95
85
73
62
52
41
31
15
77
25
72
71
74
70
76
75
79
68
65
69
63
66
64
61
59
56
54
53
55
58
60
98
96
93
91
88
86
83
81
82
84
87
89
92
94
97
99
5
SAA7333HL
4K7
4K7
4K7
4K7
4K7
4K7
VDD_201
VDD_183
VDD_169
VDD_156
VDD_144
VDD_126
VDD_108
VDD_95
VDD_85
VDD_73
VDD_62
VDD_52
VDD_41
VDD_31
VDD_15
VDD_5
VDD_181
VDD_129
VDD_77
VDD_25
M_CLKOUT
M_CLKEN
M_CASn
M_RASn
M_Wen
M_UDQM
M_LDQM
M_A13
M_A12
M_A11
M_A10
M_A9
M_A8
M_A7
M_A6
M_A5
M_A4
M_A3
M_A2
M_A1
M_A0
M_D15
M_D14
M_D13
M_D12
M_D11
M_D10
M_D9
M_D8
M_D7
M_D6
M_D5
M_D4
M_D3
M_D2
M_D1
M_D0
UART1
I101 GNDD 7101
VIP_ICLK
B SYSCLK_VSM_5508
RESETn
47
48
SYSCLK
RESETn
VBI_ICLK
VBI_IPD0
131
133
GNDD
49 43 9 3 27 14 1 MT48LC4M16A2TG-7E GNDD B
3137
3138
3114
3113
3112
3111
2128 134
UART2 1n
VBI_IPD1
VBI_IPD2
136 VDDQ VDD
VSM_UART1_RX GNDD I112 145 137
VSM_UART1_TX I113 146
UART1_RX VBI_IPD3
138 BANK0 CKE 37 I167 VSM_M_CLKEN
I183
5102 VSM_M_LDQM I169 15 DQML
UART1_TX VBI_IPD4
VSM_UART1_RTSn I114 147 139 ROW- CTRL
+3V3 VSM_UART1_CTSn I115 148
UART1_RTSn VBI_IPD5
140 ADDR LOGIC CLK 38 I171VSM_M_CLKOUT
2132
VSM_M_UDQMI172 39 DQMH
UART1_CTSn VBI_IPD6
141 LATCH &
VBI_IPD7 CS_ 19 I173
100n I116 I102 DECODER
VSM_UART2_RX 149 142 VIP_ERROR
COMMAND
UART2_RX VE_VIP_ERROR WE_ 16 I174
DECODE
GNDD VSM_UART2_TX I117 151 128 I103 VE_DTACKn VSM_M_WEn
7103 UART2_TX VE_DTACKn
REFRESH
COUNTER
I104
4100
VSM_UART2_CTSn I118 153 127 VE_DSn
NC7SZ58 5 VSM_UART2_RTSn I119 152
UART2_CTSn VE_DSn
109 2 DQ0 CAS_ 17 I175 VSM_M_CASn
6 UART2_RTSn VE_D0 BANK0
C BCLK_CTL_SERVICE VCC VE_D1
110
MEMORY RAS_ 18 I140 C
DATA OUTPUT REGISTER

111 4 DQ1 VSM_M_RASn
1 4 3104 BE_BCLK_VSM I120 101
VE_D2
112 ARRAY
ACLK_EMP
BE_BCLK VE_D3 5 DQ2
BE_WCLK I121 102 113 (4,096x256x16) REG MODE
3 47R BE_DATA_RD I123 103
BE_WCLK VE_D4
114 GNDD
GNDD GND BE_DATI VE_D5 7 DQ3 SENSE AMPLIFIERS BA0 20
1100
BE_DATA_WR I125 10R 3107 104 DVDR VERSATILE STREAM MANAGER 115
BE_DATO VE_D6 ROW
BE_SYNC I127 I128
VCC3_VSM
2 105 117 DQMH DQML
FMN BE_SYNC VE_D7 8 DQ4 BA1 21
AE_ACLK
BE_FLAG I129 106 118 ADDR
BE_FLAG VE_D8
BE_V4 I131 107 119 MUX
VSM
BE_V4 VE_D9 10 DQ5 A0 23
15 120 I/O GATING
VE_D10
GNDD
3118
22R
D_PAR_REQ 121 DQM DATA LOGIC
VE_D11 11 DQ6 READ DATA LATCH A1 24
14 D_PAR_D(7:0) 30 122
D_PAR_REQ VE_D12 WRITE DRIVERS BANK
33 123
34
D_PAR_D0 VE_D13
124 13 DQ7 CTRL A2 25
13 D_PAR_D1 VE_D14 LOGIC
3100
3117
22R
10K
GNDD
D 39 125
D
ADDRESS REGISTER
D_PAR_D2 VE_D15
4110
12 40 42 DQ8 A3 26
I111 3105 D_PAR_D3
BE_DATA_WR 42
D_PAR_D4 ACC_ACLK_DAI
160 I142 COLUMN
43 51 I184 44 DQ9 A4 29
11 2134 GNDD 47R D_PAR_D5 ACC_ACLK_DEC ADDR
35 I143
DATA INPUT REGISTER

158
37
D_PAR_D6 ACC_ACLK_OSC
159 45 DQ10 COUNTER/ A5 30
10 3131 D_PAR_D7 ACC_ACLK_PLL ACC_ACLK_PLL
10p OPTION BE_SYNC D_PAR_DVALID 38 143 I147 LATCH
D_PAR_SYNC
D_PAR_DVALID ACC_FID 3103 OPTION 47 DQ11 A6 31
TO BITENGINE
29 157
9 2147 GNDD 1R D_PAR_STR
D_PAR_SYNC ACC_PWM
32
D_PAR_STR 10K GNDD 48 DQ12 A7 32
8 3115 I186 45 174 I152
10p OPTION 3132 BE_FLAG VCC3_VSM I187
D_V4 AE_CS
VCC3_VSM 3116 10K 44
D_WCLK COLUMN
7 10K 176 I153 AE_BCLK_VSM 50 DQ13 A8 33
2148 GNDD 1R AE_BCLK DEDCODER
177 I154 AE_WCLK_VSM
AE_WCLK 51 DQ14 A9 34
6 I156 50 178 I155 AE_DATAO
10p OPTION 3133 BE_BCLK CPUINT0
I157 CPUINT0 AE_DATA
E 5
2149 GNDD 1R I137
CPUINT1
49
CPUINT1
JTAG3_TCK
53 DQ15 A10 22 E
EMPRESS_IRQn I159 171 162 I158
EXT_INT0 TCK A11 35
4 3102 10K I161 170 163 I160
10p OPTION 3134 VCC3_VSM EXT_INT1 TDI
BE_DATA_RD I163 168 164 I162 JTAG3_TD_VSM_TO_VIP VSS VSSQ
I165 167
EXT_INT2 TDO
165 I164 JTAG3_TMS NC
3 2150 GNDD 1R 5508_odd_even EXT_INT3 TMS
TRSTn
166 I166 JTAG3_TRSTn 40 36 54 41 28 52 46 12 6
2K2
172
2K2
2
HO_PROCCLK
10p OPTION 3135 BE_WCLK TEST0

173
TEST1
SDRAM
HO_CSHn
HO_BEN1
HO_BEN0
HO_WAIT
HO_CSLn
2151 GNDD VIP_INT

HO_RWn
1
VSS_155
VSS_154
VSS_132
VSS_208
VSS_192
VSS_175
VSS_161
VSS_150
VSS_135
VSS_116
VSS_100
VSS_182
VSS_130
1R GNDD
HO_D15
HO_D14
207 HO_D13
1 HO_D12
2 HO_D11
3 HO_D10
HO_A22
HO_A21
HO_A20
HO_A19
HO_A18
HO_A17
HO_A16
HO_A15
HO_A14
HO_A13
HO_A12
HO_A11
HO_A10
VSS_24
VSS_90
VSS_80
VSS_67
VSS_57
VSS_46
VSS_36
VSS_21
VSS_10
VSS_78
VSS_26
HO_D9
HO_D8
HO_D7
HO_D6
HO_D5
HO_D4
HO_D3
HO_D2
14 HO_D1
HO_D0
HO_A9
HO_A8
HO_A7
HO_A6
HO_A5
HO_A4
HO_A3
HO_A2
HO_A1
3101
3119
BE_V4
15
10p OPTION BE_SERIAL AUDIO ENCODER DATA STREAM BUS
I176 3106
I138 155
I133 154
I136 132
208
192
175
161
150
135
116
100
182
130
179
180
184
185
186
187
188
189
190
191
193
194
195
196
197
198
199
200
202
203
204
205
206
24
80
67
57
46
36
21
10
78
26
19
18
22
23
11
12
13
16
17
90
20
27
28
4
6
7
8
9
F 14 2136 47R JTAG_CHAIN3 F
I134
GNDD
GNDD
I177 GNDD
OPTION
13 3108 I168
47p 22R
4102
4103
I145
I170
12 I178 3109 47R 3125 5103 I130

+5V VCC5_4046
ACC_ACLK_OSC
11 I179 100MHZ
3110 47R
Encoding
4u7
BE_IRQn
100n
10 I180 GNDD
3127 47R
Audio PLL
GNDD
4106
2135
GNDD
4109
2139
9 3136 47R
7102
8 OPTION I132
OPTION OPTION 16
1R 74HCT9046AD
OPTION
+3V3
OPTION
4104
4105
2152
2138
2140
2142
2141
G G
10p
10p
10p
10p
47p
7 VCC
4107 I149 GNDD 3 2
100n 2137
6
COMPI PC1O|PCPO
4108 14 13 I105 3120 I106
VIP_FID_FF SIGI PC2O
5 I107 6
I181 GNDD 2129 15K
4 I126 3128
BE_FAN SYSTEM DATA BUS I108
C1A PLL
68p 7 2130
RESETn_BE C1B
3
47R 3121 I109
3129
GNDD 7104 SYSTEM ADDRESS BUS 3122 12K 11
R1
5 74HC1G04GW 2u2
2
3123 1R I182 3124 3K I110
12 10
1
47R
I188 SYSTEM_CONTROL 2K I122
R2 DEMO
2154
1101 4 2 15 4
BE_LOADN 3130 RB VCOO
FMN GNDD I124 10n
9 OPTION
VCOI
H NC t OPTION H
2131
2153
100n
22u
NTH5G16P 5
1 3 INH
2143
2145
2144
10p
22p
10p
GND
OPTION GNDD 3126 220K GNDD GNDD
GNDD 1 8
GNDD 4101 CL 16532145_022.eps
GNDD GNDD
OPTION 211101
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Digital Board: AV Decoder STI5508

1 2 3 4 5 6 7 8 9 10 11 12 13 14 1200 A11 5207 A2
2200 C5 5208 H13
2201 C11 5209 A13
F265 2202 A3 5210 A14
AV decoder : STI5508 GNDD 7 DCU 2203 I2 5211 A13
6 connector VDD_CORE
+5V 2204
2205
B4
B13
5212
7200
A13
C2
VDD_STI
VDD_STI
VDD_STI
P_SCAN_YUV(7:0)
5
2206 B13 7201 A2
EMPRESS_BOOT
100MHZ
4 2207 B5 7202-A C13
{BCLK_CTL_SERVICE,TX1P,RX1P,RTS1P,CTS1P}
A A
5212
5211
5210
I2C BUS 2231 I264 5209
2208 B13 7202-B I14
RSTN_DVIO
3
VDD_CORE
RSTN_BE
5207 I265 100n 2209 B12 7202-D G14
+3V3 HW version 2 OPTION
2210 B14 7203 B14
100MHZ 7201 2202 control GNDD
1
2211 H3 7204 I9
3201
3212
1K5
1K5
M24C64 +3V3 FMN 5202
8 100n 2212 H3 F214 C11
1 1200 VDD_RGB
VCC 5201 2213 H3 F247 C10
10K
E0 GNDD
10K
10K
3209
2 VDD_YCC
10K 2214 H3 F248 C10
VDD_STI
VDD_STI
E1 3216 5203 7203
3215
3220
3219
I229
OPTION
VDD_PLL 2215 H4 F249 C11
10K
3242 10K
3244 10K
10K
3 5 3205 LF25C
E2 SDA OPTION 10K 5204 5205
I266 2216 H4 F250 C11
6 100R 3233 GNDD VDD_PCM +3V3
3238
3240
OUT IN
SCL GNDD I267 GND 100MHZ 2217 H4 F264 C6
2209
2228
2205
2206
I239 7 I215 3206 10K
B WC_ B 2218 I10 F265 A11
100n 2208
VSS
VDD_STI
GNDD GNDD GNDD 100R 2219 I9
AE_ACLK_OEn
2230
2210
100n
4u7
D_PAR_D(7:0)
4
100n
100n
100n
100n
NVRAM
ANA_WE_LV
10K
10K
RESETn_VE
2220 H8
SEL_ACLK1
MUTEN_LV
LOAD_DVN
BE_LOADN
CPUINT0
CPUINT1
Flash_Oen
2204
2207
EMI_WAIT
33p
33p
GNDD 2221 H9
RESETn
3221
3222
VDD_STI
100R
100R
2222 H9
OPTION
BCLK_CTL_SERVICE
3241 10K
3243 10K
3245 10K
10K
VDD_STI
2223 H9
3223
GNDD
2K2
33R
33R
33R
33R
33R
33R
33R
33R
3224
3239
GNDD GNDD 2224 H10
SYSTEM ADDRESS BUS
3K3
10K
5
6
7
8
5
6
7
8
2225 H10
3217
3218
3225
10K
2200
2201
2K2
22n
2226 H10
1n
VDD_STI
SYSTEM DATA BUS GNDD 10K
10K
2227 H10
F249
3226
C VDD_125
C
3200
3211
3202 7202-A
4
3
2
1
4
3
2
1
10K
2228 B12
F247
F248
3213
3214
74HCT125D
F214
AUDIO_OUT
F250
3236-D
3236-C
3237-D
3237-C
3236-B
3236-A
3237-B
3237-A
I268
I269
I237
I238
10K
I235
I234
GNDD 14 2229 H13
I201
I203
I204
I205
I206
I208
I236
GNDD
I209
I243
I241
I242
I240
2 3 AD_ACLK
I200
2230 B13
F264
AE_ACLK
I207
7200 GNDD 7 2231 A10
151
152
153
154
155
156
157
158
161
162
163
164
165
166
167
168
169
170
173
174
175
176
177
178
179
180
181
182
183
115
124
131
186
187
188
189
190
191
192
193
194
195
196
197
200
201
202
203
204
205
206
207
208
113
112
111
110
109
127
126
125
AE_ACLK_OEn 3200 C5
10
11
12
13
39
40
41
42
43
44
45
46
STI5508 GNDD
1
2
3
6
7
8
9
1
3201 A4
GNDD
IRQ0
IRQ1
CPU-DATA10
CPU-DATA11
CPU-DATA12
CPU-DATA13
CPU-DATA14
CPU-DATA15
IRQ2
CPU-DATA8
CPU-DATA9
CPU-WAIT
RESET
PIO0-0
PIO0-1
PIO0-2
PIO0-3
PIO0-4
PIO0-5
PIO0-6
PIO0-7
PIO1-0
PIO1-1
PIO1-2
PIO1-3
PIO1-4
PIO1-5
PIO2-0
PIO2-1
PIO2-2
PIO2-3
PIO2-4
PIO2-5
PIO2-6
PIO2-7
PIO3-0
PIO3-1
PIO3-2
PIO3-3
PIO3-4
PIO3-5
PIO3-6
PIO3-7
PIO4-0
PIO4-1
PIO4-2
PIO4-3
PIO4-4
PIO4-5
PIO4-6
PIO4-7
CPU-ADR1
CPU-ADR2
CPU-ADR3
CPU-ADR4
CPU-ADR5
CPU-ADR6
CPU-ADR7
CPU-ADR8
CPU-ADR9
CPU-ADR10
CPU-ADR11
CPU-ADR12
CPU-ADR13
CPU-ADR14
CPU-ADR15
CPU-ADR16
CPU-ADR17
CPU-ADR18
CPU-ADR19
CPU-ADR20
CPU-ADR21
PWM1
TRIGGER-OUT
TCK
TDI
TDO
TMS
TRST
I251
TRIGGER-IN
VDD-PCM 48 3202 C12
VDD_PCM
3203 E13
3204 E13
D VSS-PCM 49
D 3205 B4
GNDD 3206 B4
VDD-PLL 122
I252 3207 I13
148 CPU-DATA7
VDD_PLL 3208 F1
147
146
CPU-DATA6
CPU-DATA5
3209 A8
SYSTEM I202
145 CPU-DATA4 MEMORY interface PORT 0 I/O PORT 1 I/O PORT 2 I/O PORT 3 I/O PORT 4 I/O JTAG IRQ VSS-PLL 123 3211 C11
144 CPU-DATA3 USE GNDD 3212 A5
143 CPU-DATA2
142 CPU-DATA1 DAC-PCMOUT1 53 I218 3213 C6
141 CPU-DATA0
SYSTEM CONTROL I211 3214 C6
E 138 CPU-RAS1
DAC-PCMOUT2 54
E 3215 B10
130 CPU-RW DAC-SCLK 51 I254 3227
I255 3216 B8
128 CPU-BE0 AC3 DAC-PCMOUT0 52 3203 22R
129 CPU-BE1
LPCM AUDIO DAC-PCMCLK 55 I256 3228 22R 3217 C7
139 CPU-CAS0
DECODER DAC-LRCLK 56 I257 22R
140 CPU-CAS1 uP ST20cpu MPEG1/2 SPDIF-OUT 57 I258 3204 3218 C7
134 CPU-CE1
100R 3219 B11
133 CPU-CE2
132 CPU-CE3 3220 B10
CSn 3221 B6
135 CPU-CE0 ADC-SCLK 103 I210 3234-D 4 5 4K7
117 CPU-OE ADC-LRCLK 104 I212 3234-C 3 6 4K7 3222 B6
I270
118 CPU-PROCLK KARAOKE ADC-DATA 105 I213 3234-B 2 7 4K7 3223 C7
F 3208
22R
ADC-PCMCLK 106 I217 3234-A 1 8 4K7 F 3224 C12
Audio 3225 C12
GNDD
VIDEO_OUT 3226 C8
A/V/Sub R-OUT 27 I260 3227 E13
Video MPEG G-OUT 26 I261
VIDEO B-OUT 25 I262 3228 E13
demultiplexer DECODER 33 I263
ENCODER
C-OUT
CV-OUT 34 I216
3229 H12
Y-OUT 32 I224 3230 H12
BE_SERIAL
3231 I12
FRONT-END
Interface
BE_DATA_RD 16 B-DATA
BE_WCLK 20 B-WCLK 2 Subpicture Subpicture 3232 I12
G BE_BCLK
BE_FLAG
17
18
B-BCLK
B-FLAG
IS decoder G 3233 B6
BE_SYNC 19 B-SYNC 3234-A F13
BE_V4 21 B-V4 SDRAM CONTROLLER
I233 22 NRSS-OUT VDD_125 3234-B F13
ADDRESS DATA 7202-D 3234-C F13
74HCT125D
3234-D F13
SMI-CLKOUT
SMI-DATA10
SMI-DATA11
SMI-DATA12
SMI-DATA13
SMI-DATA14
SMI-DATA15
14
SMI-ADR10
SMI-ADR11
SMI-ADR12
SMI-ADR13
SMI-DATA0
SMI-DATA1
SMI-DATA2
SMI-DATA3
SMI-DATA4
SMI-DATA5
SMI-DATA6
SMI-DATA7
SMI-DATA8
SMI-DATA9
SMI-DQMU
SMI-DQML
SMI-CLKIN
V-REF-RG
SMI-ADR0
SMI-ADR1
SMI-ADR2
SMI-ADR3
SMI-ADR4
SMI-ADR5
SMI-ADR6
SMI-ADR7
SMI-ADR8
SMI-ADR9
V-REF-YC
VDD-RGB
VDD-YCC
VSS-RGB
VSS-YCC
I-REF-RG
I-REF-YC
12 11 3235 H8
SMI-CAS
SMI-RAS
SMI-CS0
SMI-CS1
PIX-CLK
SMI-WE
Audio / Video ANA_WE_LV ANA_WE

VDD3-31
VDD3-32
VDD3-33
VDD3-34
VDD3-35
VDD3-36
VDD3-37
VDD2-51
VDD2-52
VDD2-53
VDD2-54
VDD2-55
VDD2-56
VDD2-57
VDD2-58
PWM2
PWM0
VSS10
VSS12
VSS14
VSS11
VSS15
VSS13
3236-A C10
VSS1
VSS4
VSS6
VSS8
VSS2
VSS3
VSS5
VSS7
VSS9
7
3236-B C10
decoder 13 3236-C C10
4
47
50
81
83
107
108
136
137
159
160
184
185
69
68
67
66
58
59
60
61
62
63
70
71
72
73
84
85
86
87
88
89
90
91
92
93
97
98
99
100
101
102
74
75
77
76
78
82
95
79
80
14
15
37
38
64
65
94
96
119
121
149
150
171
172
198
199
23
30
24
31
114
116
120
35
28
36
29
H GNDD GNDD
H 3236-D C10
1R
GNDD
I220
I219
I222
I221
VDD_125
3237-A C10
I225
I226
I223
I227
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
5208
+5V 3237-B C10
3235
100MHZ
3237-C C10
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
2211
2212
2213
2214
2215
2216
2217
2220
2221
2222
2223
2224
2225
2226
2227
3229
3230
2229
100n
13K
13K
5200 I244 3237-D C10
1% 1%
I245
I246
I253
I259
I231
I230
I228
I232
+3V3
100MHZ 3238 B9
3239 C9
5508_HS
5508_odd_even
7204
SYSCLK_VSM_5508
VDD_RGB
VDD_YCC
2203
4u7
LF25C 3240 B9
5206 I271
3232
3231
GNDD 7202-B
3K9
3K9
VDD_STI
+3V3 IN OUT 74HCT125D

3241 C9
100MHZ GND
I 1% 1% 14
I 3242 B9
GNDD 5 6
SDRAM Interface 3243 C9
VDD_CORE
MUTEN_LV MUTEN
2219
100n
2218
3244 B9
4u7
7
3207
10K
4
3245 C9
5200 H2
GNDD GNDD
5201 A13
5202 A13
OPTION GNDD GNDD CL 16532145_023.eps 5203 B13
211101 5204 B13
5205 B14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 5206 I9
Digital Board: AV Decoder Memory

1 2 3 4 5 6 7 8 9 10 11 12 13 14
2300 A14
SDRAM Interface 2301 A14
AV Decoder Memory 2302 A14
100n
100n
100n
100n
100n
100n
100n
SYSTEM DATA BUS I300 2303 A13
VDD_STI 2304 B8
2308
2309
2310
2303
2301
2300
2302
2305 B6
2311
4u7
SYSTEM ADDRESS BUS 2306 B6
A 7300 A 2307 B9
MT48LC4M16A2TG-7E 1 14 27 3 9 43 49 2308 A13
GNDD
GNDD VDD VDDQ
2309 A13
VDD_FLASH_H
2310 A13
VDD_FLASH_L 37 CKE BANK0
VDD_STI
CTRL ROW- DQML 15 2311 A11
5300 5302 I301
38 CLK LOGIC ADDR 2312 H7
+3V3 +3V3 DQMH 39
100MHZ 100MHZ 19 CS_ LATCH & 3300 H8
DECODER
2305
2304
3301 I8
4u7
4u7
COMMAND
DECODE
16 WE_
4300 H9
REFRESH
COUNTER
B 17 CAS_ BANK0 DQ0 2 B 4301 I9
MEMORY 5300 B5

18 RAS_ DQ1 4
GNDD 2306 GNDD 2307 ARRAY
MODE REG (4,096x256x16) DQ2 5
5302 B8
100n
7301
100n 7300 A11
7302 GNDD GNDD 20 BA0 SENSE AMPLIFIERS DQ3 7
M29W160DT 37 M29W160DT 37 ROW DQML DQMH
7301 B8
25
VCC
29 25
VCC
29 21 BA1 ADDR DQ4 8 7302 B6
A0 DQ0 A0 DQ0 MUX
24 31 24 31 23 A0 I/O GATING DQ5 10 7303-A H6
A1 DQ1 A1 DQ1 DQM DATA LOGIC 7303-B H7
23 33 23 33 24 A1 READ DATA LATCH DQ6 11
A2 DQ2 A2 DQ2 BANK WRITE DRIVERS 7303-C I6
C 22
A3 DQ3
35 22
A3 DQ3
35 25 A2 CTRL
LOGIC
DQ7 13 C 7303-D I7
ADDRESS REGISTER
21 38 21 38 26 A3 DQ8 42
A4 DQ4 A4 DQ4
20 40 20 40 29 A4 COLUMN DQ9 44
A5 DQ5 A5 DQ5 ADDR
DATA INPUT REGISTER

19 42 19 42 30 A5 COUNTER/ DQ10 45
A6 DQ6 A6 DQ6 LATCH
18 44 18 44 31 A6 DQ11 47
A7 DQ7 A7 DQ7
8 30 8 30 32 A7 DQ12 48
A8 DQ8 A8 DQ8
COLUMN
7 32 7 32 33 A8 DQ13 50
A9 DQ9 A9 DQ9 DEDCODER
D 6
A10 DQ10
34 6
A10 DQ10
34 34 A9 DQ14 51 D
5 36 5 36 22 A10 DQ15 53
A11 DQ11 A11 DQ11
4 39 4 39 35 A11
A12 DQ12 A12 DQ12
3 41 3 41 VSSQ VSS NC
A13 DQ13 A13 DQ13
6 12 46 52 28 41 54 36 40
2 43 2 43
A14 DQ14 A14 DQ14
1 45 1 45
A15 DQ15|A-1 A15 DQ15|A-1 GNDD
48 48
A16 A16
E 17
A17
17
A17
SDRAM E
16 16
A18 14 A18 14
9 9
A19 A19
15 13 15 13
NC
NC
RB_ RB_
26 26
ROML_CEn E_ 10 ROMH_CEn E_ 10
I302 28 I303 28
G_ G_
11 11
W_ W_
F I304 12
RP_
VSS1 12
RP_
F
VSS2
VSS1
VSS2
47 47
BYTE_ BYTE_
VDD_FLASH_L VDD_FLASH_H
27 46 27 46
FLASH 1 GNDD FLASH 2 GNDD
G SYSTEM CONTROL G
{EMI_RWn,FLASH_OEN,EMI_CE2n,EMI_CE3n}
VDD_FLASH_L
VDD_FLASH_L
I306
2312
7303-A
74LVC00AD 14 7303-B 100n 4300
1 74LVC00AD 14 GNDD
3 4 OPTION
I307
H 2
5
6 3300
ROMH_CEn
H
47R
7
7
GNDD
I305
I308
GNDD
VDD_FLASH_L
VDD_FLASH_L
7303-D 4301
7303-C 74LVC00AD 14
74LVC00AD 14 12 OPTION
I309 3301
9 11
8 13 ROML_CEn
I 10 47R I
7
7
GNDD
GNDD
CL 16532145024.eps
221101
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Digital Board: Video Encoder, Empress

1 2 3 4 5 6 7 8 9 10 11 12 13 14
D_EMPRESS(15:0)
2402 A1
2403 A1
Video Encoder Empress SMA(17:0) 2404
2405
B11
B11
SMD(15:0)
2406 B11
2407 B11
{SM_WEN,SM_OEN,SM_CS0N,SM_CS3N,SM_UBN,SM_LBN}
I410 5402 2408 B11
A 100MHZ
+3V3
A 2409 B11
100n
100n
2410 B11
2444
4u7
2411 A12
2402
2403
100n
100n
100n
100n
100n
100n
100n
GNDD
2412 I13
2411
4u7
2413 I13
2404
2405
2406
2407
2408
2409
2410
VDD_EMP_CORE VDD_EMP 2414 I13
GNDD 2415 I12
5400
7401 I412 I413 +3V3 2416 I12
100MHZ
33 11 K6R4016V1CT
7402 2417 I12
2443
7403
22p
2418 I12
B MT48LC4M16A2TG-7E
B
128
184
183
132
131
205
195
185
171
161
153
143
133
119
109
101
VCC 17 49 43 9 3 27 14 1 GNDD
80
79
28
27
91
81
67
57
49
39
29
SAA6752HS
5
WE_ 194 2419 I12
VDDAOSC
VDDCO8
VDDCO7
VDDCO6
VDDCO5
VDDCO4
VDDCO3
VDDCO2
VDDCO1
VDDP19
VDDP18
VDDP17
VDDP16
VDDP15
VDDP14
VDDP13
VDDP12
VDDP11
VDDP10
VDDP9
VDDP8
VDDP7
VDDP6
VDDP5
VDDP4
VDDP3
VDDP2
VDDP1
SM-D0 OPTION
6 192 VDDQ VDD
CS_ 189
SM-D1 2420 I12
SM-D2
41 187 206 BANK0 CKE 37 2421 I12
OE_ SM-D3 SM-A0
15 DQML CTRL
180 203 ROW-
39 178
SM-D4 SM-A1
201 ADDR LOGIC CLK 38 3404 2422 I11
IO1 LB_ SM-D5 SM-A2
39 DQMH
7 175
SM-D6 SM-A3
199
LATCH & 1R 2423 I11
40 173 198 CS_ 19
IO2 UB_ SM-D7 SM-A4 DECODER 2424 I11
174 169
COMMAND
8
DECODE
SM-D8 SM-A5 WE_ 16
IO3
177 167 2425 I11
REFRESH
SM-D9 SM-A6
COUNTER
9 1 179 164
A0 186
SM-D10 SM-A7
162 2 DQ0 BANK0 CAS_ 17 2426 I11
IO4 2 SM-D11 SM-A8
188 159 2427 I11
C 10 A1 SM-D12
EMPRESS SM-A9 MEMORY
C

191 160 4 DQ1 RAS_ 18
IO5 3 193
SM-D13 SM-A10
163 ARRAY 2428 I11
13 A2 SM-D14 SM-A11
196 165 5 DQ2 (4,096x256x16) REG MODE
2429 I10
IO6 4 172
SM-D15 SM-A12
168
14 A3 158
SM-WEN SM-A13
170 7 DQ3 SENSE AMPLIFIERS BA0 20 2430 I10
IO7 5 SM-OEN SM-A14 ROW
15 A4
208
197
SM-CS0_ SM-A15
202
204 8 DQ4
DQMH DQML
ADDR BA1 21 2431 I10
IO8 18 SM-CS3N SM-A16
2432 I3
16 155 207 MUX
A5 154
SM-UB_ SM-A17 10 DQ5 A0 23
IO9 19 SM-LB_
I/O GATING
DQM DATA LOGIC
2433 I3
29 A6
IO10
50
SD-DQ0 SD-A0
94 11 DQ6 READ DATA LATCH
BANK
A1 24 2434 I3
20 52 97 WRITE DRIVERS
30 A7 55
SD-DQ1 SD-A1
99 13 DQ7 CTRL A2 25 2435 I3
IO11 21 58
SD-DQ2 SD-A2
98 LOGIC 2436 I3
ADDRESS REGISTER
31
D IO12
A8
22
60
63
SD-DQ3
SD-DQ4
SD-A3
SD-A4
95
93
42 DQ8 A3 26 D 2437 I3
32 A9 SD-DQ5 SD-A5 COLUMN
65 90 44 DQ9 A4 29 2438 I3
IO13 23 SD-DQ6 SD-A6 ADDR
68 88
DATA INPUT REGISTER

35 A10 SD-DQ7 SD-A7 COUNTER/ 2439 I2
66 85 45 DQ10 A5 30
IO14 24 SD-DQ8 SD-A8 LATCH
36 A11
64
SD-DQ9 SD-A9
84 2440 I2
61 92 47 DQ11 A6 31
37
IO15 25 59
SD-DQ10 SD-A10
87 2441 I2
A12 SD-DQ11 SD-A11
48 DQ12 A7 32
IO16 26
56
SD-DQ12 SD-A12
89 2442 I2
54 83
38 A13 SD-DQ13 SD-A13 COLUMN 2443 B13
51 50 DQ13 A8 33
27 SD-DQ14 DEDCODER
A14
48
SD-DQ15 SD-CSN
82
51 DQ14 A9 34
2444 A1
104 76
42 107
SD-DQ16 SD-CKE
74 2446 H9
E 28
NC A15
43
110
112
SD-DQ17
SD-DQ18
SD-CLK
SD-CASN
73
75
53 DQ15 A10 22 E 3400 G9
GNDD A16 115
SD-DQ19 SD-RASN
71 A11 35 3401 G9
SD-DQ20 SD-WEN
44
A17
117
120
SD-DQ21 SD-DQM0
70
69
NC VSS VSSQ 3402 G13
SD-DQ22
VSS 122
SD-DQM1
102
40 36 I409 54 41 28 52 46 12 6 3403 G4
121
SD-DQ23 SD-DQM2
100
I400
34 12 3404 B13
I401
SDRAM
SD-DQ24 SD-DQM3
118
SRAM GNDD
116
113
SD-DQ25
SD-DQ26
SD-DQ27 YUV0
12 GNDD
A_EMPRESS(13:0)
3405
3406
G4
H10
111 13
SD-DQ28 YUV1
108
SD-DQ29 YUV2
14 3407 H9
106 15 {SD_CLKE,SD_CLK,SD_CSN,SD_WEN,SD_CASN,SD_RASN,SD_DQM0,SD_DQM1}
103
SD-DQ30 YUV3
16
3408 G8
F MPEG2 VIDEO
SD-DQ31 YUV4
YUV5
17
18
F 3409 G8
YUV6 3410 G8
VE_DATA(0)
VE_DATA(1)
36
37
PDO0 YUV7
19
DIGITAL VIDEO(CCIR656) 4406 F13
VDD_EMP PDO1
VE_DATA(2) 38 11 VIP_IDQ
PDO2 IDQ I414 I415 4409 G12
VE_DATA(3) 40
PDO3 HSYNC
21 4406 VIP_HS
VE_DATA(4) 41
PDO4 VSYNC
22
VIP_VS 5400 B12
VE_DATA(5) 42 23
PDO5 FID VIP_FID_FF 5402 A2
3405
3K3
VE_DATA(6) 43 24
PDO6 VCLK1 VIP_ICLK
VE_DATA(7) 45
PDO7 VCLK2
30
I402 I2C BUS 5403 H1
35 146 3400 SCL 5404 I10
VE_DTACKn PDOVAL SCL
100R
I404
46
PDIOCLK SDA
145 3401 SDA 7401 B2
31 47 100R
G VE_DSn
I405 32
PDOAV
PDIDS
I2CADDRSEL
I416 3402 G 7402 B12
I406
33
PDOSYNC VDD_EMP 7403 B8
2 3408 22R 10K
156
SDATA1
3 3409 22R AE_DATAI 7404 H2
EMPRESS_IRQn H-IRF SCLK1 AE_BCLK
4409
4 3410 22R OPTION
152
SWS1 AE_WCLK
I407 TXD
3403
AE_DATAO
10K
151 6
EMPRESS_BOOT 150
RXD SDATA2
7 AE_BCLK_VSM
VDD_EMP CTSN SCLK2
AE_WCLK_VSM
149 8
RTSN SWS2
ACLK
9
ACLK_EMP GNDD AUDIO ENCODER DATA STREAM BUS
127
VDD_EMP XTALO
126
I403 3406
XTALI SYSCLK_EMPRESS
141
H 142
144
TEST0
TEST1 EXTCLK
123
3407 47R
H
140
TEST2
147
180R GNDD
CLKOUT RESETN RESETn_VE
JTAG3_TD_VIP_TO_VE
2446
7404 I408 137
TDO TDI
134
135 JTAG3_TMS
LF25C TMS
136 JTAG3_TCK 1n
5403 VDD_EMP_CORE
TCLK
JTAG3_TRSTn GNDD
139
+3V3
100MHZ IN GND OUT VDD_EMP_CORE TRSTN
JTAG_CHAIN3
VSSAOSC
5404
VSSCO1
VSSCO2
VSSCO3
VSSCO4
VSSCO5
VSSCO6
VSSCO8
VSSCO7
VSSP10
VSSP11
VSSP12
VSSP13
VSSP14
VSSP15
VSSP16
VSSP17
VSSP18
VSSP19
VSSP20
VDD_EMP
VSSP1
VSSP2
VSSP3
VSSP4
VSSP5
VSSP6
VSSP7
VSSP8
VSSP9
VDD_EMP
100n
100n
100n
100n
100n
100n
100n
100n
100n
+3V3
100MHZ
2442
100n
4u7
2441
1
10
20
34
44
53
62
72
86
96
105
114
124
138
148
157
166
176
190
200
25
26
77
78
129
130
182
125
181
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
I I
2440
2439
2438
2437
2436
2435
2434
2433
2432
2431
4u7
2430
2429
2428
2427
2426
2425
2424
2423
2422
2421
2420
2419
2418
2417
2416
2415
2414
2413
2412
GNDD
GNDD MPEG2 / AC-3 encoder
GNDD CL 16532145_025.eps
221101
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Digital Board: VIP CVBS Y/C Video Input

1 2 3 4 5 6 7 8 9 10 11 12 13
1500 H3
2500 C4
VIP CVBS Y/C Video Input 5500 I508

2501
2502
2503
D2
D2
E2
+3V3
2504 E2
100n
100MHZ VDDA1A_7118
4u7
I509 5507 2505 E2
2517
+3V3
2506 E2
2514
100MHZ
VDDA_7118
100n
100n
100n
100n
100n
A A 2507 E2
4u7
+3V3
2508 E2
2531
2534
2538
2527
2543
2539
5501 I510
+3V3
GNDD 2509 E2
680R 100MHZ VDDA2A_7118 I511 5506 2510 H3
3504
VDD_LVC32
+3V3
2511 H4
100n
5502 I513 100MHZ
4u7
100n
100n
100n
100n
100n
100n
100n
GNDD
+3V3 2512 F11
2518
4u7
100MHZ VDDA3A_7118
100n
4u7
7501-B 2513 B3
2513
2536
2526
2524
2522
2529
2533
2537
2540
2520
I540 74LVC32AD 14
4 2514 A5
2516
6 2515 C3
VIP_IGP1 5
B 7504 GNDD B 2516 B5
BAT54 COL
BC847B GNDD 2517 A4

7
5503 I514 GNDD I515 5505
6500
+3V3 +3V3 2518 B3
100n
100MHZ 100MHZ
VDDI_7118
100n
100n
100n
100n
100n
100n
VDDA4A_7118
GNDD
4u7
2519 B3
4u7
2519
GNDD 2520 B4
2541
2515
2535
2525
2523
2521
2528
2532
I543 2521 C7
5508 I518 2522 B7
+3V3
VDDE_7118
100MHZ VDDX_7118 2523 C7
100n
GNDD 2500
4u7
RESETn GNDD +3V3
680R
2524 B7
3513
2565
150p
2542
1n I2C BUS
C I503 3500 100R I500 SDA C 2525 C7
2530
I502 3502 GNDD 2544
I504 3501 2526 B7
OPTION 100R SCL
I506
4500
2K2 I501 100n 2527 A6
VIP_FB GNDD I507 7502-A
7500 GNDD 4501
VIP_INT 74HC74D 14 GNDD
2528 C7
SAA7118E
M11
2529 B7
D13
C14
C12
C13
N13
N14
D12
H12
C10
P13
A13
B12
A12
B13
B14
SCL P10
F12
+3V3
J12
M7
M6
M3
M4
M8
M5
SDA M9
3503
G2
N6
N8
N7
N4
C3
C4
N1
N2
N3
H4
D4
C5
C9
C8
INT_A N9
P8
P7
P6
P5
P3
B2
P2
B3
E2
K4
P9
F4
L7
L6
L1
J1
1K
4 5 2530 C5
EXMCLR
CLKEXT
ADP0
ADP1
ADP2
ADP3
ADP4
ADP5
ADP6
ADP7
ADP8
CE
RESON
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
RES1
RES2
RES3
RES4
RES5
RES6
RES7
RES8
RES9
RES10
RES11
RES12
RES13
VXDD
VDDA4A
VDDA3A
VDDA2A
VDDA1A
VDDA VDDE VDDI +3V3
3 2531 A6
7502-B
GNDD AD-PORT 74HC74D 14 2532 C8
CONTROL
IIC REGISTER MAP 1ST TASK IIC REG MAP SCALER 2
M13 I512 FSW
+3V3 2533 B7
2ST TASK IIC REG MAP SCALER 1 6 10 9
CVBS_Y_IN_A 2534 A6
D J2 A|11 IGP1 K13 VIP_IGP1
D
ANALOG1 ANALOG1 ANALOG1 ANALOG1
FAST VIP_VS VIP_FID_FF

+ ADC1
OUTPUT FORMATTER I-PORT

K1 A|12 IGP0 L14
CVBS_OUT_B_VIP
CVBS_Y_IN_B 11 2535 C7
K2 A|13 SWITCH SCALER EVENT CONTROLLER IGPV K14 VIP_VS DIGITAL VIDEO(CCIR656) VIP_VS
DECODER OUTPUT CONTROL
CVBS_Y_IN_C L3 A|14 DELAY IGPH K12 VIP_HS 7 2536 B7

GNDD 2501 100n I516 K3 A|1D IDP0 G14 12
ANALOG INPUT CONTROL
2537 B7
HORIZONTAL FINE-
VERTICAL SCALING
Y
LINE FIFO BUFFER
(PHASE-) SCALING
C_IN_VIP G4 A|21 R IDP1 G12
COMP CB GNDD
FIR-PREFILTER
G
GNDD 2502 100n I517 G3 13 8
+ ADC1
2538 A6
VIDEO FIFO
BCS-SCALER
A|22
PRESCALER
IDP2 H11
G_IN_VIP H2 A|23
B PROC CR +3V3
S IDP3 H14
Y_IN_VIP J3 A|24
RAW
IDP4 H13 2539 A6
2503 100n I519 H1 A|2D C CHROM CB YCBCR IDP5 J14 7 2540 B7
2504 100n I520 E3 A|31
PROC
CR IDP6 J13
GNDD 2505 100n I521 F2 2541 B8
+ ADC1
A|32 IDP7 K11

B_IN_VIP F3 A|33 COMB GNDD
U_IN_VIP
ICLK M14 2542 C4
YCBCRS
G1 A|34 FIL
YCBCR
IDQ L13
2506 100n I522 F1 A|3D TEXT 2543 A6
E GNDD
2507 100n I523 B1
2508 100n I524 D2
A|41
Y
S
LUM Y RAW FIFO
ITRDY
ITRI
N12
L12 I551 3505 22R
VIP_ICLK E 2544 C11
A|42 PROC CBCR VBI DATA
+ ADC1
R_IN_VIP D1 A|43 S SLICER ASCLK N11

I525 VIP_IDQ 2545 G2
AUDIO
V_IN_VIP E1 A|44 S ALRCLK P12
SYNC VIDEO/TEXT I527 2565 C1
CLK
2509 100n I528 D3 A|4D CBCR AMCLK P11
I530
GNDD BOUNDARY ARBITER
VIDEO XTAL X-PORT H-PORT SCAN
AMXCLK M12
I531
VDD_LVC32 3500 C7
M1 AOUT GPO
I526
VIP ANALOG VIDEO INPUT
I532 CLK 5504 3501 C7

AGNDA
XTOUT
+3V3
TRSTN
AGND
RTCO
XTALI
XRDY
VXSS
HPD0
HPD1
HPD2
HPD3
HPD4
HPD5
HPD6
HPD7
XPD0
XPD1
XPD2
XPD3
XPD4
XPD5
XPD6
XPD7
XCLK
RST0
RST1
XTAL
LLC2
3502 C3
XTRI
XDQ
XRH
TDO
TMS
XRV
TCK
LLC
VSSA
TDI
VSSE VSSI 100MHZ
GNDD
3503 C1
2512
100n
C2
L2
A4
M2
J4
H3
E4
C1
P4
N5
M10
N10
L10
A3
B4
A2
A6
A8
B8
A9
B9
A10
B10
A11
C11
A7
B7
C7
D8
B11
D14
E11
E13
E12
E14
F13
F14
G13
A5
B5
C6
B6
D6
D5
D9
D11
G11
L4
L8
L11
D7
D10
F11
J11
L5
L9
3504 A1
I533
7501-A 3505 E8
F F
DV_IN_DATA(0)
DV_IN_DATA(1)
DV_IN_DATA(2)
DV_IN_DATA(3)
DV_IN_DATA(4)
DV_IN_DATA(5)
DV_IN_DATA(6)
DV_IN_DATA(7)
I535
I537
I536
GNDD GNDD 14 74LVC32AD 3506 H7

DV_IN_HS
DV_IN_VS
Video Input 1
I505
3 GNDD 3507 F3
processor 2 3508
3509
G5
G3
3507
4K7
7
JTAG3_TD_VSM_TO_VIP
3513 C2
JTAG3_TD_VIP_TO_VE
DV_IN_CLK
GNDD GNDD 3515 H3

4500 C2
JTAG3_TRSTn
vip_error
JTAG3_TMS
JTAG3_TCK
VIP_RTS1
4501 C7
DV_IN_DATA(0:7)
GNDD
+3V3
5500 A4
I538
G G 5501 A3
I552
JTAG_CHAIN3
5502 A4
5509
3508
5503 B3
10K
3509
VDD_LVC32 5504 E11
2545 1M VDD_LVC32 5505 B8
3515
OPTION
1R
100n 7501-C 5506 A8

7503 GNDD 7501-D 74LVC32AD 14 5507 A6
I529
FXO-31FT 4 74LVC32AD 9
I553
14
I555
12 DV_IN_HS 8 5508 C4
VDDE_7118
VDD 1500 VIP_IGP1

1 3 11 10 5509 G2
TS OUT 13
OSC
H CX-11F
VIP_RTS1
7 H 6500 B1
3506
2510
2511
GND
2K2
7500 C3
18p
18p
24M576 7
2 GNDD 7501-A F11
GNDD
7501-B B2
7501-C H7
GNDD GNDD GNDD GNDD
OPTION 7501-D H6
CL 16532145_026.eps
7502-A C10
221101
7502-B D11
7503 H2
1 2 3 4 5 6 7 8 9 10 11 12 13 7504 B1
Digital Board: Analog Board Cons. Video In / Output

1 2 3 4 5 6 7 8 9 10 11 12 13 14
1600 H14 7202-C D12
ANALOG BOARD INTERFACE AUDIO IN/OUT

AUDIO ENCODER
Analog Board Cons. VIP ANALOG VIDEO INPUT
DATA STREAM BUS
AE_BCLK
I664 22
1601
1602
D14
C14
7600
7601
E6
G10
1603 E2 7602 B3
Video In / Output Y_IN_VIP
I649 2618 I660
100n
AE_WCLK
AE_DATAI
I671 21
20
2600
2601
E6
E5
7603
7604
G6
I10
I650 2613 3605 Y_IN I603 19 2602 E5 7605 I6
I651 I645 G_IN_VIP
CVBS_Y_IN_A 2608 2603 C12 7606 E10
I629 100n 1R 18
5606
A +5V +5V_Buffer
I652
100n
I661 I635 17
A 2604 C13
4u7 2609 3629 OPTION 3623 2605 E10
3609
CVBS_Y_IN_B
75R
CVBS_Y_IN AE_ACLK
2630
4u7
100n 180R 100R 16 2606 E9
CVBS_Y_IN_C I653 2629 AUDIO OUT 2607 E9
2632 I662 3625 I637 15
GNDD AD_BCLK
100n 2608 A6
100n 100R 14 2609 A6
560R
GNDD
3632
GNDD I642 3615 CVBS_OUT_B
7602 I654 13 2610 G6
U_IN_VIP
2614 I663 AD_WCLK 3635 I638
BC847B 100R
I639 12 2611 G5
100n 100R
I665 2634 I643 3636 2612 G5
I644 I655 2633 3631 I666 3637 11
CVBS_OUT_B_VIP GNDD 2613 A9
B 22n 180R
B_IN_VIP U_IN AD_DATAO
I640 10
B 2614 B9
100n 1R 100R
2615 F10
560R
3619
3638
2K2
OPTION I667 9
3604
3634
75R
AD_ACLK
2616 G9
100R I609 8
MUTEN 2617 G9
C_IN_VIP I656 2628 I647 3630 C_IN +3V3 7 2618 A9
GNDD -5V_Buffer
2619 C9
22p
22p
22p
1p
1p
100n 180R GNDD +5V 6
2603
2623
2624
2631
2604
2620 H6
I627 2635 I668 I611 5
560R
3633
V_IN_VIP 2621 I5
100n OPTION I613 4 2622 I5
C I633 2619 3
C 2623 C12
R_IN_VIP 3610 V_IN
GNDD GNDD GNDD 2
2624 C12
GNDD 100n 1R GNDD GNDD 2625 H10
OPTION 1 2626 I9
3614
75R
VDD_125 1602
2627 I9
VIDEO_OUT 7202-C 2628 C6
74HCT125D 2629 A6
14 I669 I641 GNDD
GNDD AD_SPDIF33 9 8 3600 2630 A2
{V_IN,U_IN,Y_IN,C_IN,CVBS_Y_IN}
56R 2631 C12
D 7 D 2632 A2
10 2633 B9
DV_IN_DATA(0:7) GNDD GNDD 2634 B2
1601
+5V_Buffer +5V_Buffer V_IN
I600 2635 C9
2636 H9
ANALOG BOARD INTERFACE VIDEO IN/OUT

22
DIVIO 2600 2605 3600 D13
1603 I601 21
100n 100n
U_IN 3601 E5
84816
I618 GNDD GNDD 20 3602 E6
2 1
I628 I602 19 3603 F6
E I630
4 3
5600 I621 5605 I622
Y_IN
18
E 3604 B12
6 5 7600 B_OUT 7606 3605 A10
I631 12u BC847B 12u BC847B I604 17 3606 E8
8 7 CVBS_OUT_B B_OUT_B C_IN
I632 16 3607 E9
560R
560R
560R
560R
3601
3602
3606
3607
2601
2602
2606
2607
10 9
47p
47p
47p
47p
I634 I605 15
3608 F10
3603
3608
12 11 CVBS_Y_IN
3609 A9
1K
1K
1% 1% 1% 1%
I636 14
14 13 3610 C10
16 15
I646 GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD 13 3611 G5
{R_OUT_B,G_OUT_B,B_OUT_B,C_OUT_B,CVBS_OUT_B,Y_OUT_B}
I657 I606 12 3612 G6
DV_IN_CLK
F 18 17
-5V_Buffer -5V_Buffer CVBS_OUT_B
11
F 3613 H6
20 19
DV_IN_HS
3614 C9
3620
2K2
I658
22 21 +5V_Buffer Y_OUT_B
I607 10 3615 B3
DV_IN_VS
9 3616 G8
24 23 VSM_UART2_CTSn +5V_Buffer
2615 3617 G9
I608 8
+3V3
26 25
+3V3 2610
C_OUT_B 3618 G10
GNDD 100n
GNDD 7 3619 B2
28 27
+3V3 +3V3 100n
GNDD I610 6 3620 F1
30 29 OPTION R_OUT_B
+3V3 3621 I5
5601 I623 5
G OPTION 32 31
AE_BCLK_DV
4600 AE_BCLK
I624
G_OUT
12u
7601
BC847B I612 4
G 3622 I6
AE_DATAI
4601 AE_DATAI_DV 34 33 OPTION
Y_OUT 5603 7603 G_OUT_B G_OUT_B 3623 A12
12u BC847B 3 3624 I6
560R
560R
3616
3617
2616
2617
36 35 4602 Y_OUT_B
47p
47p
AE_WCLK_DV AE_WCLK
I614 2
3625 A12
560R
560R
3611
3612
3618
2611
2612
38 37 3626 I8
47p
47p
1% 1% B_OUT_B
1K
1
3627 I9
3613
40 39 +5V
1K
+5V 1% 1%
42 41 GNDD GNDD GNDD GNDD 3628 I10
+5V +12V
I659 GNDD 3629 A6
44 43 GNDD GNDD GNDD GNDD
RESETn_DVIO 5607 I670 -5V_Buffer UART1 1600 3630 C6
-5V -5V_Buffer FMN
H UART2 46 45
-5V_Buffer 4u7 I615 H 3631 B10
INTERFACE CONTROL
+5V_Buffer IRESET_DIG 3632 B6
2636
48 47
4u7
VSM_UART2_RTSn 10
LOAD_DVN +5V_Buffer 3633 C6
ANALOG BOARD
VSM_UART1_RX
50 49
2625
VSM_UART1_TX
9
3634 B9
2620
VSM_UART2_TX 52 51 VSM_UART2_RX
8 3635 B12
100n VSM_UART1_CTSn
54 53 100n GNDD GNDD 7
3636 B2
GNDD VSM_UART1_RTSn 3637 B12
56 55 I616 6
3638 B3
5604 I625 IOn
58 57 I626
R_OUT 7604 I617 5 4600 G3
C_OUT 5602 7605 12u BC847B ANA_WE 4601 G1
I 60 59
12u BC847B
C_OUT_B
R_OUT_B
BE_FAN
I619 4
I 4602 G3
560R
560R
3626
3627
2626
2627
47p
47p
3
5600 E5
560R
560R
3621
3622
2621
2622
47p
47p
VIP_FB
3628
5601 G9
1K
1% 1% 2
3624
1K
1% 1% 5602 I5
GNDD 1
GNDD 5603 G5
GNDD GNDD GNDD GNDD GNDD
GNDD GNDD GNDD GNDD 5604 I9
-5V_Buffer CL 16532145_027.eps 5605 E9
-5V_Buffer 5606 A2
221101
5607 H9
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Digital Board: Progressive Scan

1 2 3 4 5 6 7 8 9 10 11 12 13
2700 B9 3719-A H9
2701 B8 3719-B H8
Progressive Scan 2702
2703
B9
B9
3719-C
3719-D
H8
H8
2704 B9 3720 F6
A OPTION I712
+2V5_PLL
A 2705 B8 4700 A1
4700 2706 B8 4701 B1
+5V 7703 2707 G3 4702 E2
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
LF25C
I709
1 3 5701 I711
GNDD 2708 B8 5700 B11
IN OUT
+2V5_FLI 2709 B8 5701 A3
2718
2713
2708
2701
2719
2717
2704
2703
2702
2700
GND
2712
2711
2727
2710
2709
2706
2705
2 2710 B8 5702 B6
2724
100n
2725
2726
100n
2723
4701
4u7
47u
+3V3 I700 5700
+2V5_FLI +3V3_FLI
+3V3 2711 B8 7700 B7
5702 I710 2712 B8 7701-A E1
+2V5_PLL
2720
2713 B8 7701-B C1
4u7
4u7
I705
I704
I706
B B 2714 F13 7702-A E3
2715
2716
100n
GNDD GNDD GNDD GNDD GNDD
47u
2715 B6 7702-D C3
GNDD
7700 2716 B7 7703 A2
107
158
105
114
123
137
144
151
167
111
109
112
113
42
16
54
33
63
73
84
95
51
50
41
FLI2200 GNDD 2717 B8
1
AVDD
VDD25-1
VDD25-2
VDD25-3
VDD25-4
VDD33-1
VDD33-2
VDD33-3
VDD33-4
VDD33-5
VDD33-6
VDD33-7
VDD33-8
VDD33-9
VDD33-10
VDD33-11
VDD33-12
VDD33-13
TEST0
TEST1
TEST2
TEST3
TEST4
TESTO2
TESTO1
GNDD GNDD 2718 B8
+3V3
28
R|CRIN0 2719 B8
29
+3V3 30
R|CRIN1
88 Cr_OUT(0) Cr_OUT(9:0)
2720 B11
7701-B R|CRIN2 R|CROUT0
Cr_OUT(1)
74HC74D 14
31
R|CRIN3 R|CROUT1
87
2721 E2
32
TEST TEST
86 Cr_OUT(2)
7702-D 35
R|CRIN4 POWER R|CROUT2
83 Cr_OUT(3) 2722 E3
10 9 74LVC86ADB R|CRIN5 SUPPLY INPUT OUTPUT R|CROUT3
C +3V3 12
14 36
37
R|CRIN6
R|CRIN7
R|CROUT4
R|CROUT5
82
81
Cr_OUT(4)
Cr_OUT(5) C 2723 B3
11 11 38
R|CRIN8 R|CROUT6
80 Cr_OUT(6) 2724 B2
13 39 79 Cr_OUT(7)
12 GNDD R|CRIN9 R|CROUT7
78 Cr_OUT(8)
2725 B2
R|CROUT8
Cr_OUT(9) 2726 B3
INPUT SIGNALS
7 18 77
G|YIN0 R|CROUT9
13 8 P_SCAN_YUV(7:0) GNDD 19
+3V3
P_SCAN_YUV(0) I728 20
G|YIN1
76 Yy_OUT(0)
2727 B8
G|YIN2 G|YOUT0 Yy_OUT(9:0)
G|YIN3 G|YOUT1
75 Yy_OUT(1) 3700 G11
GNDD GNDD P_SCAN_YUV(2) I730 Yy_OUT(2)
OUTPUT SIGNALS
22 72
7 G|YIN4 G|YOUT2 3701-A F11
P_SCAN_YUV(3) I731 23 71 Yy_OUT(3)
G|YIN5 G|YOUT3
G|YIN6 G|YOUT4
70 Yy_OUT(4) 3701-B F11
GNDD GNDD P_SCAN_YUV(5) I733 25 69 Yy_OUT(5)
G|YIN7 G|YOUT5
68 Yy_OUT(6) 3701-C F11
G|YIN8 G|YOUT6
D P_SCAN_YUV(7) I735 27
G|YIN9 G|YOUT7
67 Yy_OUT(7)
D 3701-D F11
66 Yy_OUT(8)
6
G|YOUT8
65 Yy_OUT(9) 3702-A G11
B|CBIN0 G|YOUT9
7
B|CBIN1 3702-B F11
8 104 Cb_OUT(0) Cb_OUT(9:0)
9
B|CBIN2 B|CBOUT0
103 Cb_OUT(1) 3702-C F11
+3V3 B|CBIN3 B|CBOUT1
Cb_OUT(2)
10
B|CBIN4 B|CBOUT2
102 3702-D F11
2722
11 101 Cb_OUT(3)
3703-A F6
+3V3
DEINTERLACER
B|CBIN5 B|CBOUT3
12
B|CBIN6 B|CBOUT4
100 Cb_OUT(4)
2721
13
B|CBIN7 B|CBOUT5
99 Cb_OUT(5) 3703-B F6
100n 14 98 Cb_OUT(6)
7701-A
7702-A GNDD 15
B|CBIN8
B|CBIN9
B|CBOUT6
B|CBOUT7
97 Cb_OUT(7) 3703-C F6
100n 74LVC86ADB 14 GNDD Cb_OUT(8)
74HC74D
94
3703-D F6
LINE DOUBLER
B|CBOUT8
14 GNDD 1 3 93 Cb_OUT(9)
I701
3 HSYNCREFI B|CBOUT9
3704-A F6
E +3V3
4 5 2
VS_IN 4
5
VSYNCREFI
FIELDIN CCLKO
116
I703
E 3704-B F6
117
YCLKO
3 7 D_ADDR(0) 3710-C 6 3 33R 136
ADDR0 VREFO
89 3704-C F6
5508_HS D_ADDR(1) 3710-D 5 4 33R 135 90
2 D_ADDR(2) 3709-A 8 1 33R 134
ADDR1 HREFO
91
3704-D F6
OPTION ADDR2 VSYNC|CREFO VSOUT
5508_odd_even I702
D_ADDR(3) 3709-B 7 2 33R 133
ADDR3 H|CSYNCO
92
HSOUT
3705 G11
1 6 4702 GNDD D_ADDR(4) 3709-C 6 3 33R 131 108
+3V3 D_ADDR(5) 3709-D 5 4 33R 130
ADDR4 FSYNC
110
I708 3706 G11
D_ADDR(6) ADDR5 FILM I707
3704-A 8 1 33R 129
ADDR6
3707 H11
7 GNDD D_ADDR(7)
D_ADDR(8)
D_ADDR(9)
3704-B 7
3704-C 6
3704-D 5
2
3
4
33R
33R
33R
128
127
126
ADDR7
ADDR8
ADDR9
SDRAM RESETB
IFORMAT0
OE
49
53
58
I717
I719
3702-B 7
3701-A 8
2
1
4K7
4K7
+3V3_FLI
+3V3_FLI
2714
RESETn 3708
3709-A
H11
E6
GNDD D_ADDR(10) 3720 125 57 I718 3702-D 5 4 4K7
ADDRESS BUS ADDR10 IFORMAT1 +3V3_FLI 1n 3709-B E6
I725
F 33R 118
IFORMAT2
56
61 I722
3702-C 6
3701-D 5
3
4
4K7
4K7
+3V3_FLI
+3V3_FLI GNDD F 3709-C F6
3703-D
3703-C
5
6
4
3
33R
33R
119
120
MEMCLKO
WEN INTERFACE CONTROL OFORMAT0
OFORMAT1
60
59
I721
I720
3701-C 6
3701-B 7
3
2
4K7
4K7
GNDD 3709-D F6
RASN OFORMAT2 +3V3_FLI
CONTROL BUS 3703-B 7 2 33R 121 45 3710-A G6
I715 3712 I714 3703-A 8 1 33R 122
CASN
BSEL
SIGNALS DADDR0
DADDR1
44
3710-B G6
CLK4 MODE
46
GNDD
D_DATA(0) 3710-B 7 2 33R 139 47 I723 3705 100R 3710-C E6
33R D_DATA(1) 3710-A 8 1 33R 140
DATA0
DATA1
SIGNALS SDA
SCL
48 I724 3706 100R
SDA
SCL
I2C BUS
3710-D E6
2707
D_DATA(2)
10p
OPTION 3711-D 5 4 33R 141

DATA2 PIXCLK
40
SYSCLK_PROGSCAN
D_DATA(3) 3711-C 6 3 33R
D_DATA(4)
142
DATA3 POWER GND N|P|IN|OUT
62
I716
3711-A G6
3711-B 7 2 33R 143 52 3702-A 8 1 4K7 +3V3_FLI
D_DATA(5) 3711-A 8 1 33R 146
DATA4
DATA5
NOMEM
3711-B G6
D_DATA(6) 3713-D 5 4 33R
D_DATA(7)
147
DATA6 3711-C G6
G GNDD
D_DATA(8)
3713-C 6 3 33R 148
DATA7 +3V3_FLI +3V3_FLI G 3711-D G6
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
DATA24
DATA25
DATA26
DATA27
DATA28
DATA29
3713-B 7 2 33R 149
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
DATA8
AVSS
D_DATA(9)
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
WE 3713-A 8 1 33R 150
DATA9 3712 F3
3713-A G6
153
154
155
156
157
160
161
162
163
164
165
166
169
170
171
172
173
174
175
176
2
17
34
55
64
74
85
96
106
115
124
132
138
145
152
159
168
43
RAS
3700
3714
4K7
4K7
CAS
I713 3713-B G6
3713-C G6
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
33R
I726
I727
BA 3713-D G6
GNDD
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
3714 G11
3715-A H7
3707
3708
3715-B H7
4K7
4K7
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
5
6
7
8
H H 3715-C H7
3715-D
3715-C
3716-D
3716-C
3717-D
3717-C
3718-D
3718-C
3719-D
3719-C
3715-B
3715-A
3716-B
3716-A
3717-B
3717-A
3718-B
3718-A
3719-B
3719-A
OPTION OPTION
3715-D H7
3716-A H8
GNDD GNDD 3716-B H8
3716-C H8
3716-D H7
D_DATA(10)
D_DATA(11)
D_DATA(12)
D_DATA(13)
D_DATA(14)
D_DATA(15)
D_DATA(16)
D_DATA(17)
D_DATA(18)
D_DATA(19)
D_DATA(20)
D_DATA(21)
D_DATA(22)
D_DATA(23)
D_DATA(24)
D_DATA(25)
D_DATA(26)
D_DATA(27)
D_DATA(28)
D_DATA(29) 3717-A H8
3717-B H8
3717-C H8
I DATA BUS I 3717-D H8
3718-A H8
3718-B H8
CL 16532145_028.eps 3718-C H8
221101 3718-D H8
1 2 3 4 5 6 7 8 9 10 11 12 13
Digital Board: Progressive Scan

1800 D15 2806 B3 2812 B3 2818 C7 2824 C14 2832 E12 3800 G4 3806 B8 3812 D14 3818 E14 3824 F14 5801 B12 5807 E12 7802 B14
2800 B14 2807 B3 2813 B3 2819 C8 2826 D11 2833 E12 3801 C14 3807 C14 3813 D13 3819 E14 3825 F14 5802 B12 5808 E12 7803-A D14
2802 B2 2808 B2 2814 C11 2820 C9 2827 D12 2834 F14 3802 B8 3808 C14 3814 D13 3820 E10 3826 F11 5803 D12 5809 F12 7803-B E14
2803 B2 2809 B3 2815 C12 2821 C14 2828 D12 2835 F10 3803 C13 3809 D10 3815 E10 3821 E13 3827 F11 5804 D12 5810 B8
2804 B2 2810 B3 2816 C12 2822 C9 2829 D14 2836 G10 3804 C13 3810 D6 3816 D14 3822 E13 3828 G4 5805 D12 7800 B1
2805 B2 2811 B3 2817 F12 2823 C9 2831 E11 2837 B8 3805 C8 3811 D11 3817 E11 3823 F11 5800 B12 5806 E12 7801 C6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Progressive Scan
A A
+3V3_FLI DATA BUS

2804 100n
2803 100n
2802 100n
2805 100n
2808 100n
2809 100n
2806 100n
2807 100n
2810 100n
2811 100n
2812 100n
2813 100n
5810 I819 +5V
+3V3 +3V3_DD
B GNDD I2C BUS B
+3V3_ANA
+3V3_ANA
GNDD
2837
4u7
7800 2800
I871 I872 I800
MT48LC2M32B2TG 81 75 55 49 41 35 9 3 43 29 15 1
SCL
SDA
CONTROL BUS 100n
67 VDDQ VSS 2 D_DATA(0) GNDD
+3V3_FLI CKE DQ0
5800 5801 5802 I801 7802
100R
100R
3802
3806
CLK4 68 4 D_DATA(1) RESETn GNDD 3 5
CLK DQ1 AD8061
6u8 10u 2u2 I802 I821
2822 100n
2823 100n
GNDD 20 5 D_DATA(2) 1 3801
CS_ DQ2
3805
2818
2819
100n
2820
100n
4K7
1n
WE I868 17 7 D_DATA(3) 4 75R
WE_ DQ3
3804
3803
2814
2815
2816
1K2
1K2
8p2
22p
18p
2
CAS I869
2821
220p
18 8 D_DATA(4)
CAS_ DQ4
I873
I874
I875
C RAS I870 19
RAS_ DQ5
10 D_DATA(5)
7801
ADV7196A
I876
GNDD 3807 C
GNDD GNDD GNDD GNDD OPTION
11 D_DATA(6) 40 30 31 41 1 12 24 35 1K
16 DQ6 GNDD GNDD GNDD GNDD GNDD +5V 3808
DQM0 13 RESET SCL SDA ALSB VDD VAA
D_DATA(7)
71 DQ7 I824 29 HSYNC_|SYNC_ 1K
2 2824
DQM1 74 D_DATA(15) HSOUT I C MPU PORT GNDD GNDD
DQ8 I825 I877 I878
28 28 VSYNC_|TSYNC_ 1800
DQM2 76 D_DATA(14) VSOUT TIMING 100n
59 DQ9 3810 27 DV|CLKOUT GENERATOR FMN
GNDD
DQM3 77 D_DATA(13) Yy_OUT(9:0) +3V3_DD I806 1
DQ10 10K SYNC 5803 5804 5805 3 7803-A
8
ANALOG BOARD
GNDD 79 D_DATA(12) SYSCLK_PROGSCAN 25 CLKIN GEN 3809 AD8062 2
I836 DQ11 6u8 10u 2u2 I807 3812 I822
BA 22 1
D I814 23
BA0
DQ12
80 D_DATA(11)
I826
1K2
75R
3 D
Yy_OUT(0) 2 Y0 SHARPNESS GNDD 2
BA1 3811
3813
3814
2826
2827
2828
GNDD 82 D_DATA(10)
1K2
1K2
4
8p2
22p
18p
ADDRESS BUS DQ13 I827 FILTER CTRL 4
3 Y1
2829
220p
Yy_OUT(1)
D_ADDR(0) 25 83 D_DATA(9) & 1K2 5
A0 DQ14 I828 ADAPTIVE I879 3816
Yy_OUT(2) 4 Y2 GNDD
D_ADDR(1) 26 85 D_DATA(8) FILTER CTRL GNDD OPTION 6
A1 DQ15 Yy_OUT(3) I829 5 Y3 1K
D_ADDR(2) 27 31 D_DATA(22) 11-BIT DAC-A|Y 34 3818
GNDD GNDD GNDD GNDD GNDD 7
D_ADDR(3) 60
A2
A3
SDRAM DQ16
DQ17
33 D_DATA(23)
Yy_OUT(4) I830
I831
6 Y4
TEST-
LUMA
99 AF
SYNC
DAC I808
3815
1K2
1K
Yy_OUT(5) 7 Y5 PATTERN GNDD GNDD
D_ADDR(4) 61 34 D_DATA(24) CGMS +5V
I832 I809 GNDD I880 GNDD
A4 DQ18 Yy_OUT(6) 8 Y6 GENERATOR MACRO- 11-BIT DAC-B 36 3817 I881
E D_ADDR(5) 62
A5 DQ19
36 D_DATA(25)
I833
& VISION DAC 1K2 5806 5807 5808 I810 7803-B
E
Yy_OUT(7) 9 Y7 5 8
D_ADDR(6) 63 37 D_DATA(26) DELAY 2X GNDD AD8062
A6 DQ20 I834 6u8 10u 2u2 I811 3819
Yy_OUT(8) 10 Y8 & CHROMA INTER- 7
D_ADDR(7) 64 39 D_DATA(27) POLATION 11-BIT DAC-C 32
A7 DQ21 Yy_OUT(9) I835 11 Y9 GAMMA 4:2:2 TO 4:4:4 6 75R I823
DAC
Cr_OUT(9:0) I812
3821
3822
D_ADDR(8) 3820
2831
2832
2833
65 40 D_DATA(28) ( 99AF )
1K2
1K2
8p2
22p
18p
A8 DQ22 I846 4
Cr_OUT(0)
2834
220p
14 CR0 CORRECTION
D_ADDR(9) 66 42 D_DATA(29) 1K2
A9 DQ23 I803 I882 3824
Cr_OUT(1) 15 CR1 GNDD
D_ADDR(10) 24 45 D_DATA(21) 3823 GNDD OPTION
A10 DQ24 Cr_OUT(2) I805 16 CR2 1K
CHROMA 1K2 3825
47 D_DATA(20) GNDD GNDD GNDD GNDD GNDD
14 DQ25 Cr_OUT(3) I815 17 CR3 4:2:2 TO 4:4:4
F NC1 48 D_DATA(19) VREF 39
I883 2835 GNDD +3V3_ANA
I818 5809 1K F
( 99AF )
21 DQ26 Cr_OUT(4) I816 18 CR4 +3V3 GNDD GNDD
NC2 50 D_DATA(18) DAC RSET 38 100n
DQ27 Cr_OUT(5) I817 CTRL I813
2817
30 19 CR5
47u
NC3 51 D_DATA(17) BLOCK COMP 37 3826 3827
57 DQ28 Cr_OUT(6) I847 20 CR6
NC4 53 D_DATA(16) 2K2 270R
69 DQ29 Cr_OUT(7) I848 21 CR7 GNDD
NC5 54 I851
70 DQ30 Cr_OUT(8) I849 22 CR8 GNDD
NC6 56 I852
DQ31 Cr_OUT(9) I850 I884 2836
73 23 CR9
NC7 +3V3_ANA
VSSQ VSS 100n
3828
3800
10K
10K
G
CB|CR0
CB|CR1
CB|CR2
CB|CR3
CB|CR4
CB|CR5
CB|CR6
CB|CR7
CB|CR8
CB|CR9
6 12 32 38 46 52 78 84 44 58 72 86
G
GND AGND
51 50 49 48 47 46 45 44 43 42 13 52 26 33
GNDD GNDD GNDD
DENC
Cb_OUT(0)I820
Cb_OUT(1)I837
Cb_OUT(2)I838
Cb_OUT(3)I839
Cb_OUT(4)I840
Cb_OUT(5)I841
Cb_OUT(6)I842
Cb_OUT(7)I843
Cb_OUT(8)I844
Cb_OUT(9)I845
GNDD GNDD GNDD GNDD
Cb_OUT(9:0)
H H
CL 16532145_029.eps
221101
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Digital Board: Power, Clock, and Reset Audio Clock

1 2 3 4 5 6 7 8 9 10 11 12 13
1900 A13
1900
Power, Clock and Reset - AudioClock +3V3
I931 5900
100MHZ
BLM31 I905 1
PH 1901-1
1901-2
1901-3
G13
F13
G13
I900 2
5903 2906 2900 1901-4 H13
POWER SUPPLY
VDD5_MK2703
3
+5V 100MHZ 100n GNDD 100n 1901-5 F13
A A
4u7 2907
100n 2908
+3V3 GNDD 4 1901-6 H13
2901
+3V3 5 1901-7 F13
+3V3 100n
GNDD
I907
1902 I7
6
7900 +12V 1903 I6
3900
10K
MK2703S 2 7 1904 I6
2902
3924
1K5
GNDD VDD 1905 I7
3925
7 S0 8
4K7
SEL_ACLK1 PLL OUTPUT CLK 5 I901 3901 I902 7902 100n
6 S1 CLK SYNTHESIS acc_aclk_pll
NCP303
GNDD 5901 BLM31 I906 9
1906 I7
I903 BUFFER 6900 I904
AND CTRL CIRC. 22R +5V 1907 I8
3902
2
47K
IRESET_DIG INP 100MHZ

1 X1 OUTP 1 I912 10 2900 A12
3 OUTPUT 27M 4
I909 BAT54 COL 4 NC RESET
RESETn IOn
I911 CRYSTAL 2903
1 7901 8 X2 OSC BUFFER
CD GND 11 2901 A12
B BC847B GND
2916 I932 5 3 GNDD
100n I908
12
B 2902 A12
2 3 -5V 2903 B12
100K
3903
22n 2904
2904 B12
GNDD GNDD GNDD 100n 2906 A3
GNDD GNDD
+3V3 2907 A1
GNDD GNDD 2908 A1
I913
7702-B 2909 G13
74LVC86ADB 14 2911 H1
4
RSTN_BE 6 3914 2912 H13
C VCC3_CLK_BUF
5
47R
RESETn_BE
C 2914 F1
7
2915 F1
7904-E
74LVC04A 2916 B6
14 3900 A2
11 10
VCC3_CLK_BUF
GNDD GNDD 3901 B4
7
3902 B1
7904-A
74LVC04A
3903 B1
14 GNDD GNDD 3904 G2
1 2 3906 E4
+3V3
D GNDD
7 D 3907 E4
7702-C 3908 F4
GNDD 74LVC86ADB 14 3909 F4
VCC3_CLK_BUF 9
8 3915 3910 G13
7904-C RSTN_DVIO 10 RESETn_DVIO 3911 G13
74LVC04A 47R
14 3912 I4
I916 3906 I917 7
I915 5 6
SYSCLK_VSM_5508
3913 G13
VCC3_CLK_BUF 47R 3914 C10
7
7904-F
GNDD GNDD 3915 D10
E E 3916 G12
3907
74LVC04A GNDD
1K
OPTION
14 3917 H4
13 12
3918 H10
7 3919 H13
GNDD
GNDD 3920 H2
GNDD 3921 H13
3922 I13
VCC3_CLK_BUF
PH-S
3923 I12
7904-B 3924 A6
74LVC04A
I918 3925 B7
F 3
14
4
I919 3908 I920 +5V
5904 1901-7
F 5900 A12
+3V3 5907 I930 SYSCLK_PROGSCAN 100MHZ 7
{BCLK_CTL_SERVICE,TX1P,RX1P,RTS1P,CTS1P}
VCC3_CLK_BUF 22R F931 1901-2 5901 B12
100MHZ 7
2 5903 A1
4u7 2914
100n 2915
+5V
+5V +5V 1901-5 5904 F13
3909
GNDD
1K
OPTION 7905-A 5905 H1

7905-E 7905-F 74HCT14D 5
74HCT14D 74HCT14D 14 GNDD 5907 F1
I921 3910 F932 1901-1
14 14 1 2 6900 B6
10 11 12 13
100R 2909 1 7702-B C9
SERVICE CONNECTOR
GNDD GNDD +5V
7
7 7 GNDD 7702-C D9
G GNDD
7905-C
74HCT14D
1n5 G 7900 A2
GNDD GNDD GNDD GNDD 14 7901 B2
I922 3911 F933 1901-3
6 5
7902 B7
3904
22R
10K 3913 3
7 3916 7904-A D1
-5V 6K8 GNDD 7904-B F3
+5V +5V GNDD 100K
7904-C D3
+5V 5905 I925 7905-B 7904-D H3
VDD5_OSC
VCC3_CLK_BUF
100K
3918
74HCT14D
14
7904-E C3
I926 I927 3919 F934 1901-4
7906 7904-D 3 4 7904-F E1
I933
H H
2911
100n
FXO-31FT 4 74LVC04A
14 +5V 100R 2912 4 7905-A G10
VDD 3920 I923 3917 I924 7
1 3 9 8 GNDD 7905-B H10
TS OUT SYSCLK_EMPRESS 7905-D 1n5
OSC 22R 22R 7905-C G11
GNDD 74HCT14D
7
GND 14
I928 3921 F935 1901-6
7905-D H11
8 9
GNDD 2 7905-E G8
3912
GNDD
1K
OPTION 10K 3922 6

1906 1907 7 3923
7905-F G9
GNDD Hole 4.0 mm with Cu Hole 4.0 mm with Cu GNDD
-5V 6K8 7906 H1
GNDD 100K F931 F13
GNDD
1903 1904 1905 1902 F932 G13
I I F933 G13
F934 H13
GNDD GNDD GNDD GNDD GNDD GNDD F935 H13
CL 16532145_030.eps
221101
1 2 3 4 5 6 7 8 9 10 11 12 13
Layout Digital Board (Overview Top View)
1100 A4 2311 A5 2707 C4 3221 B4 3909 B4

PART 1 1101
1200
A3
A4
2403
2411
A1
A2
2708
2709
C4
C4
3222
3223
B4
B4
4102
4103
A3
B3
CL 16532145_32a.eps 1500
1600
C2
A1
2412
2413
B1
B1
2710
2711
C4
C4
3224
3225
A3
A3
4104
4105
A3
B3
1601 A1 2417 A2 2712 B4 3226 B4 4108 B2
1602 C1 2418 A2 2713 B4 3227 A5 4109 B2
1603 C2 2419 B2 2714 B4 3228 A4 4110 B2
1800 B1 2420 A1 2715 B3 3233 B4 4501 C1
1900 A2 2421 A1 2716 B4 3234 A4 4600 C1
1901 A1 2422 A1 2717 B4 3235 A4 4601 C1
2100 B2 2423 A1 2719 B4 3236 A5 4602 C1
2101 B3 2424 B1 2720 C4 3237 A5 4700 C5
2102 B3 2425 A2 2723 C4 3242 B4 4701 C5
2103 B3 2426 B2 2724 C5 3243 B4 5100 A2
2109 A3 2427 A2 2725 C4 3244 A5 5101 A3
2110 A3 2428 A2 2726 C4 3245 A5 5102 A4
2111 A3 2429 A2 2727 C4 3400 A1 5103 B3
2112 A3 2430 A1 2800 C3 3401 A1 5200 A4
2113 A3 2431 A1 2817 C4 3403 A1 5201 A5
2114 A3 2432 A2 2821 B1 3408 B1 5202 A5
2116 A2 2433 A2 2824 C3 3409 B1 5203 A4
2117 A2 2434 A2 2829 B1 3410 B1 5205 A4
2118 A2 2437 A2 2834 B1 3500 C1 5206 B5
2119 A2 2438 A2 2837 C3 3501 C1 5209 A4
2127 A3 2439 A1 2903 A2 3601 A5 5210 A4
2129 B3 2440 A1 2904 A2 3602 A5 5212 A4
2130 B2 2441 A2 2907 B3 3603 A5 5300 B4
2131 B2 2442 A2 2908 B2 3604 B1 5302 B4
2132 A4 2444 A1 2909 A2 3605 B1 5400 A2
2134 A4 2512 C1 2912 A1 3609 B1 5402 A1
2135 B3 2513 C1 2914 B3 3610 B2 5403 A2
2136 A3 2514 C1 3100 B3 3611 A5 5404 A2
2138 A3 2515 C2 3101 B3 3612 A5 5500 B1
2139 B3 2516 C1 3102 B3 3613 A5 5501 B1
2140 A3 2517 B1 3103 B2 3614 B2 5502 B1
2141 A3 2518 B1 3104 A4 3615 A1 5503 B2
2142 A3 2519 B2 3105 A4 3619 A1 5504 C1
2143 A3 2520 B1 3106 A3 3620 C2 5505 C1
2144 A3 2530 C2 3107 A2 3621 A5 5506 C1
2145 A3 2539 C1 3108 A3 3622 A5 5507 C1
2146 A2 2540 C1 3109 A3 3623 C1 5508 B2
2147 A4 2541 C1 3110 A3 3624 A5 5509 C2
2148 A4 2542 B2 3117 A3 3625 C1 5600 A5
2149 A4 2545 C2 3118 B1 3629 B1 5602 A5
2150 A4 2600 A5 3119 B2 3630 A1 5603 A5
2151 A4 2601 A5 3120 B3 3631 B2 5606 A1
2152 A3 2602 A5 3121 B3 3632 B1 5607 A1
2153 B2 2603 C1 3122 B3 3633 A1 5700 C4
2154 B2 2604 C1 3123 B3 3634 B2 5701 C4
2200 A4 2608 B1 3124 B3 3635 C1 5702 B3
2201 A4 2609 B1 3125 B2 3636 A1 5809 C4
2203 A4 2610 A5 3126 B3 3637 C1 5810 B3
2204 B4 2611 A5 3127 A3 3638 A1 5903 B3
2205 A4 2612 A5 3128 A3 3700 B4 5904 A1
2206 A5 2613 B1 3129 A3 3701 B3 5907 B3
2207 B4 2614 B2 3130 B3 3702 B3 7100 A3
2208 A4 2618 B1 3131 A4 3704 C4 7102 B3
2209 A5 2619 B2 3132 A4 3707 B4 7103 A4
2210 A4 2620 A5 3133 A4 3708 B4 7200 A4
2211 A5 2621 A5 3134 A4 3709 C4 7203 A4
2212 A5 2622 A5 3135 A4 3711 C4 7204 B5
PART 2 2213 A4 2623 C1 3136 A3 3712 C4 7403 A2
2215 A4 2624 C1 3137 B2 3713 C5 7404 A2
CL 16532145_32b.eps 2216
2217
B4
B4
2628
2629
A1
B1
3138
3200
B2
A4
3714
3715
B4
B5
7500
7501
C2
C1
2218 B5 2630 A1 3202 A3 3716 B5 7503 C2
2219 B5 2631 C1 3203 A5 3717 B5 7600 A5
2220 A5 2632 A1 3204 A4 3718 B4 7602 A1
2221 A5 2633 B2 3208 A3 3719 B4 7603 A5
2222 A4 2634 A1 3209 B5 3801 C3 7605 A5
2223 A4 2635 B2 3211 A4 3807 C3 7700 B4
2225 A4 2636 A5 3213 B4 3808 C3 7703 C5
2226 B4 2700 B4 3214 B4 3812 C3 7802 C3
2227 B4 2701 B4 3215 A4 3816 C3 7803 C3
2228 A5 2702 B4 3216 B4 3818 C3
2230 A4 2703 C4 3217 B4 3819 C3
2231 A3 2704 C4 3218 B4 3824 C3
CL 16532145_032.eps 2304 B4 2705 C4 3219 A4 3825 C3
231101 2305 B4 2706 C4 3220 A4 3907 A3
Layout Digital Board (Part 1 Top View)
PART 1
CL 16532145_32a.eps
231101
Layout Digital Board (Part 2 Top View)
PART 2 CL 16532145_32b.eps
231101
Layout Digital Board (Overview Bottom View)
2104 A3 2802 B2 3803 C3 7702 B1

2105 A3 2803 C2 3804 C3 7800 B1
2106 A3 2804 C2 3805 C2 7801 C2
2107 A3 2805 B2 3806 B2 7900 B4
PART 1 2108 A3 2806 B2 3809 C2 7901 B4
2115 B3 2807 B2 3810 B2 7902 B2
CL 16532145_33a.eps 2120 A4 2808 C2 3811 C2 7904 B3
2121 A3 2809 C2 3813 C3 7905 A5
2122 A3 2810 B1 3814 C3 7906 B3
2123 A3 2811 B1 3815 C2
2124 A3 2812 C1 3817 C2
2125 A3 2813 C1 3820 C2
2126 A3 2814 C2 3821 C3
2128 A3 2815 C2 3822 C3
2137 A3 2816 C3 3823 C2
2202 B5 2818 C2 3826 C2
2214 A2 2819 B3 3827 C2
2224 A2 2820 B2 3828 B1
2229 B3 2822 C3 3900 B3
2300 A2 2823 C2 3901 B4
2301 A2 2826 C2 3902 B4
2302 A2 2827 C2 3903 B4
2303 A1 2828 C3 3904 B3
2306 A2 2831 C2 3906 B3
2307 A2 2832 C2 3908 B3
2308 A2 2833 C3 3910 A5
2309 A2 2835 C2 3911 A5
2310 A2 2836 C2 3912 A4
2312 B3 2900 A4 3913 A5
2402 A5 2901 A4 3914 B1
2404 A4 2902 A4 3915 B1
2405 B4 2906 B4 3916 A5
2406 B4 2911 B3 3917 B3
2407 B4 2915 B3 3918 A5
2408 A4 2916 B2 3919 A5
2409 A4 3111 B5 3920 B3
2410 B4 3112 B5 3921 A5
2414 B4 3113 B4 3922 A5
2415 B4 3114 B4 3923 A5
2416 B4 3115 A3 3924 B2
2435 B4 3116 A3 3925 B2
2436 B4 3201 B5 4100 A3
2443 A4 3205 B5 4101 A3
2446 A5 3206 B5 4106 B4
2500 C5 3207 B4 4107 B3
2501 C5 3212 B5 4300 B2
2502 C5 3229 A2 4301 B3
2503 C5 3230 A1 4406 B5
2504 C4 3231 A1 4409 B4
2505 C4 3232 A2 4500 C5
2506 C4 3238 A1 4702 B1
2507 C4 3239 A1 5204 A1
2508 C4 3240 A1 5207 B5
2509 C4 3241 A1 5208 B3
2510 C4 3300 B2 5211 A1
2511 C4 3301 B3 5601 A1
2521 C5 3402 B4 5604 A1
2522 C4 3404 A4 5605 A1
2523 C4 3405 B4 5800 C2
2524 C5 3406 A4 5801 C3
2525 C5 3407 A4 5802 C3
2526 C4 3502 C5 5803 C2
2527 C4 3503 C5 5804 C3
2528 C4 3504 C5 5805 C3
2529 C4 3505 C5 5806 C2
2531 C5 3506 C5 5807 C3
2532 C4 3507 C5 5808 C3
2533 C5 3508 C4 5900 A3
2534 C5 3509 C4 5901 A4
2535 C5 3513 C5 5905 B3
2536 C5 3515 C4 6500 C5
2537 C5 3600 B4 6900 B2
2538 C4 3606 A1 7101 A3
2543 C5 3607 A1 7104 A3
2544 C4 3608 A1 7201 B5
2565 C5 3616 A1 7202 B4
2605 A1 3617 A1 7300 A2
2606 A1 3618 A1 7301 A2
PART 2 2607
2615
A1
A1
3626
3627
A1
A1
7302
7303
B2
B3
CL 16532145_33b.eps 2616
2617
A1
A1
3628
3703
A1
C2
7401
7402
A5
A4
2625 A1 3705 B2 7502 C4
2626 A1 3706 B2 7504 C5
2627 A1 3710 C2 7601 A1
CL 16532145_033.eps 2718 B2 3720 C2 7604 A1
231101 2721 B1 3800 B1 7606 A1
2722 B1 3802 B2 7701 B1
Layout Digital Board (Part 1 Bottom View)
PART 1
CL 16532145_33a.eps
231101
Layout Digital Board (Part 2 Bottom View)
PART 2
CL 16532145_33b.eps
231101
Layout Digital Board (Testlands Bottom View)
+3V3 Resetn_BE Resetn +3V3 +3V3 +12V +3V3 +5V Resetn_VE -5V
+3V3
+3V3 Sysclk_Empress
EMI_PROCCLK
Sysclk_ProgScan
AE_DATAO
ACC_ACLK_OSC
Sysclk_VSM_5508
+3V3
VSYNC
HSYNC VE_DSn
VE_DTACKn
+3V3
+3V3 ACC_ACLK_PLL
+3V3
Mute
VIP_ICLK
+3V3
CL 16532145_034.eps
VSOUT HSOUT DAC-A/Y DAC-C Cr Cb Y +5V +5V +3V3 +3V3 +3V3 +3V3 101201
DAC-B Reset_DVIO +3V3 +3V3 +3V3

Layout Digital Board (Mapping Testlands )

F214
F247
A3
A2
I175
I176
A3
A3
I300
I301
A2
A2
I610
I611
A5
B5
I720 B3
I721 B2
I880 C3
I881 C3
Personal Notes:
F248 A2 I177 A3 I302 A2 I612 A5 I722 B3 I882 C3
F249 A2 I178 A3 I303 B2 I613 B5 I723 B2 I883 C2
F250 A2 I179 A3 I304 B3 I614 A5 I724 B2 I884 C2
F264 A2 I180 A3 I305 B3 I615 B5 I725 B3 I900 B4
F265 A3 I181 A3 I306 A3 I616 A5 I726 B2 I901 B4
F931 A4 I182 B3 I307 B3 I617 A5 I727 B2 I902 B4
F932 A4 I183 A2 I308 A3 I618 C4 I728 A1 I903 B4
F933 A5 I184 A3 I309 B3 I619 A5 I729 A1 I904 B2
F934 A4 I186 A3 I400 A4 I621 A1 I730 A1 I905 A4
F935 A4 I187 A3 I401 A4 I622 A1 I731 A1 I906 A4
I100 A4 I188 A3 I402 B4 I623 A1 I732 B2 I907 A4
I101 C5 I200 A2 I403 A4 I624 A1 I733 B2 I908 A5
I102 C5 I201 B3 I404 B4 I625 A1 I734 B1 I909 B4
I103 B4 I202 A5 I405 B4 I626 A1 I735 B1 I911 B3
I104 B4 I203 A3 I406 B4 I627 B4 I800 C4 I912 A3
I105 B3 I204 C3 I407 A4 I628 C4 I801 C3 I913 B3
I106 B3 I205 A2 I408 A5 I629 A5 I802 C3 I915 B3
I107 B3 I206 A4 I409 A4 I630 C4 I803 C3 I916 B3
I108 B3 I207 A2 I410 A4 I631 C4 I805 C3 I917 B3
I109 B4 I208 B3 I412 B4 I632 C4 I806 C3 I918 A5
I110 B3 I209 B4 I413 A4 I633 B4 I807 C3 I919 B3
I111 A2 I210 A2 I414 B4 I634 C4 I808 C2 I920 B3
I112 B5 I211 A2 I415 B4 I635 C5 I809 C2 I921 A5
I113 B5 I212 A2 I416 B4 I636 C4 I810 C3 I922 A5
I114 B5 I213 A2 I500 C5 I637 C5 I811 C3 I923 B3
I115 B5 I215 B5 I501 C5 I638 C5 I812 C2 I924 A4
I116 C3 I216 A1 I502 C5 I639 C5 I813 C2 I925 B3
I117 C3 I217 A2 I503 C5 I640 C5 I814 C1 I926 A5
I118 C4 I218 A2 I504 C5 I641 B5 I815 B2 I927 A5
I119 C4 I219 A1 I505 C5 I642 A5 I816 B2 I928 A5
I120 A4 I220 A1 I506 C5 I643 A5 I817 B2 I930 B3
I121 A3 I221 B2 I507 C5 I644 A5 I818 C2 I931 A5
I122 B3 I222 B2 I508 C5 I645 B5 I819 C3 I932 B2
I123 A2 I223 A2 I509 C5 I646 C4 I820 C3 I933 B3
I124 B4 I224 A1 I510 B5 I647 A5 I821 C3
I125 A2 I225 A2 I511 C4 I649 C5 I822 C3
I126 A3 I226 A2 I512 C5 I650 B4 I823 C3
I127 A2 I227 A2 I513 B5 I651 B5 I824 B2
I128 A4 I228 A2 I514 B4 I652 B5 I825 B2
I129 A2 I229 B5 I515 C5 I653 B5 I826 C3
I130 B3 I230 A2 I516 C5 I654 B4 I827 C3
I131 A3 I231 A2 I517 C5 I655 B4 I828 C3
I132 B1 I232 A2 I518 C4 I656 B5 I829 C3
I133 A3 I233 A2 I519 C5 I657 C4 I830 C3
I134 A3 I234 A4 I520 C4 I658 C4 I831 C3
I136 A3 I235 A4 I521 C4 I659 C3 I832 C3
I137 A2 I236 B4 I522 C4 I660 B5 I833 C3
I138 A3 I237 A2 I523 C4 I661 B5 I834 B3
I140 A3 I238 A2 I524 C4 I662 C5 I835 B3
I141 A4 I239 B5 I525 C5 I663 B4 I836 B2
I142 A3 I240 A4 I526 C5 I664 B5 I837 C3
I143 B4 I241 B2 I527 C5 I665 C4 I838 C3
I145 A3 I242 B1 I528 C4 I666 C5 I839 C3
I147 B4 I243 B1 I529 C5 I667 B5 I840 C3
I149 B3 I244 A2 I530 C5 I668 B4 I841 C3
I152 B3 I245 A1 I531 C5 I669 B4 I842 C3
I153 B5 I246 A2 I532 C5 I670 A5 I843 C2
I154 B3 I251 A1 I533 C4 I671 B5 I844 C2
I155 B3 I252 A2 I535 C5 I700 B2 I845 C2
I156 A3 I253 A2 I536 C4 I701 B1 I846 B3
I157 A3 I254 A1 I537 C5 I702 B1 I847 B2
I158 B4 I255 A1 I538 C4 I703 C2 I848 B2
I159 A5 I256 A2 I540 C5 I704 C2 I849 B2
I160 B3 I257 C5 I543 C5 I705 C2 I850 B2
I161 B3 I258 A2 I551 C5 I706 C2 I851 B1
I162 C4 I259 A2 I552 C4 I707 C2 I852 B1
I163 A3 I260 A1 I553 C4 I708 C2 I868 C2
I164 B4 I261 A1 I555 C4 I709 C1 I869 C2
I165 A3 I262 A1 I600 A5 I710 B3 I870 B2
I166 B4 I263 A1 I601 A5 I711 C2 I871 C3
I167 A3 I264 A2 I602 A5 I712 C2 I872 C3
I168 C5 I265 B5 I603 C5 I713 A1 I873 B2
I169 A3 I266 A2 I604 A5 I714 C2 I874 C2
I170 A3 I267 A2 I605 A5 I715 C2 I875 C2
I171 A3 I268 B2 I606 A5 I716 B3 I876 C3
I172 A3 I269 B2 I607 A5 I717 B3 I877 C2
I173 A3 I270 A2 I608 A5 I718 B3 I878 C3
I174 A3 I271 B1 I609 B5 I719 B3 I879 C3
CL 16532145-34m.eps
101201
Personal Notes: Personal Notes:

Alignments DVDR985 /171 8. EN 157
8. Alignments
8.1 Alignment Instructions Analogue Board
Alignments Analog PCB Eur
ADJUSTMENT INSTRUCTIONS ANALOGUE BOARD

Test equipment: 2 HF - AGC adjustment [3707]:
1. Dual-trace oscilloscope Service tasks after replacement of IC 7703:
Voltage range : 0.001 ~ 50 V/div
Frequency : DC ~ 50 MHz Purpose: Set amplifier control.
Probe : 10:1, 1:1
Symptom, if incorrectly set:
2. DVM (Digital voltmeter) Picture jitter if input level is too low and picture distortion
if input level is too high.
3. Frequency counter
4. Sinus generator TP ADJ. MODE INPUT

Sinus : 0 ~ 50 MHz
Tuner 4,5mV(74dBµV)
1705 on aerial input
5. Test pattern generator Set tuned to
Pin 11 R3707 PAL white picture,
channel 27
(F700, audio IF on,
IF-out) no modulation
How to read the adjustment procedures: DISC MEAS.EQ. SPEC.
Oscilloscope 550mVpp +/-50mV
Video Pattern (use a 10:1 probe )
Generator
DVDR mode:
Example using: 3 Attenuating the 40.4 MHz [5702]:
DVDR TUNER
(SECAM only)
Connecting point
(Test Point) of
measuring Test signal Service tasks after replacement of coil 5702:
equipment required for the
adjustment and
Adjustment feed-in point Purpose: To attenuate the band I carrier rests.
component
Bad picture quality when the filter attenuates the picture
TP ADJ. MODE INPUT carrier (38.9MHz).
Pin 2 of
Con.1911 R3054 TUNER
(FMRV) TP ADJ. MODE INPUT
DISC MEAS.EQ. SPEC.
OFW 40.4 MHz, 300mVrms
Frequency- 3,800MHz 1700 L5702 TUNER
Disc Counter ±10kHz
at Tuner 1705, Pin 11
Pin 1 (F700, IF-out)
(F704)
DISC MEAS.EQ. SPEC.

Measuring
Disc needed for equipment Adjustment
adjustment Specification Oscilloscope, adjust minimum
Sinus Generator, amplitude
Counter
Front End (FV)

Service tasks after replacement of IC 7703, coil L5702 and L5703: If the adjustment is correct the signal at pin 1 of OFW [1700] must be
smaller than the input signal amplitude by at least 5 dB.
1 AFC Adjustment:
Purpose: Correct adjustment of demodulator AFC - circuit

Bad or disturbed TV channel reception.
PAL - AFC adjustment [5703]:

TP ADJ. MODE INPUT
IC 7703 38,9MHz 500mVpp
Pin 17 L5703 TUNER at Tuner 1705, Pin 11
(I976)
(F700, IF-out)
DISC MEAS.EQ. SPEC.
DC Voltmeter 2,5V ±0,2V

Frequ. Generator
CL 16532095_110.eps
150801
Figure 8-1
EN 158 8. DVDR985 /171 Alignments
8.2 Reprogramming Procedure of NVM on the 8.2.4 Slash Version

Analogue PCB
The slash version is stored with command 715 followed by the
The NVM, item 7815, on the Analogue board contains the slash version as parameter.
The slash versions used in DVDR1000 and DVDR1500 are the
following factory settings:
1. Bargraph 0dB correction factor following:
2. Clock correction factor • DVDR980/17X: 103
• DVDR985/17X: 104
3. AFC reference value
4. Slash version Example:
DD:>715 1
The settings 1,2 and 3 are stored in the NVM during the
production of the analogue board. Reset of Slash Version
The slash version is stored at the end of the production line of Use command 729 to reset the analogue board to the default
the set. setting.
In case of failure, the NVM must be replaced by an empty Procedure:
device. By way of commands via the Diagnostic Software or via • Put the set in DSW command mode
ComPair, the factory settings must be restored in the NVM. • Execute command 729 with the following parameters:
DD:> 729 w 0xA0 3 0x07 0xD0 0x00
8.2.1 Bargraph 0db Alignment • Leave the DSW command mode and start up the set in
application mode No background is visible on the TV
screen. The analogue board is ready to accept the
For an exact functionality of the bar graph in the display, a
appropriate slash version.
correction factor for the left and the right channel is stored in the
NVM.
Procedure: 8.3 Rework Procedure IEEE Unique Number
• Put the set in DSW command mode
• route Audio path from Audio front connectors to digital with 8.3.1 Scope:
the following command:
DD:> 713 01
The procedure describes how to upgrade sets with a unique
• apply a sine wave of 1 kHz, 1.65 Vrms (0 dB) to the front
number after repair. This unique number is stored in the
connectors, audio left and right
NVRAM (item 7201) of the digital board at the end of the
• store 0 dB bar graph level with command 720
production line.
DD:>720
This procedure is only valid or necessary when:
• The digital board is replaced
8.2.2 Clock Correction Adjustment • NVRAM on the digital board is replaced
• NVRAM is cleared
To guarantee an exact function of the real time clock, an In all other cases the repaired set retains its unique number.
adjustment of the clock frequency is possibe and stored in the The procedure defines several means to re-assure the unique
NVM. number depending on the possibilities of repair or the state the
Procedure: faulty set is in.
• Connect a pull up resistor of 10k between pin 7 an 8 of the
clock IC PCF8593T, item 7811, on the analogue PCB 8.3.2 Handling:
• put the set in service command mode
• execute command 722 to initiate that a 1 Hz signal is
State of Original (Defective) Board:
available on pin 7 of the clock IC
1. The digital board starts up in Diagnostics Mode: follow
DD:>722
procedure A to retrieve the valid unique number
• measure the frequency of the Clock Crystal with an
2. The digital board does NOT start up in Diagnostics Mode:
accuracy of ±1(s. Normally the measured frequency must
follow procedure B.
be between 999902 (s and 1000097 (s. If the frequency is
outside this range, the clock IC must be replaced.
• Execute command 721 with the measured frequency as an 8.3.3 Procedure A
input parameter
example: 1. Connect defective digital board to PC via serial cable (3122
DD:>721 1000023 785 90017)
2. start up hyper terminal or any other serial terminal via the
8.2.3 AFC Reference Voltage Tuner correct settings (DSW command mode interface)
3. read out existing unique number via nucleus 403
example:
This function stores the reference voltage for the tuner in the
DD:> 403
NVM. Before this value can be stored, the AFC adjustment,
40300: DV Unique ID = 00D7A1FC6C
described in the adjustment instructions of the analogue board,
Test OK @
must be carried out.
4. note read out
Procedure:
5. program new digital board via nucleus 410
• Adjust AFC circuit
example: DD:> 410 00D7A1FC6C
• Calculate the reference value
41000:
• Execute command 732 and use the calculated reference
Test OK @
value as parameter
example:
The set has now the original unique number
DD:>732 128
8.3.4 Procedure B
1. Note the serial number of the set example:

AH050136130156
Alignments DVDR985 /171 8. EN 159
– AH = production centre Hasselt. According to UAW-

500: A=1 and H=8
– 05 = change code (this is not used for this calculation)
– 01 = YEAR
– 36 = Production WEEK
– 130156 = Lot and SERIAL number
2. Calculate the unique number: this number always exists
out of 10 hexadecimal numbers.
3. First 5 numbers: First we calculate a decimal number
according to the formula below: 35828*YEAR + 676*
WEEK + 26*A + H + 8788 The figures are fixed, YEAR +
WEEK + factory code ( A + H) are variable
Example: 35828*01+676*36+26*1+8+8788 = 68986
(decimal) Then we translate the decimal number to a
hexadecimal number.
example: 68986 (decimal)= 10D7A (hex)
4. Last 5 numbers: The last 5 numbers exist out of the Lot
and SERIAL number. We have to translate the decimal
number to the next 5 hexadecimal numbers:
Example: 130156 (decimal) = 1FC6C (hex)
5. Program new digital board via nucleus 410 Therefore we
use the 10 hexadecimal numbers we calculated above:
example:
DD:> 410 10D7A1FC6C
41000:
Test OK @
The set has now its original unique numbe

EN 160 9. DVDR985 /171 Circuit-, IC Descriptions and List of Abbreviations
9. Circuit-, IC Descriptions and List of Abbreviations

9.1 Multi-Mode SOPS 50PS203
9.1.1 Why Multi-Mode SOPS?
Using ordinary SOPS results in a decrease of the efficiency at

low output loads due to the increase of the switching frequency.
The Multi-Mode SOPS will reduce the switching frequency at
low loads but still preserves valley switching.
9.1.2 Block Diagram
Lightning Rectifier
6200
Protection 5131
EMI 33Vstby
Vi MAINS
FILTER 4 2260 6201
6210
6211
2125 +12Vstby
2210 2211
6215
+ Vb 2 +12Vreg
6140 +3V9
7125
Overload Power
Overvoltage 2214
protection 2140 3141 switch
protection 7141 6221
7142
2141 2146 FLYB
7140 feed forward 6220 7220
7143 -5Nstby
Rsense 2220 2222
Control
-Vreg 6142 6230

-Vgnstby
2151 8 2220 6231 2235
6143 6144
6240
7
5.2Vstby
2240 2241
7200
7251
Regulation
+12Vreg
CL 16532095_111.eps
150801
Figure 9-1
9.1.3 Circuit Description voltage reaches a treshold value. A current starts to flow in
primary winding 2-4. The MOSFET will be fed forward via
Input Circuit winding 7-8, R3150 and C2146.
The input circuit consists of a lightning protection circuit and an
EMI filter. +Vb Supply and Negative Regulation Voltage
The lightning protection comprises R3120, sparkgaps 1124 The positive part of the voltage over winding 7-8 will be rectified
and 1125. D6128, 6129, C2127 and R3129 are optional. via R3150, D6140 and charged via R3140 into C2140. The
L5110, L5115, C2120 and L5120 form the EMI filter. It prevents voltage over C2140 has a value of +30 till +40V. This value
inflow of noises into the mains. depends on the value of the mains voltage Vi and the load.
The negative part of the voltage over winding 7-8 will be
Primary Rectifier/smoothing Circuit rectified via R3150, D6142 and charged into C2151. The
The AC input is rectified by diodes 6151,6152, 6153, 6154 and voltage over C2151 has a value of -15V and is used as
smoothed into C2125. The voltage over C2125 is regulation voltage.
approximately 300V. It can vary from 200V to 390V.
Control Circuit
Start Circuit The control circuit exists of T7140, D6141, C2144 and 2145,
This circuit is formed by R3125, 3126, R3141, C2140 and C2147, R3147 and 3148.
R3132. This circuit is fed by supply voltage +Vb via R 3141. This circuit
When the power plug is connected to the mains voltage, the controls the conduction time and the switching frequency of the
MOSFET 7125 will start conducting as soon as the gate power switch circuit. It switches off the MOSFET as soon as the
voltage over Rsense reaches a certain value. This value
Circuit-, IC Descriptions and List of Abbreviations DVDR985 /171 9. EN 161
depends on the error voltage at the emittor of T7140, which can 4. +3V3(for dig pcb + DVio)
be positive or negative (+/- 0,66V). The voltage fed back by the 5. GND(for dig pcb + DVio)
regulation circuit defines this error voltage. 6. +12V(for dig pcb + DVio)
7. GND(for dig pcb + DVio)
Power Switch Circuit 8. GND(for dig pcb + DVio)
This circuit comprises MOSFET 7125, Rsense formed by 9. +5V(for dig pcb + DVio)
R3133, 3134, 3135, 3136 and 3137, R3131, R3132, D6146. 10. STBY control(for dig pcb + DVio)
Diodes 6130, 6131 and 6132 protect the control circuit in case 11. GND(for dig pcb + DVio)
of failure of the MOSFET. 12. -5V(for dig pcb + DVio)
The +12V is switched off by the STBY_ctrl signal.
Regulation Circuit When the +12V is switched off, also the +3V3, +5V and -5V are
The regulation circuit comprises opto-coupler 7200, which switched off. All these voltages are low drop regulated.
Connector 0205
isolates the base voltage of transistor 7140 at the primary side
from a reference component 7251 at the secondary side. The Functional use: to analogue board + display board + flap motor
TL431(7251) can be represented by two components: ‘STBY‘ indicates that the voltage will not be switched off in the
standby situation.
• a very stable and accurate reference diode
• a high gain amplifier 1. +12VSTBY(= +12V Standby, for display heating, 8Vstby)
2. +5VSTBY(= +5V Standby; general use)
3. -5NSTBY(= -5V Standby; neg. voltage for drivers)
K 4. VGNSTBY(= -32V Standby; for display grids)
5. +33STBY(= +33V Standby; for tuner)
6. FLYB(flyback pulse for power fail + measurement)
R 7. GNDA(Ground for the analogue board)
Connector 0207
Functional use: to engine
2.5V 1. +3V3(for engine servo board)
2. +5V(for engine servo board)
3. GND(for engine servo board)
A 4. +4V6E(for engine analog part)
CL 96532065_071.eps 5. GND(for engine servo board)
130799
6. -5V(for engine servo board)
7. GND(for engine motor currents)
Figure 9-2 8. +12V(for engine motor currents)
TL431 will conduct from cathode to anode when the reference

is higher than the internal reference voltage of about 2.5V. If the 9.2 Display Board
reference voltage is lower, the cathode current is almost zero.
The cathode current flows through the LED of the opto-coupler. 9.2.1 Operation Unit DC (DC Part)
The collector current of the opto-coupler will adjust the
feedback level of the error voltage at the emittor of T7140. The core element of the operation unit DC is the microcontroller
TMP88CU77ZF [7156]. The TMP88CU77ZF is an 8 bit
Overload Protection Circuit microcontroller fitted with 96kB ROM and 3kB RAM and is
This circuit consists of R3145, C2143, a thyristor circuit formed responsible for following functions:
by T7141 and T7143, R3143 and R3142. When the output is • Integrated VFD driver
shortened, the thyristor circuit will start to conduct and switch • Timer
off the supply voltage over C2140. This results in a switching of • Evaluation of the keyboard matrix
f of the drain current of the MOSFET 7125 and the output will • Decoding the remote control commands from the infra-red
be disabled. The start circuit will try to start up the power supply receiver pos. 6170
again. If the circuit is still shortened, the complete start and stop • Activation of the display
sequence will repeat. The power supply comes in a hiccup • Motor driver
mode (is ticking). The system clock is generated with the 12MHz quartz (Pos.
1153).
Overvoltage Protection Circuit
This circuit consists of R3149, D6144, 6143, R3144, C2142 9.2.2 Evaluation of the Keyboard Matrix
and T7142.
When the regulation circuit is interrupted due to an error in the There are 15 different keys on the display board. A resistor
control loop, the regulated output voltage will increase network is used to generate a specific direct voltage value,
(overvoltage). This overvoltage is sensed on the primary depending on the key pressed, via the resistors 3145, 3171,
winding 7-8. 3183 and 3194 on the analog/digital (A/D) ports (7156 Pin 17,
When an overvoltage is detected, the circuit will start up the 18, 19, 20). Pressing keys simultaneously may lead to
thyristor circuit T7141-7143. The power supply will come in a undesired functions!
hiccup mode as long as the error in the control loop is present.
9.2.3 IR Receiver and Signal Evaluation
Secondary Rectifier/Smoothing Circuit
There are 6 rectifier/smoothing circuits on the secondary side. The IR receiver [7140] contains a selectively controlled
Each voltage depends on the number of windings of the amplifier as well as a photo-diode. The photo-diode changes
transformer. the received transmission (approx. 940nm) in electrical pulses,
From these circuits a lot of voltages are derived and fed to 3 which are then amplified and demodulated. On the output of
connectors. The following voltages are present at the output: the IR receiver [7140], a pulse sequence with TTL-level, which
Connector 209 corresponds to the envelope curve of the received IR remote
Functional use: to Digital board + Dvio board control command, can be measured. This pulse sequence is
1. +3V3(for dig pcb + DVio) input into the controller for further signal evaluation via input
2. +3V3(for dig pcb + DVio) IRR [7156, pin 2].
3. +3V3(for dig pcb + DVio)
9.2.4 Motor Driver Flap • A/D converters

• composite sync input
The flap-motor is controlled via the 2 Port-Pins (MD1, MD2) of • I2C bus interface
the P (7156, Pin 12, Pin 100). The motor driver part is Following connection to the mains, a positive pulse on the reset
constructed as a bridged dual power operational amplifier. input on the P is generated by the reset-IC TL7705 (Pos.7900).
Between the IC outputs (7120, Pin1, Pin3) and a Boucherot The system clock is generated with the 20MHz quartz (Pos.
circuit (2121, 3126) suppresses a spurious 3MHz oscillation 1994).
from the output stage. The two ports-pins (MD1, MD2) of the P
are PWM-outputs and are controlled in the following way: 9.3.2 Bus Systems
Flap Motor: The communication between the P and the other functional
groups is via the I2C-bus (SDA, SCL). The clock rate is approx.
MD1 MD2
95kHz.
off H L Functional groups on the I2C bus:
open H PWM(H) • E2PROM ST24E16 (Pos. 7815)
• Tuner (Pos. 1705)
close L PWM(L) • Matrix-switch STV6410 (Pos. 7507)
• Audio IC / MSP (Pos. 7600)
• Display board (Pos. 1987)
Duty Cycle 50% for OPEN and CLOSE • VPS-IC (Pos. 7990).
9.3.3 E2PROM
The E2PROM ST24E16 (Pos. 7815) is an electric erasable and

programmable, non-volatile memory. The E2PROM stores data
Duty Cycle app. 10% for CLOSE
specific to the device, such as the AFC-reference value, clock-
correction-factor, etc. The data is accessed by the P via the
I2C-bus.
9.3.4 VPS, PDC, Teletext (Europe Only)

Duty Cycle app. 10% for OPEN
The STV5348 (Pos. 7990) is a VPS, PDC, and Teletext
Decoder with an external 13,875Mhz quartz.
The following data formats are identified:
• VPS (Timer data and station name)
• PDC Format 2 (Timer data and station name)
CL 16532095_112.eps • PDC Format 1 (station name and time)
150801
• TXT header line (time for „time download“)
Figure 9-3
9.3.5 FOME
For the detection of the end-positions of the flap there are two
The FOME-circuit compares the video signal coming from the
switches (1178, 1179) installed and the information is
tuner and the one coming from the Scart-plug 1. If the video-
evaluated from the P via the signals SW_1178 and SW_1179.
signals are identical the output of the FOME-circuit is low.
Flap Switches:
9.3.6 Fan Control
SW1 SW2
open L H The fan control circuit is necessary to control the speed of the
cabinet fan (Pos. 1984) according to the requirements in
closed H L temperature and noise. The temperature is measured via an
moving H H NTC on the display board (Pos. 3145). When the temperature
is lower than 25° C the fan-voltage is approx. 5V and will reach
error L L
approx. 10V at a temperature of 40° C. It is also possible to
switch off the fan via the control line ION_FAN. The circuit
9.2.5 Bi-Color LED (Standby and ON)
generates also two control-signals: TEMP goes to the P and
BE_FAN is the control-line for the basic engine fan.
The STBY-LED is a red/green bi-color-LED and is controlled
via the STBYLED-signal of the P (7156 Pin 10) in the following
9.3.7 Power Supply
way:
Colour of STBY The 5SW and 8SW supply are switched off in case of standby
LED Status of the Set from the P via the ISTBY-line. This is possible for power-save.
red STBY The ISTBY-line must be low in case of STBY. There is also a
„power fail“ circuit on the PS-schematic which is necessary to
green ON mute AUDIO when IPFAIL is low.
9.3 Analogue Board Europe 9.3.8 Front End (TU, AP Part)
9.3.1 Microprocessor TMP93C071F The Front End Comprises the Following Parts:
• Tuner [1705]
The microcontroller „AIO“ TMP93C071F is a 16bit • IF amplifier & video demodulator IC TDA 9818 [7703]
microcontroller with internal ROM and 8kB RAM. It includes the • Sound processor MSP3415G [7600]
following functions:
Circuit-, IC Descriptions and List of Abbreviations DVDR985 /171 9. EN 163
IF Selection the I2C bus. The audio signal from the tuner is available at the
The IF frequency of the video carrier is 38.9 MHz for all pins 30 AFER and 31 AFEL.
systems except SECAM L' (33.9 MHz).
A quasi-split audio system is used. Separate surface-wave 9.3.9 Input/Output Video-Routing (Europe-Version)
filters (SAW) are required. [1700], [1701] for video, [1702] for
audio. [1700] Is switched into the signal path for DK/I-SECAM
General Description:
L/L' reception, if the signal SAWS is “high”. In this case the
The complete Video- I/O-switching is basically realised by the
switches [7701], [7702] are open and the diode [6700] is
I/O switch STV6410A. It is controlled via IIC-Bus-0 (SDA/SCL)
conducting. [1701] Is switched into the signal path for BG
by the all in one C on the analogue board. The STV 6410 has
reception, if the signal SAWS is “low”. Then the switch [7708]
three YCVBS switches, three chroma switches and one RGB
is open and the diode [6701] is conducting. For DK/I-SECAM L/
switch. All switches have 6-dB amplification on the outputs.
L' reception, an additional circuit for suppressing the adjacent
The YCVBS inputs have bottom clamp, the chroma inputs have
channel audio carrier is provided, which is set using coil [5702]
average clamp, and the RGB inputs have bottom clamp circuits
to maximum suppression at 40.4MHz.
at the inputs. The R/C inputs can be switched to average clamp
for chroma signals via I2C bus.
IF Demodulator The IC has also one slow blanking monitor and one fast
blanking switch for fast RGB insertion (see detailed description
TDA 9818 in chapter 1.5). Two pre-selectors BA 7652 are additionally
The IF signal from the tuner is processed by the demodulator used: One for switching between Rear CVBS, Y- Rear and
IC TDA 9818 [7703]. The signal PSS to pin3 switches between Front, the second for switching between Chroma- Rear and
demodulation of positive SECAM or negative PAL modulated Front signal. Both pre-selectors are controlled via IS1 and IS2
video carriers. A QSS-audio-IF signal SIF1 is generated for from the analogue board C.
demodulation in the sound processor [7600]. The audio-IF
carrier is selected in the audio SAW filter [1702]. This filter is CVBS Signals:
switched for SECAM L’. If the signal SB1 is “high”, the switch There are four CVBS input connection possibilities: Front
[7707] is closed and the diode [6702] is not conducting. For all chinch (E6), Rear Chinch (E4), Scart 1 (E1) and Scart 2 (E2).
other standards the diode [6702] is conducting and the switch Rear Chinch In is routed via the pre selector BA 7652; the other
[7707] is open. The output signal from this SAW filter is first signals are connected direct to the STV 6410. The selected
processed in the TDA 9818. Audio carriers are converted from CVBS signal is routed to Rear Chinch Out (via BA 7660, 6dB
the tuner IF level into the audio IF position and further amplification, 75 Ohm driver) and to Scart 1. Independent of
processed in the audio demodulator [7600]. The AFC coil the input signal quality (CVBS, S-Video or RGB) the digital
[5703] on the TDA 9818 is adjusted so that when a frequency board supplies also S-Video and RGB signals to the
of 38.90 MHz is supplied to the IF output of the tuner, the AFC corresponding socket.
voltage on pin 17 of the TDA 9818 is 2.5V. The setting of the
picture carrier frequency for SECAM L in the TDA 9818 is
S-Video Signals:
achieved by connecting pin 7 of the IC via a resistor [3702] to
There are also four S-Video input connection possibilities:
earth. The switch [7700] and the signal SB1 "high" do this. The
Front In (E5), Rear In (E3), Scart 1 and Scart 2. For S-Video
HF-AGC is set using the AGC controller [3707] so that, with a
from Scart this option has to be switched on in the OSD menu.
sufficiently large antenna input signal (74 dBV), the voltage at
The pre-selectors and the STV 6410 do the signal selection (for
the IF output of the tuner [1705] pin 11 is 500 mVpp. This
detailed routing see overview). Also the video quality will be S-
setting must be carried out, when the audio carrier is switched
Video, the digital board supplies also CVBS to the
off. The demodulated video signal appears on pin 16 [7703].
corresponding sockets. The S-Video signal that is coming from
The demodulator AGC voltage at pin4 is used to determine the
the digital board is routed via BA 7660 (6-dB amplification and
antenna signal strength after a buffer [7705] with the signal
75-Ohm driver) to the S-Video Rear Out socket.
AGC_MUTE. In the opposite direction this line may be used to
mute the demodulator to avoid cross talk in all cases, where the
tuner signal is not needed. In this case a „high“ signal is sent RGB Signals:
The Scart 2 RGB input signal (Decoder socket) is connected to
via AGC_MUTE and the conducting diode [6703] to pin4. The
video trap [1703] reduces adjacent channel video and sound the RGB switch of STV 6410 and to the digital board in parallel.
carrier remainders in the video for BG standards. For all other The RGB from Scart 2 is routed to Scart 1 in low power standby
mode. The direct connection (not via STV 6410) is for loop
standards the switch [7704] and signal TS "low" bypass this
trap. In this cases the selectivity of the SAW filter [1700] is through and REC. The RGB signal, which is coming from the
sufficient. A frequency response correction is achieved by the digital board, is connected to the RGB encoder input of the STV
6410 and is routed to Scart 1 in all other modes.
inductance [5009] for not BG standards. This correction is not
preferred for SECAM L' and therefore shorts circuited by As the Scart-connection can carry either RGB- or Y/C-signals
[7709], if the signal SB1 is “high”. The demodulated video it is necessary to define the available and selected signal-
property. While Pin15 of Scart (Red or Chroma-upstream) is
signal VFV is available after the buffer and limiting stage for
noise peaks [7706]. The FM-PLL demodulator function of TDA fully handled via STV6410A the Pin7 (Blue or Chroma-
9818 is not used and deactivated by the resistor [3726]. downstream) has to be extra set.
• Scart1: Pin42 of C (SC1YC_H-line):
– Low ( Blue-Out on SC1
Audio Demodulator
– High ( Chroma-In on SC1
• Scart2: Pin41 of C (SC2RGB_H-line):
Sound processor MSP 3415G – Low ( Chroma-Out on SC2
The MSP 3415G [7600] is a multistandard sound processor – High ( Blue-In on SC2
which can demodulate FM Mono/Stereo, NICAM and AM
signals. The incoming signal is first controlled and then
Detection of Status-Information
digitised. The digital signal is then demodulated in 2 separate
channels. In the first MSP channel, FM and NICAM (B/G/I/D/K)
are demodulated, whereas in the second MSP channel, FM Pin-8 (Slow-Blank):
and are demodulated again (NICAM L corresponds to NICAM Level-detection of Pin-8 (Scart-1 and -2) is realised by using
STV6410A. It can be readout via IIC-Bus by the CC-C. To
B/G). These demodulated signals are selected digitally in the I/
O and switched to the D/A converter on the outputs. Amplitude obtain the status of Scart1-Pin8, Bit 0 & 1 of register 06h must
and bandwidth of the demodulated audio signals can be be set to 0 (Input-mode). The corresponding bits for verification
of Scart2-Pin8-status are set to input-mode as default.
determined in the MSP using the corresponding commands via
Meaning of Read-Register-Bits: (OPV) the signals are delivered back to the STV 6410 and also
• Bit 7 & 6: not used direct to the 2nd rear out Cinch. The other outputs (Scart,
• Bit 5 & 4: Status Scart-2/Pin8: Cinch) are supported by the STV 6410.
– 0 1 Low-level
– 1 0 Medium-level (16:9) Detailed Description STV 6410:
– 1 1 High-level (4:3) The STV 6410 is an I2C bus controlled audio and video switch
• Bit 3 &2: not used matrix, which is able to handle audio input signals up to 2 Vrms.
• Bit 1 & 0: Status Scart-1/Pin8: The used outputs are equipped with internal level adjustment
– 0 1 Low-level possibility. Low distortion and very good channel separation is
– 1 0 Medium-level (16:9) a typical peculiarity of this IC. The output resistance is very low
– 1 1 High-level (4:3) and the frequency bandwidth is up to 50 kHz.
Pin-16 (Fast Blank): Detailed Description UDA 1360:

Only the status/level of Scart-2/Pin16 must be detected; this is The UDA 1360TS is a stereo Analog-to-Digital Converter
realised by using PortC3/AIN14 (Pin25) of the CC-C as an employing bitstream conversion techniques.
Analogue-input. The UDA supports the I2S-bus data format and the MSB-
• ADC-value lower or equal 24h ( Pin16 low (no RGB- justified data format with word lengths of up to 20 bits. The IC
signals) supports also 2Vrms input signals and is designed for 3V3
• ADC-value greater 24h ( Pin16 high (RGB present on supply voltage.
Scart-2) The device is able to handle system clocks of 256fs and 384fs.
To avoid misdetection a “software-integration” (result is first Typical THD+N at 0dB is -85dB and a S/N performance up to
valid if it was 3-times the same) must be implemented, 97dB is possible.
determination has to be done approx. every 47msec (no
multiple of V-sync). Detailed Description UDA 1328:
The UDA1328 is a 6 channel DAC employing bitstream
WSS on Y/C-Plug: conversion techniques, which can be used either in L3
Picture-Ratio-Information (16:9 or 4:3) on SVHS-connections microcontroller mode or in static pin mode.
is coded via the average DC-level of the Chroma-signal-line, The UDA 1328 supports the I2S-bus data format with word
detection is realised by using an analogue-input-port of the CC- lengths of up to 24 bits.
C. Digital sound features can be controlled with the L3 interface.
• ADC- value lower or equal 40h ( 4:3-picture-ratio delivered System clock can be set to 256fs or 384fs.
• ADC-value greater 40h ( 16:9-picture-ratio available on The Device also provides 2 high quality differential outputs.
plug Typical THD+N at 0dB is -95dB and a S/N of up to 106dB is
Y/C-Rear is determined via Port40/AIN3 (Pin14) of CC (WSRI- possible.
line) and Port41/AIN4 (Pin15) is used for Y/C-Front (WSFI- Supply voltage is 3V3.
line).
Detailed Description MC 33078:
Generation of Status-Information The MC33078 is a dual operational amplifier for audio
applications.
Pin-8 (Slow Blank): It offers low voltage noise (4,5nV/√Hz) and high frequency
Only on Scart-1 the Slow-Blank-Status (Level of Pin8) must be performances (15MHz Gain Bandwidth product, 7V/s slew
created, which is done via IIC-Bus-register 06h (Bits 0 & 1) of rate).
the STV6410A. In addition the MC33078 has a very low distortion (0,002%).
Pin-16 (Fast Blank):

Only the status/level of Pin16-Scart1 must be controlled; this is
realised by using the FB-switch-capabilities of the STV6410A,
which are set via IIC-Bus-register 04h (bits 4 & 5).
WSS on Y/C-Plug:
The appropriate DC-level on Chroma-signal-line for Y/C-Rear-
Out is produced via Port57 (Pin10) of the CC-C (WSRO-line).
• 4:3 - Picture-ratio supported on Y/C-Plug: Port57 set to 0
• 16:9 - Picture-ratio supported on Y/C-Plug: Port57 set to 1
9.3.10 Audio Routing Analogue board (Europe / Nafta)
General Description:
The Audio- I/O switching is realised by the STV6410 I/O switch.
By I2C Bus (SDA-0/SCL-0) it is possible to control all the Audio
in- and outputs (for detailed Information we refer to the
STV6410 routing overview).
Analog audio coming from DV-Board and second rear Cinch
input is routed via MSP3415 to the STV 6410. After selecting
the audio source via STV 6410, the signal must be transformed
into the digital domain. For this, the UDA 1360TS (ADC) is
responsible. An input-voltage of up to 2Vrms can be handled
from the IC´s. For further processing, the UDA 1360TS (ADC)
delivers the data-in I2S format to the digital-board. After a
certain delay the (processed) data come back from the digital
board to the UDA 1328 (DAC). The UDA 1328 (DAC)
transforms the I2S data back into the analog domain and feeds
the signals direct to the MC33078 (OPV). From the MC33078
BLOCK DIAGRAM VIDEO IN/OUT EUROPE-VERSION
SCART 2 DOWN TO VCR / SAT / DVD / DECODER 1950-2 AIO 1 FOME SCART 1 UP TO TV / MONITOR 1950-1
7 (Y/CVBS) (Y/CVBS) (Y/CVBS) (Y/CVBS)
WSRO VideoIn VideoOut R/C G B/C BL SW AudInL AudOutL AudInR AudOutR 4 VideoIn VideoOut R/C G B/C BL SW AudInL AudOutL AudInR AudOutR
20 19 15 11 7 16 8 6 3 2 1 20 19 15 11 16 3 2 1
SC2RGB_H 7 8 6
6 Y/C Rear Out

1955
SC1YC_H
Y C
4 STV6410 7507
FB SWITCH
FBIN_ENC 19 4V
0V
17 FBOUT_TV
4 1954 FBIN_AUX 18
RGB SWITCH
B_ENC 6dB 61 BOUT_TV
D_B BIN_ENC 46 B_AUX
G_ENC
G_AUX 6dB 63 GOUT_TV 4
BIN_AUX 32 R/C_ENC 1954
R/C_AUX
MUTE 6dB
D_G GIN_ENC 44 1 RCOUT_TV
C SWITCH to VIP
R/C_AUX
GIN_AUX 30 R/C_ENC
C_ENC SAA7718
C_VCR 6dB 9 VOUT_RF
D_R RCIN_ENC 42 MUTE
6 BA7660 7430
RCIN_AUX 28 Y/CVBS SWITCH
CVBS/Y_AUX TRAP
CVBS/Y_ENC
11 FILTER
D_Y 6 CIN_ENC 40 CVBS/Y_VCR A_R
7 CVBS_STB 6dB
VD to
Y_AUX 3 YCVBS/OUT_TV
Y_ENC A_G
D_C CIN_VCR 48 MUTE
AIO1
C SWITCH
FROM DIGITAL BOARD

D_CVBS 6 YCVBSIN_AUX 24 R/C_ENC
A_ B
7 C_ENC
C_VCR
C_TV 6dB 13 COUT_AUX
CIN_TV 54 MUTE
A_C
Y/CVBS SWITCH
6 CVBS/Y_ENC VPS
7 YCVBSIN_ENC 36 CVBS/Y_VCR
CVBS_STB
TO DIGITAL BOARD
3 CVBS/Y_TV 6dB 15 YCVBSOUT_AUX

YCVBSIN_VCR 50 Y_ENC A_YCVBS
FRONT MUTE
CVBSIN_STB 34 C SWITCH
END R/C_ENC
C_ENC
VFV C_TV
C_AUX 6dB 5 COUT_VCR
MUTE
TU
WU to Y/CVBS SWITCH
CVBS_STB
CVBS/Y_ENC
AIO1 Wake YCVBSIN_TV 52 CVBS/Y_AUX 7 YCVBSOUT_VCR
Figure 9-4
FOME CVBS/Y_TV
6dB
Y_AUX
up YIN_AUX 26 Y_ENC 25 SLB_TV
MUTE
Front Cinch In (E6 CVBS) YIN_ENC 38 SLOW BLANK,
4 CINCHSWITCH 27 SLB_VCR
L_ENC I/O MONITOR
L_STB -14dB 0/6dB
LIN_ENC 45 L_TV 31 SLB_AUX
L_VCR
1953 CVBSFIN
FROM FRONT L_AUX
LIN_STB 41 R_ENC
A/V BOARD 7400 7401 R_STB
R_TV -14dB 0/6dB 59 LOUT_CINCH
LIN_TV 53 R_VCR
5 5 R_AUX
2 BA7652 MUTE 58 ROUT_CINCH
BA7652 LIN_VCR 49
AUX SWITCH
IS1 L_ENC
LIN_AUX 35 L_STB

Dvd985 171 Manual

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DVD-Video Recorder DVDR985 /171

Contents Page Contents Page

1. Technical Specifications and Connection Facilities

Mains voltage : 120V (90 -140VAC) Automatic Search Tuning

1.2 RF Tuner Tuning Principle

1.3.1 Audio/video Front Input Connectors

1.2.2 Rf - Loop Through: Audio

input voltage /3 tone method (+40

1.2.5 Video Performance: Audio (EXT1/2 and EXT3)

1.2.6 Audio Performance:

SNR Luminance : > -65 dB

SNR Chrominance AM : > -65 dB 1.6 Digital Output

1.4.2 Yc Output Rear (Hosiden ; Ext1)

SNR : > -65 dB 1.7 Digital Video Input/output (Iee 1394)

2. Safety Instructions, Warnings, Notes, and Service Hints

2.1.1 General Safety 2.2.1 General

3. Direction for Use

4. Mechanical, and Dismantling Instructions, and Exploded Views

4.1.3 Digital Board

4.1.4 Analog Board

To put the analog board in service position, demount the

4.2 Exploded View of the Set

Front assy DVDR LOADER 81 Switched Operating Power supply 1002

4.4 Exploded View of the Front Assembly

5. Diagnostic Software and Faultfinding Trees

• Interconnections between components

stand alone DVD recorder; no other equipment is needed. CL 16532095_068.eps

Counter Nucleus Name Description

5.2 Player Script Interface 5.2.2 Structure of the Player Script

STEP DESCRIPTION NUCLEUS

STEP DESCRIPTION NUCLEUS

TITLE TRACK CHAPTER TOTAL TRACK TIME REMAIN CHANNEL VPS/PDC

DVD RW SAVCD HQ SP L:P EP+ MONITOR SAT TIMER RECORD DECODER

TO EXIT TEST: PRESS ONE OF FOLLOWING KEYS

LED BECOMES RED VOL + ONLY FOR TV

DIGITAL BOARD &

press <PLAY> to execute

press <PLAY> to execute

INSERT DVD +RW DISC TO EXECUTE

press <PLAY> to execute

press <PLAY> to execute

press <PLAY> to execute

press <PLAY> to execute

press <PLAY> to execute

press <STOP> to skip PRESS <STOP>

PRESS <STOP> PRESS <RECORD>

PRESS <PLAY> TO CONTINUE

5.2.3 Error Log

5.2.4 Trade Mode 5.3.2 Error Handling

Each nucleus returns an error code. This code contains six

The nucleus group numbers and nucleus numbers are the

CL 16532095_071.eps 5.3.3 Command Mode Interface

Set-Up Physical Interface Components

[ XX YY ] DVD Video Recorder Diagnostic Software version 48

Nucleus number (M) enu, (C) ommand or (S) 2B-interface? [M] : @ C

Command Overview [xx yy] Nuclei

[xx yy] Nuclei 619 Selftest

[xx yy] Nuclei [xx yy] Nuclei

Loop Nuclei [09]

Menu Structure AVENC Menu