uP7704

2A Ultra Low Dropout Linear Regulator

General Description Features
The uP7704 is a 2A ultra low dropout linear regulator † Works with 1.2V~5.5V VIN
specifically designed for motherboard, notebook and graphic „ Adjustable Output Voltage, Down to 0.8V
card applications. This device works with dual supplies, a
„ 1.5% Initial Accuracy
control input for the control circuitry and a power input as
low as 1.2V for providing current to output. The uP7704 „ Excellent Line and Load Regulation
delivers high-current and ultra-low-drop output voltage as † 2A Guaranteed Output Current
low as 0.8V for applications where VOUT is very close to
„ 300mV @ 2A Dropout Voltage
VIN.
† Very Low On-Resistance
The uP7704 features comprehensive control and protection
functions: a power on reset (POR) circuit for monitoring Ω typical
„ 150mΩ
both control and power inputs for proper operation; an EN † VOUT Pull Low Resistance when Disabled
input for enabling or disabling the device, a power OK with † VOUT Power OK Signal
time delay for indicating the output voltage status, a
† Fast Transient Response
foldback current limit function, and a thermal shutdown
function. † Low External Component Count

The uP7704 is available in PSOP-8 or WDFN3x3-10L † Low Cost and Easy to Use
packages with very low thermal resistance. † Enable Pin
† Over Current and Over Temperature Protection
Applications
† Desktop PCs, Notebooks, and Workstations Ordering Information
† Graphic Cards Order Number Package Type Remark
† Low Voltage Logic Supplies
uP7704U8 PSOP-8
† Microprocessor and Chipset Supplies
† Split Plane Microprocessor Supplies uP7704ADDA WDFN3x3-10L

† Advanced Graphics Cards Supplies Note: uPI products are compatible with the current IPC/
† SoundCards and Auxiliary Power Supplies JEDEC J-STD-020 and RoHS requirements. They are 100%
† SMPS Post Regulators matte tin (Sn) plating and suitable for use in SnPb or Pb-
free soldering processes.

Pin Configuration & Typical Application Circuit

POK 1 8 GND 5VCC

EN 2 7 FB R4 CNTL
GND 10R
VIN 3 6 VOUT EN POK

CNTL 4 5 NC
R3
PSOP-8 10K VOUT
VIN VIN VOUT
uP7704

R2
VOUT 1 10 CNTL C4
12.5K
VIN C1 option
VOUT 2 9 FB
1uF NC
VOUT 3 GND 8 VIN C3
C2 R1
10K 10uF
FB 4 7 VIN 4.7uF
GND
POK 5 6 EN

WDFN3x3-10L

uPI Semiconductor Corp., http://www.upi-semi.com 1

Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Functional Pin Description
Pin No.
Name Pin Function
PSOP WDFN
Pow er OK Indication. This pin is an open-drain output and is set high impedance once VOUT
1 5 POK
reaches 90% of its rating voltage.
Enable Input. Pulli ng thi s pi n below 0.4V turns the regulator off, reduci ng the qui escent
2 6 EN
current to a fraction of its operating value.
Input Voltage. This is the drain input to the power device that supplies current to the output
pin. Large bulk capacitors with low ESR should be placed physically close to this pin o prevent
3 7, 8, 9 VIN the i np ut ra i l fro m d ro p p i ng d uri ng la rg e lo a d tra ns i e nt. A 4 .7 uF c e ra mi c c a p a c i to r i s
recommended at this pin. VIN cannot be forced higher than VCNTL otherwise the current limit
function may be false triggered and disable the output voltage.
Supply Input for Control Circuit. This pin provides bias voltage to the control circuitry and
driver for the pass transistor.The driving capability of output current is proportioned to the
4 10 CNTL
VCNTL. For the device to regulate, the voltage on this pin must be at least 1.5V greater than
the output voltage, and no less than VCNTL_MIN.
5 X NC Not Internally Connected
Output Voltage. This pin is power output of the device. A pull low resistance exists when the
device is disabled by pulling low the EN pin. To maintain adequate transient response to large
6 1, 2, 3 VOUT
load change, typical value of 1000uF Al electrolytic capacitor with 10uF ceramic capacitors
are recommended to reduce the effects of current transients on VOUT.
Feedback Voltage. This pin is the inverting input to the error amplifier. A resistor divider from
7 4 FB
the output to GND is used to set the regulation voltage as VOUT = 0.8x(R1+R2)/R1 (V)
8 X GND Ground.
Ground. The exposed pad acts the dominant power dissipation path and should be soldered
Exposed Pad GND
to well designed PCB pads as described in the Application Inform ations Chapter.

Functional Block Diagram

EN CNTL VIN

Power On
Thermal Limit
Reset

Softstart &
Current Limit
Control Logic

FB

0.8V
VOUT

Delay

90% VREF

POK GND

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Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Functional Description
Definitions Output Voltage Programming
Some important terminologies for LDO are specified below. Figure 1 shows a typical application of 2.5V to 1.8V
conversion with a 5.0V control supply. The output voltage
Dropout Voltage
is sensed through a voltage divider and regulated to internal
The input/output voltage differential at which the regulator reference voltage VREF. The output voltage is programmed
output no longer maintains regulation against further as:
reductions in input voltage. Measured when the output drops
VOUT = VREF x (R1+R2) / R1 = 0.8V x (22.5k/10k) = 1.8V
2% below its nominal value. Dropout voltage is affected by
junction temperature, load current and minimum input It’s recommended to maintain 50-100uA through the output
supply requirements. divider network for a tight load and line regulation. The
internal voltage reference is VREF = 0.8V with 1.5% initial
Line Regulation
accuracy. This commands the use of 0.5% or better
The change in output voltage for a change in input voltage. accuracy resistors to build a precision power supply.
The measurement is made under conditions of low
dissipation or by using pulse techniques such that average 5VCC
chip temperature is not significantly affected.
R4 CNTL
10R
Load Regulation
EN POK

The change in output voltage for a change in load current

R3
at constant chip temperature. The measurement is made 10K VOUT
VIN VIN VOUT

uP7704
under conditions of low dissipation or by using pulse
R2
techniques such that average chip temperature is not 12.5K C4
option
significantly affected. C1 FB
1uF NC
C3
Maximum Power Dissipation C2 R1
10uF
4.7uF 10K
GND
The maximum total device dissipation for which the
regulator will operate within specifications.
Quiescent Bias Current
Figure 1. Typical application of 2.5V to 1.8V conversion
Current which is used to operate the regulator chip and is with a 5.0V control supply
not delivered to the load.
Over Current and Short Circuit Protection
The quiescent current IQ is defined as the supply current
used by the regulator itself that does not pass into the The uP7704 features a foldback over current protection
load. It typically includes all bias currents required by the function as shown in Figure 2. The current limit threshold
LDO and any drive current for the pass transistor. level is proportional to VOUT/VNOM and is typically 2.5A when
VOUT = VNOM, where VNOM is the target output voltage. If the
Initialization output continuously demands more current than the
The uP7704 automatically initiates upon the receipt of maximum current, output voltage will eventually drops below
supply voltage and power voltage. A power on reset circuit its nominal value. This, in turns, will lower its OCP threshold
continuously monitors VIN and CNTL pins voltages with level. This will limit power dissipation in the device when
rising threshold levels of 0.6V and 2.7V respectively. over current limit happens.
Chip Enable and Soft Start When output short circuit occurs, the uP7704 will try to
rebuild the output voltage with maximum allowable current
The uP7704 features an enable pin for enable/disable as shown if Figure 3. The duty cycle is about 20% and the
control of the chip. Pulling VEN lower than 0.4V disables averaged short circuit current is about 400mA.
the chip and reduces its quiescent current down to 25uA.
When disabled, an internal MOSFET of 50Ω RDS(ON) turns
on to pull output voltage to ground. Pulling VEN higher than
1.4V enables the output voltage, providing POR is
recognized. The uP7704 features soft start function that
limits inrush current for charging the output capacitors. The
soft start time is typically 4ms.

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Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Functional Description

VIN
(1V/Div)
2.0V VOUT
(20mV/Div)
1.5V

1.0V

0.5V

0V IIN
0A 0.5A 1.0A 1.5A 2.0A 2.5A 3.0A 3.5A
(0.5A/Div)

Figure 2. Current Limit Behavior Figure 3. Output Short Circuit Protection

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Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Absolute Maximum Rating
Control Input Voltage VCNTL (Note 1) ------------------------------------------------------------------------------------------------- -0.3V to +7V
Power Input Voltage VIN -------------------------------------------------------------------------------------------------------------------- -0.3V to +7V
Other Pins --------------------------------------------------------------------------------------------------------------- -0.3V to (VCNTL + 0.3V)
Storage Temperature Range ----------------------------------------------------------------------------------------------------------- -65OC to +150OC
Junction Temperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC
Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V

Thermal Information
Package Thermal Resistance (Note 3)
PSOP-8 θJA ---------------------------------------------------------------------------------------------------------------------------------- 52°C/W
PSOP-8 θJC ---------------------------------------------------------------------------------------------------------------------------------- 5°C/W
WDFN3x3-10L θJA -------------------------------------------------------------------------------------------------------------------------- 60°C/W
WDFN3x3-10L θJC ------------------------------------------------------------------------------------------------------------------------- 5°C/W
Power Dissipation, PD @ TA = 25°C
PSOP-8 ------------------------------------------------------------------------------------------------------------------------------------------- 1.9W
WDFN3x3-10L θJA -------------------------------------------------------------------------------------------------------------------------- 1.67W

Recommended Operation Conditions

Operating Junction Temperature Range (Note 4) ------------------------------------------------------------------------ -40°C to +125°C
Operating Ambient Temperature Range -------------------------------------------------------------------------------------- -40°C to +85°C
Supply Input Voltage, VCNTL ------------------------------------------------------------------------------------------------------------ +3.0V to +5.5V
Power Input Voltage, VIN ------------------------------------------------------------------------------------------------------------ +1.0V to VCNTL

Electrical Characteristics
(VCNTL = 5V, TA = 25OC, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Units

Supply Input Voltage

Control Input Voltage VCNTL VOUT = VREF 2.9 -- 6 V

POR Threshold VCNTLRTH 2.5 2.7 2.9 V
POR Hysteresis VCNTLHYS 0.1 0.2 -- V
Power Input Voltage VIN VOUT = VREF 1.0 -- VCNTL V
Control Input Current in
ICNTL_SD VCNTL = VIN = 5.0V, IOUT = 0A, VEN = 0V -- 20 30 uA
Shutdown
Control Input Current ICNTL VCNTL = VIN = VEN = 5.0V, IOUT = 0A, VOUT = VREF -- 0.3 0.6 mA
Quiescent Current IQ VCNTL = VIN = VEN = 5.0V, IOUT = 0A, VOUT = VREF -- 0.3 0.6 mA
Feedback Voltage
Reference Voltage VREF VCNTL = VIN = VEN = 5.0V, IOUT = 0A. VOUT = VREF 0.788 0.8 0.812 V
Feedback Input Current IFB -- 20 -- nA
1.2V < VIN < 5.0V, VCNTL = VEN = 5.0V, IOUT = 0A. VOUT =
VIN Line Regulation VREF(LINE) -- 0.01 0.1 %/V
VREF
VCNTL Line Regulation VREF(CNTL) 3.0V < VCNTL < 5.0V,VIN = 1.2V, IOUT = 0A. VOUT = VREF -- 0.01 0.1 %/V

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Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Electrical Characteristics
Parameter Symbol Test C onditions Min Typ Max U nits
Feedback Voltage
Load Regulati on VREF(LOAD) 0mA < IOUT < 2.0A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF -- 0.1 0.5 %/A
Load Regulati on over 0mA < IOUT < 2.0A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF,
VREF(TOTAL) -- 0.5 3 %
Temperature -40OC < TJ < 125OC , by desi gn
On Resi stance RDS(ON) IOUT = 100mA, VCNTL = VEN = 5.0V, VOUT = 1.6V -- 150 250 mΩ
D ropout Voltage VDROP IOUT = 2.0A, VCNTL = VEN = 5.0V, VOUT = 1.6V, by desi gn -- 300 500 mV

VOUT Pull Low Resi stance VCNTL = VIN = 5.0V, VEN = 0V, -- 50 -- Ω

Enable

Enable Hi gh Level V EN 1.4 -- -- V

D i sable Low Level V SD -- -- 0.4 V
EN Source C urrent IEN VEN = 0V, VCNTL = 5.0V -- 10 20 uA
EN Input Impedance ZEN -- 65 -- KΩ
Output Voltage Ramp Up
1.5 3.0 4.5 ms
Ti me
PWR OK
FB Power OK Threshold VPOKTH IOUT = 0A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF -- 92 -- %
Power OK Hysteresi s VPOKHYS IOUT = 0A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF -- 8 -- %
POK D elay Ti me From VOUT > 92% VNOM to POK ri si ng 2 4 6 ms
Overcurrent Protection
OC P Threshold Level IOCP VCNTL = VIN = VEN = 5.0V, VOUT = VREF 2.5 2.8 -- A
Averaged Output Short
ISC VCNTL = VIN = VEN = 5.0V, VOUT = 0V 100 400 -- mA
C i rcui t C urrent
Thermal Protection
Thermal Shutdown O
TSD IOUT = 0A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF -- 170 -- C
Temperature
Thermal Shutdown O
TSDHYS IOUT = 0A, VCNTL = VIN = VEN = 5.0V, VOUT = VREF -- 30 -- C
Hysteresi s

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-7 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.

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Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Typical Operation Characteristics
Power On from VCNTL Power On from VIN

VCNTL VIN
(2V/Div) (2V/Div)

VOUT VOUT
(0.5V/Div) (0.5V/Div)

POK POK
(2V/Div) (2V/Div)

IIN IIN
(0.5A/Div) (0.5A/Div)

2.5ms/Div 2.5ms/Div
VCNTL = VIN = 5V, COUT = 470uF, No Load. VCNTL = VIN = 5V, COUT = 470uF, No Load.

Turn On Waveform Power Off from VCNTL

EN
(2V/Div)

VCNTL
VOUT (2V/Div)
(0.5V/Div)

POK
POK
(2V/Div)
(2V/Div)

VOUT
(0.5V/Div)
IIN
(0.5A/Div) IIN
(0.5A/Div)

2.5ms/Div 2.5ms/Div
VCNTL = VIN = 5V, COUT = 470uF, No Load. VIN = 5V, COUT = 470uF, IOUT = 0.2A.

Power Off from VIN Turn Off Waveforms

VIN
(2V/Div)

VOUT
(0.5V/Div)
VOUT VEN
(0.5V/Div) (5V/Div)
POK POK
(2V/Div) (5V/Div)
IIN IIN
(0.5A/Div) (0.5A/Div)

2.5ms/Div 2.5ms/Div
VCNTL = 5V, COUT = 470uF, IOUT = 0.2A. VCNTL = VIN = 5V, COUT = 470uF, IOUT = 0.2A.

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Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Typical Operation Characteristics
Load Transient Response Dropout Voltage vs. Output Current

VOUT 300mV
(50mV/Div)

Dropout Voltage (mV)

250mV

200mV

150mV
IOUT
(1A/Div) 100mV

50mV

0mV
0A 0.5A 1.0A 1.5A 2.0A

2.5us/Div Output Current (A)

VCNTL = 5V, COUT = 4.7uF, IOUT = 0A to 1.6A

Quiescent Current vs. Input Voltage Enable/Disable Threshold vs. Input Voltage
400 1.2
Disable
350 1.1
Enable/Disable Threshold (V)

Enable
Quiescent Current (uA)

300 1
250 0.9
200 0.8
150 0.7
100 0.6
50 0.5
0 0.4
2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5
VIN = VCNTL (V) VIN = VCNTL (V)
VOUT = VREF VOUT = VREF

Output Voltage Line Regulation Output Voltage Load Regulation

0.1 0.9

0.7
Output Voltage Variation (%)

0.05
Output voltage Variation (%)

0.5
0
0.3
-0.05
0.1
-0.1
-0.1
-0.15 -0.3

-0.2 -0.5
2.5 3 3.5 4 4.5 5 5.5 0 0.5 1 1.5 2
VIN = VCNTL (V) Output Current (A)

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Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Typical Operation Characteristics
On Resistance vs. Input Voltage Output Voltage vs. Temperature
200 1
190

Output Voltage Variation (%)

180 0.5
On Resistance (mΩ)

170
0
160
150 -0.5
140
130 -1
120
-1.5
110
100 -2
2.5 3 3.5 4 4.5 5 5.5 -50 0 50 100 150
Control Input VCNTL (V) Junction Temperature (OC)
VOUT = 1.8V

Current Limit
Output Voltage (V)

2.0V

1.5V

1.0V

0.5V

0V
0A 0.5A 1.0A 1.5A 2.0A 2.5A 3.0A 3.5A

Output Current (A)

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Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Application Information
The uP7704 is a high performance linear regulator This allows for the device being some distance from any
specifically designed to deliver up to 2A output current with bulk capacitance on the rail. Additionally, bulk capacitance
very low input voltage and ultra low dropout voltage. With may be added closely to the input supply pin of the uP7704
dual-supply configuration, the uP7704 operates with a wide to ensure that VIN does not sag, improving load transient
input voltage VIN range from 1.2V to 5.5V and is ideal for response.
applications where VOUT is very close to VIN . Output capacitor: A minimum bulk capacitance of 10uF,
Supply Voltage for Control Circuit VCNTL along with a 0.1uF ceramic decoupling capacitor is
Unlike other linear regulators that use a P-Channel recommended. Increasing the bulk capacitance will improve
MOSFET as the pass transistor, the uP7704 uses an N- the overall transient response. The use of multiple lower
Channel as the pass transistor. N-Channel MOSFET value ceramic capacitors in parallel to achieve the desired
provides lower on-resistance and better stability meeting bulk capacitance will not cause stability issues. Although
stringent requirements of current generation designed for use with ceramic output capacitors, the uP7704
microprocessors and other sensitive electronic devices. is extremely tolerant of output capacitor ESR values and
The drain of N-Channel MOSFET is connected to VIN and thus will also work comfortably with tantalum output
the source is connected to VOUT. This requires that the capacitors.
supply voltage VCNTL for control circuit is at least 1.5V higher Thermal Consideration
than the output voltage to provide enough overdrive capability The uP7704 integrates internal thermal limiting function to
for the pass transistor thus to achieve low dropout and fast protect the device from damage during fault conditions.
transient response. It is highly recommended to bias the However, continuously keeping the junction near the thermal
device with 5V voltage source if available. shutdown temperature may remain possibility to affect
Use a minimum 1uF ceramic capacitor plus a 10Ω resistor device reliability. It is highly recommended to keep the
to locally bypass the control voltage. junction temperature below the recommended operation
Input/Output Capacitor Selection condition 125OC for maximum reliability.

The uP7704 has a fast transient response that allows it to Power dissipation in the device is calculated as:
handle large load changes associated with high current PD = (VIN - VOUT) x IOUT + VCNTL x ICNTL
applications. Proper selection of the output capacitor and It is adequate to neglect power loss with respective to
its ESR value determines stable operation and optimizes control circuit VCNTL x ICNTL when considering thermal
performance. The typical application circuit shown in Figure management in uP7704 Take the following moderate
1 was tested with a wide range of different capacitors. The operation condition as an example: VIN = 3.3V, VOUT = 1.5V,
circuit was found to be unconditionally stable with capacitor IOUT = 1A, the power dissipation is:
values from 10uF to 1000uF and ESR ranging from 0.5mΩ
to greater then 75mΩ. PD = (3.3V- 1.5V) x 1A = 1.8W
This power dissipation is conducted through the package
5VCC into the ambient environment, and, in the process, the
R4 temperature of the die (TJ) rises above ambient. Large power
CNTL
10R dissipation may cause considerable temperature raise in
EN POK
the regulator in large dropout applications. The geometry
R3 of the package and of the printed circuit board (PCB) greatly
10K VOUT influences how quickly the heat is transferred to the PCB
VIN VIN VOUT
uP7704

R2
and away from the chip. The most commonly used thermal
C4
12.5K
option
metrics for IC packages are thermal resistance from the
C1 FB
1uF NC chip junction to the ambient air surrounding the package
R1 C3
C2
10K 10uF (θJA):
4.7uF
GND
θJA = ( TJ -TA ) / PD
θJA specified in the Thermal Information section is measured
in the natural convection at TA = 25OC on a high effective
Figure 1. Typical Application Circuit thermal conductivity test board (4 Layers, 2S2P) of JEDEC
Input capacitor: A minimum of 4.7uF ceramic capacitor 51-7 thermal measurement standard. The case point of
is recommended to be placed directly next to the VIN pin.

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Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Application Information
θJC is on the exposed pad for PSOP-8 package.
Given power dissipation PD, ambient temperature and

VOUT
thermal resistance θ JA, the junction temperature is

GND

NC
FB
calculated as:
TJ = TA + ΔTJA = TA + PD x θJA

8
7
6
5
To limit the junction temperature within its maximum rating,

uP7704
GND
the allowable maximum power dissipation is calculated
as:

1
2
3
4
PD(MAX) = ( TJ(MAX) -TA ) /θJA
where T J(MAX) is the maximum operation junction

VIN
POK
EN

CNTL
temperature 125OC, TA is the ambient temperature and the
θJA is the junction to ambient thermal resistance. θJA of
PSOP-8 packages is 75OC/W on JEDEC 51-7 (4 layers, Figure 4. Recommended PCB Layout.
2S2P) thermal test board with minimum copper area. The
Layout Consideration
maximum power dissipation at TA = 25OC can be calculated
as: 1. Place a local bypass capacitor as closed as possible
O O O to the VIN pin. Use short and wide traces to minimize
PD(MAX) = (125 C - 25 C) / 75 C/W = 1.33W
parasitic resistance and inductance.
The thermal resistance θJA highly depends on the PCB
2. The exposed pad should be soldered on GND plane
design. Copper plane under the exposed pad is an effective
with maximum area and with multiple vias to inner layer
heatsink and is useful for improving thermal conductivity.
of ground place for improving thermal performance.
Figure 3 show the relationship between thermal resistance
θJA vs. copper area on a standard JEDEC 51-7 (4 layers, 3. Connect voltage divider directly to the point where
2S2P) thermal test board at TA = 25OC. A 50mm2 copper regulation is required. Place voltage divider close to
plane reduces θJA from 75OC/W to 52OC/W and increases the device.
maximum power dissipation from 1.33W to 1.9W.

100

90
Thermal Resistance θ JA (OC/W)

80

70

60

50

40

30
0 10 20 30 40 50 60 70
Copper Area (mm2)

Figure 3. Thermal Resistance θJA vs. Copper Area

Figure 4 illustrated the recommended PCB layout for best
thermal performance.

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Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Package Information
PSOP-8 Package

4.80 - 5.00
0.70 REF 1.27 REF
3.00 BSC

1.50 REF
3.00 REF

5.80 - 6.20
3.80 - 4.00
7.00 REF

2.20 REF
5.50 REF

2.20 BSC
4.00 REF

1.27 BSC 0.32 - 0.52

Recommended Solder Pad Layout

1.45 - 1.60

0.20 BSC 0.18 - 0.25 1.75 MAX

0.05 - 0.25

0.40 - 0.90 3.81 BSC

Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.

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Rev. F00, File Name: uP7704-DS-F0001
 uP7704
Package Information
WDFN3x3-10L Package

2.90 - 3.10 0.35 - 0.45 2.25 - 2.35

6 10

1.55 - 1.65
2.90 - 3.10

5 1

0.50 BSC 0.18 - 0.28

2.25 - 2.35
0.80 MAX

1.55 - 1.65
1.95 - 2.05
3.55 - 3.65
0.20 REF 0.00 - 0.05

0.50 BSC 0.18 - 0.28

Recommended Solder Pitch and Dimensions

Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.

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Rev. F00, File Name: uP7704-DS-F0001