Simulation of MOS Capacitor for C/Vg Characterization

Ajay K. Srivastavaa,1 E. Fretwursta, R.Klannera

Internal note (within AGIPD collaboration)

Abstract

For the European XFEL a silicon pixel detector with a high dynamic range (105 12 keV photons per

pixel per pulse) and a radiation tolerance up to 1GGy (≈1016 12 keV photons/cm2) will be built. In the

absence of bulk damage (threshold energy 300 keV), the study of surface damage in silicon pixel

detectors due to x-ray irradiation is very important for the long term performance of these devices.

The gated diode test-structures fabricated by CiS (Institut für Milcrosensorik GmbH, Erfurt,

Germany) are used for surface damage analysis and the current-voltage (I/Vg) and capacitance-voltage

(C/Vg) characteristics as function of gate bias and frequency have been measured for different doses.

The aim is to determine the relevant surface damage parameters (oxide charge density Nox and

interface trap density Dit at Si-SiO2 interface) for detailed comparison of experimental data and

simulations of MOS test structures and the microscopic parameters will be also implemented in

TCAD for the simulation of radiation hard silicon pixel detector development for AGIPD (Adaptive

Gain Integrating Pixel Detector). The C/Vg technique is broadly used to study the surface charge

effects (Nox) and the interface trap behaviour on the slope of the C/Vg. In the present work, very

preliminary simulation results and observations on the MOS-test structures are presented using ISE T-

CAD DESSIS 2-D device simulator. The simulation results are found in good agreement with the

experimental data.

PACS: 85.30.De; 29.40.Wk; 29.40.Gx

Keywords: Gated diode, MOS capacitor, Si sensor, Surface damage, Capacitance, Conductance, Simulation.

1
Corresponding Author: Ajay Kumar Srivastava, Institute for Experimental Physics, University of Hamburg, Germany , Luruper Chaussee
149, D-22761 Hamburg, DESY Bldg., Room No. 67b/24, Tel: 040-8998-4726, Fax No. 040-8998-2170, Email: [email protected]
1. Introduction

European X-Ray Free-Electron-Laser experiment, X-FEL at DESY, Hamburg will be

expected to start in 2013 and provide fully coherent, < 100 fs long X-ray pulses. The high

intensity per pulse will allow recording diffraction pattern of single macromolecules or small

crystal in single shot [1]. For AGIPD (Adaptive Gain Integrating Pixel Detector) of XFEL,

n+n-p+ Si pixel sensors are proposed as first design idea [2] for higher performance in the

presence of high instantaneous photon fluxes.

In the absence of bulk damage, surface damage affects the performance of Si pixel sensors

and it will degrade the macroscopic performance of used Si sensors after irradiations in terms

of change of depletion voltage due to delayed depletion depth (15-20 V full depletion voltage

increase), increases of surface current due to increases of dominant interface trap density near

to mid gap of Si (shot noise), change of interstrip capacitance due to change of fixed positive

oxide charges in oxide and interface trap (change of noise), and change of interstrip

resistance due to change of surface current (change of spatial resolution) [2-3]. Therefore,

systematic investigations of surface damage on sensors are very crucial for long term

performance of XFEL experiment.

Physicists have already reported the effect of surface damage on current-gate voltage (I/Vg)

and CMOS capacitance-gate voltage (C/Vg) characteristics of gate controlled diode [4-6].

Several attempts has been made to describe the donor and acceptor nature of interface trap

using conductance- gate voltage (G/Vg) technique and it has been found that donors lie just

below half of the band gap and acceptors are in the upper half of the band gap [7]. A lot of

efforts have been made already made in order to study the effect of interface trap on C/Vg and

G/Vg characterstics of MOS capacitor but detailed understanding of theses effect is not well

understood [8-10]. Therefore simulation is recommended for detailed understanding of

surface charge effects (oxide charge density, and interface charge trap density).

Here, we have shown the 2-D detailed simulation of MOS test structure for C/Vg analysis

to see the effect of different physical and process parameters using ISE T-CAD DESSIS 2-D
device simulation. Within the framework of AGIPD collaboration [11], 2-D numerical device

simulation has emerged as a practical means for approaching the design of radiation-hardened

devices. In particular, device simulations can allow fast and relatively inexpensive

predictions of detector performance in various radiation environments. In this work, the

simulator has been rigorously calibrated against experimental data.

This paper is organized in this way, in sections 2 below, test structure design are

summarized. Simulation procedures are presented in section 3. Result and discussions are

covered in section 4. Conclusions are eventually drawn in section 5.

2. Test structure design

For simulation purpose, we have considered a simple two-dimensional geometry of test

structure, consisting of a Metal-Oxide-Semiconductor (MOS) of gate width of 50 µm and

device depth (WN) of 50 µm is shown in Fig.1a. Fig.1b shows the rectangular grid of MOS

capacitor of 50 x 50 µm2. The gate area of 4.04 x 10-3 cm2 is normalized from the design of

gated diode fabricated at CiS (Institut für Milcrosensorik GmbH, Erfurt), Germany.

In MOS test structure, the doping concentration (ND) was set to 1.28x1012cm−3,

corresponding to a resistivity of ~ 3.4 kΩ cm) of a high resistivity n-type Si substrate and the

ND was 6.28 x1012cm−3 (experimentally calculated from the slope of 1/C2 versus Vg in the

depletion region of MOS) in the depletion region of MOS test structure (up to 20 µm from Si-

SiO2 interface). Therefore non-uniform doping profile obtained in the bulk of Si material.

The insulator SiO2 thickness (tox) was taken to 0.405 µm in the simulation. The value of oxide

charge density (Nox) was taken from the experimental measurement (from flat band voltage,

Vfb) of non-irradiated gated diode and interface charge trap density (Nit) of 2.1 x 1010 cm-2

was calculated from the experimental measured surface current (Iox). The MOS test structure

is assumed to be an ideal (only Nox) and in practical non-irradiated MOS test structure (both

Nox, Nit present). In simulation, it was assumed that there was donor, acceptor interface trap at
mid band gap of silicon, acceptor and donor interface trap at trap energy level (Et) of 0.16 eV

from conduction band (homogeneous distribution in the band gap of Si), and also double

acceptor at 0.16 eV and 0.26 eV from the conduction band just to check the shape of the C/Vg

characterstics in the different section of simulated results. The effective-capture cross-section

(бeff) of charge carrier of 7 x 10-17 cm2, time constant (‫ح‬eff) of 130 µs , surface recombination

velocity (S0) of 2.4 cm/sec and thermal velocity of charge carriers ( vth (n/p)) of 2 x 107

cm/sec was used for all simulations of non-unirradiated MOS test structure. In the present

work, time constant is modelled as effective life time of charge carriers. For small-signal AC

analysis for C/Vg characteristics simulation of MOS test structure is performed at TCAD

default temperature (Tlattice=300K), we have applied 0.1 volt AC voltage with DC gate contact

voltage of -1 to -12 volt for three range of frequency (f) i.e. 5, 10 and 15 kHz.

Homogeneous (reflecting) Neumann boundary conditions are applied on the non-

contacted outer ages of the structures. The ohmic contact on the backside is on ground and

the front side of MOS with aluminium gate are implemented by Dirichlet boundary

conditions. ØMS (work function difference between aluminium metal and n-Si) of -0.69 volt

was used for given doping concentration.

3. Simulation procedures

The above-mentioned MOS test structure design is used to study the effect of different

physical and process parameters on the C/Vg characteristics of MOS test structure using the

two-dimensional device simulation software program ISE T-CAD DESSIS [12].

Simulations in 2-D were performed using a device simulation software package ISE-T-

CAD of Integrated Systems Engineering (ISE). Subprograms MDRAW-ISE and DESSIS-ISE

of ISE-TCAD were used to perform the physical simulations and subprograms TECPLOT-

ISE and INSPECT-ISE were used for the visualization and analysis of the result data,

respectively.
 DESSIS-ISE: DESSIS-ISE simulates the electrical characteristics of semiconductor

devices. It contains a comprehensive set of physical models, handles 2D and 3D geometries,

mixed-mode circuit simulation with compact models, and numeric devices. In addition, one is

able to perform mixed-mode transient simulations in 3D to study the charge collection

characteristics of the detector structure. At each simulation step, the Poisson equation along

with the continuity equations is solved using a Newton iteration method. A quasi-stationary

simulation is used to ramp the bias voltage in a way that at each bias step the simulation is

restarted after alternation of the parameter values and the boundary conditions.

INSPECT-ISE: INSPECT-ISE permits the analysis of the simulated x–y data, the

extraction of characteristic data from TECPLOT-ISE. The final plots can be printed in ps or

encapsulated ps (eps) form and .png form.

DESSIS solves the Poisson equation, the continuity equation, the energy–balance

equation and the lattice heat equation for holes and electrons and traps. All of the above

equations describe the static and dynamic behaviour of charge carriers and interface trap in

semiconductors under the influence of the electric field. The physical models used throughout

the simulations were picked up from the ISE-DESSIS physical model library.

Doping dependent Shockley-Read-Hall (SRH) recombination, Auger recombination,

charge trap model at Si-SiO2 interface, impact ionization, doping-dependent mobility, high

field saturation models, surface recombination, lucky physical model for gate current is

taken into account in the present simulation.

For C/Vg characteristics of MOS test structure, we have done mixed mode simulation i.e.

device and SPICE (Simulation Program of Integrated Circuit with Emphasis) in ISE T-CAD

DESSIS. For small signal AC analysis to obtain small signal admittance (Y) matrix, it will

current response at a node to a small signal voltage (v) and can be expressed as follows,

i = Y .v = (G + jωC ).v [1]

The capacitance will be measured in parallel mode and AC analysis of MOS test

structure gives the conductance (G) and capacitance (C) matrix for every gate voltage. Oxide

capacitances (Cox ), high frequency inversion capacitance (Cinv ), flat band voltage (Vfb) (for

known Nox from experimental result), interface trap density (Nit ) (for single level trap of

homogeneous distribution) calculation was done from standard equation for this numerical

modelling just for cross check our simulated result [13-14].

4. Result and discussions

In this paper, numerical device simulation has been exploited in order to see the effect of

various physical and process parameters (Nox, Nit, f, resistivity ρ, interface trap types) , which

is taken into account for surface damage analysis on C/Vg characteristics.

Fig.2a shows the C/Vg characteristics of an ideal (no interface trap only Nox) and practical

non-irradiated MOS test structure (with Nox and Nit both). When there was only Nox used then

Vfb was -5.32 volt but when I have taken the single level acceptor trap at mid gap of Si with

Nox then Vfb was -5.69 volt. It has been found that C/Vg curve is stretched (depletion region)

in the presence of interface trap due to movement of Fermi level in Si band gap and Vfb is

modified up to 0.37 volt due to interface trap. Therefore, we can say flat band voltage (Vfb )

will be modify by Nox and Nit both and there is no change observed in CMOS oxide

capacitance (Cox) and high frequency inversion capacitance (Cinv).

Fig.2 (b) shows the G/Vg of non-irradiated MOS test structure in presence of acceptor trap

at mid gap and no trap only Nox (ideal MOS). In order to understand the G/Vg characteristics,

we can divide G/Vg characteristics into three zones i.e. conductance in accumulation region

(Gaccumulation), conductance peak (Gpeak) and conductance in inversion region (Ginversion).

For the first zone, Gaccumulation is same for an ideal MOS and practical MOS test structure and

it is related to the bulk/series resistance (Rs) of the bulk silicon material. It is observed that Rs

remain constant for same device depth (WN). Gpeak is very sensitive to interface trap

concentration at certain gate bias, traps will be active and thus giving rise to their long peak
in the presence of traps (practical MOS test structure). Ginversion is affected by constant doping

concentration in the depletion region of MOS test structure and measurement temperature.

It has been found that that Gpeak is at almost around Vfb because interface traps are very

sensitive at this gate bias and thus giving long peak.

Fig.3 shows the comparison of data and simulation of C/Vg characteristics for practical

MOS test structure at three different frequencies (5 , 10 and 15 kHz) for single level donor

interface trap at mid gap with same trap concentration as per the previous acceptor interface

level trap. There is in good agreement observed with experimental data for three different

frequencies. Thus, we can say that the simulator has been rigorously calibrated against

experimental data. It has been found that there is no frequency dispersion effect in strong

accumulation (change of Cox with frequency) for this frequency range in non-irradiated MOS

test structure because of low Nit.

In Fig.4, the influences of different interface trap types on C/Vg characteristics are shown.

It has been found that interface trap modified Vfb but different trap shows a little change in

slope of the C/Vg curve in the depletion to inversion region because of fixed low Nit.

The influence of Nox is clearly visible in Fig.5 just for cross-check our simulated result,

when Nox increases from 1.97 x 1011 cm-2 to 2.67 x 1011 cm-2 (Nox experimental) at 10 kHz

frequency then Vfb also increases. It is well known effect flat band shift will observe when

increasing Nox.

In Fig.6, C/Vg characteristics for High resistivity Silicon, HRS (3.4 kΩ cm) is differ from

low resistivity silicon, LRS (200 Ω cm) and it is due to high potential drop and increase of

debye length.

5. Conclusions

We have shown the good description of C/Vg characterstics as function of low frequency

where the interface trap will respond and there is good agreement observed in the experiment

results and simulation. It should be noted that the very preliminary simulation results on non-

irradiated MOS capacitor for C/Vg characterization are presented for the surface charge and
resistivity effect and the detailed comparison of experiment and simulation for irradiated

MOS capacitors at different high frequency are under way.

Acknowledgements

The author would like to thank the XFEL company for support and also would like to

thank to the peoples involved in the development of AGPID for XFEL experiment from

DESY (Deutsches Elektronen Synchrotron), PSI (Paul Scherer institute), Switzerland and

University of Bonn, Germany for constant interest and support. This work was profited from

the infrastructure grant of the Helmholtz Alliance “Physics at the Terascale”.

References

[1] The European X-Ray Laser Project XFEL, http://xfel.desy.de/

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surface effects of silicon detectors”, C. Becker., Nucl. Instr. and Meth A 444 (2000) 605-613.

[6] “Study of the Radiation Hardness of Silicon Sensors for the XFEL” poster presented in

IEEE NSS 2008, Dresden, Germany, E. Fretwurst, et al, conference record N30-400.

[7] “Donor/Acceptor nature of radiation induced interface trap”, P.J. McWhorter., IEEE

Transaction on Nuclear Science, Vol. 35, No.6, December 1988.

[8] “Generation and Transformation of Interface traps in MOS structures”, T.P. Ma,

Microelectronics Engineering 22(1993) 197.200.

Density of states of pb1 Silicon Dangling Centers”, P.M. Lenahan et al., IEEE Trans. Nucl.

Sci., vol. 49, 2708 (2002).

[10] “Interface trap transformation in radiation or hot electron damage MOS structures”,

Semicond. Sci. Technol., vol.4, p.1061, 1989.

[11] Adaptive gain integrating pixel detectors, web page (2010).

URL http://hasylab.desy.de/science/developments/detectors/agipd

[12] Integrated Systems Engineering (ISE), Release 6.1, 2005.10, ISE website. Available

online: /http://www.ise.ch/S.

[13] Physics of Semiconductors devices, S.M.Sze, John. Wiley and sons, second edition,

1981 pp. 390-391.

[14] “Characterization of ionization induced surface effects for the optimization of silicon

detectors for particle physics applications” Ph.D. thesis, Jens WÜstenfeld, university of

Dortmund, June 2001.

Figure.1a: Cross-section of MOS test structure used in the simulation work.

Figures.1b: Rectangular grid of MOS test structure (50 x 50 µm2).

Figure.2 (a): C/Vg characteristics of non-irradiated MOS structure in presence of acceptor

trap at mid gap and no trap only Nox (Ideal MOS).

Figure.2 (b): G/Vg of non-irradiated MOS test structure in presence of acceptor trap at mid

gap and no trap only Nox (Ideal MOS).

Figure.3: C/Vg of non-irradiated MOS test structure in the presence of donor level trap at mid

gap of Si for three frequency (a) 5 kHz (b) 10 kHz (c) 15 kHz : comparison with data from

experiment.

Figure.4: C/Vg of non-irradiated MOS test structure at one fixed frequency 10 kHz for

different traps types.

Figure.5: C/Vg of non-irradiated MOS test structure at one fixed frequency 10 kHz for

different oxide charge density.

Figure.6: C/Vg of non-irradiated MOS test structure at one fixed frequency 10 kHz for single

level acceptor trap, Ec-Et=0.16 eV (from conduction band) for two resistivity (low and high)

of Si material.
LIST OF FIGURES

FIG.1 a
FIG.1 b

FIG.2 a
FIG.2 b
Fig.3

(a)
(b)

(c)
FIG.4
FIG.5

FIG.6