SV Uvm Ramdas
SV Uvm Ramdas
SV Uvm Ramdas
Verilog
Ramdas M
Expert Verification Engineer
Static Gate
Formal Power
Timing Level
Verification Estimation
Analysis Simulation
Layout Design
1/4/2016 Tapeout
Verification with System Verilog 7
Verification in a SOC Project Life Cycle
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Directed vs. Random Testing
initial : clock_drive
begin
clk = 1’b0;
forever #10 clk = ~clk;
end : clock_drive
• Example
x = 0;
repeat (16)
begin
$display(“%d”, x++);
end
Syntax:
enum [enum_base_type] { enum_name_declaration {,enum_name_declaration} }
enum_base_type: default is int
for (int i=0; i < q1.size; i++) // step through a list using integers (NO POINTERS)
begin … end
program helloWorld();
initial
begin: hello
$display("Hello World");
end
initial
begin: there
$display(“Hello There”);
end
endprogram: helloWorld
• Overloading
– deals with multiple methods in the same class with the same name but
different signatures
– lets you define a similar operation in different ways for different data
• Overriding
– deals with two methods, one in a parent class and one in a child class,
that have the same signature
– lets you define a similar operation in different ways for different object
types.
• Example:
• constraint a_le_b { a <= b; }
• constraint c_eq_10 {c == 10;}
• constraint b_in_range { b >= 2 && b <= 8; }
• constraint all_gt_0 {a > 0; b > 0; c > 0;}
• Advanced note:
a -> b is equivalent to !a || b
constraint c1 {
foreach ( A[i] )
A[i] inside {2, 4, 6, 8, 10};
}
constraint c2 {
foreach ( A[k] )
(k < A.size-1) -> A[k+1] > A[k];
}
endmodule : test_rand
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Sequential vs.. Concurrent Blocks
• Sequential Block: • Concurrent Block
– Simulator executes statements – Simulator executes statements
in a sequential block in in a concurrent block in parallel
sequence – It starts executing all
– It finishes the current statements simultaneously
statement, then begins the – You can not know the order in
next which it actually executes
– You always know the order in statements scheduled for the
which it actually executes the same simulation time
statements – The simulator exits the block
– The simulator exits the block after finishing the latest
after finishing the last statement.
statement – A return statement in the
context of fork..join is illegal.
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Process and Threads
• Threads are created via fork…join
• Threads execute until a blocking statement
– wait for: (event, mailbox, semaphore, variable, etc.)
• $exit terminates the main program thread
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Events Trigger Types [2]
• Nonblocking event trigger
Example
– They are triggered using always @(posedge clk)
->> operator. begin
– The statement executes if (counter == 2)
->> a;
without blocking and it
counter++;
creates a nonblocking assign end
update event in the time in
which the event occurs. initial
begin
– The effect of this event is
forever @(a)
felt during the nonblocking $display("event a
assignment region of a triggered @ %0t, $time);
simulation cycle. end
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Waiting for an event
Example
• @ is used to wait for an module event_testing ();
event. event a, b, c;
bit clk;
• The @ operator blocks the always @(posedge clk)
calling process until the -> a;
always @(negedge clk)
given event is triggered. -> b;
always @(a or b)
-> c;
initial
begin
clk = 1'b0;
forever #10 clk = !clk ;
end
endmodule
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Event Variables [1]
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Event Variables [2]
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Semaphores
• Semaphores are typically used for mutual exclusion, access
control to shared resources, and basic synchronization
• Can be described as counters used to control access to
shared resources by multiple processes [threads].
– eg: Accessing a shared bus
• Implemented as a bucket with fixed number of keys
– Processes using semaphores must first procure a key before
executing
– All others must wait until a sufficient number of keys is
returned to the bucket.
Method Use
new() Create a semaphore with
specified number of keys.
put() Return one or more keys
back.
get() Obtain one or more keys.
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Semaphore example
module semaphore_test (); initial
semaphore spr = new(2); begin:init2
#5 spr.get(2);
initial $display(" inital2 takes 2
begin:init1 keys at %0t",$time);
#1 spr.get(1); #5 spr.put(1);
$display("initial1 takes $display(" inital2 returns
1 key at %0t", $time); 1 key at %0t",$time);
#6 spr.put(1); end
$display("initial1 returns endmodule: semaphore_test
1 key at %0t",$time);
#1 spr.get(1);
$display("initial1 takes 1
key at %0t", $time);
end
Output:
# initial1 takes 1 key at 1
# initial1 returns 1 key at 7
# inital2 takes 2 keys at 7
# inital2 returns 1 key at 12
# initial1 takes 1 key at 12
# q -f
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Mailboxes
• Mailbox is a communication mechanism that allows
messages to be exchanged between different processes.
– Data can be sent to a mailbox by one process and retrieved
by another
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Mailbox example
module mailbox_ex (); mb_size = mb.num();
class Xaction; for (int i=0; i<mb_size; i++)
rand bit [2:0] addr; begin: dis_l
endclass Xaction d_x;
typedef mailbox #(Xaction) mbx; mb.get(d_x);
mbx mb = new (); $display("Addr = %h",
d_x.addr);
initial end: dis_l
begin: t end: t
Xaction xaction; endmodule: mailbox_ex
int mb_size;
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www.verificationexcellence.in
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System Verilog Scheduling
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System Verilog Enhanced Scheduling
• Testbench activated
with a call to run_test()
which starts build
phases