CHAPTER-1

INTRODUCTION

Since many years people try to replace human work with machines. Machines called
robots are faster and more effective than people. The term robotics is practically defined as the
study, design and use of robot systems for manufacturing. Robots are generally used to perform
unsafe, hazardous, highly repetitive, and unpleasant tasks. They have many different functions
such as material handling, assembly, arc welding, resistance welding and machine tool load and
unload functions, painting, spraying, etc. Many elements of robots are built with inspiration from
the nature. Construction of the manipulator as the arm of the robot is based on human arm. The
robot has the ability to manipulate objects such as pick and place operations. It is also able to
function by itself. The development of electronic industry robot system technology has been
expanded increasingly. As one such application, the service robot with machine vision capability
has been developed recently In this highly developing society time and man power are critical
constrains for completion of task in large scales. The automation is playing important role to save
human efforts in most of the regular and frequently carried works. One of the major and most
commonly performed works is picking and placing of jobs from source to destination. Present day
industry is increasingly turning towards computer-based automation mainly due to the need for
increased productivity and delivery of end products with uniform quality. The inflexibility and
generally high cost of hard-automation systems, which have been used for automated
manufacturing tasks in the past, have led to a broad based interest in the use of mechanical arm
capable of performing a variety of manufacturing functions in a flexible environment and at lower
costs. The use of Industrial mechanical arm characterizes some of contemporary trends in
automation of the manufacturing process. However, present day industrial mechanical arm also
exhibit a monolithic mechanical structure and closed-system software architecture. They are
concentrated on simple repetitive tasks, which tend not to require high precision. The pick and
place mechanical arm is a human controlled based system that detects the object, picks that object
from source location and places at the desired location. For detection of object, human detect
presence of object and move machine accordingly.

1
 CHAPTER-2

LITERATURE SURVEY

Robotics researchers regularly endow robot platforms with new capabilities that increase
the breadth of potential applications and push the boundaries of autonomy. In contrast, industrial
automation is driven by a pragmatism dictated by the need to optimize throughput and reliability.
The hope of both is that, as multi-purpose robotic platforms become more capable, they will be
able to take over an increasing fraction of the tasks currently handled by application specific, fixed
installation automation, thereby granting all applications greater levels of modularity and adapt
ability which is expressed in [1]. We are now seeing an acceleration of the rate at which research
robotics feeds into engineering practice. In this project we are trying to establish both wireless
communication between the mobile robot and the remote base station, and serial communication
between the remote base station and the GUI application. The base station requires the serial
communication with the GUI application and also needs to be hardwired with the radio packet
controller

2
 CHAPTER-3

EXISTING SYSTEM

A robot is a mechanical device that performs automated tasks and movements, according
to either pre-defined program or a set of general guidelines and direct human supervision. These
tasks either replace or enhance human work, such as in manufacturing, contraction or
manipulation of heavy or hazardous material. Robot is an integral part in automating the flexible
manufacturing system that one greatly in demand these days. Robots are now more than a
machine, as robots have become the solution of the future as cost labour wages and customers
demand. Even though the cost of acquiring robotic system is quite expensive but as today's rapid
development and a very high demand in quality with IS0 standards, human are no longer capable
of such demands. Research and development of future robots is moving at a very rapid pace due to
the constantly improving and upgrading of the quality standards of products..

3
 CHAPTER-4

IMPLEMENTATION

4.1 Block Diagram

4.2 Modular Description

4.2.1 Regulated Power Supply (RPS)

All digital circuits require regulated power supply. In this article we are going to learn how
to get a regulated positive supply from the mains supply.

Figure 1 shows the basic block diagram of a fixed regulated power supply. Let us go through each
block.

TRANSFORMER

4
A transformer consists of two coils also called as “WINDINGS” namely PRIMARY &
SECONDARY.
They are linked together through inductively coupled electrical conductors also called as CORE. A
changing current in the primary causes a change in the Magnetic Field in the core & this in turn
induces an alternating voltage in the secondary coil. If load is applied to the secondary then an
alternating current will flow through the load. If we consider an ideal condition then all the energy
from the primary circuit will be transferred to the secondary circuit through the magnetic field.

So

The secondary voltage of the transformer depends on the number of turns in the Primary as well as
in the secondary.

Rectifier
A rectifier is a device that converts an AC signal into DC signal. For rectification purpose we use a
diode, a diode is a device that allows current to pass only in one direction i.e. when the anode of
the diode is positive with respect to the cathode also called as forward biased condition & blocks
current in the reversed biased condition.

5
Rectifier can be classified as follows:
Half Wave rectifier

This is the simplest type of rectifier as you can see in the diagram a half wave rectifier consists of
only one diode. When an AC signal is applied to it during the positive half cycle the diode is
forward biased & current flows through it. But during the negative half cycle diode is reverse
biased & no current flows through it. Since only one half of the input reaches the output, it is very
inefficient to be used in power supplies.

Full wave rectifier

Half wave rectifier is quite simple but it is very inefficient, for greater efficiency we would like to
use both the half cycles of the AC signal. This can be achieved by using a center tapped
transformer i.e. we would have to double the size of secondary winding & provide connection to
the center. So during the positive half cycle diode D1 conducts & D2 is in reverse biased

6
condition. During the negative half cycle diode D2 conducts & D1 is reverse biased. Thus we get
both the half cycles across the load.
One of the disadvantages of Full Wave Rectifier design is the necessity of using a center tapped
transformer, thus increasing the size & cost of the circuit. This can be avoided by using the Full
Wave Bridge Rectifier.
Bridge Rectifier

As the name suggests it converts the full wave i.e. both the positive & the negative half cycle into
DC thus it is much more efficient than Half Wave Rectifier & that too without using a center
tapped transformer thus much more cost effective than Full Wave Rectifier.

Full Bridge Wave Rectifier consists of four diodes namely D1, D2, D3 and D4. During the
positive half cycle diodes D1 & D4 conduct whereas in the negative half cycle diodes D2 & D3
conduct thus the diodes keep switching the transformer connections so we get positive half cycles
in the output.

7
If we use a center tapped transformer for a bridge rectifier we can get both positive & negative
half cycles which can thus be used for generating fixed positive & fixed negative voltages.

Filter Capacitor

Even though half wave & full wave rectifier give DC output, none of them provides a constant
output voltage. For this we require to smoothen the waveform received from the rectifier. This can
be done by using a capacitor at the output of the rectifier this capacitor is also called as “FILTER
CAPACITOR” or “SMOOTHING CAPACITOR” or “RESERVOIR CAPACITOR”. Even after
using this capacitor a small amount of ripple will remain.
We place the Filter Capacitor at the output of the rectifier the capacitor will charge to the peak
voltage during each half cycle then will discharge its stored energy slowly through the load while
the rectified voltage drops to zero, thus trying to keep the voltage as constant as possible.

8
If we go on increasing the value of the filter capacitor then the Ripple will decrease. But then the
costing will increase. The value of the Filter capacitor depends on the current consumed by the
circuit, the frequency of the waveform & the accepted ripple.

Where,
Vr= accepted ripple voltage.( should not be more than 10% of the voltage)
I= current consumed by the circuit in Amperes.
F= frequency of the waveform. A half wave rectifier has only one peak in one cycle so F=25hz
Whereas a full wave rectifier has Two peaks in one cycle so F=100hz.

Voltage Regulator

A Voltage regulator is a device which converts varying input voltage into a constant regulated
output voltage. Voltage regulator can be of two types

9
1) Linear Voltage Regulator
Also called as Resistive Voltage regulator because they dissipate the excessive voltage
resistively as heat.
2) Switching Regulators.
They regulate the output voltage by switching the Current ON/OFF very rapidly. Since their
output is either ON or OFF it dissipates very low power thus achieving higher efficiency as
compared to linear voltage regulators. But they are more complex & generate high noise due to
their switching action. For low level of output power switching regulators tend to be costly but for
higher output wattage they are much cheaper than linear regulators.
The most commonly available Linear Positive Voltage Regulators are the 78XX series where the
XX indicates the output voltage. And 79XX series is for Negative Voltage Regulators.

After filtering the rectifier output the signal is given to a voltage regulator. The maximum input
voltage that can be applied at the input is 35V.Normally there is a 2-3 Volts drop across the
regulator so the input voltage should be at least 2-3 Volts higher than the output voltage. If the
input voltage gets below the Vmin of the regulator due to the ripple voltage or due to any other
reason the voltage regulator will not be able to produce the correct regulated voltage.

Fig 2.3. Circuit Diagram of power supply

10
IC 7805
7805 is an integrated three-terminal positive fixed linear voltage regulator. It supports an input
voltage of 10 volts to 35 volts and output voltage of 5 volts. It has a current rating of 1 amp
although lower current models are available. Its output voltage is fixed at 5.0V. The 7805 also has
a built-in current limiter as a safety feature. 7805 is manufactured by many companies, including
National Semiconductors and Fairchild Semiconductors.

The 7805 will automatically reduce output current if it gets too hot.The last two digits represent
the voltage; for instance, the 7812 is a 12-volt regulator. The 78xx series of regulators is designed
to work in complement with the 79xx series of negative voltage regulators in systems that provide
both positive and negative regulated voltages, since the 78xx series can't regulate negative
voltages in such a system.

The 7805 & 78 is one of the most common and well-known of the 78xx series regulators, as it's
small component count and medium-power regulated 5V make it useful for powering TTL
devices. Specifications of IC7805

SPECIFICATIONS IC 7805

Vout 5V
Vein - Vout Difference 5V - 20V
Operation Ambient Temp 0 - 125°C
Output Imax 1A

4.2.2 ARM CONTROLLER

LPC2148
Introduction
The LPC2148 microcontrollers are based on a 32/16 bit ARM7TDMI-S CPU with real-time
emulation and embedded trace support, that combines the microcontroller with embedded high
speed flash memory ranging from 32 kB to 512 kB . A 128-bit wide memory interface and unique
accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code
size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with
minimal performance penalty. Due to their tiny size and low power consumption,
LPC2141/2/4/6/8 are ideal for applications where miniaturization is a key requirement, such as
access control and point-of-sale. A blend of serial communications interfaces ranging from a USB

11
2.0 Full Speed device, multiple UARTS, SPI, SSP to I2Cs and on-chip SRAM of 8 kB up to 40
kB, make these devices very well suited for communication gateways and protocol converters, soft
modems, voice recognition and low end imaging, providing both large buffer size and high
processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC, PWM
channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins
make these microcontrollers particularly suitable for industrial control and medical systems.

Features

• 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

• 8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory.128 bit
wide interface/accelerator enables high speed 60 MHz operation.
• In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software. Single
flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.
• Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip
Real Monitor software and high speed tracing of instruction execution.
• USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM. In addition, the
LPC2146/8 provides 8 kB of on-chip RAM accessible to USB by DMA.
• One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of 6/14 analog
inputs, with conversion times as low as 2.44 μs per channel.
• Single 10-bit D/A converter provide variable analog output.
• Two 32-bit timers/external event counters (with four capture and four compare channels each),
PWM unit (six outputs) and watchdog.
• Low power real-time clock with independent power and dedicated 32 kHz clock input.
• Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 Kbit/s), SPI
and SSP with buffering and variable data length capabilities.
• Vectored interrupt controller with configurable priorities and vector addresses.
• Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
• Up to nine edge or level sensitive external interrupt pins available.

12
• 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of
100 μs.
• On-chip integrated oscillator operates with an external crystal in range from 1 MHz to 30 MHz
and with an external oscillator up to 50 MHz
• Power saving modes include idle and Power-down.
• Individual enable/disable of peripheral functions as well as peripheral clock scaling for
Additional power optimization.
• Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out
Detect (BOD) or Real-Time Clock (RTC).
• Single power supply chip with Power-On Reset (POR) and BOD circuits:
– CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O
Pads.
Applications
• Industrial control
• Medical systems
• Access control
• Point-of-sale
• Communication gateway
• Embedded soft modem
• General purpose applications
Device information

Architectural overview

The LPC2148 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus
for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB)

13
for interface to the interrupt controller, and the VLSI Peripheral Bus (VPB, a compatible superset
of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions. The
LPC2148 configures the ARM7TDMI-S processor in little-endian byte order. AHB peripherals are
allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space.
Each AHB peripheral is allocated a 16 kB address space within the AHB address space. LPC2148
peripheral functions (other than the interrupt controller) are connected to the VPB bus. The AHB
to VPB bridge interfaces the VPB bus to the AHB bus. VPB peripherals are also allocated a 2
megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each VPB peripheral is
allocated a 16 kB address space within the VPB address space. The connection of on-chip
peripherals to device pins is controlled by a Pin Connect Block (see chapter "Pin Connect Block"
on page 75). This must be configured by software to fit Specific application requirements for the
use of peripheral functions and pins.
ARM7TDMI-S processor
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance
and very low power consumption. The ARM architecture is based on Reduced Instruction Set
Computer (RISC) principles, and the instruction set and related decode mechanism are much
simpler than those of micro programmed Complex Instruction Set Computers. This simplicity
results in a high instruction throughput and impressive real-time interrupt response from a small
and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems can
operate continuously. Typically, while one instruction is being executed, its successor is being
decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also
employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-
volume applications with memory restrictions, or applications where code density is an issue. The
key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S
processor has two instruction sets:
• The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a traditional
16-bit processor using 16-bit registers. This is possible because THUMB code operates on the
same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the
performance of an equivalent ARM processor connected to a 16-bit memory system. The
14
ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found
on official ARM website.
On-chip Flash memory system

The LPC2141/2/4/6/8 incorporates a 32 kB, 64 kB, 128 kB, 256 kB, and 512 kB Flash
memory system respectively. This memory may be used for both code and data storage.
Programming of the Flash memory may be accomplished in several ways: over the serial built-in
JTAG interface, using In System Programming (ISP) and UART0, or by means of In Application
Programming (IAP) capabilities. The application program, using the IAP functions, may also erase
and/or program the Flash while the application is running, allowing a great degree of flexibility for
data storage field firmware upgrades, etc. When the LPC2148 on-chip boot loader is used, 32 kB,
64 kB, 128 kB, 256 kB, and 500 kB of Flash memory is available for user code. The LPC2148
Flash memory provides minimum of 100,000 erase/write cycles and 20 years of data-retention.

On-chip Static RAM (SRAM)

On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip
SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2148 provide 8/16/32 kB of static
RAM respectively. The LPC2148 SRAM is designed to be accessed as a byte-addressed memory.
Word and half-word accesses to the memory ignore the alignment of the address and
access the naturally-aligned value that is addressed (so a memory access ignores address bits 0 and
1 for word accesses, and ignores bit 0 for half-word accesses).Therefore valid reads and writes
require data accessed as half-words to originate from addresses with address line 0 being 0
(addresses ending with 0, 2, 4, 6, 8, A, C, and E in hexadecimal notation) and data accessed as
words to originate from addresses with address lines 0 and 1 being 0 (addresses ending with 0, 4,
8, and C in hexadecimal notation). This rule applies to both off and on-chip memory usage. The
SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-
back writes. The write-back buffer always holds the last data sent by software to the SRAM.
This data is only written to the SRAM when another write is requested by Software (the
data is only written to the SRAM when software does another write). If a chip reset occurs, actual
SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the
SRAM does not reflect the last write operation). Any software that checks SRAM contents after
reset must take this into account. Two identical writes to a location guarantee that the data will be
present after a Reset. Alternatively, a dummy write operation before entering idle or power-down
15
mode will similarly guarantee that the last data written will be present in SRAM after a subsequent
Reset.

16
Block diagram

17
Memory maps

The LPC2141/2/4/6/8 incorporates several distinct memory regions, shown in the

following figures. Figure 2 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping, which
is described later in this section.

LPC2141/2142/2144/2146/2148 memory re-mapping and boot block

18
Memory map concepts and operating modes

The basic concept on the LPC2141/2/4/6/8 is that each memory area has a "natural"
location in the memory map. This is the address range for which code residing in that area is
written. The bulk of each memory space remains permanently fixed in the same location,
eliminating the need to have portions of the code designed to run in different address ranges.
Because of the location of the interrupt vectors on the ARM7 processor (at addresses 0x0000 0000
through 0x0000 001C, as shown in Table 3 below), a small portion of the Boot Block and SRAM
spaces need to be re-mapped in order to allow alternative uses of interrupts in the different
operating modes described in Table 4.

19
Memory re-mapping

In order to allow for compatibility with future derivatives, the entire Boot Block is mapped
to the top of the on-chip memory space. In this manner, the use of larger or smaller flash modules
will not require changing the location of the Boot Block (which would require changing the Boot
Loader code itself) or changing the mapping of the Boot Block interrupt vectors. Memory spaces
other than the interrupt vectors remain in fixed locations. Shows the on-chip memory mapping in
the modes defined above.
The portion of memory that is re-mapped to allow interrupt processing in different modes
includes the interrupt vector area (32 bytes) and an additional 32 bytes, for a total of 64 bytes. The
re-mapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. A typical user
program in the Flash memory can place the entire FIQ handler at address 0x0000 001C without
any need to consider memory boundaries. The vector contained in the SRAM, external memory,
and Boot Block must contain branches to the actual interrupt handlers, or to other instructions that
accomplish the branch to the interrupt handlers. There are three reasons this configuration was
chosen:
1. To give the FIQ handler in the Flash memory the advantage of not having to take a memory
boundary caused by the remapping into account.
2. Minimize the need to for the SRAM and Boot Block vectors to deal with arbitrary boundaries
in the middle of code space.
3. To provide space to store constants for jumping beyond the range of single word branch
instructions.
Re-mapped memory areas, including the Boot Block and interrupt vectors, continue to
appear in their original location in addition to the re-mapped address.
4. Minimize the need to for the SRAM and Boot Block vectors to deal with arbitrary boundaries
in the middle of code space.
5. To provide space to store constants for jumping beyond the range of single word branch
instructions.
Re-mapped memory areas, including the Boot Block and interrupt vectors, continue to
appear in their original location in addition to the re-mapped address.

20
Pin description for LPC2148

21
22
GPIO

Features

1. GPIO will give the direction control (whether the selected pin is used as input pin or output
pin) of individual bits. It can be achieved by IODIR [1].

2. We can set the values of register by writing one, produces high at the corresponding port pins,
whereas writing zero will have no effect. It can be done by using IOSET. Whenever we use
i.e. when we set any value we have to clear those bit using IOCLR. IOCLR will clear the
particular bits we have selected [1].

3. After reset, by default all the I/O will act as input pins.

Pin Description

TheLPC2148 processor has totally four ports.

1. Port0 has 32 pins and all can be used as input/output. All pins of this port can be used as
general purpose input/output. The number of pins available for input/output operation will
depends on the use of alternate functions i.e. if we use less alternate functions more are the
available input/output’s [1].Port Pins P0.24,P0.26,P0.27 are not available.

Pin Name Type Description

General purpose input/output. The number of GPIOs
available depends on the use of functions.
P0.0 – P0.31 Input/

P1.16 – P1.31 Output

1. Port1 has16 pins and all can be used as input/output. All pins of this port can be used as
general purpose input/output. This is same as port0, only difference is this port has only
16pins where as port0 has 32 pins [1].

Table 2.1: GPIO PIN Description

23
Register Description:
As we seen in the above table it is clear that LPC2148 has two 32-bit general purpose
input/output ports. For Port0 29 pins (24, 26, 27 are not available) out of 32 pins are
available for GPIO functions and for port1 only 16 (0-15pins are not available) out of 32 are
available for GPIO functions. Port0 and port1 are controlled by two groups of four registers
(IOPIN, IOSET, IODIR and IOCLR) which are explained in detail below.
There are four registers associated with the GPIO and are shown below:

Generic Reset PORT0 PORT1

Name Description Access Value Address & NameAddress & Name

GPIO Port Pin Value Register. The current

status of the GPIO configured port pins can
always be read from this register, regardless
of pin direction and mode. Read

IOPIN Only NA 0xE0028000 0xE0028010

IO0PIN IO1PIN

GPIO Port Output Set Register. This register

controls the state of output pins along with
the IOCLR register. Writing 1 produces highs
Read/
at the corresponding port pins. Writing zeros 0x0000 0xE0028004 0xE0028014
has no effect.
IOSET Write 0000 IO0PIN IO1SET

GPIO Port Direction Control Register. This

Read/ 0x0000 0xE0028008 0xE0028018
register is used to control the direction of
IODIR Write 0000 IO0DIR IO1DIR
each port pin.

GPIO Port Output Clear Register. This

register is used to control the state of output
0xE0028008
pins. Writing ones produces lows at the
corresponding port pins and clears Write
the Only 0x0000 IO0DIR 0xE0028014
corresponding bits in the IOSET register.
IOCLR 0000 IO1SET
Writing zeros has no effect.

Table 2.2: GPIO Register Description.

24
GPIO Port Pin Value Register:

This is a 32 bit register. In our project we are not using this register as we are selecting the particular port
pins as outputs. Here we know the output pins. This register is used when we would like to know whether
the particular port pins used as output or not.

IOPIN Description Value after

Reset

31:0 GPIO pin value bits. Bit0 in IOPIN corresponds to P0.0.... Bit 31 undefined
in
IOPIN corresponds to P0.31.

Table 2.3: GPIO Port PIN Value Register (IOPIN Register) [1].

GPIO Port Output Set Register:

GPIO Output Set Register is a 32 bit register used to make the particular bits to high level output at the
port pins if they are configured as GPIO in an output mode. Writing 1 makes a high level at the particular
port pins, whereas writing 0 will have no effect. If any pin is configured as input then writing to IOSET has
no effect.

IOSET Description Value after

Reset

31:0 Output value SET bits. Bit0 in IOSET corresponds to P0.0.... Bit 31 0
in IOSET corresponds to P0.31.

Table 2.4: GPIO Port Output Set Register (IOSET Register) [1].

GPIO Port Direction Register:

25
GPIO Direction Register is a 32 bit register used to control the direction of the pins whether the
port pins used as input or output. If we write 1 then the corresponding port pin is selected or used
as output. Direction bit for any pin must be set according to the pin functionality.

IOSET Description Value after

Reset

31:0 Output value SET bits. Bit0 in IOSET corresponds to P0.0.... Bit 31 0
in IOSET corresponds to P0.31.

Table 2.5: GPIO Port Direction Register (IODIR Register) [1].

GPIO Port Output Clear Register:

GPIO Output Clear Register is a 32 bit register used to produce a low level at port pins if
they are configured as GPIO in output mode. In this register writing 1 will produce low level
at the corresponding port pins and clears the corresponding bits in the IOSET register,
because once the bits are set using IOSET register, they must be made low by using IOCLR
register. Writing 0 will have no effect.

IOSET Description Value after Reset

31:0 Output value SET bits. Bit0 in IOSET corresponds to 0

P0.0.... Bit 31 in IOSET corresponds to P0.31.

GPIO Port Output Clear Register (IOCLR Register) [1].

2.2.1 UART0

26
Features

1. It has 16 byte Transmit and Receive FIFO’s.

2. It has built-in baud rate generator.

3. UART0 Register locations are confirmed to 550 industry standards.

Pin Description

In LPC2148 we are having only one UART which is UART0. Generally RS-232 is used as the
UART0. In Every UART input is to receive the data and output is to transmit the data i.e. Receiver
we will receive the input data and transmitter will output the data. TXD pin of UART0 is
connected to 8th pin of port0 which is TDX1 of the processor and RXD pin of UART0 is
connected to 9th pin of port0 of the processor [1].

IOSET Description Value after

Reset

31:0 Output value SET bits. Bit0 in IOSET corresponds to P0.0.... Bit 31 0
in IOSET corresponds to P0.31.

Table 2.7: UART0 PIN Description [1].

Register Description

UART0 of LPC2148 contains ten 8-bit registers [1]. All these registers are listed below:

1. UART0 Receive Buffer Register (U0RBR).

2. UART0 Transmitter Holding Register (U0THR).
3. UART0 Interrupt Enable Register (U0IER).
4. UART0 Interrupt Identification Register (U0IIR).
5. UART0 FIFO Control Register (U0FCR).
6. UART0 Line Control Register (U0LCR).
7. UART0 Line Status Register (U0LSR).
8. UART0 Scratch Pad Register (U0SCR).
27
 9. UART0 Divisor Latch LSB (U0DLL).
10. UART0 Divisor Latch MSB (U0DLM).

The below figure shows all the registers of UART0 along with their bit description, their access
(whether they are read only or write only or both read and write), their reset values and their address.

Reset

Name DescriptionBit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Access Value Address
Receive
Buffer
U0RB MSB READ DATA RO Un-define
0xE000C000
Register
LSB
DLAB = 0
Transmit
Holding
U0THR MSB WRITE DATA WO NA 0xE000C000
Register
LSB
DLAB = 0
Enable

Rx Data
Enable
THRE INT
U0IER Interrupt 0 0 0 0 0 R/W 0 0xE000C004
Rx Line
Enable

Enable
DLAB = 0
Register

U0IIR Interrupt ID FIFO

0 0 IIR3 IIR2 IIR1 IIR0 RO 0x01 0xE000C008
Register Enabled
Rx FIFO
Tx FIFO

enable
FIFO
Reset
Reset

U0FCR FIFO Control

Rx Trigger - WO 0 0xE000C008
Register
Reserved

28
 No.Paritof

Bits
Stick
Even
Word

Parit
Enable
U0LCR Line Control 0xE000C008

Parity
Length

Stop
Set

y
y
Brek
DLAB
Register Sel R/W 0
ect

Rx

U0LSR Line Status

FIFO TEMTTHRE BI FE PE OE DR RO 0x60 0xE000C008
Register Err

U0SCR Scratch Pad

MSB R/W 0 0xE000C008
Register LSB

U0DLL Divisor Latch

MSB R/W 0x01 0xE000C008
LSB LSB

U0DLM Divisor Latch

MSB R/W 0 0xE000C008
MSB LSB

Table 2.8: Registers of UART0 [1].

Out of these ten register only U0RBR, U0THR, U0LCR, U0LSR U0DLL, andU0DLM are used.
The role of these registers is discussed later in our project.

UART0 Receiver Buffer Register:

In order to access UART0 Receiver buffer register, firstly we have to make the Divisor Latch
Access Bit (DLAB) in Line Control Register (U0LCR) to zero. The UART0RBR is always read
only. We know that U0RBR is the top byte of the UART0 Rx FIFO. Here the top byte of the Rx
FIFO contains the oldest character received and can be read via the bus interface and the LSB
represents the oldest received data bit. In our project we are using the characters which are less

29
than 8-bits. If the character is less than 8-bits, the unused MSB’s must me padded with zeros [1]
[9].

U0RBR Function Description Reset

value

7:0 Receive Buffer The UART0 Receive Buffer Register contains the
Undefined
oldest received byte in the UART0 Rx FIFO.
Register

Table 2.9: UART0 Receive Buffer Register (U0RBR) [1].

UART0 Transmitter Holding Register:

In order to access UART0 Transmitter Holding Register, firstly we have to make the Divisor Latch
Access Bit (DLAB) which is present in Line Control Register (U0LCR) to zero. The U0THR is
always writing only. We know that U0THR is the top byte of the UART0 Tx FIFO. Here the top
byte is the newest character in the Tx FIFO and can be written via the bus interface. We know that
the LSB represents the first bit to transmit. In our project we are keeping our command (values
given to the processor in order to control the devices) in UART0 Transmitter Holding Register. If
the data present in the UART0 THR matches with the predefined command, we can get control to
monitor the devices on the board. We are placing the command in between “$A__@” to
differentiate the next command with the previous command [1] [9].

U0THR Function Description Reset

value

30
 Writing to the UART0 Transmit Holding Register
causes the data to be stored in the UART0 Transmit
7:0 Transmit Holding Undefined
FIFO. The byte will be sent when it reaches the
Register
bottom of the FIFO and the transmitter s available.

UART0 Transmitter Holding Register (U0THR) [9].

UART0 Line Control Register:

The UART0 Line Control Register determines the format of the data character that is to be
transmitted or received. In our project U0LCR is used to get access to U0DLL, U0DLM, U0LCR
and U0THR by using the DLAB bit. In our program we are using 8bit character length, 1 start bit
with no parity. After setting the DLAB bit we can get access to set the baud rate. After setting the
baud rate we have to disable this bit to keep the baud rate constant [1] [9].

U0LCR Function Description Reset

value
00: 5 bit character length

01: 6 bit character length

1:0 Word Length 10: 7 bit character length 0

Select 11: 8 bit character length

2 Stop Bit 0:1 Stop bit

Select 1:2 Stop bits (1.5 if U0LCR[1:0]=00) 0

3 Parity Enable 0: Disable parity generation and checking 0

1: Enable parity generation and checking

00: Odd parity

5:4 Parity Select 01: Even parity 0

31
 10: Forced “1” stick parity

11: Forced “0” stick parity

0: Disable break transmission

6 Break Control 1: Enable break transmission 0

Divisor Latch
0: Disable access to Divisor Latches
Access Bit
7 1: Enable access to Divisor Latches 0

UART0 Line Control Register (U0LCR) [9].

UART0 Line Status Register:

The UART0 Line Status Register will provide the status information which is present on the
UART0 Tx and Rx. U0LSR is a read-only register. In our project we are using this register to
check whether the data is received or not. When we send a character, the control will stay there till
the character is received or when next character is pressed [1] [9].

UOLSR
Function Description Reset
Value
0: U0RBR is empty

Receiver 1: U0RBR contains valid data

0 Data Ready
U0LSR0 is set when the U0RBR holds an unread character and is cleared
0
(RDR) when the UART0 RBR FIFO is empty.
0: Overrun error status is in inactive state.

1: Overrun error status is in active state.

Overrun The overrun error condition is set as soon as it occurs. An U0LSR read
clears U0LSR1. U0LSR1 is set when UART0 RSR has a new character
1 Error 0
assembled and the UART0 RBR FIFO is full. In this case, the UART0 RBR
(OE) FIFO will not be overwritten and the character in the UART0 RSR will be
lost.

32
 0: Parity error status is in inactive stat.

1: Parity error status is in active state.

2 Parity Error A parity error occurs, when the parity bit of a received character is in the
0
wrong state. An U0LSR read clears U0LSR2. Time of parity error detection
(PE)
is dependent on U0FCR0. A prity error is associated with the character
being read from the UART0 RBR FIFO.
0: Framing error status is in inactive state.

1: Framing error status is in active state.

A framing error occurs, When the stop bit of a received character is at logic
0,. An U0LSR read clears U0LSR3. The framing error time detection is
3 Framing
dependent on U0FCR0. Framing error is linked with the character being
Error read from the UART0 RBR FIFO. Upon detection of a framing error, the

(FE) Rx will attempt to resynchronize to the data and assume that the bad stop 0
bit is actually an early start bit. However, it cannot be assumed that the next
received byte will be correct even if there is no Framing Error.
0: Break interrupt status is in inactive state.

1: Break interrupt status is in active state.

When RxD0 is held in the spacing state (all 0’s), a break interrupt occurs
for one full character transmission (start, data, parity, stop). The receiver
4 Break
goes idle until RxD0 goes to marking state (all 1’s), once the break
Interrupt 0
condition has been detected,. An U0LSR clears the status bit when it has

(BI) read. The break detection time is dependent on U0FCR0.

The break interrupt is associated with the character being read from the
UART0 RBR FIFO.
Transmitter 0: U0THR contains valid data.
Holding Register
5 1:U0THR is empty. 1
Empty (THRE)
Upon detection of an empty UART0 THR, the THRE is set immediately
and is cleared on a U0THR write.

33
 Transmitter 0: U0THR and/or the U0TSR contain valid data.

6 Empty 1: U0THR and U0TSR are empty.

(TEMT) TEMT is set when both U0THR and U0TSR are empty, TEMT is cleared
1
when either the U0TSR or the U0THR contain valid data.
0: U0RBR contains no UART0 Rx errors or U0FCR0=0.

Error in Rx 1: UART0 RBR contains at least one UART0 Rx error.

7 FIFO U0LSR7 is set when a character with a Rx error such as framing error,
0
parity error or break interrupt, is loaded into the U0RBR. This bit is cleared
(RXFE)
when the U0LSR register is read and there are no subsequent errors in the
UART0 FIFO.

UART0 Line Status Register (U0LSR) [1].

UART0 Divisor Latch MSB Register:

When we are using UART0 Divisor Latches, the DLAB bit present in the U0LCR must be one.
U0DLM along with U0DLL is a 16-bit divisor. In this 16-bit divisor U0DLL will occupy the lower
8-bits and U0DLM will have higher 8-bits of the divisor. The UART0 Divisor Latch is a part of
UART0 baud rate generator. It will divide the VPB clock in order to produce the baud rate clock.
Baud rate clock must be 16x the desired baud rate [1].

U0DLM Function Description Reset

value

Divisor Latch MSB

The UART0 Divisor Latch MSB Register along with
Register U0DLL register determines the baud rate of the
7:0 Undefined
UART0.

34
UART0 Divisor Latch MSB Register (U0DLM).

UART0 Divisor Latch LSB Register:

DLAB bit in U0LCR register must be one in order to access this register. By using this register we
can set the baud rate which is required. Generally we use baud rate of 9600.

This baud rate is achieved by passing 0x62 to this register.

Diagram of UART0 Divisor Latch LSB Register is shown below:

U0DLL Function Description Reset

value

Divisor Latch LSBThe UART0 Divisor Latch LSB Register along with
U0DLM register determines the baud rate of the
7:0 Register Undefined
UART0.

UART0 Divisor Latch LSB Register (U0DLL) [1].

PIN CONNECT BLOCK

The pin connect block allows selected pins of the microcontroller to have more than one function.
Configuration registers control the multiplexers to allow connection between the pin and the on
chip peripherals.

35
Peripherals should be connected to the appropriate pins prior to being activated, and prior to any
related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped
to a related pin should be considered undefined.
Selection of a single function on a port pin completely excludes all other functions otherwise
available on the same pin.
The only partial exception from the above rule of exclusion is the case of inputs to the A/D
converter. Regardless of the function that is selected for the port pin that also hosts the A/D input,
this A/D input can be read at any time and variations of the voltage level on this pin will be
reflected in the A/D readings. However, valid analog reading(s) can be obtained if and only if the
function of an analog input is selected. Only in this case proper interface circuit is active in
between the physical pin and the A/D module. In all other cases, a part of digital logic necessary
for the digital function to be performed will be active, and will disrupt proper behavior of the A/D.
7.4 Register description
The Pin Control Module contains 2 registers as shown in Table 59 below.
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

Register Description:

There are two registers in the Pin Control Module.

1. Pin Function Select Register 0 (PINSEL0).

2. Pin Function Select Register 1 (PINSEL1).
3. Pin Function Select Register 2 (PINSEL2).

In our project we are using both registers. We are using Pin Function Select
Register 0 to select the UART0 by passing a value of 0x0000005 to this register (PINSEL0|
=0x00000005). We are selecting Pin Function Select Register 1 to select ADC by passing a value
of 0x15400000 to this register (PINSEL1|=0x15400000) [1].(PINSEL2|=0xE002 C014)

Pin Function Select Register 0 (PINSEL0):

There are many functions provided by each port pins. This register is used to controls the
functions of the pins which are shown below:

36
 PIN Pin Function Function Function Function Reset
Vale
SEL0 Name when 00 When 01 When 10 When11
1:0 P0.0 GPIO Port0.0 TxD(UART0) PWM1 Reserved 00
3:2 P0.1 GPIO Port0.1 RxD(UART0) PWM3 EINT0 00
5:4 P0.2 GPIO Port0.2 SCL(I2C) Capture 0.0(T0) Reserved 00
7:6 P0.3 GPIO Port0.3 SDA(I2C) Match 0.0(T0) EINT1 00
9:8 P0.4 GPIO Port0.4 SCK(SPI0) Capture 0.1(T0) Reserved 00
11:10 P0.5 GPIO Port0.5 MISO(SPI0) Match 0.1(T0) Reserved 00
13:12 P0.6 GPIO Port0.6 MOSI(SPI0) Capture 0.2(T0) Reserved 00
15:14 P0.7 GPIO Port0.7 SSEL(SPI0) PWM2 EINT2 00
17:16 P0.8 GPIO Port0.8 TxD(UART1) PWM4 Reserved 00
19:18 P0.9 GPIO Port0.9 RxD(UART1) PWM6 EINT3 00
21:20 P0.10 GPIO Port0.10 RTS(UART1) Capture 1.0(T1) Reserved 00
23:22 P0.11 GPIO Port0.11 CTS(UART1) Capture 1.1(T1) Reserved 00
25:24 P0.12 GPIO Port0.12 DSR(UART1) Match 1.0(T1) Reserved 00
27:26 P0.13 GPIO Port0.13 DTR(UART1) Match 1.1(T1) Reserved 00
29:28 P0.14 GPIO Port0.14 CD(UART1) EINT 1 Reserved 00
31:30 P0.15 GPIO Port0.15 RI(UART1) EINT 2 Reserved 00

Table 2.17: PIN Function Select Register 0 (PINSEL0) [1].

From the above diagram we can select UART0 by using pins 0, 1, 2 and 3. If we give
values 0101 to these pins (P0.0=01 and P0.1=01), we can select UART0.

Pin Function Select Register 1 (PINSEL1):

This register is mainly used to select the UART’s of the processor and control the functions of the
pins which are shown below:

Reset
Val
PIN Pin Function Function Function Function

SEL1 Name when 00 When 01 When 10 When11

1:0 P0.16 GPIO Port0.16 EINT0 Match 0.2(T0) Capt0.2(T0) 00

37
 3:2 P0.17 GPIO Port0.17 Capture 1.2(T1) SCK(SPl1) Mat1.2(T1) 00
5:4 P0.18 GPIO Port0.18 Capture 1.3(T1) MISO(SPl1) Mat1.3(T1) 00
7:6 P0.19 GPIO Port0.19 Match 1.2(T1) MOSI(SPl1) Mat1.3(T1) 00
9:8 P0.20 GPIO Port0.20 Match 1.3(T1) SSEL(SPl1) EINT3 00
11:10 P0.21 GPIO Port0.21 PMW5 Reserved Capt1.3(T1) 00
13:12 P0.22 GPIO Port0.22 Reserved Capture0.0(T0) Mat0.0(T1) 00
15:14 P0.23 GPIO Port0.23 RD2(CAN Con2 ) Reserved Reserved 00
17:16 P0.24 GPIO Port0.24 TD2(CAN Con2 ) Reserved Reserved 00
19:18 P0.25 GPIO Port0.25 RD1(CAN Con1 ) Reserved Reserved 00
21:20 P0.26 Reserved 00
23:22 P0.27 GPIO Port0.27 AIN0 (ADC) Capture0.1(T0) Mat0.1(T0) 01
25:24 P0.28 GPIO Port0.28 AIN1 (ADC) Capture 0.2(T0) Mat0.2(T0) 01
27:26 P0.29 GPIO Port0.29 AIN2 (ADC) Capture 0.3(T0) Mat0.3(T0) 01
29:28 P0.30 GPIO Port0.30 AIN3 (ADC) EINT 3 Capt0.0(T0) 01
31:30 P0.31 Reserved 00

Table 2.18: PIN Function Select Register 1 (PINSEL1) [1].

We are selecting ADC using the PINSEL1 register. From the above diagram we can clearly
see that P0.27, P0.28, P0.29 and P0.30 pins are used to select ADC and timer0. ADC is selected by
passing values of 01010101 to the four port pins (P0.27=01, P0.28=01, P0.29=01 and P0.30=01).

38
39
40
41
42
Pin function Select register 2 (PINSEL2 - 0xE002 C014)
The PINSEL2 register controls the functions of the pins as per the settings listed in Table 62. The
direction control bit in the IO1DIR register is effective only when the GPIO function is selected
for a pin. For other functions direction is controlled automatically.
Warning: use read-modify-write operation when accessing PINSEL2 register. Accidental write of
0 to bit 2 and/or bit 3 results in loss of debug and/or trace functionality! Changing of either bit 4 or
bit 5 from 1 to 0 may cause an incorrect code execution!

Table 62: Pin function Select register 2 (PINSEL2 - 0xE002 C014) bit description
Bit Symbol Value Function Reset value
1:0 - - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.

2 GPIO/DEBUG 0 Pins P1.31-26 are used as GPIO pins. P1.26/RTCK

1 Pins P1.36-26 are used as a Debug port.
3 GPIO/TRACE 0 Pins P1.25-16 are used as GPIO pins. P1.20/TRACESYNC
1 Pins P1.25-16 are used as a Trace port.
31:4 - - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
4.2.3 LCD MODULE
To display interactive messages we are using LCD Module. We examine an intelligent
LCD display of two lines, 16 characters per line that is interfaced to the controllers. The protocol
(handshaking) for the display is as shown. Whereas D0 to D7th bit is the Data lines, RS, RW and
EN pins are the control pins and remaining pins are +5V, -5V and GND to provide supply. Where
RS is the Register Select, RW is the Read Write and EN is the Enable pin.

The display contains two internal byte-wide registers, one for commands (RS=0) and the
second for characters to be displayed (RS=1). It also contains a user-programmed RAM area (the
character RAM) that can be programmed to generate any desired character that can be formed
using a dot matrix. To distinguish between these two data areas, the hex command byte 80 will be
used to signify that the display RAM address 00h will be chosen.Port1 is used to furnish the
command or data type, and ports 3.2 to 3.4 furnish register select and read/write levels.

The display takes varying amounts of time to accomplish the functions as listed. LCD bit 7 is
monitored for logic high (busy) to ensure the display is overwritten.
43
Liquid Crystal Display also called as LCD is very helpful in providing user interface as well as for
debugging purpose. The most common type of LCD controller is HITACHI 44780 which provides
a simple interface between the controller & an LCD. These LCD's are very simple to interface
with the controller as well as are cost effective.

2x16 Line Alphanumeric LCD Display

The most commonly used ALPHANUMERIC displays are 1x16 (Single Line & 16 characters),
2x16 (Double Line & 16 character per line) & 4x20 (four lines & Twenty characters per line).
The LCD requires 3 control lines (RS, R/W & EN) & 8 (or 4) data lines. The number on data lines depends
on the mode of operation. If operated in 8-bit mode then 8 data lines + 3 control lines i.e. total 11 lines are
required. And if operated in 4-bit mode then 4 data lines + 3 control lines i.e. 7 lines are required. How do
we decide which mode to use? It’s simple if you have sufficient data lines you can go for 8 bit mode & if
there is a time constrain i.e. display should be faster then we have to use 8-bit mode because basically 4-
bit mode takes twice as more time as compared to 8-bit mode.
Pin Symbol Function
1 Vss Ground
2 Vdd Supply Voltage
3 Vo Contrast Setting
4 RS Register Select
5 R/W Read/Write Select
6 En Chip Enable Signal
7-14DB0-DB7 Data Lines
15 A/Vee Gnd for the backlight
16 K Vcc for backlight
When RS is low (0), the data is to be treated as a command. When RS is high (1), the data being
sent is considered as text data which should be displayed on the screen.
When R/W is low (0), the information on the data bus is being written to the LCD. When RW is
high (1), the program is effectively reading from the LCD. Most of the times there is no need to
read from the LCD so this line can directly be connected to Gnd thus saving one controller line.
The ENABLE pin is used to latch the data present on the data pins. A HIGH - LOW signal is
required to latch the data. The LCD interprets and executes our command at the instant the EN
line is brought low. If you never bring EN low, your instruction will never be executed.

44
COMMANDS USED IN LCD

4.2.4 RFID

45
History of RFID:

In a very interesting article, the San Jose Mercury News tells us about Charles Walton, the man
behind the radio frequency identification technology (RFID). Since his first patent about it in
1973, Walton, now 83 years old, collected about $3 million from royalties coming from his
patents. Unfortunately for him, his latest patent about RFID expired in the mid-1990s. So he will
not make any money from the billions of RFID tags that will appear in the years to come. But he
continues to invent and his latest patent about a proximity card with incorporated PIN code
protection was granted in June 2004.
What is RFID.
RFID is short for Radio Frequency Identification. Generally a RFID system consists of 2 arts. A
Reader, and one or more Transponders, also known as Tags. RFID systems evolved from barcode
labels as a means to automatically identify and track products and people. Yo will be generally
familiar with RFID systems as seen in:
 Access Control.
RFID Readers placed at entrances that require a person to pass their proximity card (RF
tag) to be "read' before the access can be made.
 Contact less Payment Systems.
RFID tags used to carry payment information. RFIDs are particular suited to electronic
Toll collection systems. Tags attached to vehicles, or carried by people transmit payment
information to a fixed reader attached to a Toll station. Payments are then routinely
deducted from a users account, or information is changed directly on the RFID tag.
 Product Tracking and Inventory Control. RFID systems are commonly used to track
and record the movement of ordinary items such as library books, clothes, factory pallets,
electrical goods and numerous items.
How do RFIDs work.
Shown below is a typical RFID system. In every RFID system the transponder Tags contain
information. This information can be as little as a single binary bit, or be a large array of bits
representing such things as an identity code, personal medical information, or literally any type of
information that can be stored in digital binary format.
INCLUDEPICTURE "http://www.priority1design.com.au/basic_rfid_system.jpg" \*
MERGEFORMATINET INCLUDEPICTURE
"http://www.priority1design.com.au/basic_rfid_system.jpg" \* MERGEFORMATINET
INCLUDEPICTURE "http://www.priority1design.com.au/basic_rfid_system.jpg" \*

46
MERGEFORMATINET INCLUDEPICTURE
"http://www.priority1design.com.au/basic_rfid_system.jpg" \* MERGEFORMATINET

Shown is a RFID transceiver that communicates with a passive Tag. Passive tags have no power
source of their own and instead derive power from the incident electromagnetic field. Commonly
the heart of each tag is a microchip. When the Tag enters the generated RF field it is able to draw
enough power from the field to access its internal memory and transmit its stored information.
When the transponder Tag draws power in this way the resultant interaction of the RF fields
causes the voltage at the transceiver antenna to drop in value. This effect is utilized by the Tag to
communicate its information to the reader. The Tag is able to control the amount of power drawn
from the field and by doing so it can modulate the voltage sensed at the Transceiver according to
the bit pattern it wishes to transmit.
COMPONENTS OF RFID
Basic RFID systems consist of three components:

 An antenna or coil

 A transceiver (with decoder)

 A transponder (RF tag) electronically programmed with unique information

47
These are described below:

1. ANTENNA

The antenna emits radio signals to activate the tag and read and write data to it. Antennas are the
conduits between the tag and the transceiver, which controls the system's data acquisition and
communication. Antennas are available in a variety of shapes and sizes; they can be built into a
door frame to receive tag data from persons or things passing through the door, or mounted on an
interstate tollbooth to monitor traffic passing by on a freeway. The electromagnetic field produced
by an antenna can be constantly present when multiple tags are expected continually. If constant
interrogation is not required, a sensor device can activate the field.

Often the antenna is packaged with the transceiver and decoder to become a reader (a.k.a.
interrogator), which can be configured either as a handheld or a fixed-mount device. The reader
emits radio waves in ranges of anywhere from one inch to 100 feet or more, depending upon its
power output and the radio frequency used. When an RFID tag passes through the electromagnetic
zone, it detects the reader's activation signal. The reader decodes the data encoded in the tag's
integrated circuit (silicon chip) and the data is passed to the host computer for processing.

2. TAGS (Transponders)
An RFID tag is comprised of a microchip containing identifying information and an antenna that
transmits this data wirelessly to a reader. At its most basic, the chip will contain a serialized
identifier, or license plate number, that uniquely identifies that item,

48
similar to the way many bar codes are used today. A key difference, however is that RFID tags
have a higher data capacity than their bar code counterparts. This increases the options for the type
of information that can be encoded on the tag, including the manufacturer, batch or lot number,
weight, ownership, destination and history (such as the temperature range to which an item has
been exposed). In fact, an unlimited list of other types of information can be stored on RFID tags,
depending on application needs. An RFID tag can be placed on individual items, cases or pallets
for identification purposes, as well as on fixed assets such as trailers, containers, totes, etc.

Tags come in a variety of types, with a variety of capabilities. Key variables include:

"Read-only" versus "read-write"

There are three options in terms of how data can be encoded on tags: (1) Read-only tags contain
data such as a serialized tracking number, which is pre-written onto them by the tag manufacturer
or distributor. These are generally the least expensive tags because they cannot have any additional
information included as they move throughout the supply chain. Any updates to that information
would have to be maintained in the application software that tracks SKU movement and activity.
(2) "Write once" tags enable a user to write data to the tag one time in production or distribution
processes. Again, this may include a serial number, but perhaps other data such as a lot or batch
number. (3) Full "read-write" tags allow new data to be written to the tag as needed—and even
written over the original data. Examples for the latter capability might include the time and date

of ownership transfer or updating the repair history of a fixed asset. While these are the most
costly of the three tag types and are not practical for tracking inexpensive items, future standards
for electronic product codes (EPC) appear to be headed in this direction.

RFID TAGS

49
Data capacity

The amount of data storage on a tag can vary, ranging from 16 bits on the low end to as much as
several thousand bits on the high end. Of course, the greater the storage capacity, the higher the
price per tag.

Form factor

The tag and antenna structure can come in a variety of physical form factors and can either be self-
contained or embedded as part of a traditional label structure (i.e., the tag is inside what looks like
a regular bar code label—this is termed a 'Smart Label') companies must choose the appropriate
form factors for the tag very carefully and should expect to use multiple form factors to suit the
tagging needs of different physical products and units of measure. For example, a pallet may have
an RFID tag fitted only to an area of protected placement on the pallet itself. On the other hand,
cartons on the pallet have RFID tags inside bar code labels that also provide operators human-
readable information and a back-up should the tag fail or pass through non RFID-capable supply
chain links.

Passive versus active

“Passive” tags have no battery and "broadcast" their data only when energized by a reader. That
means they must be actively polled to send information. "Active" tags are capable of broadcasting
their data using their own battery power. In general, this means that the read ranges are much
greater for active tags than they are for passive tags—perhaps a read range of 100 feet or more,
versus 15 feet or less for most passive tags. The extra capability and read ranges of active tags,
however, come with a cost; they are several times more expensive than passive tags. Today, active
tags are much more likely to be used for high-value items or fixed assets such as trailers, where
the cost is minimal compared to item value, and very long read ranges are required. Most
traditional supply chain applications, such as the RFID-based tracking and compliance programs
emerging in the consumer goods retail chain, will use the less expensive passive tags.

Frequencies

Like all wireless communications, there are a variety of frequencies or spectra through which
RFID tags can communicate with readers. Again, there are trade-offs among cost, performance

50
and application requirements. For instance, low-frequency tags are cheaper than ultra high-
frequency (UHF) tags, use less power and are better able to penetrate non-metallic substances.
They are ideal for scanning objects with high water content, such as fruit, at close range. UHF
frequencies typically offer better range and can transfer data faster. But they use more power and
are less likely to pass through some materials. UHF tags are typically best suited for use with or
near wood, paper, cardboard or clothing products. Compared to low-frequency tags, UHF tags
might be better for scanning boxes of goods as they pass through a bay door into a warehouse.
While the tag requirements for compliance mandates may be narrowly defined, it is likely that a
variety of tag types will be required to solve specific operational issues. You will want to work
with a company that is very knowledgeable in tag and reader technology to appropriately identify
the right mix of RFID technology for your environment and applications.

EPC Tags

EPC refers to "electronic product code," an emerging specification for RFID tags, readers and
business applications first developed at the Auto-ID Center at the Massachusetts Institute of
Technology. This organization has provided significant intellectual leadership toward the use and
application of RFID technology. EPC represents a specific approach to item identification,
including an emerging standard for the tags themselves, including both the data content of the tag
and open wireless communication protocols. In a sense, the EPC movement is combining the data
standards embodied in certain bar code specifications, such as the UPC or UCC-128 bar code
standards, with the wireless data communication standards that have been developed by ANSI and
other groups.

3. RF Transceiver:

The RF transceiver is the source of the RF energy used to activate and power the passive RFID
tags. The RF transceiver may be enclosed in the same cabinet as the reader or it may be a separate
piece of equipment. When provided as a separate piece of equipment, the transceiver is commonly
referred to as an RF module. The RF transceiver controls and modulates the radio frequencies that
the antenna transmits and receives. The transceiver filters and amplifies the backscatter signal
from a passive RFID tag.

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Typical Applications for RFID

 Automatic Vehicle identification

 Inventory Management

 Work-in-Process

 Container/ Yard Management

 Document/ Jewellery tracking

 Patient Monitoring

The Advantages of RFID Over Bar Coding

 No "line of sight" requirements: Bar code reads can sometimes be limited or problematic
due to the need to have a direct "line of sight" between a scanner and a bar code. RFID
tags can be read through materials without line of sight.
 More automated reading: RFID tags can be read automatically when a tagged product
comes past or near a reader, reducing the labor required to scan product and allowing more
proactive, real-time tracking.
 Improved read rates: RFID tags ultimately offer the promise of higher read
rates than bar codes, especially in high-speed operations such as carton sortation.
 Greater data capacity: RFID tags can be easily encoded with item details
such as lot and batch, weight, etc.
 "Write" capabilities: Because RFID tags can be rewritten with new data as
supply chain activities are completed, tagged products carry updated
information as they move throughout the supply chain.

Common Problems with RFID

Some common problems with RFID are reader collision and tag collision. Reader collision occurs
when the signals from two or more readers overlap. The tag is unable to respond to simultaneous
queries. Systems must be carefully set up to avoid this problem. Tag collision occurs when many
52
tags are present in a small area; but since the read time is very fast, it is easier for vendors to
develop systems that ensure that tags respond one at a time. See Problems with RFID for more
details.

4.2.5 L293D

L293D is a dual H-bridge motor driver integrated circuit (IC). Motor drivers act as current
amplifiers since they take a low-current control signal and provide a higher-current signal. This
higher current signal is used to drive the motors. L293D contains two inbuilt H-bridge driver
circuits. In its common mode of operation, two DC motors can be driven simultaneously, both in
forward and reverse direction. The motor operations of two motors can be controlled by input
logic at pins 2 & 7 and 10 & 15. Input logic 00 or 11 will stop the corresponding motor. Logic 01
and 10 will rotate it in clockwise and anticlockwise directions, respectively. Enable pins 1 and 9
(corresponding to the two motors) must be high for motors to start operating. When an enable
input is high, the associated driver gets enabled. As a result, the outputs become active and work
in phase with their inputs. Similarly, when the enable input is low, that driver is disabled, and their
outputs are off and in the high-impedance state.

Description/ordering information (continued)

1.On the L293, external high-speed output clamp diodes should be used for inductive transient
suppression.
2.A VCC1 terminal, separate from VCC2, is provided for the logic inputs to minimize device
power dissipation.
3.The L293and L293D are characterized for operation from 0C to 70C.
Pin Diagram:

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 The L293 and L293D are quadruple high-current half-H drivers. The L293 is
designed to provide bidirectional drive currents of up to 1 A at voltages from 4.5 V to 36 V. The
L293D is designed to provide bidirectional drive currents of up to 600-mA at voltages from 4.5 V
to 36 V. Both devices are designed to drive inductive loads such as relays, solenoids, dc and
bipolar stepping motors, as well as other high-current/high-voltage loads in positive-supply
applications.
All inputs are TTL compatible. Each output is a complete totem-pole drive circuit,
with a Darlington transistor sink and a pseudo-Darlington source. Drivers are enabled in pairs,
with drivers 1 and 2 enabled by 1,2EN and drivers 3 and 4 enabled by 3,4EN. When an enable
input is high, the associated drivers are enabled, and their outputs are active and in phase with
their inputs. When the enable input is low, those drivers are disabled, and their outputs are off and
in the high-impedance state. With the proper data inputs, each pair of drivers forms a full-H (or
bridge) reversible drive suitable for solenoid or motor applications.

Features

 Featuring Uni-trode L293 and L293D Products Now From Texas Instruments
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  Wide Supply-Voltage Range: 4.5 V to 36 V

 Separate Input-Logic Supply

 Internal ESD Protection

 Thermal Shutdown

 High-Noise-Immunity Inputs

 Functional Replacements for SGS L293 and SGS L293D

 Output Current 1 A Per Channel (600 mA for L293D)

 Peak Output Current 2 A Per Channel (1.2 A for L293D)

 Output Clamp Diodes for Inductive Transient Suppression (L293D)

Controlling Motors

While turning a motor on and off requires only one switch (or transistor) controlling the direction
is
deceptively difficult. It requires no fewer than four switches (or transistors) arranged in a clever
way.
H-Bridges
These four switches (or transistors) are arranged in a shape that resembles an 'H' and thus called an
H-Bridge. Each side of the motor has two transistors, one is responsible for pushing that side
HIGH
the other for pulling it LOW. When one side is pulled HIGH and the other LOW the motor will
spin in
one direction. When this is reversed (the first side LOW and the latter HIGH) it will spin the
opposite
way.
DC Motor Example
Confused? that's alright it all starts making sense with an example. Cut out the breadboard layout
sheet below and download the example code from http://tinyurl.com/qcpah9 and play around.
Stepper Motor Example (for use with 4, 5,6 & 8 wire motors)
The Arduino IDE has an included library for controlling stepper motors. To test it out with this
setup,
plug the stepper motor in with coil A across OUT 1 & 2, and coil B across OUT 3 & 4. Then
download
example code from http://tinyurl.com/nyylun and play around.
4.2.6 DC MOTOR

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 DC motors are configured in many types and sizes, including brush less, servo, and gear
motor types. A motor consists of a rotor and a permanent magnetic field stator. The magnetic
field is maintained using either permanent magnets or electromagnetic windings. DC motors
are most commonly used in variable speed and torque.Motion and controls cover a wide range
of components that in some way are used to generate and/or control motion. Areas within this
category include bearings and bushings, clutches and brakes, controls and drives, drive
components, encoders and resolves, Integrated motion control, limit switches, linear actuators,
linear and rotary motion components, linear position sensing, motors (both AC and DC motors),
orientation position sensing, pneumatics and pneumatic components, positioning stages, slides
and guides, power transmission (mechanical), seals, slip rings, solenoids, springs.
Motors are the devices that provide the actual speed and torque in a drive
system. This family includes AC motor types (single and multiphase motors, universal, servo
motors, induction, synchronous, and gear motor) and DC motors (brush less, servo motor, and
gear motor) as well as linear, stepper and air motors, and motor contactors and starters.

In any electric motor, operation is based on simple electromagnetism. A current-carrying

conductor generates a magnetic field; when this is then placed in an external magnetic field, it
will experience a force proportional to the current in the conductor, and to the strength of the
external magnetic field. As you are well aware of from playing with magnets as a kid, opposite
(North and South) polarities attract, while like polarities (North and North, South and South)
repel. The internal configuration of a DC motor is designed to harness the magnetic interaction
between a current-carrying conductor and an external magnetic field to generate rotational
motion.

Let's start by looking at a simple 2-pole DC electric motor (here red represents a magnet or
winding with a "North" polarization, while green represents a magnet or winding with a
"South" polarization).

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Every DC motor has six basic parts -- axle, rotor (a.k.a., armature), stator, commutator, field
magnet(s), and brushes. In most common DC motors (and all that Beamers will see), the
external magnetic field is produced by high-strength permanent magnets1. The stator is the
stationary part of the motor -- this includes the motor casing, as well as two or more permanent
magnet pole pieces. The rotor (together with the axle and attached commutator) rotates with
respect to the stator. The rotor consists of windings (generally on a core), the windings being
electrically connected to the commutator. The above diagram shows a common motor layout --
with the rotor inside the stator (field) magnets.

The geometry of the brushes, commutator contacts, and rotor windings are such
that when power is applied, the polarities of the energized winding and the stator magnet(s) are
misaligned, and the rotor will rotate until it is almost aligned with the stator's field magnets. As
the rotor reaches alignment, the brushes move to the next commutator contacts, and energize
the next winding. Given our example two-pole motor, the rotation reverses the direction of
current through the rotor winding, leading to a "flip" of the rotor's magnetic field, and driving it
to continue rotating.
In real life, though, DC motors will always have more than two poles (three is a very
common number). In particular, this avoids "dead spots" in the commutator. You can imagine
how with our example two-pole motor, if the rotor is exactly at the middle of its rotation
(perfectly aligned with the field magnets), it will get "stuck" there. Meanwhile, with a two-pole
motor, there is a moment where the commutator shorts out the power supply (i.e., both brushes
touch both commutator contacts simultaneously). This would be bad for the power supply,
waste energy, and damage motor components as well. Yet another disadvantage of such a
simple motor is that it would exhibit a high amount of torque” ripple" (the amount of torque it
could produce is cyclic with the position of the rotor).

57
 So since most small DC motors are of a three-pole design, let's tinker with the workings of one
via an interactive animation (JavaScript required):

You'll notice a few things from this -- namely, one pole is fully energized at a time
(but two others are "partially" energized). As each brush transitions from one commutator
contact to the next, one coil's field will rapidly collapse, as the next coil's field will rapidly
charge up (this occurs within a few microsecond). We'll see more about the effects of this later,
but in the meantime you can see that this is a direct result of the coil windings' series wiring:

There's probably no better way to see how an average dc motor is put together, than by
just opening one up. Unfortunately this is tedious work, as well as requiring the destruction of a
perfectly good motor.

4.3 Working Procedure

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 CHAPTER-5
RESULTS & DISCUSSION

59
 CHAPTER-6
ADVANTAGES AND APPLICATIONS

 Reduces the Human Power.

 More accuracy and fast working.
 Used in Auto motive Industries

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 CHAPTER-7
CONCLUSION
The objectives of this project has been achieved which was developing the hardware and software for an
accelerometer controlled robotic arm. From observation that has been made, it clearly shows that its
movement is precise, accurate, and is easy to control and user friendly to use. The robotic arm has been
developed successfully as the movement of the robot can be controlled precisely. This robotic arm control

61
method is expected to overcome the problem such as placing or picking object that away from the user,
pick and place hazardous object in a very fast and easy manner.

FUTURE SCOPE
Future work items include the following: (i) designing a more flexible pick pose estimation for
finer adjustments in the grasping process, (ii) developing a more efficient motion planning
algorithm, (iii) designing and implementing a multi-robot pick-and-sort application, and (iv)
further testing of the Vox Net object recognition process. Lack of flexibility is a weakness in the

62
current pick-pose alignment process, which leads to lowered precision in the grasping process. In
our Gilbreth application, we define one pick pose for each object type and save the pick pose in a
data set. For each identified object, we use the ICP algorithm to match the saved pick pose with
the pose of the arriving object, and compute the output pick pose. For more agile robotics
applications, autonomous pick pose estimation is better than our current approach. Makhal et al.
proposed a real-time algorithm to compute the grasping pose for unknown-object by super-quadric
representations based on point cloud data [35]. This algorithm could be a good approach because:
(i) it is suitable for single-view objects, (ii) it is a real-time approach, and (iii) it has a good
success rate for simple-geometry objects. Fine control in the grasping pipeline is required in order
to reach a pick pose with high accuracy. A majority of the grasping failures were caused by
inaccurate robot-arm control, which resulted in the actual ending pose being slightly deviated from
the target pose. The deviation causes the vacuum gripper to miss making contact with the object. A
fine-control adjustment in the pipeline can solve this problem and increase the grasping success
rate of Gilbreth.

CHAPTER-9
REFERANCES
[1] Mohd Ashiq Kamaril Yusoffa, Reza Ezuan Saminb, Babul Salam Kader Ibrahimc, “Wireless Mobile
Robotic Arm”, International Symposium on Robotics and Intelligent Sensors 2012 (IRIS 2012), July 2012.

63
[2] Wan Muhamad Hanif Wan Kadir, Reza Ezuan Samin, Babul Salam Kader Ibrahim, “Internet Controller
Robotic Arm”. International Symposium on Robotics and Intelligent Sensors 2012 (IRIS 2012), July 2012.

[3] Avinash Jain, “Servo Motor Control by Using AVR ATmega32 Microcontroller”, http://extr
emeelectronics.co.in/avr-tutorials/servo-motor-control-by-using-avr-atmega32- microcontroller/, June
2010.

[4] Paul Smith, “Programming with AVRDUDE”, http://www.ladyada.net/learn/avr/ avrdude .html/, April
2012.

[5] Avinash, “Using LCD Modules with AVR”, http://extremeelectronics.co.in/avrtutorials/using -lcd-

module-with-avrs/, July 2008.

[6] Avinash, “Using ADC on AVR”, http://extremeelectronics.co.in/avr-tutorials/using-the- analog-to-

digital-converter/, September 2008.

[7] Avinash, “Using the USART of Microcontrollers”, http://extremeelectronics.co.in /avrtutorials/using-

the-usart-of-avr-microcontrollers/, December 2008.

[8] Atmel ATmega32 Datasheet, AVR Corporation, Feb 2011.

[9] Atmel ATmega640 Datasheet, AVR Corporation, April 2012.

[10] ATmega640 Development Board Manual, Nex Robotics, Oct 2010.

[11] MMA7361L Datasheet, Freescale Semiconductors, Apr 2008.

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