RC Coupled Amplifier

RC Coupled Amplifier Contd…

Looks Like a HPF

Coupling Capacitor Results in Low Frequency Fall

 RC Coupled Amplifier Contd…

CC

CE

CC & CE are Junction Capacitors Looks Like a LPF

Junction Capacitors Results in High Frequency Fall

 Simulating a RC Coupled Amplifier

What will be the shape of the frequency response?

Simulating a RC Coupled Amplifier Contd..

Make sure to use proper Device Model

 At low frequencies,

At ω = 1/(RDCL),

Since 20 log√2 ≈ 3 dB, → 1/(RDCL) can be called as 3dB frequency (BW)

At very high frequencies →0

 low-frequency gain =

Power Consumed = ICVCC

bandwidth = 1/(RCCL)

For the best performance, Maximize gain and BW

Minimize power dissipation

Define a “figure of merit”,

 Overall performance can be improved,
by lowering the temperature

by lowering VCC, but limits voltage swings

by lowering load capacitance

Pole frequency = 1/ (total R at a node

to ground  total C at the same node to
ground)

“input pole”

λ=0
“output pole”

low-frequency gain, −gmRD

Miller’s theorem
Input capacitance increases by (1 + A0)CF

Output capacitance 
λ=0
Circuit is a source follower used in a audio amplifier. Here, Ri
establishes VGS = VDD forM1, and I1 defines ID. Assume λ = 0,
gm = 1/(200), and RI = 100k. Determine the minimum required
value of C1 and the maximum tolerable value of CL.

Let audio frequency range is 20Hz to 20kHz

Ri and Ci attenuates low frequencies

1/(RiCi) = 2π × 20 → Ci = 79.6nF

CL and Rout attenuates high frequencies

1/[(1/gm)CL ] = 2π × 20k → CL = 39.8nF
 High-Frequency Model of Bipolar Transistor

During turn on, proper operation does not begin until charge carriers create the
necessary carrier profile. Depletion region associated with the B-E is denoted
by Cje, and B-C is denoted by Cµ

Similarly, during turn off, the charge stored in the base must be removed for the
collector current to drop to zero
Is modeled by a second capacitor (Cb) between B to E,

Is more significant than Cje

Since Cb and Cje are in parallel, they are together denoted by Cπ

BJT is fabricated on a grounded substrate and C–S junction remains reverse-

biased : is denoted by CCS
Identify all of the capacitances
 High-Frequency Model of MOSFET

Identify all of the capacitances

CSB1 and CSB2 are shorted to ac ground on both ends

CGD2 is shorted “out”

CDB1, CDB2, and CGS2 appear in parallel at the output node

 Transit Frequency

“Transit” or “Cut-off” frequency (fT) is the measure of the intrinsic

speed of the device,

Is defined as the frequency at which the small-signal current gain

of the device falls to unity

Inject a sinusoidal current into the base or gate and measure the
resulting collector or drain current while the input frequency, fin,
is increased

As fin increases, Zin lowers, → Vin = IinZin and and hence Iout reduces
 We neglect Cμ and CGD time being

At the transit frequency, ωT(= 2π fT), the magnitude of the current

gain falls to unity →

CCSor CDS do not affect fT due to the ac ground at the output

The transit frequency of MOSFETs is obtained as

The minimum channel length of MOSFETs has been scaled from 1μm in
the late 1980s to 65nm today. Also, the inevitable reduction of the
supply voltage has reduced the gate-source over drive voltage from
about 400 mV to 100 mV. By what factor has the fT of MOSFETs
increased?

In saturation, CGS is about 2/3 of the gate-channel capacitance whereas,

CGD ≈ 0

Gate-channel capacitance = WLCOX

 CGS = (2/3)WLCOX

= [(W/L)nCOX(VGS - VTH)[ / [(2/3)WLCOX]

Thus, the transit frequency has increased by

approximately a factor of 59

For example, if µn = 400cm2/Vs, then 65nm devices

having an overdrive of 100mV exhibit an fT of 226GHz
 Frequency Response of CE and CS Stages

At low frequencies, device capacitances can be neglected

→ only Ci present
In applications with higher midband gain, we place a “bypass”
capacitor in parallel with RS

For very low frequencies

For very high frequencies

 High-Frequency Response

Small-signal Equivalent differs only by rπ

Can be made to look identical if Vin, RS and rπ are replaced with

their Thevenin equivalent
Use of Miller’s Theorem
The Miller multiplication makes it undesirable to have a
high gain in the circuit

For large gmRL, the capacitance at the output node  Cout + CXY
In the circuit, RS = 200, IC = 1mA, β = 100, Cπ = 100 fF, Cμ = 20fF,
and CCS = 30 fF.
(a) Calculate the input and output poles if RL = 2k. Which node
limits the bandwidth?
(b) Is it possible to choose RL such that the output pole limits
the bandwidth?
gm = 0.038A/V rπ = 2.6k

RThev = 186

→fp,in = 516MHz

→fp,out = 1.59GHz

Input pole limits the bandwidth

We must find a value of RL such that |ωp,in| > ωp,out|

If gmRL>>1,

LHS is negative → no solution exists

Even if gmRL is not much greater than unity, we cannot satisfy

above condition →input pole limits the bandwidth
 Input Impedance

CE stage consists of two parallel components

With high voltage gain,

Miller effect will lower Zin at high frequencies
 CB and CG stages - Low-Frequency Response

Signal does not “feel” the effect of Ci if |(Cis)−1| << (RS + 1/gm)

There is a pole at

The pole should be located much below

the minimum frequency of interest
 CB and CG stages – High Frequency Response

No capacitance appears between input and output

→ Does not suffer from Miller effect
Compute the poles of the circuit with λ = 0.
 Frequency Response of Followers

Current through rπ and Cπ is;

KCL at node X;

KCL at output node;

on substituting in and assuming rπ >>1/gm
If rπ →, Previous results could be applied to source follower
A source follower is driven by a resistance of RS=200 and drives a
load capacitance of 100fF. For the FET, CGS = 250fF, CGD = 80fF,
CSB = CDB = 100fF, gm = (150)−1, λ = 0, and RL = 2k.
Determine the pole – zero locations.

Zero is located at f = gm/2CGS = 4.24GHz

= 2.5810-21

= 5.810-11 check this

→ fp1 = -1.79GHz + j2.57GHz check this

→ fp2 = -1.79GHz - j2.57GHz

Determine the transfer function with M2 acting as a current source
 Cin = CX + C

In case of MOSFET, replace C by CGS

Estimate the input capacitance for the voltage follower, 0
Output impedance

→
 small RS large RS

Zout exhibits capacitive behavior small RS and

inductive behavior for large RS

Since a follower is used to reduce Zout, we assume that low-

frequency output impedance is lower than RS

→ Inductive behavior is more commonly encountered

→ May lead to oscillation if the follower sees a particular CL

 Output impedance

letting rπ & β → 
Replace C by CGS

Inductive impedance seen at the output of followers is useful

to realize “active inductors”
Assuming λ  0 for M1 and M2 but λ = 0 for M3, and neglecting
all capacitances except CGS3, compute Zout

We have

Replace RS by rO1//rO2
In the circuit determine the low-frequency cut-off. Assume
IS = 5 × 10−16A, β = 100, and VA = .

IB1 = (VCC − VBE1) / RB1 and IC1 = IB1

VBE1 = 0.800V → IB1 = 17.00A IC1 = 1.7mA

→ VBE1 = 0.748V → IB1 = 17.52A IC1 = 1.75mA

→ gm1 = (14.84)-1 rπ1 = 1.49k

VCC = IB2RB2 + VBE2 + REIC2

→ VBE2 ≈ 800 mV, = 1.13mA

→ VBE2 = 0.739V → IC1 = 1.174mA

→ gm2 = (22.15)-1 rπ2 = 2.21k

first stage:
Rin1 = rπ1||RB1
Low frequency cutoff : 1/(2Rin1C1) = 542Hz
second stage: ωL1 “dominates”
Rin2 = RB2||[rπ2 + (β + 1)RE] the low-frequency
Low frequency cutoff : 1/(2Rin2C2) = 23.6Hz response
Assuming M1 and M2 are identical and RS = 200,CGS = 250fF,
CGD = 80fF, CSB = CDB = 100fF, gm = (150)−1, λ = 0, and RL = 2 k.
Plot the frequency response of the amplifier
 Mid frequency Behavior

C1 and C2 act as a short circuit

transistor capacitances have no role

Gain = [ −gm1(RD1||Rin2) ] [ −gm2RD2 ]

 C1 contributes a low frequency cut-off
Low frequency Behavior
Gain

fL1 = 37.1 MHz

C2 contributes another low frequency cut-off

fL1 “dominates”
the low-frequency
Since RF >> RD2, response

→Rin2 = 1.3k fL2 = 6.92 MHz

High-Frequency Behavior
In the circuit, RD = 1k, CL = 1pF,  = 0, no junction capacitances,
determine the frequency at which the gain falls by 10% (≈1 dB).

|Gain| = gmRD/(1+jRDCL)

Maximum Gain = dc gain = gmRD

0.9gmRD = gmRD/(1+(RDCL)2)0.5

→ f = 77MHz
Due to a manufacturing error, a parasitic resistance Rp has
appeared in series with the source of M. Assuming λ = 0 and
neglecting other capacitances, determine the input and output
poles of the circuit.

Input pole is at 1/[(RP+gm)//RS]Cin

Output pole is at 1/RDCL

Derive the transfer function assuming λ > 0, neglecting other
capacitances. Explain why the circuit operates as an ideal
integrator if λ → 0.

Vout = [Vin] [gmrO/(1+srOCL)]

If λ → 0
Vout = [Vin] [gm/sCL)] → Integrator
Using Miller’s theorem to resistor RF in estimate AV. Assume VA
= and RF is large enough so that vout/vX  −gmRC.

RF
AV = -gmRC
RC//RFRC
RXF = RF / (1 – AV) = RF / (1 + gmRC)

VX = Vin(r//RXF) / (RB + r//RXF)

Overall gain = (-gmRC)(r//RF / (RB + r//RXF)

Using Miller’s theorem to estimate the gain. Assume rO is large
enough to assume vout/vX = gmRC.

rO

RC//rORC
Using Miller’s theorem, estimate the input capacitance. Assume λ
> 0 but neglect other capacitances. What happens if λ → 0?

If λ > 0; DC gain AV = -gmrO

→ Cin = CF(1+gmrO)

→ If λ = 0; rO → → Cin → 
→ low frequency cutoff (BW) → 0