Ecesyllabus Scheme 18 19 PDF
Ecesyllabus Scheme 18 19 PDF
Ecesyllabus Scheme 18 19 PDF
PSO1: Specify, design, build and test analog and digital systems for signal processing
including multimedia applications, using suitable components or simulation tools.
PSO2: Understand and architect wired and wireless analog and digital communication
systems as per specifications, and determine their performance.
Note
1. The Course Outcomes and RBT levels indicated for each course in the syllabus are
indicative/suggestive. The faculty can set them appropriately according to their lesson
plan.
Examination will be conducted for 100 marks with question paper containing 10
full questions, each of 20 marks
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from each
There
module.
will be 2 full questions from each module covering all the topics of the module.
Students
The total
willmarks will
have to be proportionally
answer reduced
5 full questions, to 60 one
selecting marks
fullasquestion
SEE marks
fromiseach
60
module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60
4
Department
Teaching
Practical/
Credits
Drawing
Total Marks
Tutorial
CIE Marks
Lecture
SEE Marks
Duration in
Theory
Sl. Course and
Course Title
hours
No Course Code
L T P
Mathematics
1 BSC 18MAT31 (Title as per the decision of Mathematics 2 2 -- 03 40 60 100 3
BoS in Sciences)
2 PCC 18EC32 Network Theory 3 2 -- 03 40 60 100 4
3 PCC 18EC33 Electronic Devices 3 0 -- 03 40 60 100 3
4 PCC 18EC34 Digital System Design 3 0 -- 03 40 60 100 3
5 PCC Computer Organization & -- 40 60 100 3
18EC35 3 0 03
Architecture
6 PCC 18EC36 Power Electronics & 3 0 -- 03 40 60 100 3
Instrumentation
7 PCC Electronic Devices & -- 2 2 40 60 100 2
18ECL37 03
Instrumentation Laboratory
8 PCC 18ECL38 Digital System Design Laboratory -- 2 2 03 40 60 100 2
Vyavaharika Kannada (Kannada for
18KVK39/49
communication)/
-- 2 -- -- 100 --
Aadalitha Kannada (Kannada for
18KAK39/49
9 Administration) HSMC 100 1
HSMC
OR
Constitution of India, Professional 1 -- -- 03 40 60
18CPC39/49
Ethics and Cyber Law Examination is by objective type questions
17 10 24 420 480
TOTAL OR OR 04 OR OR OR 900 24
18 08 27 360 540
Note: BSC: Basic Science, PCC: Professional Core, HSMC: Humanity and Social Science, NCMC: Non-credit mandatory course.
18KVK39 Vyavaharika Kannada (Kannada for communication) is for non-kannada speaking, reading and writing students and 18KAK39 Aadalitha
Kannada (Kannada for Administration) is for students who speak, read and write kannada.
Course prescribed to lateral entry Diploma holders admitted to III semester of Engineering programs
NC
10 18MATDIP31 Additional Mathematics - I Mathematics 02 01 -- 03 40 60 100 0
MC
(a)The mandatory non – credit courses Additional Mathematics I and II prescribed for III and IV semesters respectively, to the lateral entry Diploma
holders admitted to III semester of BE/B.Tech programs, shall attend the classes during the respective semesters to complete all the formalities of the
course and appear for the University examination. In case, any student fails to register for the said course/ fails to secure the minimum 40 % of the
prescribed CIE marks, he/she shall be deemed to have secured F grade. In such a case, the students have to fulfill the requirements during subsequent
semester/s to appear for SEE.
(b) These Courses shall not be considered for vertical progression, but completion of the courses shall be mandatory for the award of degree.
Courses prescribed to lateral entry B. Sc degree holders admitted to III semester of Engineering programs
Lateral entrant students from B.Sc. Stream, shall clear the non-credit courses Engineering Graphics and Elements of Civil Engineering and
Mechanics of the First Year Engineering Programme. These Courses shall not be considered for vertical progression, but completion of the courses
shall be mandatory for the award of degree.
AICTE Activity Points to be earned by students admitted to BE/B.Tech/B. Plan day college programme (For more details refer to Chapter
6,AICTE Activity Point Programme, Model Internship Guidelines):
Over and above the academic grades, every Day College regular student admitted to the 4 years Degree programme and every student entering 4 years
Degree programme through lateral entry, shall earn 100 and 75 Activity Points respectively for the award of degree through AICTE Activity Point
Programme. Students transferred from other Universities to fifth semester are required to earn 50 Activity Points from the year of entry to VTU. The
Activity Points earned shall be reflected on the student’s eighth semester Grade Card.
The activities can be can be spread over the years, anytime during the semester weekends and holidays, as per the liking and convenience of the student
from the year of entry to the programme. However, minimum hours’ requirement should be fulfilled. Activity Points (non-credit) have no effect on
SGPA/CGPA and shall not be considered for vertical progression.
In case students fail to earn the prescribed activity Points, Eighth semester Grade Card shall be issued only after earning the required activity Points.
Students shall be admitted for the award of degree only after the release of the Eighth semester Grade Card.
5
Department
Practical/
Drawing
Total Marks
Tutorial
Teaching
CIE Marks
Lecture
SEE Marks
Duration in
Theory
Credits
Course and
Sl.
hours
Course code Course Title
No
L T P
Mathematics
1 BSC 18MAT41 (Title as per the decision of Mathematics 2 2 -- 03 40 60 100 3
BoS in Sciences)
2 PCC 18EC42 Analog Circuits 3 2 -- 03 40 60 100 4
3 PCC 18EC43 Control Systems 3 0 -- 03 40 60 100 3
4 PCC Engineering Statistics & Linear -- 40 60 100 3
18EC44 3 0 03
Algebra
5 PCC 18EC45 Signals & Systems 3 0 -- 03 40 60 100 3
6 PCC 18EC46 Microcontroller 3 0 -- 03 40 60 100 3
7 PCC 18ECL47 Microcontroller Laboratory -- 2 2 03 40 60 100 2
8 PCC 18ECL48 Analog Circuits Laboratory -- 2 2 03 40 60 100 2
Vyavaharika Kannada (Kannada for
18KVK39/49
communication)
-- 2 -- -- 100 --
Aadalitha Kannada (Kannada for
HSMC
18KAK39/49
9 Administration) HSMC 100 1
OR
Constitution of India, Professional 1 -- -- 03 40 60
18CPC39/49
Ethics and Cyber Law Examination is by objective type questions
TOTAL 17 10 24 420 480
OR OR 04 OR OR OR 900 24
18 08 27 360 540
Note: BSC: Basic Science, PCC: Professional Core, HSMC: Humanity and Social Science, NCMC: Non-credit mandatory course.
18KVK39/49 Vyavaharika Kannada (Kannada for communication) is for non-kannada speaking, reading and writing students and 18KAK39/49
Aadalitha Kannada (Kannada for Administration) is for students who speak, read and write kannada.
Course prescribed to lateral entry Diploma holders admitted to III semester of Engineering programs
10 NCMC 18MATDIP41 Additional Mathematics – II Mathematics 02 01 -- 03 40 60 100 0
((a)The mandatory non – credit courses Additional Mathematics I and II prescribed for III and IV semesters respectively, to the lateral entry Diploma
holders admitted to III semester of BE/B.Tech programs, shall attend the classes during the respective semesters to complete all the formalities of the
course and appear for the University examination. In case, any student fails to register for the said course/ fails to secure the minimum 40 % of the
prescribed CIE marks, he/she shall be deemed to have secured F grade. In such a case, the student have to Fulfill the requirements during subsequent
semester/s to appear for SEE.
(b) These Courses shall not be considered for vertical progression, but completion of the courses shall be mandatory for the award of degree.
Courses prescribed to lateral entry B. Sc degree holders admitted to III semester of Engineering programs
Lateral entrant students from B.Sc. Stream, shall clear the non-credit courses Engineering Graphics and Elements of Civil Engineering and
Mechanics of the First Year Engineering Programme. These Courses shall not be considered for vertical progression, but completion of the courses
shall be mandatory for the award of degree.
AICTE activity Points: In case students fail to earn the prescribed activity Points, Eighth semester Grade Card shall be issued only after earning the
required activity Points. Students shall be admitted for the award of degree only after the release of the Eighth semester Grade Card.
6
Department
Teaching
Practical/
Credits
Drawing
Total Marks
Tutorial
CIE Marks
Lecture
SEE Marks
Duration in
Theory
Sl. Course and
Course Title
hours
No Course code
L T P
1 HSMC 18ES51 Technological Innovation
Management And 3 0 -- 03 40 60 100 3
Entrepreneurship
2 PCC 18EC52 Digital Signal Processing 3 2 -- 03 40 60 100 4
3 PCC Principles of Communication -- 40 60 100
18EC53 3 2 03 4
Systems
4 PCC 18EC54 Information Theory & Coding 3 -- -- 03 40 60 100 3
5 PCC 18EC55 Electromagnetic Waves 3 -- -- 03 40 60 100 3
6 PCC 18EC56 Verilog HDL 3 -- -- 03 40 60 100 3
7 PCC Digital Signal Processing -- 2 2 40 60 100 2
18ECL57 03
Laboratory
8 PCC 18ECL58 HDL Laboratory -- 2 2 03 40 60 100 2
Civil/
Environmental
9 HSMC 18CIV59 Environmental Studies [Paper setting: 1 -- -- 02 40 60 100 1
Civil Engineering
Board]
TOTAL 19 08 4 26 360 540 900 25
AICTE activity Points: In case students fail to earn the prescribed activity Points, Eighth semester Grade Card shall be issued only after earning the
required activity Points. Students shall be admitted for the award of degree only after the release of the Eighth semester Grade Card.
7
Department
Practical/
Drawing
Total Marks
Tutorial
Teaching
CIE Marks
Lecture
SEE Marks
Duration in
Theory
Credits
Sl. Course and
hours
Course Title
No Course code
L T P
1 PCC 18EC61 Digital Communication 3 2 -- 03 40 60 100 4
2 PCC 18EC62 Embedded Systems 3 2 -- 03 40 60 100 4
3 PCC 18EC63 Microwave & Antennas 3 2 -- 03 40 60 100 4
4 PEC 18XX64X Professional Elective -1 3 -- -- 03 40 60 100 3
5 OEC 18XX65X Open Elective –A 3 -- -- 03 40 60 100 3
6 PCC 18ECL66 Embedded Systems Laboratory -- 2 2 03 40 60 100 2
7 PCC 18ECL67 Communication Laboratory -- 2 2 03 40 60 100 2
8 MP 18ECMP68 Mini-project -- -- 2 03 40 60 100 2
To be carried out during the vacation/s of VI and VII semesters and /or VII
9 Internship -- Internship
and VIII semesters.
TOTAL 15 10 6 24 320 480 800 24
Note: PCC: Professional core, PEC: Professional Elective, OE: Open Elective, MP: Mini-project.
Professional Elective -1
Course code under Course Title
18XX64X
18EC641 Operating System
18EC642 Artificial Neural Networks
18EC643 Object Oriented Programming using C++
18EC644 Digital System Design using Verilog
18EC645 Nanoelectronics
Open Elective –A
(i) 18EC651 Signal Processing (ii) 18EC652 Sensors & Signal Conditioning
Students can select any one of the open electives offered by other Departments except those that are offered by the parent Department (Please refer to
the list of open electives under 18XX65X).
Selection of an open elective shall not be allowed if,
The candidate has studied the same course during the previous semesters of the programme.
The syllabus content of open elective is similar to that of the Departmental core courses or professional electives.
A similar course, under any category, is prescribed in the higher semesters of the programme.
Registration to electives shall be documented under the guidance of Programme Coordinator/ Advisor/Mentor.
Mini-project work:
Based on the ability/abilities of the student/s and recommendations of the mentor, a single discipline or a multidisciplinary Mini- project can be
assigned to an individual student or to a group having not more than 4 students.
CIE procedure for Mini-project:
(i) Single discipline: The CIE marks shall be awarded by a committee consisting of the Head of the concerned Department and two senior faculty
members of the Department, one of whom shall be the Guide.
The CIE marks awarded for the Mini-project work, shall be based on the evaluation of project report, project presentation skill and question and answer
session in the ratio 50:25:25.The marks awarded for the project report shall be the same for all the batch mates.
(ii) Interdisciplinary: Continuous Internal Evaluation shall be group wise at the college level with the participation of all the guides of the college.
The CIE marks awarded for the Mini-project, shall be based on the evaluation of project report, project presentation skill and question and answer
session in the ratio 50:25:25.The marks awarded for the project report shall be the same for all the batch mates.
SEE for Mini-project:
(i) Single discipline: Contribution to the Mini-project and the performance of each group member shall be assessed individually in the semester end
examination (SEE) conducted at the department.
(ii) Interdisciplinary: Contribution to the Mini-project and the performance of each group member shall be assessed individually in semester end
examination (SEE) conducted separately at the departments to which the student/s belong to.
Internship: All the students admitted to III year of BE/B.Tech shall have to undergo mandatory internship of 4 weeks during the vacation of VI and
VII semesters and /or VII and VIII semesters. A University examination shall be conducted during VIII semester and the prescribed credit shall be
included in VIII semester. Internship shall be considered as a head of passing and shall be considered for the award of degree. Those, who do not take-
up/complete the internship shall be declared fail and shall have to complete during subsequent University examination after satisfying the internship
requirements.
AICTE activity Points: In case students fail to earn the prescribed activity Points, Eighth semester Grade Card shall be issued only after earning the
required activity Points. Students shall be admitted for the award of degree only after the release of the Eighth semester Grade Card.
8
Department
Practical/
Drawing
Total Marks
Tutorial
Teaching
CIE Marks
Lecture
SEE Marks
Duration in
Theory
Credits
Sl. Course and
hours
Course Title
No Course code
L T P
1 PCC 18EC71 Computer Networks 3 -- -- 03 40 60 100 3
2 PCC 18EC72 VLSI Design 3 -- -- 03 40 60 100 3
3 PEC 18XX73X Professional Elective - 2 3 -- -- 03 40 60 100 3
4 PEC 18XX74X Professional Elective - 3 3 -- -- 03 40 60 100 3
5 OEC 18XX75X Open Elective -B 3 -- -- 03 40 60 100 3
6 PCC 18ECL76 Computer Networks Lab -- 2 2 03 40 60 100 2
7 PCC 18ECL77 VLSI Laboratory -- 2 2 03 40 60 100 2
8 Project 18ECP78 Project Work Phase - 1 -- -- 2 -- 100 -- 100 1
(If not completed during the vacation of VI and VII semesters, it shall be
9 Internship -- Internship
carried out during the vacation of VII and VIII semesters )
TOTAL 15 4 6 21 380 420 800 20
Note: PCC: Professional core, PEC: Professional Elective.
Professional Elective - 2
Course code under Course Title
18XX73X
18EC731 Real Time System
18EC732 Satellite Communication
18EC733 Digital Image Processing
18EC734 Data Structures using C++
18EC735 DSP Algorithms & Architecture
Professional Electives - 3
Course code under Course Title
18XX74X
18EC741 IOT & Wireless Sensor Networks
18EC742 Automotive Electronics
18EC743 Multimedia Communication
18EC744 Cryptography
18EC745 Machine Learning
Open Elective –B
(i) 18EC751 Communication Theory (ii) 18EC752 Neural Networks
Students can select any one of the open electives offered by other Departments except those that are offered by the parent Department (Please refer to
the list of open electives under 18XX75X).
Selection of an open elective shall not be allowed if,
The candidate has studied the same course during the previous semesters of the programme.
The syllabus content of open elective is similar to that of the Departmental core courses or professional electives.
A similar course, under any category, is prescribed in the higher semesters of the programme.
Registration to electives shall be documented under the guidance of Programme Coordinator/ Advisor/Mentor.
Project work:
Based on the ability/abilities of the student/s and recommendations of the mentor, a single discipline or a multidisciplinary project can be assigned to an
individual student or to a group having not more than 4 students. In extraordinary cases, like the funded projects requiring students from different
disciplines, the project student strength can be 5 or 6.
CIE procedure for Project Work Phase - 1:
(i) Single discipline: The CIE marks shall be awarded by a committee consisting of the Head of the concerned Department and two senior faculty
members of the Department, one of whom shall be the Guide.
The CIE marks awarded for the project work phase -1, shall be based on the evaluation of the project work phase -1 Report (covering Literature Survey,
Problem identification, Objectives and Methodology), project presentation skill and question and answer session in the ratio 50:25:25.The marks
awarded for the Project report shall be the same for all the batch mates.
(ii) Interdisciplinary: Continuous Internal Evaluation shall be group wise at the college level with the participation of all guides of the college.
Participation of external guide/s, if any, is desirable.
The CIE marks awarded for the project work phase -1, shall be based on the evaluation of project work phase -1 Report, project presentation skill and
question and answer session in the ratio 50:25:25.The marks awarded for the project report shall be the same for all the batch mates.
Internship: All the students admitted to III year of BE/B.Tech shall have to undergo mandatory internship of 4 weeks during the vacation of VI and
VII semesters and /or VII and VIII semesters. A University examination shall be conducted during VIII semester and the prescribed credit shall be
included in VIII semester. Internship shall be considered as a head of passing and shall be considered for the award of degree. Those, who do not take-
up/complete the internship shall be declared fail and shall have to complete during subsequent University examination after satisfying the internship
requirements.
AICTE activity Points: In case students fail to earn the prescribed activity Points, Eighth semester Grade Card shall be issued only after earning the
required activity Points. Students shall be admitted for the award of degree only after the release of the Eighth semester Grade Card.
9
Department
Total Marks
Practical/
Teaching
CIE Marks
SEE Marks
Duration in
Drawing
Tutorial
Lecture
Credits
Theory
Course and
Sl.
hours
Course code Course Title
No
L T P
1 PCC 18EC81 Wireless and Cellular 3 -- -- 03 40 60 100
3
Communication
2 PEC 18XX82X Professional Elective - 4 3 -- -- 03 40 60 100 3
3 Project 18ECP83 Project Work Phase - 2 -- -- 2 03 40 60 100 8
4 Seminar 18ECS84 Technical Seminar -- -- 2 03 100 -- 100 1
Completed during the vacation/s of
5 Internship 18ECI85 Internship VI and VII semesters and /or VII 03 40 60 100 3
and VIII semesters.)
TOTAL 06 -- 4 15 260 240 500 18
Professional Electives - 4
Course code Course Title
under 18XX82X
18EC821 Network Security
18EC822 Micro Electro Mechanical Systems
18EC823 Radar Engineering
18EC824 Optical Communication Networks
18EC825 Biomedical Signal Processing
Project Work
CIE procedure for Project Work Phase - 2:
(i) Single discipline: The CIE marks shall be awarded by a committee consisting of the Head of the concerned Department and two senior faculty
members of the Department, one of whom shall be the Guide.
The CIE marks awarded for the project work phase -2, shall be based on the evaluation of project work phase -2 Report, project presentation skill and
question and answer session in the ratio 50:25:25.The marks awarded for the project report shall be the same for all the batch mates.
(ii) Interdisciplinary: Continuous Internal Evaluation shall be group wise at the college level with the participation of all guides of the college.
Participation of external guide/s, if any, is desirable.
The CIE marks awarded for the project work phase -2, shall be based on the evaluation of project work phase -2 Report, project presentation skill and
question and answer session in the ratio 50:25:25.The marks awarded for the project report shall be the same for all the batch mates.
SEE for Project Work Phase - 2:
(i) Single discipline: Contribution to the project and the performance of each group member shall be assessed individually in semester end examination
(SEE) conducted at the department.
(ii) Interdisciplinary: Contribution to the project and the performance of each group member shall be assessed individually in semester end
examination (SEE) conducted separately at the departments to which the student/s belong to.
Internship: Those, who have not pursued /completed the internship shall be declared as fail and have to complete during subsequent University
examination after satisfying the internship requirements.
AICTE activity Points: In case students fail to earn the prescribed activity Points, Eighth semester Grade Card shall be issued only after earning the
required activity Points. Students shall be admitted for the award of degree only after the release of the Eighth semester Grade Card.
Activity points of the students who have earned the prescribed AICTE activity Points shall be sent the University along with the CIE marks of 8th
semester. In case of students who have not satisfied the AICTE activity Points at the end of eighth semester, the column under activity Points shall be
marked NSAP (Not Satisfied Activity Points).
BE 2018 SCHEME THIRD SEMESTER SYLLABUS EC / TC
Exam Hours 03
CREDITS – 04
Course objectives: This course will enable students to:
Module – 2
Network Theorems:
Superposition, Reciprocity, Millman‘s theorems, Thevinin‘s and
L1, L2, L3,
Norton‘s theorems, Maximum Power transfer theorem. L4
Module – 3
Transient behavior and initial conditions: Behavior of circuit
elements under switching condition and their Representation,
L1 , L2 , L3
evaluation of initial and final conditions in RL, RC and RLC circuits
for AC and DC excitations.
Module – 4
Laplace Transformation & Applications: Solution of networks, L1, L2, L3,
step, ramp and impulse responses, waveform Synthesis. L4
Module – 5
Module-4
Field Effect Transistors
Basic pn JFET Operation, Equivalent Circuit and Frequency
Limitations, MOSFET- Two terminal MOS structure- Energy band
L1,L2
diagram, Ideal Capacitance – Voltage Characteristics and Frequency
Effects, Basic MOSFET Operation- MOSFET structure, Current-
Voltage Characteristics.
(Text 2: 9.1.1, 9.4, 9.6.1, 9.6.2, 9.7.1, 9.7.2, 9.8.1, 9.8.2).
Module-5
Fabrication of p-n junctions
Thermal Oxidation, Diffusion, Rapid Thermal Processing, Ion
implantation, chemical vapour deposition, photolithography, Etching,
metallization. (Text 1: 5.1) L1,L2
Integrated Circuits
Background, Evolution of ICs, CMOS Process Integration, Integration
of Other Circuit Elements. (Text 1: 9.1, 9.2, 9.3.1, 9.3.2).
Course outcomes: After studying this course, students will be able
to:
Understand the principles of semiconductor Physics
Understand the principles and characteristics of different types
of semiconductor devices
Understand the fabrication process of semiconductor devices
Utilize the mathematical models of semiconductor junctions and
MOS transistors for circuits and systems.
Text Books:
1. Ben. G. Streetman, Sanjay Kumar Banergee, “Solid State Electronic Devices”,
7thEdition, Pearson Education, 2016, ISBN 978-93-325-5508-2.
2. Donald A Neamen, Dhrubes Biswas, “Semiconductor Physics and Devices”,
4th Edition, MCGraw Hill Education, 2012, ISBN 978-0-07-107010-2.
Reference Book:
1. S. M. Sze, Kwok K. Ng, “Physics of Semiconductor Devices”, 3rd Edition,
Wiley, 2018.
2. A. Bar-Lev, “Semiconductor and Electronic Devices”, 3rd Edition, PHI, 1993.
DIGITAL SYSTEM DESIGN
SEMESTER – III (EC/TC)
[As per Choice Based Credit System (CBCS) Scheme]
Course Code 18EC34 CIE Marks 40
Number of LectureHours/Week 03 SIE Marks 60
40 (08 Hours per Exam
Total Number of Lecture Hours 03
Module) Hour
CREDITS – 03
Course objectives: This course will enable students to:
Illustrate simplification of Algebraic equations using Karnaugh Maps and
Quine-McClusky Techniques.
Design Decoders, Encoders, Digital Multiplexer, Adders, Subtractors and
Binary Comparators.
Describe Latches and Flip-flops, Registers and Counters.
Analyze Mealy and Moore Models.
Develop state diagrams Synchronous Sequential Circuits.
Appreciate the applications of digital circuits.
Module -4
Sequential Circuit Design: Design of a synchronous counter,
Design of a synchronous mod-n counter using clocked JK, D, T and
SR flip-flops. (Text 2 - Chapter 6) L1, L2, L3
Mealy and Moore models, State machine notation, Construction of
state diagrams. (Text 1 - Chapter 6)
Module -5
Applications of Digital Circuits: Design of a Sequence Detector,
Guidelines for construction of state graphs, Design Example – Code
Converter, Design of Iterative Circuits (Comparator), Design of
L1, L2, L3
Sequential Circuits using ROMs and PLAs, CPLDs and FPGAs, Serial
Adder with Accumulator, Design of Binary Multiplier, Design of
Binary Divider.
(Text 3 – 14.1, 14.3, 16.2, 16.3, 16.4, 18.1, 18.2, 18.3)
Course Outcomes: After studying this course, students will be able to:
Explain the concept of combinational and sequential logic circuits.
Design the combinational logic circuits.
Design the sequential circuits using SR, JK, D, T flip-flops and Mealy & Moore
machines
Design applications of Combinational & Sequential Circuits.
Text Books:
1. John M Yarbrough,-Digital Logic Applications and Design, Thomson
Learning,2001.
2. Donald D. Givone, ―Digital Principles and Design‖, McGraw Hill, 2002.
3. Charles H Roth Jr., Larry L. Kinney ―Fundamentals of Logic Design, Cengage
Learning, 7th Edition.
Reference Books:
1. D. P. Kothari and J. S Dhillon, ―Digital Circuits and Design‖, Pearson, 2016,
2. Morris Mano, ―Digital Design‖, Prentice Hall of India, Third Edition.
3. K. A. Navas, ―Electronics Lab Manual‖, Volume I, PHI, 5th Edition, 2015.
COMPUTER ORGANIZATION AND ARCHITECTURE
SEMESTER – III (EC/TC)
Exam
Total Number of Lecture Hours 40 (08Hours per Module) 03
Hours
CREDITS– 03
Course Objectives: This course will enable students to:
Explain the basic sub systems of a computer, their organization, structure
and operation.
Illustrate the concept of programs as sequences of machine instructions.
Demonstrate different ways of communicating with I/O devices
Describe memory hierarchy and concept of virtual memory.
Illustrate organization of simple pipelined processor and other computing
systems.
Module 1 RBT Level
Module 2
Addressing Modes, Assembly Language, Basic Input and Output
Operations, Stacks and Queues, Subroutines, Additional Instructions L1, L2, L3
(from 2.4.7 of Chap 2, except 2.9.3, 2.11 & 2.12 of Text).
Module 3
Module 4
Memory System: Basic Concepts, Semiconductor RAM Memories-
Internal organization of memory chips, Static memories,
Asynchronous DRAMS, Read Only Memories, Cash Memories, Virtual
Memories, Secondary Storage-Magnetic Hard Disks (5.1, 5.2, 5.2.1, L1, L2, L3
5.2.2, 5.2.3, 5.3, 5.5 (except 5.5.1 to 5.5.4), 5.7 (except 5.7.1),
5.9, 5.9.1 of Chap 5 of Text).
Module 5
Basic Processing Unit: Some Fundamental Concepts, Execution of a
Complete Instruction, Multiple Bus Organization, Hardwired Control,
Microprogrammed Control (upto 7.5 except 7.5.1 to 7.5.6 of Chap L1,L2, L3
7 of Text).
Course Outcomes: After studying this course, students will be able to:
Explain the basic organization of a computer system.
Explain different ways of accessing an input / output device including
interrupts.
Illustrate the organization of different types of semiconductor and other
secondary storage memories.
Illustrate simple processor organization based on hardwired control and
micro programmed control.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module
The total marks will be proportionally reduced to 60 marks as SEE marks is
60.
Text Book:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky: Computer Organization, 5th
Edition, Tata McGraw Hill, 2002.
Reference Books:
1. David A. Patterson, John L. Hennessy: Computer Organization and Design –
The Hardware / Software Interface ARM Edition, 4th Edition, Elsevier, 2009.
2. William Stallings: Computer Organization & Architecture, 7th Edition, PHI,
2006.
3. Vincent P. Heuring & Harry F. Jordan: Computer Systems Design and
Architecture, 2nd Edition, Pearson Education, 2004.
POWER ELECTRONICS AND INSTRUMENTATION
SEMESTER – III (EC/TC)
[As per Choice Based Credit System (CBCS) Scheme]
Course Code 18EC36 CIE Marks 40
2. Half wave rectifier and Full wave rectifier with and without filter and measure
the ripple factor
3. Characteristics of Zener diode and design a Simple Zener voltage regulator
determine line and load regulation
4. Characteristics of LDR and Photo diode and turn on an LED using LDR
Course Outcomes: On the completion of this laboratory course, the students will
be able to:
Understand the characteristics of various electronic devices and measurement
of parameters.
Design and test simple electronic circuits
Use of circuit simulation software for the implementation and characterization
of electronic circuits and devices.
NOTE:
1. Use discrete components to test and verify the Revised
logic gates. The IC numbers given are suggestive; Bloom’s
any equivalent ICs can beused.
Taxonomy
2. For experiment No. 11 and 12 any open source or (RBT) Level
licensed simulation tool may be used.
Laboratory Experiments:
1. Verify
(i) Demorgan’s Theorem for 2 variables.
L1, L2, L3
(ii) The sum-of product and product-of-sum
expressions using universal gates.
2. Design and implement
(i) Half Adder & Full Adder using i) basic gates. ii) NAND
gates L3, L4
(ii) Half subtractor& Full subtractor using i) basic gates
ii) NAND gates
3. Design and implement
(i) 4-bitParallelAdder/Subtractor using IC 7483.
L3, L4
(ii) BCD to Excess-3 code conversion and vice-
versa.
4. Design and Implementation of
(i) 1-bit Comparator L3, L4
(ii) 5-bit Magnitude Comparator using IC 7485.
5. Realize
(i) Adder & Subtactors using IC 74153. L2, L3, L4
(ii) 4-variable function using IC74151(8:1MUX).
6. Realize (i) Adder & Subtractors using IC74139.
(ii) Binary to Gray code conversion & vice-versa
L2, L3, L4
(74139)
7. Realize the following flip-flops using NANDGates.
L2, L3
Master-Slave JK, D & T Flip-Flop.
Exam Hours 03
CREDITS – 01
Course objectives: This course will enable students to:
To know the fundamental political codes, structure, procedures, powers, and
duties of Indian government institutions, fundamental rights, directive
principles, and the duties of citizens
To understand engineering ethics and their responsibilities, identify their
individual roles and ethical responsibilities towards society.
To know about the cybercrimes and cyber laws for cyber safety measures.
Module - 2
Union Executive and State Executive:
Parliamentary System, Federal System, Centre-State Relations.
Union Executive – President, Prime Minister, Union Cabinet,
Parliament - LS and RS, Parliamentary Committees, Important
Parliamentary Terminologies. Supreme Court of India, Judicial
Reviews and Judicial Activism. State Executives – Governor, Chief L1, L2, L3
Minister, State Cabinet, State Legislature, High Court and
Subordinate Courts, Special Provisions (Articles 370.371,371J)
for some States.
Module – 3
Elections, Amendments and Emergency Provisions:
Elections, Electoral Process, and Election Commission of India,
Election Laws. Amendments - Methods in Constitutional
Amendments (How and Why) and Important Constitutional
Amendments. Amendments – 7,9,10,12,42,44, 61, 73,74, ,75,
L1, L2, L3
86, and 91,94,95,100,101,118 and some important Case
Studies. Emergency Provisions, types of Emergencies and its
consequences.
Constitutional special provisions:
Special Provisions for SC and ST, OBC, Women, Children and
Backward Classes.
Module - 4
Professional / Engineering Ethics:
Scope & Aims of Engineering & Professional Ethics - Business
Ethics, Corporate Ethics, Personal Ethics. Engineering and
Professionalism, Positive and Negative Faces of Engineering
Ethics, Code of Ethics as defined in the website of Institution of
Engineers (India): Profession, Professionalism, and Professional L1, L2, L3
Responsibility. Clash of Ethics, Conflicts of Interest.
Responsibilities in Engineering Responsibilities in Engineering
and Engineering Standards, the impediments to Responsibility.
Trust and Reliability in Engineering, IPRs (Intellectual Property
Rights), Risks, Safety and liability in Engineering.
Module - 5
Internet Laws, Cyber Crimes and Cyber Laws:
Internet and Need for Cyber Laws, Modes of Regulation of
Internet, Types of cyber terror capability, Net neutrality, Types of
L1, L2, L3
Cyber Crimes, India and cyber law, Cyber Crimes and the
information Technology Act 2000, Internet Censorship.
Cybercrimes and enforcement agencies.
Course Outcomes: At the end of the course, the students will be able to
Have constitutional knowledge and legal literacy.
Understand Engineering and Professional ethics and responsibilities of
Engineers.
Understand the cybercrimes and cyber laws for cyber safety measures.
Number of Lecture
2+2 (Tutorial) SEE Marks 60
Hours/Week
CREDITS – 03
Text Book:
Number of Lecture
3+2 (Tutorial) SEE Marks 60
Hours/Week
Exam Hours 03
CREDITS – 04
Module -5
Op-Amp Circuits: DAC - Weighted resistor and R-2R ladder, ADC-
Successive approximation type, Small Signal half wave rectifier, Active
Filters, First and second order low-pass and high-pass Butterworth
filters, Band-pass filters, Band reject filters.
555 Timer and its applications: Monostable and Astable L1, L2, L3
Multivibrators.
[Text 2: 8.11(8.11.1a, 8.11.1b), 8.11.2a, 8.12.2, 7.2, 7.3, 7.4, 7.5,
7.6, 7.8, 7.9, 9.4.1, 9.4.1(a), 9.4.3, 9.4.3(a)]
Course Outcomes:At the end of this course students will demonstrate the ability
to
Understand the characteristics of BJTs and FETs.
Design and analyze BJT and FET amplifier circuits.
Design sinusoidal and non-sinusoidal oscillators.
Understand the functioning of linear ICs.
Design of Linear IC based circuits.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is
60.
Text Books:
Reference Books:
CREDITS – 03
Course objectives: This course will enable students to:
Understand the basic features, configurations and application of control
systems.
Understand various terminologies and definitions for the control systems.
Learn how to find a mathematical model of electrical, mechanical and
electro- mechanical systems.
Know how to fin d time response from the transfer function.
Find the transfer function via Mason s’ rule.
Analyze the stability of a system from the transfer function.
Modules RBT Level
Module – 1
Introduction to Control Systems: Types of Control Systems, Effect
of Feedback System s, Differential equation of Physical Systems –
L1, L2, L3
Mechanical Systems, Electrical Systems, Electromechanical
systems, Analogous Systems.
Module – 2
Block diagrams and signal flow graphs: Transfer functions,
L1, L2, L3
Block diagram algebra and Signal Flow graphs.
Module – 3
Time Response of feedback control systems: Standard test
signals, Unit step response of First and Second order Systems.
Time response specifications, Time response specifications of L1, L2, L3
second order systems, steady state errors and error constants.
Introduction to PI, PD and PID Controllers (excluding design).
Module – 4
Stability analysis: Concepts of stability, Necessary conditions for
Stability, Routh stability criterion, Relative stability analysis:
more on the Routh stability criterion.
Introduction to Root-Locus Techniques, The root locus
L1, L2, L3
concepts, Construction of root loci.
Frequency domain analysis and stability: Correlation between
time and frequency response, Bode Plots, Experimental
determination of transfer function.
Module – 5
Introduction to Polar Plots, (Inverse Polar Plots excluded)
Mathematical preliminaries, Nyquist Stability criterion,
(System s with transportation lag excluded)
Introduction to lead, lag and lead- lag compensating networks
L1, L2, L3
(excluding design).
Introduction to State variable analysis: Concepts of state, state
variable and state models for electrical systems, Solution of state
equations.
Course Outcomes: At the end of the course, the students will be able to
Develop the mathematical model of mechanical and electrical systems.
Develop transfer function for a given control system using block diagram
reduction techniques and signal flow graph method.
Determine the time domain specification s for first an d second order
systems.
Deter mine the stability of a system in the time domain using Routh-
Hurwitz criterion and Root-locus technique.
Determine the s stability of a system in the frequency domain u sing
Nyquist and bode plots.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is
60.
Text Book:
J. Nagarath an d M. Gopal, “ Control System s Engineering”, New Age
International (P) Limited, Publishers, Fifth edition- 2005,ISBN: 81 - 224 -
2008-7.
Reference Books:
1. “Modern Control Engineering,” K. Ogata, Pearson Education Asia/
PHI, 4th Edition, 2002. ISBN 978 - 81 - 203 - 4010 - 7.
2. “Automatic Control Systems”, Benjamin C. Kuo, John Wiley India Pvt.
Ltd., 8 th Edition, 2008.
3. “Feedback and Control System,” Joseph J Distefano III et al.,
Schaum’s Outlines, TMH, 2 n d Edition 2007.
ENGINEERING STATISTICS and LINEAR ALGEBRA
SEMESTER – IV (EC/TC)
[As per Choice Based Credit System (CBCS) Scheme]
Course Code 18EC44 CIE Marks 40
Number of Lecture
03 SEE Marks 60
Hours/Week
40 (8 Hours per
Total Number of Lecture Hours Exam Hours 03
Module)
CREDITS – 03
Course Objectives: This course will enable students to:
Understand and Analyze Single and Multiple Random Variables, and their
extension to Random Processes.
Familiarization with the concept of Vector spaces and orthogonality with a
qualitative insight into applications in communications.
Compute the quantitative parameters for functions of single and Multiple
Random Variables and Processes.
Compute the quantitative parameters for Matrices and Linear
Transformations.
Module-1 RBT Level
Course outcomes: After studying this course, students will be able to:
Identify and associate Random Variables and Random Processes in
Communication events.
Analyze and model the Random events in typical communication events to
extract quantitative statistical parameters.
Analyze and model typical signal sets in terms of a basis function set of
Amplitude, phase and frequency.
Demonstrate by way of simulation or emulation the ease of analysis
employing basis functions, statistical representation and Eigenvalues.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is
60.
Text Books:
1. Richard H Williams, “Probability, Statistics and Random Processes for
Engineers” Cengage Learning, 1st Edition, 2003, ISBN 13: 978-0-534-
36888-3, ISBN 10: 0-534-36888-3.
2. Gilbert Strang, “Linear Algebra and its Applications”, Cengage Learning, 4th
Edition, 2006, ISBN 97809802327
Reference Books:
1. Hwei P. Hsu, “Theory and Problems of Probability, Random Variables, and
Random Processes” Schaums Outline Series, McGraw Hill. ISBN 10: 0-07-
030644-3.
2. K. N. HariBhat, K AnithaSheela, JayantGanguly, “Probability Theory and
Stochastic Processes for Engineers”, Cengage Learning India, 2019, ISBN:
Not in book
SIGNALS AND SYSTEMS
SEMESTER – IV (EC/TC)
[As per Choice Based Credit System (CBCS)
Course Code 18EC45 CIE Marks 40
40 (8 Hours per
Total Number of Lecture Hours Exam Hours 03
Module)
CREDITS – 03
Course objectives: This course will enable students to:
Course Outcomes: At the end of the course, students will be able to:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is
60.
Text Book:
1. “The 8051 Microcontroller and Embedded Systems – using assembly and C”,
Muhammad Ali Mazidi and Janice Gillespie Mazidi and Rollin D. McKinlay;
PHI, 2006 / Pearson, 2006.
2. “The 8051 Microcontroller”, Kenneth J. Ayala, 3rd Edition,
Thomson/Cengage Learning.
Reference Books:
Laboratory Experiments
I. PROGRAMMING
1. Data Transfer: Block Move, Exchange, Sorting, Finding largest element in
an array.
2. Arithmetic Instructions - Addition/subtraction, multiplication and division,
square, Cube – (16 bits Arithmetic operations – bit addressable).
3. Counters.
4. Boolean & Logical Instructions (Bit manipulations).
5. Conditional CALL & RETURN.
6. Code conversion: BCD – ASCII; ASCII – Decimal; Decimal - ASCII; HEX -
Decimal and Decimal - HEX.
7. Programs to generate delay, Programs using serial port and on-Chip
timer/counter.
II. INTERFACING
1. Interface a simple toggle switch to 8051 and write an ALP to generate an
interrupt which switches on an LED (i) continuously as long as switch is on
and (ii) only once for a small time when the switch is turned on.
2. Write a C program to (i) transmit and (ii) to receive a set of characters serially
by interfacing 8051 to a terminal.
3. Write ALPs to generate waveforms using ADC interface.
4. Write ALP to interface an LCD display and to display a message on it.
5. Write ALP to interface a Stepper Motor to 8051 to rotate the motor.
6. Write ALP to interface ADC-0804 and convert an analog input connected to it.
Course Outcomes: On the completion of this laboratory course, the students will
be able to:
Write Assembly language programs in 8051 for solving simple problems that
manipulate input data using different instructions of 8051.
Interface different input and output devices to 8051 and control them using
Assembly language programs.
Interface the serial devices to 8051 and do the serial transfer using C
programming.
Conduct of Practical Examination:
All laboratory experiments are to be included for practical
examination.
Students are allowed to pick one experiment from the lot.
Strictly follow the instructions as printed on the cover page of
answer script for breakup of marks.
Change of experiment is allowed only once and 15% Marks
allotted to the procedure part to be made zero.
ANALOG CIRCUITS LABORATORY
SEMESTER – IV (EC/TC)
[As per Choice Based Credit System (CBCS) scheme]
Laboratory Code 18ECL48 CIE 40
Marks
Number of Lecture 02 Hr Tutorial (Instructions)
SEE Marks 60
Hours/Week
+ 02 Hours Laboratory
RBT Level L1, L2, L3 Exam Hours 03
CREDITS – 02
2. Design and set up the BJT common emitter voltage amplifier with and without
feedback and determine the gain- bandwidth product, input and output
impedances.
3. Design and set-up BJT/FET i) Colpitts Oscillator, and ii) Crystal Oscillator
4. Design active second order Butterworth low pass and high pass filters.
6. Test a comparator circuit and design a Schmitt trigger for the given UTP and
LTP values and obtain the hysteresis.
7. Design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary
input from toggle switches and (ii) by generating digital inputs using mod-16
8. counter.
Design Monostable and Astable Multivibrator using 555 Timer.
Course Outcomes: On the completion of this laboratory course, the students will
be able to:
CREDITS – 0
Provide essential concepts of linear algebra, second & higher order differential
equations along with methods to solve them.
Provide an insight into elementary probability theory and numerical methods.
Module -3
Higher order ODE’s: Linear differential equations of second and
higher order equations with constant coefficients. Homogeneous
/non-homogeneous equations. Inverse differential operators. L1, L2
[Particular Integral restricted to R(x)= e , sin ax /cos ax for f D y Rx . ]
ax
Module -4
1. Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
2. Each full question can have a maximum of 4 sub questions.
3. There will be 2 full questions from each module covering all the topics of the
module.
4. Students will have to answer 5 full questions, selecting one full question from
each module.
5. The total marks will be proportionally reduced to 60 marks as SEE marks is
60.
Text Book:
CREDITS – 01
Course objectives: This course will enable students to:
To know the fundamental political codes, structure, procedures, powers, and
duties of Indian government institutions, fundamental rights, directive
principles, and the duties of citizens
To understand engineering ethics and their responsibilities, identify their
individual roles and ethical responsibilities towards society.
To know about the cybercrimes and cyber laws for cyber safety measures.
The SEE question paper will be set for 100 marks and the marks scored by
the students will proportionately be reduced to 60. The pattern of the
question paper will be objective type (MCQ).
For the award of 40 CIE marks, refer the University regulations 2018.
Text Books:
1. Shubham Singles, Charles E. Haries, and et al: “Constitution of India,
Professional Ethics and Human Rights” by Cengage Learning India, Latest
Edition – 2019.
2. Alfred Basta and et al: “Cyber Security and Cyber Laws” by Cengage Learning
India - 2018. Chapter – 19, Page No’s: 359 to 383.
Reference Books:
V Semester (EC/TC)
Module-3
Design of FIR Filters: Characteristics of practical frequency –selective
filters, Symmetric and Antisymmetric FIR filters, Design of Linear-phase
FIR filters using windows - Rectangular, Hamming, Hanning, Bartlett L1,2,
windows. Design of FIR filters using frequency sampling method. L3
Structure for FIR Systems: Direct form, Cascade form and Lattice
structures. [Text1]
Module-4
IIR Filter Design: Infinite Impulse response Filter Format, Bilinear
Transformation Design Method, Analog Filters using Lowpass prototype
transformation, Normalized Butterworth Functions, Bilinear L1,L2,
Transformation and Frequency Warping, Bilinear Transformation Design L3
Procedure, Digital Butterworth Filter Design using BLT. Realization of IIR
Filters in Direct form I and II. [Text 2]
Module-5
Digital Signal Processors: DSP Architecture, DSP Hardware Units, Fixed
point format, Floating point Format, IEEE Floating point formats, Fixed L1,L2,
point digital signal processors, Floating point processors, FIR and IIR filter L3
implementations in Fixed point systems. [Text 2]
Course Outcomes: After studying this course, students will be able to:
Determine response of LTI systems using time domain and DFT techniques.
Compute DFT of real and complex discrete time signals.
Computation of DFT using FFT algorithms and linear filtering approach.
Design and realize FIR and IIR digital filters
Understand the DSP processor architecture.
Text Book:
1. Proakis & Monalakis, “Digital signal processing – Principles Algorithms &
Applications”, 4th Edition, Pearson education, New Delhi, 2007. ISBN: 81-317-
1000-9.
2. Li Tan, Jean Jiang, “Digital Signal processing – Fundamentals and
Applications”, Academic Press, 2013, ISBN: 978-0-12-415893.
Reference Books:
1. Sanjit K Mitra, “Digital Signal Processing, A Computer Based Approach”, 4th
Edition, Mc Graw Hill Education, 2013,
2. Oppenheim & Schaffer, “Discrete Time Signal Processing” , PHI, 2003.
3. D.Ganesh Rao and Vineeth P Gejji, “Digital Signal Processing” Cengage India
Private Limited, 2017, ISBN: 9386858231
PRINCIPLES OF COMMUNICATION SYSTEMS
V Semester (EC/TC)
[As per Choice Based Credit System (CBCS) scheme]
Exam Hours 03
CREDITS – 04
Course objectives: This course will enable students to
Understand and analyse concepts of Analog Modulation schemes viz; AM,
FM., Low pass sampling and Quantization as a random process.
Understand and analyse concepts digitization of signals viz; sampling,
quantizing and encoding.
Evolve the concept of SNR in the presence of channel induced noise and
study Demodulation of analog modulated signals.
Evolve the concept of quantization noise for sampled and encoded signals
and study the concepts of reconstruction from these samples at a receiver.
Module-1 RBT
Level
AMPLITUDE MODULATION: Introduction, Amplitude Modulation: Time &
Frequency Domain description, Switching modulator, Envelop detector.
(3.1 – 3.2 in Text)
DOUBLE SIDE BAND-SUPPRESSED CARRIER MODULATION: Time and
Frequency Domain description, Ring modulator, Coherent detection, L1,
Costas Receiver, Quadrature Carrier Multiplexing. (3.3 – 3.4 in Text) L2, L3
SINGLE SIDE–BAND AND VESTIGIAL SIDEBAND METHODS OF
MODULATION: SSB Modulation, VSB Modulation, Frequency Translation,
Frequency- Division Multiplexing, Theme Example: VSB Transmission of
Analog and Digital Television. (3.5 – 3.8 in Text)
Module-2
ANGLE MODULATION: Basic definitions, Frequency Modulation: Narrow
Band FM, Wide Band FM, Transmission bandwidth of FM Signals,
Generation of FM Signals, Demodulation of FM Signals, FM Stereo L1,
Multiplexing, Phase–Locked Loop: Nonlinear model of PLL, Linear model of L2,L3
PLL, Nonlinear Effects in FM Systems. The Superheterodyne Receiver (4.1 –
4.6 of Text)
Module-3
[Review of Mean, Correlation and Covariance functions of Random
L1,
Processes.
L2,L3
(No questions to be set on these topics)]
NOISE - Shot Noise, Thermal noise, White Noise, Noise Equivalent
Bandwidth (5.10 in Text)
NOISE IN ANALOG MODULATION: Introduction, Receiver Model, Noise in
DSB-SC receivers. Noise in AM receivers, Threshold effect, Noise in FM
receivers, Capture effect, FM threshold effect, FM threshold reduction, Pre-
emphasis and De-emphasis in FM (6.1 – 6.6 in Text)
Module-4
SAMPLING AND QUANTIZATION: Introduction, Why Digitize Analog
Sources?, The Low pass Sampling process Pulse Amplitude Modulation. L1,
Time Division Multiplexing, Pulse-Position Modulation, Generation of PPM L2,L3
Waves, Detection of PPM Waves.(7.1 – 7.7 in Text)
Module-5
SAMPLING AND QUANTIZATION (Contd):
The Quantization Random Process, Quantization Noise,
Pulse–Code Modulation: Sampling, Quantization, Encoding, Regeneration, L1,
Decoding, Filtering, Multiplexing; Delta Modulation (7.8 – 7.10 in Text), L2,L3
Application examples - (a) Video + MPEG (7.11 in Text) and (b) Vocoders
(refer Section 6.8 of Reference Book 1).
Course Outcomes: After studying this course, students will be able to:
Analyze and compute performance of AM and FM modulation in the presence
of noise at the receiver.
Analyze and compute performance of digital formatting processes with
quantization noise.
Multiplex digitally formatted signals at Transmitter and demultiplex the
signals and reconstruct digitally formatted signals at the receiver.
Design/Demonstrate the use of digital formatting in Multiplexers, Vocoders
and Video transmission.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is
60.
Text Book:
“Communication Systems”, Simon Haykins & Moher, 5th Edition, John Willey,
India Pvt. Ltd, 2010, ISBN 978 – 81 – 265 – 2151 – 7.
Reference Books:
1. Modern Digital and Analog Communication Systems, B. P. Lathi, Oxford
University Press., 4th edition.
2. An Introduction to Analog and Digital Communication, Simon Haykins, John
Wiley India Pvt. Ltd., 2008, ISBN 978–81–265–3653–5.
3. Principles of Communication Systems, H.Taub & D.L.Schilling, TMH,2011.
4. Communication Systems, Harold P.E, Stern Samy and A.Mahmond, Pearson
Edition, 2004.
INFORMATION THEORY and CODING
V Semester (EC/TC)
[As per Choice Based Credit System (CBCS) scheme]
Reference Books:
1. Vinay K Ingle, John G Proakis, Digital Signal Processing using MATLAB,
Fourth Edition, Cengage India Private Limited, 2017.
HDL LABORATORY
V Semester, EC/TC
[As per Choice Based Credit System (CBCS) scheme]
1. Write Verilog program for the following combinational design along with test
bench to verify the design:
a. 2 to 4 decoder realization using NAND gates only (structural model)
b. 8 to 3 encoder with priority and without priority (behavioural model)
c. 8 to 1 multiplexer using case statement and if statements
d. 4-bit binary to gray converter using 1-bit gray to binary converter 1-bit
adder and subtractor
2. Model in Verilog for a full adder and addfunctionality to perform logical
operations of XOR, XNOR, AND and OR gates. Write test bench with
appropriate input patterns to verify the modeled behaviour.
3. Verilog 32-bit ALU shown in figure below and verify the functionality of ALU by
selecting appropriate test patterns. The functionality of the ALU is presented
in Table 1.
a. Write test bench to verify the functionality of the ALU considering all
possible input patterns
b. The enable signal will set the output to required functions if enabled, if
disabled all the outputs are set to tri-state
c. The acknowledge signal is set high after every operation is completed
A(31:0) B(31:0)
4. Write Verilog code for SR, D and JK and verify the flip flop.
6. Write Verilog code for counter with given input clock and check whether it
works as clock divider performing division of clock by 2, 4, 8 and 16. Verify the
functionality of the code.
2.
3. Interface a Stepper motor to FPGA and write Verilog code to control the
Stepper motor rotation which in turn may control a Robotic Arm. External
switches to be used for different controls like rotate the Stepper motor (i) +N
steps if Switch no.1 of a Dip switch is closed (ii) +N/2 steps if Switch no. 2 of
a Dip switch is closed (iii) –N steps if Switch no. 3 of a Dip switch is closed
etc.
4. Interface a DAC to FPGA and write Verilog code to generate Sine wave of
frequency F KHz (eg. 200 KHz) frequency. Modify the code to down sample the
frequency to F/2 KHz. Display the Original and Down sampled signals by
connecting them to an oscilloscope.
5. Write Verilog code using FSM to simulate elevator operation.
6. Write Verilog code to convert an analog input of a sensor to digital form and to
display the same on a suitable display like set of simple LEDs, 7-segment
display digits or LCD display.
Course Outcomes: At the end of this course, students should be able to:
Write the Verilog/VHDL programs to simulate Combinational circuits in
Dataflow, Behavioral and Gate level Abstractions.
Describe sequential circuits like flip flops and counters in Behavioral
description and obtain simulation waveforms.
Synthesize Combinational and Sequential circuits on programmable ICs and
test the hardware.
Interface the hardware to the programmable chips and obtain the required
output.
Textbook/s
Tata Mc Graw –
Environmental 2ndEdition,
1 Benny Joseph Hill.
Studies 2012
Environmental Pristine Publishing 3rdEdition,
2 S M Prakash
Studies House, Mangalore 2018
Environmental
3 Studies – From R Rajagopalan Oxford Publisher 2005
Crisis to Cure
Reference Books
Principals of
Environmental Raman Cengage learning, 2ndEdition,
1
Science and Sivakumar Singapur. 2005
Engineering
Environmental Thomson Brooks
G.Tyler Miller 11thEdition,
2 Science – working /Cole,
Jr. 2006
with the Earth
Pratiba Sing,
Text Book of Acme Learning
Anoop Singh&
3 Environmental and Pvt. Ltd. New 1stEdition
Piyush
Ecology Delhi.
Malaviya
BE 2018 Scheme Sixth Semester EC Syllabus
DIGITAL COMMUNICATION
SEMESTER – VI (EC/TC)
[As per Choice Based Credit System (CBCS) Scheme]
Course Code 18EC61 CIE Marks 40
Number of Lecture Hours/Week 03 + 02 (Tutorial) SEE Marks 60
Exam Hours 03
CREDITS – 04
Course Objectives: This course will enable students to:
Understand the mathematical representation of signal, symbol, and noise.
Understand the concept of signal processing of digital data and signal
conversion to symbols at the transmitter and receiver.
Compute performance metrics and parameters for symbol processing and
recovery in ideal and corrupted channel conditions.
Compute performance parameters and mitigate channel induced
impediments in corrupted channel conditions.
RBT
Module-1
Level
Bandpass Signal to Equivalent Low pass: Hilbert Transform, Pre-
envelopes, Complex envelopes, Canonical representation of bandpass
signals, Complex low pass representation of bandpass systems, Complex
representation of band pass signals and systems (Text 1: 2.8, 2.9, L1,L2,
2.10, 2.11, 2.12, 2.13). L3
Line codes: Unipolar, Polar, Bipolar (AMI) and Manchester code and
their power spectral densities (Text 1: Ch 6.10).
Overview of HDB3, B3ZS, B6ZS (Ref. 1: 7.2)
Module-2
Signaling over AWGN Channels- Introduction, Geometric
representation of signals, Gram-Schmidt Orthogonalization procedure, L1,L2,
Conversion of the continuous AWGN channel into a vector channel, L3
Optimum receivers using coherent detection: ML Decoding, Correlation
receiver, matched filter receiver (Text 1: 7.1, 7.2, 7.3, 7.4).
Module – 3
Exam Hours 03
CREDITS – 04
Course objectives: This course will enable students to:
Explain the architectural features and instructions of 32 bit microcontroller -
ARM Cortex M3.
Develop Programs using the various instructions of ARM Cortex M3 and C
language for different applications.
Understand the basic hardware components and their selection method based
on the characteristics and attributes of an embedded system.
Develop the hardware software co-design and firmware design approaches.
Explain the need of real time operating system for embedded system
applications.
RBT
Module 1
Level
ARM-32 bit Microcontroller: Thumb-2 technology and applications of
ARM, Architecture of ARM Cortex M3, Various Units in the architecture,
Debugging support, General Purpose Registers, Special Registers,
L1,L2
exceptions, interrupts, stack operation, reset sequence
(Text 1: Ch-1, 2, 3)
Module 2
ARM Cortex M3 Instruction Sets and Programming: Assembly basics,
Instruction list and description, Thumb and ARM instructions, Special L1,L2,
instructions, Useful instructions, CMSIS, Assembly and C language L3
Programming (Text 1: Ch-4, Ch-10.1 to 10.6)
Module 3
Embedded System Components: Embedded Vs General computing
system, Classification of Embedded systems, Major applications and
purpose of ES. Elements of an Embedded System (Block diagram and
explanation),
Differences between RISC and CISC, Harvard and Princeton, Big and
Little Endian formats, Memory (ROM and RAM types), Sensors, Actuators,
Optocoupler, Communication Interfaces (I2C, SPI, IrDA, Bluetooth, Wi-Fi,
L1,L2
Zigbee only)
(Text 2: All the Topics from Ch-1 and Ch-2 (Fig and explanation
before 2.1) 2.1.1.6 to 2.1.1.8, 2.2 to 2.2.2.3, 2.3 to 2.3.2, 2.3.3.3,
selected topics of 2.4.1 and 2.4.2 only).
Module 4
Embedded System Design Concepts: Characteristics and Quality
Attributes of Embedded Systems, Operational and non-operational quality
attributes, Embedded Systems-Application and Domain specific,
L1,L2,
Hardware Software Co-Design and Program Modeling (excluding UML),
L3
Embedded firmware design and development (excluding C language). Text
2: Ch-3, Ch-4 (4.1, 4.2.1 and 4.2.2 only), Ch-7 (Sections 7.1, 7.2
only), Ch-9 (Sections 9.1, 9.2, 9.3.1, 9.3.2 only)
Module 5
RTOS and IDE for Embedded System Design: Operating System basics,
Types of operating systems, Task, process and threads (Only POSIX
Threads with an example program), Thread preemption, Preemptive Task
scheduling techniques, Task Communication, Task synchronization L1,L2,
issues – Racing and Deadlock, Concept of Binary and counting L3
semaphores (Mutex example without any program), How to choose an
RTOS, Integration and testing of Embedded hardware and firmware,
Embedded system Development Environment – Block diagram (excluding
Keil), Disassembler/decompiler, simulator, emulator and debugging
techniques (Text 2: Ch-10 (Sections 10.1, 10.2, 10.3, 10.5.2 , 10.7,
10.8.1.1, 10.8.1.2, 10.8.2.2, 10.10 only), Ch-12, Ch-13 (a block
diagram before 13.1, 13.3, 13.4, 13.5, 13.6 only)
Course outcomes: After studying this course, students will be able to:
Reference Books:
1. James K. Peckol, "Embedded systems- A contemporary design tool", John
Wiley, 2008, ISBN: 978-0-471-72180-2.
Exam Hours 03
CREDITS – 04
Course objectives: This course will enable students to:
Describe the microwave properties and its transmission media
Describe microwave devices for several applications
Understand the basics of antenna theory
Select antennas for specific applications
RBT
Module 1
Level
Microwave Tubes: Introduction, Reflex Klystron Oscillator, Mechanism
of Oscillations, Modes of Oscillations, Mode Curve (Qualitative Analysis
only). (Text 1: 9.1, 9.2.1)
Microwave Transmission Lines: Microwave Frequencies, Microwave
devices, Microwave Systems, Transmission Line equations and solutions,
L1,L2
Reflection Coefficient and Transmission Coefficient, Standing Wave and
Standing Wave Ratio, Smith Chart, Single Stub matching.
(Text 2: 0.1, 0.2, 0.3, 3.1, 3.2, 3.3, 3.5, 3.6 Except Double stub
matching)
Module 2
Microwave Network theory: Introduction, Symmetrical Z and Y-
Parameters for reciprocal Networks, S matrix representation of Multi-Port
Networks. (Text1: 6.1, 6.2, 6.3)
Microwave Passive Devices: Coaxial Connectors and Adapters, L1,L2
Attenuators, Phase Shifters, Waveguide Tees, Magic tees. (Text 1: 6.4.2,
6.4.14, 6.4.15, 6.4.16)
Module 3
Strip Lines: Introduction, Micro Strip lines, Parallel Strip lines, Coplanar
Strip lines, Shielded Strip Lines. (Text 2: 11.1, 11.2, 11.3, 11.4)
Antenna Basics: Introduction, Basic Antenna Parameters, Patterns, L1,L2,L
Beam Area, Radiation Intensity, Beam Efficiency, Directivity and Gain, 3
Antenna Apertures, Effective Height, Radio Communication Link,
Antenna Field Zones. (Text 3: 2.1 - 2.7, 2.9 – 2.11, 2.13)
Module 4
Point Sources and Arrays: Introduction, Point Sources, Power Patterns,
Power Theorem, Radiation Intensity, Arrays of two isotropic point
sources, Linear Arrays of n Isotropic Point Sources of equal Amplitude
and Spacing. (Text 3: 5.1 – 5.6, 5.9, 5.13) L1,L2,L
Electric Dipoles: Introduction, Short Electric Dipole, Fields of a Short 3,L4
Dipole, Radiation Resistance of a Short Electric Dipole, Thin Linear
Antenna (Field Analyses) (Text 3: 6.1 - 6.5)
Module 5
Loop and Horn Antenna: Introduction, Small loop, The Loop Antenna
General Case, The Loop Antenna as a special case, Radiation resistance
of loops, Directivity of Circular Loop Antennas with uniform current, L1,L2,L
Horn antennas Rectangular Horn Antennas. (Text 3: 7.1, 7.2, 7.4, 7.6, 3
7.7, 7.8, 7.19, 7.20)
Antenna Types: The Helix geometry, Helix modes, Practical Design
considerations for the mono-filar axial mode Helical Antenna, Yagi-Uda
array, Parabolic reflector (Text 3: 8.3, 8.4, 8.5, 8.8, 9.5)
Course outcomes: At the end of the course students will be able to:
Describe the use and advantages of microwave transmission
Analyze various parameters related to microwave transmission lines and
waveguides
Identify microwave devices for several applications
Analyze various antenna parameters necessary for building a RF system
Recommend various antenna configurations according to the applications.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is
60.
Text Books:
1. Microwave Engineering – Annapurna Das, Sisir K Das, TMH, Publication,
2nd, 2010.
2. Microwave Devices and circuits- Samuel Y Liao, Pearson Education
3. Antennas and Wave Propagation- John D. Krauss, Ronald J Marhefka,
Ahmad S Khan, 4th Edition, McGraw Hill Education, 2013
Reference Books:
1. Microwave Engineering - David M Pozar, John Wiley India Pvt. Ltd., 3rd
Edn, 2008.
2. Microwave Engineering – Sushrut Das, Oxford Higher Education, 2ndEdn,
2015
3. Antennas and Wave Propagation – Harish and Sachidananda: Oxford
University
Press, 2007
OPERATING SYSTEM
SEMESTER – VI (EC/TC)
[As per Choice Based Credit System (CBCS) System (CBCS) Scheme]
RBT
Module-1
Leve
Introduction: Biological Neuron – Artificial Neural Model - Types of l
activation functions – Architecture: Feedforward and Feedback, Convex
Sets, Convex Hull and Linear Separability, Non-Linear Separable
Problem. XOR Problem, Multilayer Networks. L1, L2
Learning: Learning Algorithms, Error correction and Gradient Descent
Rules, Learning objective of TLNs, Perceptron Learning Algorithm,
Perceptron Convergence Theorem.
Module-2
Supervised Learning: Perceptron learning and Non Separable sets, α-
Least Mean Square Learning, MSE Error surface, Steepest Descent
L1,L2,
Search, µ-LMS approximate to gradient descent, Application of LMS to
L3
Noise Cancelling, Multi-layered Network Architecture, Back propagation
Learning Algorithm, Practical consideration of BP algorithm.
Module-3
Module-4
Attractor Neural Networks: Associative Learning Attractor Associative
Memory, Linear Associative memory, Hopfield Network, application of L1,L2,
Hopfield Network, Brain State in a Box neural Network, Simulated L3
Annealing, Boltzmann Machine, Bidirectional Associative Memory.
Module-5
Self-organization Feature Map: Maximal Eigenvector Filtering,
Extracting Principal Components, Generalized Learning Laws, Vector L1,L2,
Quantization, Self-organization Feature Maps, Application of SOM, L3
Growing Neural Gas.
Course outcomes: At the end of the course, students should be able to:
Understand the role of neural networks in engineering, artificial intelligence,
and cognitive modelling.
Understand the concepts and techniques of neural networks through the
study of the most important neural network models.
Evaluate whether neural networks are appropriate to a particular
application.
Apply neural networks to particular application, and to know what steps to
take to improve performance.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is
60.
Text Book:
Neural Networks A Classroom Approach– Satish Kumar, McGraw Hill
Education (India) Pvt. Ltd, Second Edition.
Reference Books:
1. Introduction to Artificial Neural Systems-J.M. Zurada, Jaico Publications
1994.
2. Artificial Neural Networks-B. Yegnanarayana, PHI, New Delhi 1998.
OBJECT ORIENTED PROGRAMMING USING C++
SEMESTER – VI (EC/TC)
[As per Choice Based Credit System (CBCS) System (CBCS) Scheme]
Module-3
Constructors, Destructors and Operator overloading: Constructors,
Multiple constructors in a class, Copy constructor, Dynamic constructor,
L1, L2,
Destructors, Defining operator overloading, Overloading Unary and binary
L3
operators, Manipulation of strings using operators (Selected topics from
Chap-6, 7 of Text).
Module-4
Inheritance, Pointers, Virtual Functions, Polymorphism: Derived
Classes, Single, multilevel, multiple inheritance, Pointers to objects and L1, L2,
derived classes, this pointer, Virtual and pure virtual functions (Selected L3
topics from Chap-8, 9 of Text).
Module-5
Streams and Working with files: C++ streams and stream classes,
formatted and unformatted I/O operations, Output with manipulators, L1, L2,
Classes for file stream operations, opening and closing a file, EOF L3
(Selected topics from Chap-10, 11 of Text).
Course outcomes: At the end of the course, students should be able to:
Explain the basics of Object Oriented Programming concepts.
Apply the object initialization and destroy concept using constructors and
destructors.
Apply the concept of polymorphism to implement compile time polymorphism
in programs by using overloading methods and operators.
Use the concept of inheritance to reduce the length of code and evaluate the
usefulness.
Apply the concept of run time polymorphism by using virtual functions,
overriding functions and abstract class in programs.
Use I/O operations and file streams in programs.
Course outcomes: After studying this course, students will be able to:
Construct the combinational circuits, using discrete gates and programmable
logic devices.
Describe how arithmetic operations can be performed for each kind of code,
and also combinational circuits that implement arithmetic operations.
Design a semiconductor memory for specific chip design.
Design embedded systems using small microcontrollers, larger
CPUs/DSPs, or hard or soft processor cores.
Synthesize different types of I/O controllers that are used in embedded
system.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is
60.
Text Book:
Peter J. Ashenden, “Digital Design: An Embedded Systems Approach Using
VERILOG”, Elesvier, 2010.
Reference Books:
1. Ming-Bo Lin, “Digital System Designs and Practices: Using Verilog HDL and
FPGAs”, Wiley, 2008
2. Charles Roth, Lizy K. John, “Byeong Kil LeeDigital Systems Design Using
Verilog, Cengage”, Cengage, 1st Edition.
3. Donald E. Thomas, Philip R. Moorby, “The Verilog Hardware Description
Language”, Springer, Fifth edition.
4. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL” Pearson
(Prentice Hall), Second edition.
NANOELECTRONICS
SEMESTER – VI EC
[As per Choice Based Credit System (CBCS) System (CBCS) Scheme]
CREDITS – 02
Course objectives: This course will enable students to:
Understand the instruction set of ARM Cortex M3, a 32 bit microcontroller
and the software tool required for programming in Assembly and C language.
Program ARM Cortex M3 using the various instructions in assembly level
language for different applications.
Interface external devices and I/O with ARM Cortex M3.
Develop C language programs and library functions for embedded system
applications.
Laboratory Experiments
Conduct the following experiments on an ARM CORTEX M3 evaluation board to
learn ALP and using evaluation version of Embedded 'C' & Keil uVision-4
tool/compiler.
PART A:
1. ALP to multiply two 16 bit binary numbers.
2. ALP to find the sum of first 10 integer numbers.
3. ALP to find the number of 0’s and 1’s in a 32 bit data
4. ALP to find determine whether the given 16 bit is even or odd
5. ALP to write data to RAM
PART B:
6. Display “Hello world” message using internal UART
7. Interface and Control the speed of a DC Motor.
8. Interface a Stepper motor and rotate it in clockwise and anti-clockwise
direction.
9. Interface a DAC and generate Triangular and Square waveforms.
10. Interface a 4x4 keyboard and display the key code on an LCD.
11. Demonstrate the use of an external interrupt to toggle an LED On/Off.
12. Display the Hex digits 0 to F on a 7-segment LED interface, with an
appropriate delay.
13. Measure Ambient temperature using a sensor and SPI ADC IC.
Course outcomes: After studying this course, students will be able to:
Understand the instruction set of 32 bit microcontroller ARM Cortex M3, and
the software tool required for programming in Assembly and C language.
Develop assembly language programs using ARM Cortex M3 for different
applications.
Interface external devices and I/O with ARM Cortex M3.
Develop C language programs and library functions for embedded system
applications.
Laboratory Experiments
PART-A: Experiments No. 1 to 5 has to be performed using discrete
components.
1. Simulate NRZ, RZ, half-sinusoid and raised cosine pulses and generate eye
diagram for binary polar signaling.
2. Pulse code modulation and demodulation system.
3. Computations of the Probability of bit error for coherent binary ASK, FSK and
PSK for an AWGN Channel and Compare them with their Performance curves.
4. Digital Modulation Schemes i) DPSK Transmitter and receiver, ii) QPSK
Transmitter and Receiver.
Course Outcomes: On the completion of this laboratory course, the students will
be able to:
Determine the characteristics and response of microwave waveguide.
Determine the characteristics of microstrip antennas and devices and compute
the parameters associated with it.
Design and test the digital and analog modulation circuits and display the
waveforms.
Simulate the digital modulation systems and compare the error performance of
basic digital modulation schemes.
Conduct of Practical Examination:
All laboratory experiments are to be considered for practical examination.
For examination one question from PART-A and one question from PART-B or
only one question from PART-B experiments based on the complexity, to be
set.
Students are allowed to pick one experiment from the lot.
Strictly follow the instructions as printed on the cover page of answer script for
breakup of marks.
Change of experiment is allowed only once and Marks allotted to the procedure
part to be made zero.
OPEN ELECTIVES-A OFFERED BY EC/TC BOARD
SIGNAL PROCESSING
SEMESTER – VI
[As per Choice Based Credit System (CBCS) System (CBCS) Scheme]
Course Code 18EC651 CIE Marks 40
Number of Lecture Hours/Week 03 SEE Marks 60
Total Number of Lecture Hours 40 (8Hours/Module) Exam Hours 03
CREDITS – 03
Course objective: This course will enable students to:
Understand, represent and classify continuous time and discrete time signals
and systems, together with the representation of LTI systems.
Ability to represent continuous time signals (both periodic and non-periodic)
in the time domain, s-domain and the frequency domain
Understand the properties of analog filters, and have the ability to design
Butterworth filters
Understand and apply sampling theorem and convert a signal from
continuous time to discrete time or from discrete time to continuous time
(without loss of information)
Able to represent the discrete time signal in the frequency domain
Able to design FIR and IIR filters to meet given specifications
RBT
Module-1
Level
Signal Definition, Signal Classification, System definition, System
classification, for both continuous time and discrete time. Definition of LTI L1, L2
systems (Chapter 1)
Module-2
Introduction to Fourier Transform, Fourier Series, Relating the Laplace
Transform to Fourier Transform, Frequency response of continuous time
L1, L2
systems, (Chapter 3)
Module-3
Frequency response of ideal analog filters, Salient features of Butterworth
L1,L2,
filters Design and implementation of Analog Butterworth filters to meet
L3
given specifications (Chapter 8)
Module-4
Sampling Theorem- Statement and proof, converting the analog signal to a
digital signal. Practical sampling. The Discrete Fourier Transform, L1,L2,
Properties of DFT. Comparing the frequency response of analog and digital L3
systems. (FFT not included) (Chapter 3, 4)
Module-5
Definition of FIR and IIR filters. Frequency response of ideal digital filters
Transforming the Analog Butterworth filter to the Digital IIR Filter using
L1,L2,
suitable mapping techniques, to meet given specifications. Design of FIR
L3
Filters using the Window technique, and the frequency sampling
technique to meet given specifications Comparing the designed filter with
the desired filter frequency response (Chapter 8)
Course Outcomes: After studying this course, students will be able to:
Understand and explain continuous time and discrete time signals and
systems, in time and frequency domain
Apply the concepts of signals and systems to obtain the desired parameter/
representation
Analyse the given system and classify the system/arrive at a suitable
conclusion
Design analog/digital filters to meet given specifications
Design and implement the analog filter using components/ suitable
simulation tools (assignment component)
Design and implement the digital filter (FIR/IIR) using suitable simulation
tools, and record the input and output of the filter for the given audio signal
(assignment component)
References:
1. 'Theory and Application of Digital Signal Processing', Rabiner and Gold
2. ‘Signals and Systems’, Schaum’s Outline series
3. ‘Digital Signal Processing’, Schaum’s Outline series
SENSORS and SIGNAL CONDITIONING
SEMESTER – VI Open Elective A
[As per Choice Based Credit System (CBCS)
System (CBCS) Scheme]
Course Code 18EC652 CIE Marks 40
Number of Lecture Hours/Week 03 SEE marks 60
Total Number of Lecture Hours 40 (08 Hrs/module) Exam Hours 03
CREDITS – 03
RBT
Module 1
Level
Introduction to sensor bases measurement systems:
General concepts and terminology, sensor classification, primary sensors,
material for sensors, microsensor technology, magnetoresistors, light
L1, L2
dependent resistors, resistive hygrometers, resistive gas sensors, liquid
conductivity sensors
(Selected topics from ch.1 & 2 of Text)
Module 2
Reactance Variation and Electromagnetic Sensors: -Capacitive
Sensors, Inductive Sensors, Electromagnetic Sensors.
Signal Conditioning for Reactance Variation Sensors-Problems and
L1, L2
Alternatives, ac Bridges Carrier Amplifiers, Coherent Detection, Specific
Signal Conditioners for Capacitive Sensors, Resolver-to-Digital and Digital-
to-Resolver Converters.
Module 3
Self-generating Sensors-Thermoelectric sensors, piezoelectric sensors,
pyroelectric sensors, photovoltaic sensors, electrochemical sensors. L2,L3
Module 4
Digital and intelligent sensors-position encoders, resonant sensors,
sensors based on quartz resonators, SAW sensors, Vibrating wire strain L2,L3
gages, vibrating cylinder sensors, Digital flow meters.
Module 5
Sensors based on semiconductor junctions - Thermometers based on
semiconductor junctions, magneto diodes and magneto transistors,
photodiodes and phototransistors, sensors based on MOSFET transistors, L2,L3
charge- coupled sensors – types of CCD imaging sensors, ultrasonic-based
sensors.
Course Outcomes: After studying this course, students will be able to:
Appreciate various types of sensors and their construction
Use sensors specific to the end use application
Design systems integrated with sensors
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
COMPUTER NETWORKS
B.E., VII Semester, Electronics & Communication Engineering
[As per Choice Based Credit System (CBCS) scheme]
RBT
Module-1 Level
Introduction: Data communication: Components, Data representation,
Data flow, Networks: Network criteria, Physical Structures, Network
types: LAN, WAN, Switching, The Internet.
(1.1, 1.2, 1.3(1.3.1 to 1.3.4 of Text).
L1, L2
Network Models: Protocol Layering: Scenarios, Principles, Logical
Connections, TCP/IP Protocol Suite: Layered Architecture, Layers in
TCP/IP suite, Description of layers, Encapsulation and Decapsulation,
Addressing, Multiplexing and Demultiplexing, The OSI Model: OSI Versus
TCP/IP. (2.1, 2.2, 2.3 of Text)
Module-2
Data-Link Layer: Introduction: Nodes and Links, Services, Two
Categories’ of link, Sublayers, Link Layer addressing: Types of addresses,
ARP. Data Link Control (DLC) services: Framing, Flow and Error Control,
Data Link Layer Protocols: Simple Protocol, Stop and Wait protocol,
Piggybacking. (9.1, 9.2 (9.2.1, 9.2.2), 11.1, 11.2 of Text)
L1,L2,
Media Access Control: Random Access: ALOHA, CSMA, CSMA/CD, L3
CSMA/CA. (12.1 of Text).
Module-4
Transport Layer: Introduction: Transport Layer Services, Connectionless
and Connection oriented Protocols, Transport Layer Protocols: Simple
protocol, Stop and wait protocol, Go-Back-N Protocol, Selective repeat
protocol. (23.1, 23.2.1, 23.2.2, 23.2.3, 23.2.4 of Text)
Course Outcomes: At the end of the course, the students will be able to:
Understand the concepts of networking thoroughly
Identify the protocols and services of different layers.
Distinguish the basic network configurations and standards associated with
each network.
Analyze a simple network and measurement of its parameters.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60.
TEXT BOOK:
Forouzan, “Data Communications and Networking” , 5th Edition, McGraw
Hill, 2013, ISBN: 1-25-906475-3.
REFERENCE BOOKS:
1. James J Kurose, Keith W Ross, Computer Networks, , Pearson Education.
2. Wayarles Tomasi , Introduction to Data Communication and Networking,
Pearson Education.
3. Andrew Tanenbaum, “Computer networks”, Prentice Hall.
4. William Stallings, “Data and computer communications”, Prentice Hall,
VLSI DESIGN
SEMESTER – VII EC
1. “CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang &
Yosuf Leblebici, Third Edition, Tata McGraw-Hill.
REFERENCE BOOKS:
Describe the satellite orbits and its trajectories with the definitions of parameters
associated with it.
Describe the electronic hardware systems associated with the satellite
subsystem and earth station.
Describe the various applications of satellite with the focus on national satellite
system.
Compute the satellite link parameters under various propagation conditions with
the illustration of multiple access techniques.
Module -2
Image E n h a n c e m e n t i n t h e S p a t i a l D o m a i n : Image S a m p l i n g
a n d Quantization, Some Basic Relationships Between Pixels, Linear and
Nonlinear Operations. Some Basic Intensity Transformation
Functions, Histogram Processing, Fundamentals of Spatial Filtering,
Smoothing Spatial Filters, Sharpening Spatial Filters
L1,L2
(Text: Chapter 2: Sections 2.3 to 2.62 , Chapter 3: Sections 3.2 to
3.6)
Module -3
Module -4
Restoration: Noise models, Restoration in the Presence of Noise Only
using Spatial Filtering and Frequency Domain Filtering, Linear,
Position- Invariant degradations, Estimating the Degradation
Function, Inverse Filtering, Minimum Mean Square Error (Wiener)
Filtering, Constrained Least Squares Filtering. L1,L2
(Text: Chapter 5: Sections 5.2, to 5.9)
Module -5
Morphological Image Processing: Preliminaries, Erosion and
Dilation, Opening and Closing.
Understand image formation and the role human visual system plays in
perception of gray and color image data.
Apply image processing techniques in both the spatial and frequency (Fourier)
domains.
Design and evaluate image analysis techniques
Conduct independent study and analysis of Image Enhancement and restoration
techniques.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is
60.
Text Book:
Digital Image Processing- Rafel C Gonzalez and Richard E. Woods,
PHI 3rd Edition 2010.
Reference Books:
1. Digital Image Processing- S.Jayaraman, S.Esakkirajan, T.Veerakumar, Tata
McGraw Hill 2014.
2. Fundamentals of Digital Image Processing-A. K. Jain, Pearson 2004.
3. Image Processing analysis and Machine vision with MindTap by Milan Sonka
and Roger Boile, Cengage Publications, 2018.
DATA STRUCTURES USING C++
B.E., VII Semester (EC/TC)
Examination will be conducted for 100 marks with question paper containing 10
full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60.
Text Book:
Data structures, Algorithms, and applications in C++, Sartaj Sahni,
Universities Press, 2nd Edition, 2005.
Reference Books:
1. Data structures, Algorithms, and applications in C++, Sartaj Sahni, Mc.
Graw Hill, 2000.
2. Object Oriented Programming with C++, E.Balaguruswamy, TMH, 6th Edition,
2013.
3. Programming in C++, E.Balaguruswamy. TMH, 4th, 2010.
DSP ALGORITHMS and ARCHITECTURE
VII Semester (EC)
Module -5
Interfacing Memory and Parallel I/O Peripherals to Programmable DSP
Devices: L1, L2
Introduction, Memory Space Organization, External Bus Interfacing Signals.
Memory Interface, Parallel I/O Interface, Programmed I/O, Interrupts and
I/O Direct Memory Access (DMA).
Course Outcomes: At the end of the course, students will be able to:
Examination will be conducted for 100 marks with question paper containing 10
full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from each
module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60.
Text Books:
1. Raj Kamal, ”Internet of Things-Architecture and design principles”, McGraw
Hill Education.
2. Holger Karl & Andreas Willig, "Protocols And Architectures for Wireless
Sensor Networks", John Wiley, 2005.
Reference Books:
1. Feng Zhao & Leonidas J. Guibas, “Wireless Sensor Networks- An Information
Processing Approach", Elsevier, 2007.
2. Kazem Sohraby, Daniel Minoli, & Taieb Znati, “Wireless Sensor Networks-
Technology, Protocols, And Applications”, John Wiley, 2007.
3. Anna Hac, “Wireless Sensor Network Designs”, John Wiley, 2003.
AUTOMOTIVE ELECTRONICS
B.E., VII Semester (EC/TC)
Module -3
Digital Engine Control Systems – Digital Engine control features, L1, L2
Control modes for fuel Control (Seven Modes), EGR Control, Electronic
Ignition Control - Closed loop Ignition timing, Spark Advance Correction
Scheme, Integrated Engine Control System - Secondary Air Management,
Evaporative Emissions Canister Purge, Automatic System Adjustment,
System Diagnostics. (Text 1: Chapter 7)
Module -4
Automotive Networking –Bus Systems – Classification, Applications in
the vehicle, Coupling of networks, Examples of networked vehicles
Buses - CAN Bus, LIN Bus, MOST Bus, Bluetooth, Flex Ray, Diagnostic L1,L2
Interfaces. (Text 2: Pg. 92-151)
Course Outcomes: At the end of the course, students will be able to:
Acquire an overview of automotive components, subsystems, and basics of
Electronic Engine Control in today’s automotive industry.
Use available automotive sensors and actuators while interfacing with
microcontrollers / microprocessors during automotive system design.
Understand the networking of various modules in automotive systems,
communication protocols and diagnostics of the sub systems.
Design and implement the electronics that attribute the reliability, safety, and
smartness to the automobiles, providing add-on comforts and get fair idea on
future Automotive Electronic Systems.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing 10
full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60.
Text Books:
Module -3
Module -4
Audio and video compression: Introduction, Audio compression,
video compression, video compression principles, video L1,L2
compression.(Chapter 4 of Text 1)
Module -5
Multimedia Information Networks: Introduction, LANs, Ethernet,
Token ring, Bridges, FDDI High-speed LANs, LAN protocol (Chap. 8 of
Text 1).
L1,L2
The Internet: Introduction, IP Datagrams, Fragmentation, IP Address,
ARP and RARP, QoS Support, IPv8. (Chap. 9 of Text 1)
Course Outcomes: After studying this course, students will be able to:
Understand basics of different multimedia networks and applications.
Understand different compression techniques to compress audio and video.
Describe multimedia Communication across Networks.
Analyse different media types to represent them in digital form.
Compress different types of text and images using different compression
techniques.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing 10
full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60.
Text Book:
1. Multimedia Communications- Fred Halsall, Pearson Education, 2001, ISBN -
9788131709948.
2. Multimedia Communication Systems- K. R. Rao, Zoran S. Bojkovic, Dragorad
A. Milovanovic, Pearson Education, 2004. ISBN -9788120321458.
Reference Book:
Multimedia: Computing, Communications and Applications- Raifsteinmetz,
Klara Nahrstedt, Pearson Education, 2002. ISBN -978817758
CRYPTOGRAPHY
VII Semester (EC/TC)
Module -1 RBT
Level
Classical Encryption Techniques: Symmetric cipher model,
Substitution techniques, Transposition techniques (Text 1: Chapter 1)
L1,L2
Basic Concepts of Number Theory and Finite Fields: Euclidean
algorithm, Modular arithmetic (Text 1: Chapter 3)
Module -2
SYMMETRIC CIPHERS: Traditional Block Cipher structure, Data L1,L2
encryption standard (DES), The AES Cipher.
(Text 1: Chapter 2: Section1, 2, Chapter 4: Section 2, 3, 4)
Module -3
Basic Concepts of Number Theory and Finite Fields: Groups, Rings L1,L2
and Fields, Finite fields of the form GF(p), Prime Numbers, Fermat’s and
Euler’s theorem, discrete logarithm.
(Text 1: Chapter 3 and Chapter 7: Section 1, 2, 5)
Module -4
ASYMMETRIC CIPHERS: Principles of Public-Key Cryptosystems, The
RSA algorithm, Diffie - Hellman Key Exchange, Elliptic Curve Arithmetic, L1,L2,L
Elliptic Curve Cryptography 3
(Text 1: Chapter 8, Chapter 9: Section 1, 3, 4)
Module -5
Pseudo-Random-Sequence Generators and Stream Ciphers:
Linear Congruential Generators, Linear Feedback Shift Registers, Design
and analysis of stream ciphers, Stream ciphers using LFSRs, A5, Hughes L1,L2,
XPD/KPD, Nanoteq, Rambutan, Additive generators, Gifford, Algorithm L3
M, PKZIP (Text 2: Chapter 16)
Course Outcomes: After studying this course, students will be able to:
Explain basic cryptographic algorithms to encrypt and decrypt the data.
Use symmetric and asymmetric cryptography algorithms to encrypt and
decrypt the information.
Apply concepts of modern algebra in cryptography algorithms.
Apply pseudo random sequence in stream cipher algorithms.
Reference Books:
1. Cryptography and Network Security, Behrouz A. Forouzan, TMH, 2007.
2. Cryptography and Network Security, Atul Kahate, TMH, 2003.
MACHINE LEARNING
VII Semester (EC/TC)
40 (08 Hours
Total Number of Lecture Hours Exam Hours 03
per Module)
CREDITS – 03
Acquire some concepts and techniques that are core to Machine Learning.
Understand learning and decision trees.
Acquire knowledge of neural networks, Bayesian techniques and instant
based learning.
Understand analytical learning and reinforced learning.
Module -1 RBT
Level
Learning: Designing Learning systems, Perspectives and Issues,
Concept Learning, Version Spaces and Candidate Elimination
Algorithm, Inductive bias. L1,L2
Module -2
Decision Tree and ANN: Decision Tree Representation, Hypothesis L1,L2
Space Search, Inductive bias in decision tree, issues in Decision tree.
Neural Network Representation, Perceptrons, Multilayer Networks and
Back Propagation Algorithms.
Module -3
Bayesian and Computational Learning: Bayes Theorem, Bayes
Theorem Concept Learning, Maximum Likelihood, Minimum L1,L2
Description Length Principle, Bayes Optimal Classifier, Gibbs
Algorithm, Naïve Bayes Classifier.
Module -4
Instant Based Learning and Learning set of rules: K- Nearest
Neighbour Learning, Locally Weighted Regression, Radial Basis
Functions, Case-Based Reasoning. L1,L2
Sequential Covering Algorithms, Learning Rule Sets, Learning First
Order Rules, Learning Sets of First Order Rules.
Module -5
Analytical Learning and Reinforced Learning: Perfect Domain
Theories, Explanation Based Learning, Inductive-Analytical
L1,L2
Approaches, FOCL Algorithm, Reinforcement Learning.
Course outcomes: At the end of the course, students should be able to:
Laboratory Experiments
PART-A: Simulation experiments using NS2/ NS3/ OPNET/ NCTUNS/
NetSim/QualNet or any other equivalent tool
1. Implement a point to point network with four nodes and duplex links between
them. Analyze the network performance by setting the queue size and varying the
bandwidth.
2. Implement a four node point to point network with links n0-n2, n1-n2 and n2-
n3. Apply TCP agent between n0-n3 and UDP between n1-n3. Apply relevant
applications over TCP and UDP agents changing the parameter and determine
the number of packets sent by TCP/UDP.
3. Implement Ethernet LAN using n (6-10) nodes. Compare the throughput by
changing the error rate and data rate.
4. Implement Ethernet LAN using n nodes and assign multiple traffic to the nodes
and obtain congestion window for different sources/ destinations.
5. Implement ESS with transmission nodes in Wireless LAN and obtain the
performance parameters.
6. Implementation of Link stateImplement
PART-B: routing algorithm.
the following in C/C++
1. Write a program for a HLDC frame to perform the following.
i) Bit stuffing
ii) Character stuffing.
2. Write a program for distance vector algorithm to find suitable path for
transmission.
3. Implement Dijkstra’s algorithm to compute the shortest routing path.
4. For the given data, use CRC-CCITT polynomial to obtain CRC code. Verify the
program for the cases
a. Without error
b. With error
5. Implementation of Stop and Wait Protocol and Sliding Window Protocol
6. Write a program for congestion control using leaky bucket algorithm.
Course outcomes: On the completion of this laboratory course, the students will
be able to:
Use the network simulator for learning and practice of networking algorithms.
Illustrate the operations of network protocols and algorithms using C
programming.
Simulate the network with different configurations to measure the
performance parameters.
Implement the data link and routing protocols using C programming.
Laboratory Experiments
Part – A
Analog Design
Use any VLSI design tools to carry out the experiments, use library files and
technology files below 180 nm.
1. a) Capture the schematic of CMOS inverter with load capacitance of 0.1pF and
set the widths of inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at
selected technology. Carry out the following:
a. Set the input signal to a pulse with rise time, fall time of 1ns and pulse
width of 10ns and time period of 20ns and plot the input voltage and
output voltage of designed inverter?
b. From the simulation results compute tpHL, tpLH and td for all three
geometrical settings of width?
c. Tabulate the results of delay and find the best geometry for minimum delay
for CMOS inverter?
1. b) Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods.
Verify for DRC and LVS, extract parasitic and perform post layout simulations,
compare the results with pre-layout simulations. Record the observations.
2. a) Capture the schematic of 2-input CMOS NAND gate having similar delay as
that of CMOS inverter computed in experiment 1. Verify the functionality of NAND
gate and also find out the delay td for all four possible combinations of input
vectors. Table the results. Increase the drive strength to 2X and 4X and tabulate
the results.
2. b) Draw layout of NAND with Wp/Wn = 40/20, use optimum layout methods.
Verify for DRC and LVS, extract parasitic and perform post layout simulations,
compare the results with pre-layout simulations. Record the observations.
3. a) Capture schematic of Common Source Amplifier with PMOS Current Mirror
Load and find its transient response and AC response? Measures the Unity Gain
Bandwidth (UGB), amplification factor by varying transistor geometries, study the
impact of variation in width to UGB.
3. b) Draw layout of common source amplifier, use optimum layout methods. Verify
for DRC and LVS, extract parasitic and perform post layout simulations,
compare the results with pre-layout simulations. Record the observations.
4. a) Capture schematic of two-stage operational amplifier and measure the
following:
a. UGB
b. dB bandwidth
c. Gain margin and phase margin with and without coupling capacitance
d. Use the op-amp in the inverting and non-inverting configuration and verify its
functionality
e. Study the UGB, 3dB bandwidth, gain and power requirement in op-amp by
varying the stage wise transistor geometries and record the observations.
4. b) Draw layout of two-stage operational amplifier with minimum transistor width
set to 300 (in 180/90/45 nm technology), choose appropriate transistor geometries
as per the results obtained in 4.a. Use optimum layout methods. Verify for DRC and
LVS, extract parasitic and perform post layout simulations, compare the results
with pre-layout simulations. Record the observations.
Part - B
Digital Design
Carry out the experiments using semicustom design flow or ASIC design flow,
use technology library 180/90/45nm and below
Note: The experiments can also be carried out using FPGA design flow, it is
required to set appropriate constraints in FPGA advanced synthesis options
1.Write verilog code for 4-bit up/down asynchronous reset counter and carry out the
following:
a. Verify the functionality using test bench
b. Synthesize the design by setting area and timing constraint. Obtain the gate
level netlist, find the critical path and maximum frequency of operation.
Record the area requirement in terms of number of cells required and
properties of each cell in terms of driving strength, power and area
requirement.
c. Perform the above for 32-bit up/down counter and identify the critical path,
delay of critical path, and maximum frequency of operation, total number of
cells required and total area.
2. Write verilog code for 4-bit adder and verify its functionality using test bench.
Synthesize the design by setting proper constraints and obtain the net list. From
the report generated identify critical path, maximum delay, total number of cells,
power requirement and total area required. Change the constraints and obtain
optimum synthesis results.
3. Write verilog code for UART and carry out the following:
4. Write verilog code for 32-bit ALU supporting four logical and four arithmetic
operations,
use case statement and if statement for ALU behavioral modeling.
a. Perform functional verification using test bench
b. Synthesize the design targeting suitable library by setting area
and timing constraints
c. For various constrains set, tabulate the area, power and delay for
the synthesized netlist
d. Identify the critical path and set the constraints to obtain
optimum gate level netlist with suitable constraints
Compare the synthesis results of ALU modeled using IF and CASE statements.
5. Write verilog code for Latch and Flip-flop, Synthesize the design and compare the synthesis report
(D, SR, JK).
6. For the synthesized netlist carry out the following for any two above experiments:
a. Floor planning (automatic), identify the placement of pads
b. Placement and Routing, record the parameters such as no. of layers used
for routing, flip method for placement of standard cells, placement of
standard cells, routes of power and ground, and routing of standard cells
c. Physical verification and record the LVS and DRC reports
d. Perform Back annotation and verify the functionality of the design
e. Generate GDSII and record the number of masks and its color composition
Course outcomes: On the completion of this laboratory course, the students will be
able to:
Design and simulate combinational and sequential digital circuits using
Verilog HDL
Understand the Synthesis process of digital circuits using EDA tool.
Perform ASIC design flow and understand the process of synthesis, synthesis
constraints and evaluating the synthesis reports to obtain optimum gate level
net list
Design and simulate basic CMOS circuits like inverter, common source
amplifier and differential amplifiers.
Perform RTL-GDSII flow and understand the stages in ASIC design.
OPEN ELECTIVE-B OFFERED BY EC/TC BOARD
COMMUNICATION THEORY
Examination will be conducted for 100 marks with question paper containing 10
full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60.
Text Book:
40 (08 Hours
Total Number of Lecture Hours Exam Hours 03
per Module)
CREDITS – 03
Course Objectives: This course will enable students to:
Course outcomes: At the end of the course, students should be able to:
Reference Books:
RBT
Module-1
Level
Mobile Radio Propagation –
Large Scale Path Loss - Free Space Propagation Model, Relating Power
to Electric Field, Three Basic Propagation Mechanisms – Reflection
(Ground Reflection) , Diffraction, Scattering, Practical Link Budget,
( Text 1 - 2.2 and Ref1 - Chapter 4).
Fading and Multipath – Broadband wireless channel, Delay Spread L1, L2
and Coherence Bandwidth, Doppler Spread and Coherence Time,
Angular spread and Coherence Distance (Text 1 – 2.4) ,
Statistical Channel Model of a Broadband Fading Channel
(Text 1 – 2.5.1)
The Cellular Concept – Cellular Concept , Analysis of Cellular
Systems, Sectoring (Text 1- 2.3)
Module-2
GSM and TDMA Technology
GSM System overview – Introduction, GSM Network and System
Architecture, GSM Channel Concept.
L1,L2,L3
GSM System Operations – GSM Identities, System Operations –
Traffic cases, GSM Infrastructure Communications (Um Interface)
(Text 2, Part1 and Part 2 of Chapter 5)
Module-3
CDMA Technology
CDMA System Overview – Introduction, CDMA Network and System
Architecture
CDMA Basics – CDMA Channel Concepts, CDMA System (Layer 3) L1,L2,L3
operations, 3G CDMA
(Text 2-Part 1, Part2 and Part 3 of Chapter 6)
Module-4
LTE – 4G
Key Enablers for LTE 4G – OFDM, SC-FDE, SC-FDMA, Channel
Dependant Multiuser Resource Scheduling, Multi-Antenna Techniques,
Flat IP Architecture, LTE Network Architecture. (Text 1, Sec 1.4)
Multi-Carrier Modulation – Multicarrier concepts, OFDM Basics, L1,L2,L3
OFDM in LTE, Timing and Frequency Synchronization, Peak to Average
Ration, SC-Frequency Domain Equalization, Computational Complexity
Advantage of OFDM and SC-FDE.
(Text 1, Sec 3.1 – 3.7)
Module-5
LTE - 4G
OFDMA and SC-FDMA – Multiple Access for OFDM Systems, OFDMA,
SCFDMA, Multiuser Diversity and Opportunistic Scheduling, OFDMA
and SC-FDMA in LTE, OFDMA system Design Considerations.
(Text 1, Sec 4.1 – 4.6) L1, L2,L3
The LTE Standard – Introduction to LTE and Hierarchical Channel
Structure of LTE, Downlink OFDMA Radio Resources, Uplink SC-FDMA
Radio Resources.
(Text 1, Sec 6.1 – 6.4)
Course Outcomes: After studying this course, students will be able to:
Explain concepts of propagation mechanisms like Reflection, Diffraction,
Scattering in wireless channels.
Develop a scheme for idle mode, call set up, call progress handling and call
tear down in a GSM cellular network.
Develop a scheme for idle mode, call set up, call progress handling and call
tear down in a CDMA cellular network.
Understand the Basic operations of Air interface in a LTE 4G system.
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60.
Text Books:
1. “Fundamentals of LTE” Arunabha Ghosh, Jan Zhang, Jefferey Andrews,
Riaz Mohammed, Pearson education (Formerly Prentice Hall,
Communications Engg and Emerging Technologies), ISBN-13: 978-0-13-
703311-9.
2. “Introduction to Wireless Telecommunications Systems and Networks”,
Gary Mullet, First Edition, Cengage Learning India Pvt Ltd., 2006, ISBN -
13: 978-81-315-0559-5.
Reference Books:
1. “Wireless Communications: Principles and Practice” Theodore
Rappaport, 2nd Edition, Prentice Hall Communications Engineering
and Emerging Technologies Series, 2002, ISBN 0-13-042232-0.
2. LTE for UMTS Evolution to LTE-Advanced’ Harri Holma and Antti
Toskala, Second Edition - 2011, John Wiley & Sons, Ltd. Print ISBN:
9780470660003. 2
NETWORK SECURITY
VIII Semester EC/TC
RBT
Module-1
Level
Attacks on Computers and Computer Security: Need for Security,
Security Approaches, Principles of Security Types of Attacks. L1, L2
(Chapter 1-Text 2)
Module-2
Module-3
IP Security: Overview of IP Security (IPSec), IP Security Architecture,
Modes of Operation, Security Associations (SA), Authentication Header
L1,L2
(AH), Encapsulating Security Payload (ESP), Internet Key Exchange.
(Chapter 19-Text 1)
Module-4
Intruders, Intrusion Detection.(Chapter 20-Text 1)
L1,L2
MALICIOUS SOFTWARE: Viruses and Related Threats, Virus
Countermeasures, (Chapter 21-Text 1)
Module-5
Firewalls: The Need for firewalls, Firewall Characteristics, Types of
Firewalls, Firewall Biasing, Firewall location and configuration L1, L2
(Chapter 22-Text 1)
Course Outcomes: After studying this course, students will be able to:
Explain network security services and mechanisms and explain security
concepts
Understand the concept of Transport Level Security and Secure Socket Layer.
Explain Security concerns in Internet Protocol security
Explain Intruders, Intrusion detection and Malicious Software
Describe Firewalls, Firewall Characteristics, Biasing and Configuration
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60.
TEXT BOOKS:
1. Cryptography and Network Security Principles and Practice‖, Pearson
Education Inc., William Stallings, 5th Edition, 2014, ISBN: 978-81-317-
6166-3.
2. Cryptography and Network Security, Atul Kahate, TMH, 2003.
REFERENCE BOOKS:
1. Cryptography and Network Security, Behrouz A. Forouzan, TMH, 2007.
MICRO ELECTRO MECHANICAL SYSTEMS
VIII Semester, EC/TC
RBT
Module-1
Level
Module-2
Working Principles of Microsystems: Introduction,
Microsensors, Microactuation, MEMS with Microactuators, Micro
accelerometers, Microfluidics.
L1,L2
Engineering Science for Microsystems Design and Fabrication:
Introduction, Molecular Theory of Matter and Inter-molecular Forces,
Plasma Physics, Electrochemistry.
Module-3
Engineering Mechanics for Microsystems Design: Introduction,
Static Bending of Thin Plates, Mechanical Vibration, Thermo
L1,L2
mechanics, Fracture Mechanics, Thin Film Mechanics, Overview on
Finite Element Stress Analysis.
Module-4
Scaling Laws in Miniaturization: Introduction, Scaling in Geometry,
Scaling in Rigid-Body Dynamics, Scaling in Electrostatic Forces, L1,L2
Scaling in Fluid Mechanics, Scaling in Heat Transfer.
Module-5
Overview of Micro manufacturing: Introduction, Bulk Micro
manufacturing, Surface Micromachining, The LIGA Process, L1, L2
Summary on Micro manufacturing.
Course Outcomes: After studying this course, students will be able to:
Appreciate the technologies related to Micro Electro Mechanical Systems.
Understand design and fabrication processes involved with MEMS
Devices.
Analyze the MEMS devices and develop suitable mathematical models
Know various application areas for MEMS device
RBT
Module-1
Level
Basics of Radar: Introduction, Maximum Unambiguous Range,
Radar Waveforms, Definitions with respect to pulse waveform - PRF,
PRI, Duty Cycle, Peak Transmitter Power, Average transmitter Power. L1,
Simple form of the Radar Equation, Radar Block Diagram and L2,L3
Operation, Radar Frequencies, Applications of Radar, The Origins of
Radar, Illustrative Problems. (Chapter 1 of Text)
Module-2
The Radar Equation: Prediction of Range` Performance, Detection of
signal in Noise, Minimum Detectable Signal, Receiver Noise, SNR,
Modified Radar Range Equation, Envelope Detector — False Alarm
Time and Probability, Probability of Detection, Radar Cross Section of L1,L2,L
Targets: simple targets – sphere, cone-sphere, Transmitter 3
Power, PRF and Range Ambiguities, System Losses (qualitative
treatment), Illustrative Problems.
(Chapter 2 of Text, Except 2.4, 2.6, 2.8 & 2.11)
Module-3
MTI and Pulse Doppler Radar: Introduction, Principle, Doppler
Frequency Shift,Simple CW Radar, Sweep to Sweep subtraction and
Delay Line Canceler, MTI Radar with – Power Amplifier Transmitter,
Delay Line Cancelers — Frequency Response of Single Delay- Line
L1,L2,L
Canceler, Blind Speeds, Clutter Attenuation, MTI Improvement
3
Factor, N- Pulse Delay-Line Canceler, Digital MTI Processing – Blind
phases, I and Q Channels, Digital MTI Doppler signal processor,
Moving Target Detector- Original MTD.
(Chapter 3: 3.1, 3.2, 3.5, 3.6 of Text)
Module-4
Tracking Radar:
Tracking with Radar- Types of Tracking Radar Systems, Monopulse
Tracking- Amplitude Comparison Monopulse (one-and two-
L1,L2,L
coordinates), Phase Comparison Monopulse.
3
Sequential Lobing, Conical Scan Tracking, Block Diagram of Conical
Scan Tracking Radar, Tracking in Range, Comparison of Trackers.
(Chapter 4: 4.1, 4.2, 4.3 of Text)
Module-5
The Radar Antenna: Functions of The Radar Antenna, Antenna
Parameters, Reflector Antennas and Electronically Steered Phased
array Antennas. (Chapter 9: 9.1, 9.2 9.4, 9.5 of Text) L1,
Radar Receiver: The Radar Receiver, Receiver Noise Figure, Super L2,L3
Heterodyne Receiver, Duplexers and Receivers Protectors, Radar
Displays. (Chapter 11 of Text)
Course outcomes: At the end of the course, students will be able to:
Understand the radar fundamentals and radar signals.
Explain the working principle of pulse Doppler radars, their
applications and limitations
Describe the working of various radar transmitters and receivers.
Analyze the range parameters of pulse radar system which
affect the system performance
Question paper pattern:
Examination will be conducted for 100 marks with question paper containing
10 full questions, each of 20 marks.
Each full question can have a maximum of 4 sub questions.
There will be 2 full questions from each module covering all the topics of the
module.
Students will have to answer 5 full questions, selecting one full question from
each module.
The total marks will be proportionally reduced to 60 marks as SEE marks is 60.
TEXT BOOK:
Introduction to Radar Systems- Merrill I Skolink, 3e, TMH, 2001
REFERENCE BOOKS:
1 . Radar Principles, Technology, Applications — Byron Edde, Pearson
Education, 2004.
2. Radar Principles – Peebles. Jr, P.Z. Wiley. New York, 1998.
3. Principles of Modem Radar: Basic Principles – Mark A. Rkhards, James A.
Scheer, William A. HoIm. Yesdee, 2013
OPTICAL COMMUNICATION NETWORKS
VIII Semester EC
Module -4
WDM Concepts and Components: Overview of WDM: Operational
Principles of WDM, WDM standards, Mach-Zehnder Interferometer
Multiplexers, Isolators and Circulators, Fiber grating filters, Dielectric
Thin-Film Filters, Diffraction Gratings. Optical amplifiers: Basic L1, L2
application and Types, Semiconductor optical amplifiers, Erbium
Doped Fiber Amplifiers, Raman Amplifiers, Wideband Optical
Amplifiers. (Text 1)
Module -5
Course Outcomes: At the end of the course, students will be able to:
Classification and working of optical fiber with different modes of signal
propagation.
Describe the transmission characteristics and losses in optical fiber
communication.
Describe the construction and working principle of optical connectors,
multiplexers and amplifiers.
Describe the constructional features and the characteristics of optical
Sources and detectors.
Illustrate the networking aspects of optical fiber and describe various
standards associated with it.
Question paper pattern:
Reference Book:
Biomedical Signal Analysis-Rangaraj M. Rangayyan, John Wiley & Sons
2002.