Micron MTFC2GMVEA 0M WT Datasheet

Micron Confidential and Proprietary
2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

Features
e·MMC™ Memory
MTFC2GMVEA-0M WT, MTFC4GLVEA-0M WT, MTFC4GMVEA-1M WT,
MTFC8GLVEA-1M WT, MTFC16GJVEC-2M WT, MTFC32GJVED-3M WT,
MTFC64GJVDN-3M WT
Features Figure 1: Micron e·MMC Device
• MultiMediaCard (MMC) controller and NAND Flash

• 153- or 169-ball WFBGA/VFBGA/LFBGA (RoHS 6/6-
compliant)
• VCC: 2.7–3.6V
• VCCQ (dual voltage): 1.65–1.95V; 2.7–3.6V
• Temperature ranges MMC MMC controller MMC
power interface
– Operating temperature: –25˚C to +85˚C
– Storage temperature: –40˚C to +85˚C
• Typical current consumption
– Standby current: 110µA for 2GB, 120µA for 4GB,
8GB, 16GB; 140µA for 32G; 160µA for 64GB
– Active current (RMS): 70mA (2GB); 80mA (4GB, NAND Flash
power NAND Flash
8GB, 16GB, 32GB, 64GB)
MMC-Specific Features
• JEDEC/MMC standard version 4.41-compliant
(JEDEC Standard No. 84-A441) – SPI mode not
supported (see www.jedec.org/sites/default/files/
docs/JESD84-A441.pdf) MMC-Specific Features (Continued)
– Advanced 11-signal interface – Enhanced reliable write
– x1, x4, and x8 I/Os, selectable by host – Configurable reliability settings
– MMC mode operation – Background operation
– Command classes: class 0 (basic); class 2 (block – Fully enhanced configurable
read); class 4 (block write); class 5 (erase); – Backward-compatible with previous MMC
class 6 (write protection); class 7 (lock card) modes
– MMCplus™ and MMCmobile™ protocols • ECC and block management implemented
– Temporary write protection
– 52 MHz clock speed (MAX)
– Boot operation (high-speed boot)
– Sleep mode
– Replay-protected memory block (RPMB)
– Secure erase and trim
– Hardware reset signal
– Multiple partitions with enhanced attribute
– Permanent and power-on write protection
– Double data rate (DDR) function
– High-priority interrupt (HPI)
PDF: 09005aef84d69f8a
emmc_2gb_4gb_8gb_16gb_32gb_64gb-wt.pdf - Rev. A 6/12 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

Features
e·MMC Performance
Table 1: MLC Partition Performance
Part Number
MTFC16GJVEC-2M WT
MTFC2GMVEA-0M WT MTFC4GMVEA-1M WT MTFC32GJVED-3M WT
Condition MTFC4GLVEA-0M WT MTFC8GLVEA-1M WT MTFC64GJVDN-3M WT Units
Sequential write 6.6 13.5 20 MB/s
Sequential read 30 44 44 MB/s
Note: 1. Random access of 4KB chunk; sequential read access of 1MB chunk. Additional performance data, such as
power consumption or timing for different device modes, will be provided in a separate document upon
customer request.
Ordering Information
Table 2: Ordering Information
NAND Flash
Base Part Number Density Package Type Shipping Media
MTFC2GMVEA-0M WT 2GB 153-ball WFBGA 1 x 16Gb, MLC, 25nm Tray
11.5mm x 13.0mm x 0.8mm Tape and reel
MTFC4GLVEA-0M WT 4GB 153-ball WFBGA 1 x 32Gb, MLC, 25nm Tray
MTFC4GMVEA-1M WT 4GB 153-ball WFBGA 2 x 16Gb, MLC, 25nm Tray
MTFC8GLVEA-1M WT 8GB 153-ball WFBGA 2 x 32Gb, MLC, 25nm Tray
MTFC16GJVEC-2M WT 16GB 169-ball WFBGA 2 x 64Gb, MLC, 25nm Tray
MTFC32GJVED-3M WT 32GB 169-ball VFBGA 4 x 64Gb, MLC, 25nm Tray
MTFC64GJVDN-3M WT 64GB 169-ball LFBGA 8 x 64Gb, MLC, 25nm Tray

Features
Part Numbering Information

Micron®e·MMC memory devices are available in different configurations and densities. Verify valid part numbers
by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 2: Marketing Part Number Chart

MT FC 2G M V x EA - 0 M WT
Micron Technology Production Status

Blank = Production
Product Family ES = Engineering samples
FC = NAND Flash + controller MS = Mechanical samples
NAND Flash Density Operating Temperature Range

2G = 2GB Blank = 0°C to 70°C
4G = 4GB WT = Standard (–25°C to +85°C)
8G = 8GB IT = Extended (–40°C to +85)°C
16G = 16GB
32G = 32GB SLC Enhanced Area
64G = 64GB F = 40%
M = 100%
NAND Flash Component
Mark Device Maximum Boot Size
J MLC 64Gb, x8, 3.3V (25nm) 0 = 1MB
L MLC 32Gb, x8, 3.3V (25nm) 1 = 2MB
M MLC 16Gb, x8, 3.3V (25nm) 2 = 4MB
3 = 8MB
Controller Revision 4 = 16MB
Mark (Rev.) Controller ID
T Enhanced Package Codes (Pb-free)
V Combo DN = 169 LFBGA 14mm x 18mm x 1.4mm
DQ = 100 LFBGA 14mm x 18mm x 1.4mm
EA = 153 WFBGA 11.5mm x 13mm x 0.8mm
EC = 169 WFBGA 14mm x 18mm x 0.8mm
ED = 169 VFBGA 14mm x 18mm x 1.0mm
Reserved for Future Use
Note: 1. Not all combinations are necessarily available. For a list of available devices or for further information on
any aspect of these products, please contact your nearest Micron sales office.

General Description
General Description
Micron e·MMC is a communication and mass data storage device that includes a Multi-
MediaCard (MMC) interface, a NAND Flash component, and a controller on an ad-
vanced 11-signal bus, which is compliant with the MMC system specification. Its low
cost, small size, Flash technology independence, and high data throughput make
e·MMC ideal for embedded applications like set-top boxes, digital cameras/camcor-
ders, digital TVs, and a variety other consumer products.
The nonvolatile e·MMC draws no power to maintain stored data, delivers high perform-
ance across a wide range of operating temperatures, and resists shock and vibration dis-
ruption.

Signal Descriptions
Signal Descriptions
Table 3: Signal Descriptions
Symbol Type Description

CLK Input Clock: Each cycle of the clock directs a transfer on the command line and on the data line(s). The
frequency can vary between the minimum and the maximum clock frequency.
RST_n Input Reset: The RST_n signal is used by the host for resetting the device, moving the device to the pre-
idle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD
register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.
CMD I/O Command: This signal is a bidirectional command channel used for command and response trans-
fers. The CMD signal has two bus modes: open-drain mode and push-pull mode (see Operating
Modes). Commands are sent from the MMC host to the device, and responses are sent from the
device to the host.
DAT[7:0] I/O Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull mode. By de-
fault, after power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. The
MMC controller can configure a wider data bus for data transfer either using DAT[3:0] (4-bit mode)
or DAT[7:0] (8-bit mode). e·MMC includes internal pull-up resistors for data lines DAT[7:1]. Immedi-
ately after entering the 4-bit mode, the device disconnects the internal pull-up resistors on the
DAT[3:1] lines. Upon entering the 8-bit mode, the device disconnects the internal pull-ups on the
DAT[7:1] lines.
VCC Supply VCC: NAND interface (I/F) I/O and NAND Flash power supply.
VCCQ Supply VCCQ: e·MMC controller core and e·MMC I/F I/O power supply.
VSS1 Supply VSS: NAND I/F I/O and NAND Flash ground connection.
VSSQ1 Supply VSSQ: e·MMC controller core and e·MMC I/F ground connection.
VDDI Internal voltage node: At least a 0.1μF capacitor is required to connect VDDI to ground. A 1μF ca-
pacitor is recommended. Do not tie to supply voltage or ground.
NC – No connect: No internal connection is present.
RFU – Reserved for future use: No internal connection is present. Leave it floating externally.
Note: 1. VSS and VSSQ are connected internally.

153-Ball Signal Assignments
Figure 3: 153-Ball FBGA (top view, ball down)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A NC NC DAT0 DAT1 DAT2 RFU RFU NC NC NC NC NC NC NC
B NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC
C NC VDDI NC VSSQ RFU VCCQ NC NC NC NC NC NC NC NC
D NC NC NC NC NC NC NC
E NC NC NC RFU VCC VSS RFU RFU RFU NC NC NC
F NC NC NC VCC RFU NC NC NC
G NC NC RFU VSS RFU NC NC NC
H NC NC NC RFU VSS NC NC NC
J NC NC NC RFU VCC NC NC NC
K NC NC NC RST_n RFU RFU VSS VCC RFU NC NC NC
L NC NC NC NC NC NC
M NC NC NC VCCQ CMD CLK NC NC NC NC NC NC NC NC
N NC VSSQ NC VCCQ VSSQ NC NC NC NC NC NC NC NC NC
P NC NC VCCQ VSSQ VCCQ VSSQ RFU NC NC RFU NC NC NC NC
Notes: 1. Some test pads on the device are not shown. They are not solder balls and are for Mi-
cron internal use only.
2. Some previous versions of the JEDEC product or mechanical specification had defined
reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-
vious specifications could have been connected to ground on the system board. To ena-
ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-
chanical specification. Any new PCB footprint implementations should use the new ball
assignments and leave the RFU balls floating on the system board.


Figure 4: 169-Ball FBGA (top view, ball down)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A NC NC NC NC
B 1
NC NC
D NC NC
H NC NC DAT0 DAT1 DAT2 RFU RFU NC NC NC NC NC NC NC
J NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC
K NC VDDI NC VSSQ RFU VCCQ NC NC NC NC NC NC NC NC
L NC NC NC NC NC NC NC
M NC NC NC RFU VCC VSS RFU RFU RFU NC NC NC
N NC NC NC VCC RFU NC NC NC
P NC NC RFU VSS RFU NC NC NC
R NC NC NC RFU VSS NC NC NC
T NC NC NC RFU VCC NC NC NC
U NC NC NC RST_n RFU RFU VSS VCC RFU NC NC NC
V NC NC NC NC NC NC
W NC NC NC VCCQ CMD CLK NC NC NC NC NC NC NC NC
Y NC VSSQ NC VCCQ VSSQ NC NC NC NC NC NC NC NC NC
AA NC NC VCCQ VSSQ VCCQ VSSQ RFU NC NC RFU NC NC NC NC
AB
AC
AD
AE NC NC
AF
AG NC NC
AH NC NC NC NC
Notes: 1. Empty balls do not denote actual solder balls; they are position indicators only.

2. Some test pads on the device are not shown. They are not solder balls and are for Mi-
cron internal use only.
3. Some previous versions of the JEDEC product or mechanical specification had defined
reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-
vious specifications could have been connected to ground on the system board. To ena-
ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-
chanical specification. Any new PCB footprint implementations should use the new ball
assignments and leave the RFU balls floating on the system board.

Package Dimensions
Package Dimensions
Figure 5: 153-Ball WFBGA – 11.5mm x 13.0mm x 0.8mm (Package Code: EA)
Seating plane
A 0.08 A
153X Ø0.30
Dimensions apply to Pin A1 index
solder balls post- (covered by SR)
reflow on Ø0.30 SMD Pin A1 index
OSP ball pads. 14 12 10 8 6 4 2
13 11 9 7 5 3 1
A
B
C
D
E
6.5 CTR F
G
H
13 ±0.1 J
K
L
M
N
P
0.5 TYP
0.5 TYP 0.7 ±0.1
6.5 CTR 0.17 MIN
11.5 ±0.1
Note: 1. Dimensions are in millimeters.

Package Dimensions
Figure 6: 169-Ball WFBGA – 14.0mm x 18.00mm x 0.8mm (Package Code: EC)
Seating plane
A 0.08 A
169X Ø0.3
Dimensions apply to
solder balls post-reflow Pin A1 index Pin A1 index
on Ø0.30 SMD OSP ball 14 12 10 8 6 4 2
pads. 13 11 9 7 5 3 1
A
B
C
D
E
F
G
H
J
K
13.5 CTR L
M
N
P
6.5 CTR R
T
U
18 ±0.1 V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
0.5 TYP 0.5 TYP 0.7 ±0.1

6.5 CTR 0.17 MIN
14 ±0.1

Package Dimensions
Figure 7: 169-Ball VFBGA – 14.0mm x 18.00mm x 1.0mm (Package Code: ED)
Seating plane
A 0.08 A
169X Ø0.3
Dimensions apply to
solder balls post-reflow Pin A1 index Pin A1 index
on Ø0.30 SMD ball pads. 14 12 10 8 6 4 2
13 11 9 7 5 3 1
A
B
C
D
E
F
G
H
J
K
13.5 CTR L
M
N
P
6.5 CTR R
T
U
V
18 ±0.1 W
Y
AA
AB
AC
AD
AE
AF
AG
AH
0.5 TYP 0.5 TYP 0.9 ±0.1

6.5 CTR 0.17 MIN
14 ±0.1

Package Dimensions
Figure 8: 169-Ball LFBGA – 14.0mm x 18.00mm x 1.4mm (Package Code: DN)
Seating plane
A 0.08 A
169X Ø0.3
Ball A1 ID
Dimensions apply
(covered by SR)
to solder balls post- Ball A1 ID
reflow on Ø0.30 SMD
ball pads. 14 12 10 8 6 4 2
13 11 9 7 5 3 1
A
B
C
D
E
F
G
H
J
K
13.5 CTR L
M
N
P
6.5 CTR R
T
U
V
18 ±0.1 W
Y
AA
AB
AC
AD
AE
AF
AG
AH
0.5 TYP 0.5 TYP 1.3 ±0.1

6.5 CTR 0.16 MIN
14 ±0.1

Architecture
Architecture
Figure 9: e·MMC Functional Block Diagram
e·MMC
MMC VCC
controller VCCQ
RST_n
CMD Registers
DAT[7:0]
CLK
OCR CSD RCA
VDDI
VSS1
CID ECSD DSR
VSSQ1
NAND Flash
Note: 1. VSS and VSSQ are internally connected.
MMC Protocol Independent of NAND Flash Technology

The MMC specification defines the communication protocol between a host and a de-
vice. The protocol is independent of the NAND Flash features included in the device.
The device has an intelligent on-board controller that manages the MMC communica-
tion protocol.
The controller also handles block management functions such as logical block alloca-
tion and wear leveling. These management functions require complex algorithms and
depend entirely on NAND Flash technology (generation or memory cell type).
The device handles these management functions internally, making them invisible to
the host processor.
Defect and Error Management

Micron e·MMC incorporates advanced technology for defect and error management. If
a defective block is identified, the device completely replaces the defective block with
one of the spare blocks. This process is invisible to the host and does not affect data
space allocated for the user.
The device also includes a built-in error correction code (ECC) algorithm to ensure that
data integrity is maintained.
To make the best use of these advanced technologies and ensure proper data loading
and storage over the life of the device, the host must exercise the following precautions:
• Check the status after WRITE, READ, and ERASE operations.
• Avoid power-down during WRITE and ERASE operations.

CID Register
CID Register
The card identification (CID) register is 128 bits wide. It contains the device identifica-
tion information used during the card identification phase as required by e·MMC proto-
col. Each device is created with a unique identification number.
Table 4: CID Register Field Parameters
Name Field Width CID Bits CID Value

Manufacturer ID MID 8 [127:120] FEh
Reserved – 6 [119:114] –
Card/BGA CBX 2 [113:112] 01h
OEM/application ID OID 8 [111:104] –
Product name PNM 48 [103:56] MMC02G
MMC04G
MMC08G
MMC16G
MMC32G
MMC64G
Product revision PRV 8 [55:48] –
Product serial number PSN 32 [47:16] –
Manufacturing date MDT 8 [15:8] –
CRC7 checksum CRC 7 [7:1] –
Not used; always 1 – 1 0 –

CSD Register
CSD Register
The card-specific data (CSD) register provides information about accessing the device
contents. The CSD register defines the data format, error correction type, maximum da-
ta access time, and data transfer speed, as well as whether the DS register can be used.
The programmable part of the register (entries marked with W or E in the following ta-
ble) can be changed by the PROGRAM_CSD (CMD27) command.
Table 5: CSD Register Field Parameters
Cell CSD CSD

Name Field Width Type1 Bits Value
CSD structure CSD_STRUCTURE 2 R [127:126] 03h
System specification version SPEC_VERS 4 R [125:122] 4h
Reserved2 – 2 TBD [121:120] –
Data read access time 1 TAAC 8 R [119:112] 4Fh
Data read access time 2 in CLK NSAC 8 R [111:104] 01h
cycles (NSAC × 100)
Maximum bus clock frequency TRAN_SPEED 8 R [103:96] 32h
Card command classes CCC 12 R [95:84] 0F5h
Maximum read data block READ_BL_LEN MTFC2GMVEA-0M WT 4 R [83:80] 0Ah
length MTFC4GLVEA-0M WT, 09h
MTFC4GMVEA-1M WT,
MTFC8GLVEA-1M WT,
MTFC16GJVEC-2M WT,
MTFC32GJVED-3M WT,
MTFC64GJVDN-3M WT
Partial blocks for reads suppor- READ_BL_PARTIAL 1 R 79 0h
ted
Write block misalignment WRITE_BLK_MISALIGN 1 R 78 0h
Read block misalignment READ_BLK_MISALIGN 77 R 77 0h
DS register implemented DSR_IMP 1 R 76 1h
Reserved – 2 R [75:74] –
Device size C_SIZE MTFC2GMVEA-0M WT 12 R [73:62] E4Fh
MTFC4GLVEA-0M WT, FFFh
MTFC4GMVEA-1M WT,
MTFC8GLVEA-1M WT,
MTFC16GJVEC-2M WT,
MTFC32GJVED-3M WT,
MTFC64GJVDN-3M WT
Maximum read current at VDD_R_CURR_MIN 3 R [61:59] 7h
VDD,min
Maximum read current at VDD_R_CURR_MAX 3 R [58:56] 7h
VDD,max
Maximum write current at VDD_W_CURR_MIN 3 R [55:53] 7h
VDD,min

CSD Register
Table 5: CSD Register Field Parameters (Continued)
Cell CSD CSD

Name Field Width Type1 Bits Value
Maximum write current at VDD_W_CURR_MAX 3 R [52:50] 7h
VDD,max
Device size multiplier C_SIZE_MULT 3 R [49:47] 7h
Erase group size ERASE_GRP_SIZE 5 R [46:42] 1Fh
Erase group size multiplier ERASE_GRP_MULT 5 R [41:37] 1Fh
Write protect group size WP_GRP_SIZE MTFC2GMVEA-0M WT 5 R [36:32] 03h
MTFC4GLVEA-0M WT, 07h
MTFC4GMVEA-1M WT
MTFC8GLVEA-1M WT 0Fh
MTFC16GJVEC-2M WT, 1Fh
MTFC32GJVED-3M WT,
MTFC64GJVDN-3M WT
Write protect group enable WP_GRP_ENABLE 1 R 31 1h
Manufacturer default ECC DEFAULT_ECC 2 R [30:29] 0h
Write-speed factor R2W_FACTOR 3 R [28:26] 2h
Maximum write data block WRITE_BL_LEN 4 R [25:22] 9h
length
Partial blocks for writes suppor- WRITE_BL_PARTIAL 1 R 21 0h
ted
Reserved – 4 R [20:17] –
Content protection application CONTENT_PROT_APP 1 R 16 0h
File-format group FILE_FORMAT_GRP 1 R/W 15 0h
Copy flag (OTP) COPY 1 R/W 14 0h
Permanent write protection PERM_WRITE_PROTECT 1 R/W 13 0h
Temporary write protection TMP_WRITE_PROTECT 1 R/W/E 12 0h
File format FILE_FORMAT 2 R/W [11:10] 0h
ECC ECC 2 R/W/E [9:8] 0h
CRC CRC 7 R/W/E [7:1] –
Not used; always 1 – 1 – 0 1h
Notes: 1. R = Read-only
R/W = One-time programmable and readable
R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_n
signal, and any CMD0 reset, and readable
TBD = To be determined
2. Reserved bits should be read as 0.

ECSD Register
ECSD Register
The 512-byte extended card-specific data (ECSD) register defines device properties and
selected modes. The most significant 320 bytes are the properties segment. This seg-
ment defines device capabilities and cannot be modified by the host. The lower 192
bytes are the modes segment. The modes segment defines the configuration in which
the device is working. The host can change the properties of modes segments using the
SWITCH command.
Table 6: ECSD Register Field Parameters
Size Cell ECSD ECSD

Name Field (Bytes) Type1 Bytes Value
Properties Segment
Reserved2 – 7 – [511:505] –
Supported command sets S_CMD_SET 1 R 504 1h
HPI features HPI_FEATURES 1 R 503 3h
Background operations support BKOPS_SUPPORT 1 R 502 1h
Reserved – 255 – [501:247] –
Background operations status BKOPS_STATUS 1 R 246 0h
Number of correctly program- CORRECTLY_PRG_ 4 R [245:242] –
med sectors SECTORS_NUM
First initialization time after INI_TIMEOUT_PA MTFC2GMVEA-0M WT 1 R 241 7Ah
partitioning MTFC4GLVEA-0M WT F6h
(first CMD1 to device ready)
MTFC4GMVEA-1M WT 7Ah
MTFC8GLVEA-1M WT, F6h
MTFC16GJVEC-2M WT
MTFC32GJVED-3M WT, FFh
MTFC64GJVDN-3M WT
Reserved – 1 – 240 –
Power class for 52 MHz, DDR at PWR_CL_DDR_52_360 1 R 239 0h
3.6V3
Power class for 52 MHz, DDR at PWR_CL_DDR_52_195 1 R 238 0h
1.95V3
Reserved – 2 – [237:236] –
Minimum write performance MIN_PERF_DDR_W_8_52 1 R 235 0h
for 8-bit at 52 MHz in DDR
mode
Minimum read performance for MIN_PERF_DDR_R_8_52 1 R 234 0h
8-bit at 52 MHz in DDR mode

ECSD Register
Table 6: ECSD Register Field Parameters (Continued)
Size Cell ECSD ECSD

TRIM multiplier TRIM_MULT MTFC2GMVEA-0M WT 1 R 232 06h
MTFC4GLVEA-0M WT,
MTFC4GMVEA-1M WT,
MTFC8GLVEA-1M WT
MTFC16GJVEC-2M WT, 0Fh
MTFC32GJVED-3M WT,
MTFC64GJVDN-3M WT
Secure feature support SEC_FEATURE_SUPPORT 1 R 231 15h
SECURE ERASE multiplier SEC_ERASE_MULT MTFC2GMVEA-0M WT 1 R 230 02h
MTFC4GLVEA-0M WT,
MTFC4GMVEA-1M WT,
MTFC8GLVEA-1M WT
MTFC16GJVEC-2M WT, 06h
MTFC32GJVED-3M WT,
MTFC64GJVDN-3M WT
SECURE TRIM multiplier SEC_TRIM_MULT MTFC2GMVEA-0M WT 1 R 229 03h
MTFC4GLVEA-0M WT,
MTFC4GMVEA-1M WT,
MTFC8GLVEA-1M WT
MTFC32GJVED-3M WT,
MTFC64GJVDN-3M WT
Boot information BOOT_INFO 1 R 228 7h
Boot partition size BOOT_SIZE_MULT MTFC2GMVEA-0M WT, 1 R 226 08h
MTFC4GLVEA-0M WT
MTFC4GMVEA-1M WT, 10h
MTFC8GLVEA-1M WT
MTFC16GJVEC-2M WT 20h
MTFC32GJVED-3M WT, 40h
MTFC64GJVDN-3M WT
Access size ACC_SIZE MTFC2GMVEA-0M WT, 1 R 225 05h
MTFC4GLVEA-0M WT
MTFC8GLVEA-1M WT
MTFC32GJVED-3M WT,
MTFC64GJVDN-3M WT

ECSD Register
Size Cell ECSD ECSD

High-capacity erase unit size HC_ERASE_GRP_S MTFC2GMVEA-0M WT 1 R 224 00h
IZE MTFC4GLVEA-0M WT 04h
MTFC8GLVEA-1M WT
MTFC32GJVED-3M WT,
MTFC64GJVDN-3M WT
High-capacity erase timeout ERASE_TIMEOUT_MULT 1 R 223 01h
Reliable write-sector count REL_WR_SEC_C 1 R 222 01h
High-capacity write protect HC_WP_GRP_SIZE MTFC2GMVEA-0M WT 1 R 221 00h
group size MTFC4GLVEA-0M WT 02h
MTFC4GMVEA-1M WT 01h
MTFC8GLVEA-1M WT, 02h
MTFC16GJVEC-2M WT
MTFC32GJVED-3M WT 04h
MTFC64GJVDN-3M WT 08h
Sleep current (VCC) S_C_VCC 1 R 220 08h
Sleep current (VCCQ) S_C_VCCQ 1 R 219 08h
Sleep/awake timeout S_A_TIMEOUT 1 R 217 10h
Sector count SEC_COUNT MTFC2GMVEA-0M WT 4 R [215:212] 00000000h
MTFC4GLVEA-0M WT 00750000h
MTFC4GMVEA-1M WT 00728000h
MTFC8GLVEA-1M WT 00EA0000h
MTFC16GJVEC-2M WT 01D40000h
MTFC32GJVED-3M WT 03B20000h
MTFC64GJVDN-3M WT 07700000h
Minimum write performance MIN_PERF_W_8_52 1 R 210 08h
for 8-bit at 52 MHz
Minimum read performance for MIN_PERF_R_8_52 1 R 209 08h
8-bit at 52 MHz
Minimum write performance MIN_PERF_W_8_26_4_52 1 R 208 08h
for 8-bit at 26 MHz and 4-bit at
52 MHz
Minimum read performance for MIN_PERF_R_8_26_4_52 1 R 207 08h
8-bit at 26 MHz and 4-bit at 52
MHz

ECSD Register
Size Cell ECSD ECSD

Minimum write performance MIN_PERF_W_4_26 1 R 206 08h
for 4-bit at 26 MHz
Minimum read performance for MIN_PERF_R_4_26 1 R 205 08h
4-bit at 26 MHz
Power class for 26 MHz at 3.6V3 PWR_CL_26_360 1 R 203 00h
Power class for 52 MHz at 3.6V3 PWR_CL_52_360 1 R 202 00h
Power class for 26 MHz at PWR_CL_26_195 1 R 201 00h
1.95V3
Power class for 52 MHz at PWR_CL_52_195 1 R 200 00h
1.95V3
Partition switching timing PARTITION_SWITCH_TIME 1 R 199 1h
Out-of-interrupt busy timing OUT_OF_INTERRUPT_TIME 1 R 198 02h
Card type CARD_TYPE 1 R 196 07h
CSD structure version CSD_STRUCTURE 1 R 194 2h
Extended CSD revision EXT_CSD_REV 1 R 192 5h
Modes Segment
Command set CMD_SET 1 R/W/E_P 191 0h
Command set revision CMD_SET_REV 1 R 189 0h
Power class POWER_CLASS 1 R/W/E_P 187 0h
High-speed interface timing HS_TIMING 1 R/W/E_P 185 0h
Bus width mode BUS_WIDTH 1 W/E_P 183 0h
Erased memory content ERASED_MEM_CONT 1 R 181 0h
Partition configuration PARTITION_CONFIG 1 R/W/E, 179 0h
R/W/E_P
Boot configuration protection BOOT_CONFIG_PROT 1 R/W, 178 0h
R/W/C_P
Boot bus width BOOT_BUS_WIDTH 1 R/W/E 177 0h

ECSD Register
Size Cell ECSD ECSD

High-density erase group defi- ERASE_GROUP_DEF 1 R/W/E_P 175 00h
nition
Boot area write protection reg- BOOT_WP 1 R/W, 173 0h
ister R/W/C_P
User write protection register USER_WP 1 R/W, 171 0h
R/W/C_P,
R/W/E_P
Firmware configuration FW_CONFIG 1 R/W 169 0h
RPMB size RPMB_SIZE_MULT 1 R 168 1h
Write reliability setting regis- WR_REL_SET 1 R/W 167 00h4
ter3
Write reliability parameter reg- WR_REL_PARAM 1 R 166 05h
ister
Manually start background op- BKOPS_START 1 W/E_P 164 –
erations
Enable background operations BKOPS_EN 1 R/W 163 0h
handshake
Hardware reset function RST_n_FUNCTION 1 R/W 162 0h
HPI management HPI_MGMT 1 R/W/E_P 161 0h
Partitioning support PARTITIONING_SUPPORT 1 R 160 3h
Maximum enhanced area size MAX_ENH_SIZE_ MTFC2GMVEA-0M WT 3 R [159:157] 0001CAh
MULT MTFC4GLVEA-0M WT 0001D4h
MTFC4GMVEA-1M WT 0001CAh
MTFC8GLVEA-1M WT, 0001D4h
MTFC16GJVEC-2M WT
MTFC32GJVED-3M WT 0001D9h
MTFC64GJVDN-3M WT 0001DCh
Partitions attribute PARTITIONS_ATTRIBUTE 1 R/W 156 0h
Partitioning setting PARTITION_SETTING_COMPLETED 1 R/W 155 0h
General-purpose partition size GP_SIZE_MULT 12 R/W [154:143] 0h
Enhanced user data area size ENH_SIZE_MULT 3 R/W [142:140] 0h
Enhanced user data start ad- ENH_START_ADDR 4 R/W [139:136] 0h
dress
Bad block management mode SEC_BAD_BLK_MGMNT 1 R/W 134 0h

ECSD Register
Size Cell ECSD ECSD

Reserved – 134 – [133:0] –
Notes: 1. R = Read-only
R/W = One-time programmable and readable
R/W/E = Multiple writable with the value kept after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable
R/W/C_P = Writable after the value is cleared by a power cycle and assertion of the
RST_n signal (the value not cleared by CMD0 reset) and readable
R/W/E_P = Multiple writable with the value reset after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable
W/E_P = Multiple writable with the value reset after power cycle, assertion of the RST_n
signal, and any CMD0 reset, and not readable
TBD = To be determined
2. Reserved bits should be read as 0.
3. Micron has tested power failure under best application knowledge conditions with posi-
tive results. Customers may request a dedicated test for their specific application condi-
tion.
4. Can be set to 1Fh to enable reliability settings. This byte is one-time programmable.

DC Electrical Specifications – Device Power

The device current consumption for various device configurations is defined in the
power class fields of the ECSD register.
VCC is used for the NAND Flash device and its interface voltage; V CCQ is used for the
controller and the e·MMC interface voltage. A CREG capacitor must be connected to the
VDDI terminal to stabilize regulator output on the system.
Figure 10: Device Power Diagram
VCC
VCCQ
Core regulator
NAND NAND Flash
VDDI control signals
I/O block
I/O block
CREG
NAND
MMC
CLK Core NAND

CMD logic block
data bus
DAT[7:0]
MMC controller
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only, and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not guaranteed. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Table 7: Absolute Maximum Ratings
Parameters Symbol Min Max Unit

Voltage input VIN –0.6 4.6 V
VCC supply VCC –0.6 4.6 V
VCCQ supply VCCQ –0.6 4.6 V
Storage temperature TSTG –40 85 °C
Note: 1. Voltage on any pin relative to VSS.

Table 8: Operating Conditions
Parameters Symbol Min Typ Max Unit

Supply voltage (controller VCCQ 1.65 – 1.95 V
and I/O) 2.70 – 3.6
Supply voltage (NAND) VCC 2.70 – 3.6 V
Supply power-on for 3.3V tPRUH – – 35 ms
Supply power-on for 1.8V tPRUL – – 25 ms
VDDI capacitance value CREG1 0.1 – – µF
Operating temperature TA –25 – 85 ºC
Note: 1. CREG is used to stabilize the internal regulator output to controller core logic voltages.
Micron recommends using the following capacitor values:
CVCC (capacitor for VCC) = 4.3µF.
CVCCQ (capacitor for VCCQ) = 4.3µF
CREG = 1.0µF.

Revision History
Revision History
Rev. A – 06/12
• Initial release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

Features Figure 1: Micron e·MMC Device

• MultiMediaCard (MMC) controller and NAND Flash

2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

Table 1: MLC Partition Performance

Table 2: Ordering Information

2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

Part Numbering Information

Figure 2: Marketing Part Number Chart

Micron Technology Production Status

NAND Flash Density Operating Temperature Range

Reserved for Future Use

2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

Table 3: Signal Descriptions

Symbol Type Description

Note: 1. VSS and VSSQ are connected internally.

2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

153-Ball Signal Assignments

Figure 3: 153-Ball FBGA (top view, ball down)

A NC NC DAT0 DAT1 DAT2 RFU RFU NC NC NC NC NC NC NC

B NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC

C NC VDDI NC VSSQ RFU VCCQ NC NC NC NC NC NC NC NC

E NC NC NC RFU VCC VSS RFU RFU RFU NC NC NC

G NC NC RFU VSS RFU NC NC NC

K NC NC NC RST_n RFU RFU VSS VCC RFU NC NC NC

M NC NC NC VCCQ CMD CLK NC NC NC NC NC NC NC NC

N NC VSSQ NC VCCQ VSSQ NC NC NC NC NC NC NC NC NC

P NC NC VCCQ VSSQ VCCQ VSSQ RFU NC NC RFU NC NC NC NC

2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

169-Ball Signal Assignments

H NC NC DAT0 DAT1 DAT2 RFU RFU NC NC NC NC NC NC NC

J NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC

K NC VDDI NC VSSQ RFU VCCQ NC NC NC NC NC NC NC NC

M NC NC NC RFU VCC VSS RFU RFU RFU NC NC NC

P NC NC RFU VSS RFU NC NC NC

U NC NC NC RST_n RFU RFU VSS VCC RFU NC NC NC

W NC NC NC VCCQ CMD CLK NC NC NC NC NC NC NC NC

Y NC VSSQ NC VCCQ VSSQ NC NC NC NC NC NC NC NC NC

AA NC NC VCCQ VSSQ VCCQ VSSQ RFU NC NC RFU NC NC NC NC

2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

Figure 5: 153-Ball WFBGA – 11.5mm x 13.0mm x 0.8mm (Package Code: EA)

0.5 TYP 0.7 ±0.1

6.5 CTR 0.17 MIN

Note: 1. Dimensions are in millimeters.

2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

Figure 6: 169-Ball WFBGA – 14.0mm x 18.00mm x 0.8mm (Package Code: EC)

0.5 TYP 0.5 TYP 0.7 ±0.1

Note: 1. Dimensions are in millimeters.

2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

Figure 7: 169-Ball VFBGA – 14.0mm x 18.00mm x 1.0mm (Package Code: ED)

0.5 TYP 0.5 TYP 0.9 ±0.1

Note: 1. Dimensions are in millimeters.

2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMC

Figure 8: 169-Ball LFBGA – 14.0mm x 18.00mm x 1.4mm (Package Code: DN)

0.5 TYP 0.5 TYP 1.3 ±0.1