AN4660

Application note
Migration of microcontroller applications from
STM32F42xxx/F43xxx devices to STM32F7 Series devices

Introduction
The designers of STM32 microcontroller applications must have the possibility to easily
replace one microcontroller type with another one from the same product family. The
reasons for migrating an application to a different microcontroller can be for example:
• To fulfill higher product requirements, extra demands on the memory size, or an increased
number of I/Os.
• To meet cost reduction constraints that require to switch to smaller components and to
shrink the PCB area.
This application note analyzes the steps required to migrate from an existing
STM32F42xxx/F43xxx device to a STM32F7 Series device based design.
This application note provides a guideline on the hardware migration and the peripheral
migration. To fully benefit from this application note, the user should be familiar with the
STM32 microcontroller family.
For additional information, refer to the following documents available on www.st.com:
• STM32F405/415, STM32F407/417, STM32F427/437 and STM32F429/439 advanced
ARM®-based 32-bit MCUs reference manual (RM0090)
• STM32F72xxx and STM32F73xxx advanced ARM®-based 32-bit MCUs reference
manual (RM0431)
• STM32F75xxx and STM32F74xxx advanced ARM®-based 32-bit MCUs reference
manual (RM0385)
• STM32F76xxx and STM32F77xxx advanced ARM®-based 32-bit MCUs reference
manual (RM0410)

Table 1. Applicable products

Type Product lines and Series

STM32F427/437 line, STM32F429/439 line

Microcontrollers
STM32F7 Series

February 2017 DocID027558 Rev 3 1/39

www.st.com 1
Contents AN4660

Contents

1 Hardware migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Pinout compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.2 LQFP208 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.3 LQFP176 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.4 TFBGA216 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1.5 LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.2 Boot mode compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3 System bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2 Peripheral migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 STM32 product cross-compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.6 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.7 External interrupt lines (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.8 RCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.8.1 Maximum frequency according to power scale parameter . . . . . . . . . . 28
2.9 PWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.10 RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.11 U(S)ART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.12 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.13 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.14 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.15 USB OTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.16 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.16.1 External trigger for regular channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.16.2 External trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2/39 DocID027558 Rev 3

AN4660 Contents

4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DocID027558 Rev 3 3/39

3
List of tables AN4660

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F42xxx/F43xxx and STM32F4xxx/F75xxx/F76xxx/F77xxx/F7x2xx
pinout differences (LQFP100). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. List of LQFP208 pinout differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. List of LQFP176 pinout differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. List of TFBGA216 ballout differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Boot mode selection comparison between the STM32F42xxx/F43xxx and
STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. STM32F42xxx/F43xxx and STM32F7 Series bootloader communication
peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. STM32 peripheral compatibility analysis between the STM32F42xxx/F43xxx and
STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. IP bus mapping differences between the STM32F42xxx/F43xxx and
STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Flash memory differences between the STM32F42xxx/F43xxx
and STM32F7 Series devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. Flash module 1 Mbyte single bank organization (STM32F7 Series) . . . . . . . . . . . . . . . . . 23
Table 12. FMC differences between the STM32F42xxx/F43xxx and STM32F7 Series devices . . . . 24
Table 13. Interrupt vector differences between the STM32F42xxx/F43xxx and
STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. EXTI line differences between the STM32F42xxx/F43xxx and
STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. RCC differences between the STM32F42xxx/F43xxx and
STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Maximum frequency comparison between the STM32F42xxx/F43xxx and
STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. PWR differences between the STM32F42xxx/F43xxx and STM32F7 Series devices . . . . 29
Table 18. RTC comparison between the STM32F42xxx/F43xxx and STM32F7 Series devices . . . . 30
Table 19. U(S)ART differences between the STM32F42xxx/F43xxx and STM32F7 Series devices . 31
Table 20. I2C differences between the STM32F42xxx/F43xxx and STM32F7 Series devices . . . . . 32
Table 21. SPI differences between the STM32F42xxx/F43xxx and STM32F7 Series devices . . . . . 32
Table 22. CRC differences between the STM32F42xxx/F43xxx and STM32F7 Series devices . . . . 33
Table 23. USB OTG differences between the STM32F42xxx/F43xxx and
STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 24. External trigger for regular channel differences between the
STM32F42xxx/F43xxx and STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 25. External trigger for injected channel differences between the
STM32F42xxx/F43xxx and STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4/39 DocID027558 Rev 3

AN4660 List of figures

List of figures

Figure 1. Incompatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. LQFP208 pinout differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. LQFP176 pinout differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. TFBGA216 ballout differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DocID027558 Rev 3 5/39

5
Hardware migration

1 Hardware migration

1.1 Pinout compatibility

1.1.1 LQFP100 package

The STM32F74xxx/F75xxx/F76xxx/F77xxx/F7x2xx devices are fully pin-to-pin compatible
with the STM32F42xxx/F43xxx devices except for the LQFP100 package, allowing the user
to try different peripherals, and reaching higher performances (higher frequency) for a
greater degree of freedom during the development cycle.
The STM32F7x3xx devices (x=2 or 3) are not compatible with the STM32F42xxx/F43xxx
devices due to the USB PHY HS functionality on some pins.
In this application note, the pinout migration to the STM32F7x3xx product is not covered. In
order to migrate to this product, refer to Migration of microcontroller applications between
STM32F74xxx/75xxx and STM32F72xxx/F73xxx application note (AN4946).
Figure 1 and Table 2 present the pinout differences between the STM32F42xxx/F43xxx and
STM32F74xxx/F75xxx/F76xxx/F77xxx/F7x2xx devices for the LQFP100 package.

Figure 1. Incompatible board design for LQFP100 package

670)[[[)[[[
3& 
9'' 
966$ 
95() 
9''$ 
3$:.83 
3$ 
3$ 

3(

9&$3
3(
3(

3%
3(
3(
9''

3%
966

9''
3$

3&
3&

3%
3%

3(
3$
3$

3%

3(
3$

3(
3$

3(

3&  670)[[[)[[[)[[[)[[[)[[[
966$ 
95() 
9''$ 
3$:.83 
3$ 
3$ 3LQVWRDUHQRWFRPSDWLEOH

3$ 

9&$3
3(

3(

3%
3(

3(

3%
3(

3(

9''
966
9''

3$
966

3&

3&

3%

3(

3(
3%

3(
3$

3%
3$
3$

06Y9

6/39 DocID027558 Rev 3

 Hardware migration

Table 2. STM32F42xxx/F43xxx and STM32F4xxx/F75xxx/F76xxx/F77xxx/F7x2xx

pinout differences (LQFP100)
STM32F74xxx/F75xxx/
LQFP100 STM32F42xxx/F43xxx pinout F76xxx/F77xxx/F76xxx/
F7x2xx pinout

19 VDD VSSA
20 VSSA VREF+
21 VREF+ VDDA
22 VDDA PA0-WKUP
23 PA0-WKUP PA1
24 PA1 PA2
25 PA2 PA3
26 PA3 VSS
27 VSS VDD
28 VDD PA4
29 PA4 PA5
30 PA5 PA6
31 PA6 PA7
32 PA7 PC4
33 PC4 PC5
34 PC5 PB0
35 PB0 PB1
36 PB1 PB2
37 PB2 PE7
38 PE7 PE8
39 PE8 PE9
40 PE9 PE10
41 PE10 PE11
42 PE11 PE12
43 PE12 PE13
44 PE13 PE14
45 PE14 PE15
46 PE15 PB10
47 PB10 PB11
48 PB11 VCAP1
49 VCAP1 VSS
53 PB14 PB14
54 PB15 PB15

DocID027558 Rev 3 7/39

38
Hardware migration

Table 2. STM32F42xxx/F43xxx and STM32F4xxx/F75xxx/F76xxx/F77xxx/F7x2xx

pinout differences (LQFP100) (continued)
STM32F74xxx/F75xxx/
LQFP100 STM32F42xxx/F43xxx pinout F76xxx/F77xxx/F76xxx/
F7x2xx pinout

55 PD8 PD8
56 PD9 PD9
57 PD10 PD10

1.1.2 LQFP208 package

Figure 2 and Table 3 present the pinout differences between the
STM32F74xxx/STM32F756xx/STM32F765xx/STM32F767xx/STM32F777xx/STM32F42xB
xT/STM32F43xBxT and the
STM32F768Ax/STM32F769xx/STM32F779xx/STM32F469BxT/STM32F479BxT devices for
the LQFP208 package.

Figure 2. LQFP208 pinout differences

 3&  3&

 9''  9''B86%
 966  966
 3*  3*
 3*  3*
 3*  3*
 3*  3*
670)[[[  3*  3*
670)[[  3* 670)$[  3*
670)[[  3* 670)[[  3*
670)[[  3. 670)[[  966'6,
670)[[  3. 670)%[7  '6,+267B'1
670)[%[7  3. 670)%[7  '6,+267B'3
670)[%[7  966  9'''6,
 9'' /4)3  '6,+267B&.1
/4)3  3-  '6,+267B&.3
 3-  966'6,
 3-  '6,+267B'1
 3-  '6,+267B'3
 3-  9&$3'6,
 3-  9'''6,
 3'  3'
 3'  3'

1RWFRPSDWLEOHSLQV
06Y9

For the highlighted (blue) terminals, the DSIHOST dedicated IOs on the
STM32F768Ax/STM32F769xx/STM32F779xx/STM32F469BxT/STM32F479BxT devices
substitute some of
STM32F74xxx/STM32F756xx/STM32F765xx/STM32F767xx/STM32F777xx/STM32F42xB
xT/STM32F43xBxT IO ports.

8/39 DocID027558 Rev 3

 Hardware migration

Table 3. List of LQFP208 pinout differences

STM32F74xxx STM32F74xxx
STM32F756xx STM32F768Ax STM32F756xx STM32F768Ax
STM32F765xx STM32F769xx STM32F765xx STM32F769xx
Terminal STM32F767xx STM32F779xx Terminal STM32F767xx STM32F779xx
STM32F777xx STM32F469BxT STM32F777xx STM32F469BxT
STM32F42xBxT STM32F479BxT STM32F42xBxT STM32F479BxT
STM32F43xBxT STM32F43xBxT

128 PK2 VSSDSI 122 PJ10 VSSDSI

127 PK1 DSIHOST_D1N 121 PJ9 DSIHOST_D0N
126 PK0 DSIHOST_D1P 120 PJ8 DSIHOST_D0P
125 VSS VDD12DSI 119 PJ7 VCAPDSI
124 VDD DSIHOST_CKN 118 PJ6 VDDDSI
123 PJ11 DSIHOST_CKP 137 VDD VDD_USB

1.1.3 LQFP176 package

Figure 3 and Table 4 present the pinout differences between the
STM32F74xxx/STM32F756xx/STM32F765xx/STM32F767xx/STM32F777xx/STM32F7x2xx
/STM32F42xIxT/STM32F43xIxT and the
STM32F768Ax/STM32F769xx/STM32F469IxT/STM32F479IxT devices for the LQFP176
package.

DocID027558 Rev 3 9/39

38
Hardware migration

Figure 3. LQFP176 pinout differences

966

966
3,

3,

3,

3,
     
 3,  3,
 3,  9''
 3+  966
 3+  9&$3
 3+  3$
 9''  3$
 966  3$
 9&$3  3$
 3$  3$
 3$  3$
 3$  3&
 3$  3&
 3$  3&
 3$  3&
 3&  9''86%
 3&  966
 3&  3*
670)[[[  3&  3*
670)[[
 9''RU9''86% 670)$[  3*
670)[[
 966 670)[[  3*
670)[[
 3* 670)[[  3*
670)[[
 3* 670),[7  3*
670)[[[
 3* 670),[7  3*
670)[,[7
670)[,[7  3*  966'6,
 3* /4)3  '6,+267B'1
/4)3  3*  '6,+267B'3
 3*  9'''6,
 3'  '6,+267B&.3
 3'  '6,+267B&.1
 9''  966'6,
 966  '6,+267B'1
 3'  '6,+267B'3
 3'  9&$3'6,
 3'  9''6,
 3'  3'
 3'  3'
 3'  9''
 3%  966
 3%  3'
 3%  3'
 3%  3'
 9''  3'
 966  3'
 3+  3'
         
3+

3+

3+

3+

3+

3+

3+

3%

3%

3%

1RWFRPSDWLEOHSLQV
06Y9

The highlighted (blue) terminals have different IO port assignment.

10/39 DocID027558 Rev 3

 Hardware migration

Table 4. List of LQFP176 pinout differences

STM32F74xxx
STM32F756xx
STM32F768Ax
STM32F765xx
STM32F769xx
STM32F767xx
Terminal STM32F779xx
STM32F777xx
STM32F469IxT
STM32F7x2xx
STM32F479IxT
STM32F42xIxT
STM32F43xIxT

133 PI2 PI1

132 PI1 PI0
131 PI0 VDD
130 PH15 VSS
129 PH14 VCAP2
128 PH13 PA13
127 VDD PA12
126 VSS PA11
125 VCAP2 PA10
124 PA13 PA0
123 PA12 PA8
122 PA11 PC9
121 PA10 PC8
120 PA9 PC7
119 PA8 PC6
118 PC9 VDDUSB
117 PC8 VSS
116 PC7 PG8
115 PC6 PG7
114 VDD or VDDUSB PG6
113 VSS PG5
112 PG8 PG4
111 PG7 PG3
110 PG6 PG2
109 PG5 VSSDSI
108 PG4 DSIHOST_D1N
107 PG3 DSIHOST_D1P
106 PG2 VDD12DSI
105 PD15 DSIHOST_CKP
104 PD14 DSIHOST_CKN

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38
Hardware migration

Table 4. List of LQFP176 pinout differences (continued)

STM32F74xxx
STM32F756xx
STM32F768Ax
STM32F765xx
STM32F769xx
STM32F767xx
Terminal STM32F779xx
STM32F777xx
STM32F469IxT
STM32F7x2xx
STM32F479IxT
STM32F42xIxT
STM32F43xIxT

103 VDD VSSDSI

102 VSS DSIHOST_D0N
101 PD13 DSIHOST_D0P
100 PD12 VCAPDSI
99 PD11 VDDDSI
98 PD10 PD15
97 PD9 PD14
96 PD8 VDD
95 PB15 VSS
94 PB14 PD13
93 PB13 PD12
92 PB12 PD11
91 VDD PD10
90 VSS PD9
89 PH12 PD8
88 PH11 PB15
87 PH10 PB14
86 PH9 PB13

1.1.4 TFBGA216 package

Figure 4 and Table 5 present the ballout differences between the
STM32F74xxx/STM32F756xx/STM32F765xx/STM32F767xx/STM32F777xx/STM32F42xN
xH/STM32F43xNxH and the
STM32F768Ax/STM32F769xx/STM32F469NxH/STM32F479NxH devices for the
TFBGA216 package.

12/39 DocID027558 Rev 3

 Hardware migration

Figure 4. TFBGA216 ballout differences

              

$ 3( 3( 3( 3* 3( 3( 3% 3% 3% 3% 3' 3& 3$ 3$ 3$

% 3( 3( 3* 3% 3% 3% 3* 3* 3- 3- 3' 3' 3& 3& 3$

& 9%$7 3, 3, 3. 3. 3. 3* 3* 3- 3' 3' 3' 3, 3, 3$

' 3& 3) 3, 3, 3, 3, 3. 3. 3* 3- 3' 3' 3+ 3, 3$

3'5
( 3& 3) 3, 3,
21
%227 9'' 9'' 9'' 9'' 9&$3 3+ 3+ 3, 3$

) 3& 966 3, 9'' 9'' 966 966 966 966 966 966 3& 3$

* 3+ 3) 3, 3, 9'' 966 966 3& 3&

+ 3+ 3) 3, 3+ 9'' 966 966 3* 3&

- 1567 3) 3+ 3+ 9'' 966 966 9'' 3* 3*

. 3) 3) 3) 3+ 9'' 966 966 966 966 966 9'' 3' 3% 3'

%<3$66
/ 3) 3) 3) 3&
5(*
966 9'' 9'' 9'' 9'' 9&$3 3' 3% 3' 3'

0 966$ 3& 3& 3& 3% 3) 3* 3) 3- 3' 3' 3* 3* 3- 3+

1 95() 3$ 3$ 3$ 3& 3) 3* 3- 3( 3' 3* 3* 3+ 3+ 3+

3 95() 3$ 3$ 3$ 3& 3) 3- 3) 3( 3( 3( 3% 3+ 3+ 3+

5 9''$ 3$ 3$ 3% 3% 3- 3- 3( 3( 3( 3( 3( 3% 3% 3%

7)%*$
670)[[[
670)[[
670)[[ 670)$[
670)[[ 670)[[
670)[[ 670)[[
670)[1[+ 670)1[+
670)[1[+ 670)1[+
'6, '6,
) 966 3. 3/ ) 966 +267B +267B
'3 '1

9''' 966 9''

* 9'' 3- 3. *
86% '6, '6,

'6, '6,
9''
+ 9'' 3- 3- + +267B +267B
'6,
&.3 &.1

'6, '6,
- 9'' 3- 3- - 9'' +267B +267B
'3 '1

9&$3
. 9'' 3- 3' . 9'' 3'
'6,

1RWFRPSDWLEOHEDOOV      
06Y9

DocID027558 Rev 3 13/39

38
Hardware migration

For the highlighted (blue) terminals, the DSIHOST dedicated IOs on the
STM32F768Ax/STM32F769xx/STM32F779xx/STM32F469NxH/STM32F479NxH devices
substitute some of
STM32F74xxx/STM32F756xx/STM32F765xx/STM32F767xx/STM32F777xx/
STM32F42xNxH/STM32F43xNxH IO ports.

Table 5. List of TFBGA216 ballout differences

STM32F74xxx STM32F74xxx
STM32F756xx STM32F768Ax STM32F756xx STM32F768Ax
STM32F765xx STM32F769xx STM32F765xx STM32F769xx
Terminal STM32F767xx STM32F779xx Terminal STM32F767xx STM32F779xx
STM32F777xx STM32F469NxH STM32F777xx STM32F469NxH
STM32F42xNxH STM32F479NxH STM32F42xNxH STM32F479NxH
STM32F43xNxH STM32F43xNxH

11G VDD VDDDUSB 12K PJ6 VCAPDSI

11H VDD VDDDSI 13F PL2 DSIHOST_D1N
12F PK1 DSIHOST_D1P 13G PK0 VDD12DSI
12G PJ11 VSSDSI 13H PJ10 DSIHOST_CKN
12H PJ8 DSIHOST_CKP 13J PJ9 DSIHOST_D0N
12J PJ7 DSIHOST_D0P - - -

1.1.5 LQFP64 package

The LQFP64 is available on the STM32F7x2xx devices.

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 Hardware migration

1.2 Boot mode compatibility

The STM32F42xxx/F43xxx boot space is based on boot mode selection pins: BOOT0 and
BOOT1 while the STM32F7 Series boot space is based on BOOT0 and boot address option
bytes as described in Table 6.
For the STM32F74xxx/F75xxx devices, the boot base address supports any address in the
range from 0x0000 0000 to 0x2004 FFFF while the STM32F76xxx/F77xxx devices extend
the boot address to any address in the range from 0x0000 0000 to 0x2007 FFFF. The
STM32F7x2xx/F7x3xx devices allow to program any boot memory address from 0x0000
0000 to 0x3FFF FFFF.

Table 6. Boot mode selection comparison between the STM32F42xxx/F43xxx and

STM32F7 Series devices
STM32F7 Series

Boot mode selection

Boot address Boot space
BOOT
Option Bytes

BOOT_ADD0 Boot address defined by user option byte BOOT_ADD0[15:0]

0
[15:0] - ST programmed value: Flash on ITCM at 0x0020 0000

BOOT_ADD1 Boot address defined by user option byte BOOT_ADD1[15:0]

1
[15:0] - ST programmed value: system bootloader at 0x0010 0000

STM32F42xxx/F43xxx

Boot mode
selection Pins Boot Mode Aliasing
BOOT1 BOOT0
Main Flash
x 0 Main Flash memory is selected as the boot space at 0x0800 0000
memory
System
0 1 System memory is selected as the boot space at 0x1FFF 0000
memory

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Hardware migration

1.3 System bootloader

The system bootloader is located in the system memory, programmed by ST during the
production. It is used to reprogram the Flash memory using one of the following serial
interfaces.
Table 7 shows the supported communication peripherals by the system bootloader.

Table 7. STM32F42xxx/F43xxx and STM32F7 Series bootloader communication

peripherals
System bootloader
STM32F42xxx/F43xxx I/O pin STM32F7 Series I/O pin
peripherals

DFU USB OTG FS (PA11 / PA12) in device mode

USART1 PA9 / PA10
USART3 PB10 / PB11 and PC10 / PC11
CAN2 PB5 / PB13
CAN1 in STM32F72xxx/F73xxx PB8/PB9
I2C1 NA PB6 / PB9
I2C2 NA PF0 / PF1
I2C3 NA PA8 / PC9

SPI1 NA PA4 / PA5 / PA6 / PA7

SPI2 NA PI0 / PI1 /PI2/ PI3

SPI4 NA PE11 / PE12 / PE13 / PE14

By default, in the STM32F7 Series devices, when the boot from system bootloader is
selected, the code is executed from the ITCM interface. It could be reprogrammed by option
byte executed from the AXIM interface. For more details on system bootloader refer to
AN2606.

16/39 DocID027558 Rev 3

 Peripheral migration

2 Peripheral migration

2.1 STM32 product cross-compatibility

The STM32 series embed a set of peripherals which can be classed in three categories:
• The first category is for the peripherals which are by definition common to all products.
Those peripherals are identical, so they have the same structure, registers and control
bits. There is no need to perform any firmware change to keep the same functionality at
the application level after migration. All the features and behavior remain the same.
• The second category is for the peripherals which are shared by all STM32 products but
have only minor differences (in general to support new features), so the migration from
one product to another is very easy and does not need any significant new
development effort.
• The third category is for peripherals which have been considerably changed from one
product to another (new architecture, new features...). For this category of peripherals,
the migration will require a new development at application level.
• The SW compatibility mentioned in the Table 8 only refers to the register description for
"low level" drivers.
The Cube Hardware Abstraction Layer (HAL) is compatible between the
STM32F42xxx/F43xxx and STM32F7 Series devices.
Table 8 shows the STM32 peripheral compatibility between the STM32F42xxx/F43xxx and
STM32F7 Series devices.

Table 8. STM32 peripheral compatibility analysis between the STM32F42xxx/F43xxx and

STM32F7 Series devices
STM32F42xxx STM32F74xxx STM32F76xxx STM32F72xxx
Peripherals Compatibility
/F43xxx /F75xxx /F77xxx /F73xxx

- - - - SW Comments
Flash memory in
2048 1024 2048 512
Kbyte
256
320 512 256
System (115+16+64+ - -
(240+16+64) (386+16+128) (176+16+64)
SRAM 64)
(Kbyte)
Instruction NA 16 16 16
Backup 4 4 4 4
GP 10 10 10 10 Yes -
Advanced
2 2 2 Yes -
Timers control
Basic 2 2 2 Yes -
Low-power NA 1 1 NA -

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38
Peripheral migration

Table 8. STM32 peripheral compatibility analysis between the STM32F42xxx/F43xxx and

STM32F7 Series devices (continued)
STM32F42xxx STM32F74xxx STM32F76xxx STM32F72xxx
Peripherals Compatibility
/F43xxx /F75xxx /F77xxx /F73xxx

Quad-SPI No Yes NA -
3/3 (simplex)
6/2 (full 4/3 (simplex) No/
SPI / I2S 4/3 (simplex) I2S compatible.
duplex) 6/3 (simplex)(1) Yes
5/3 (simplex)(2)
Programmable
I2C 3 4 3 No clock source for
STM32F7 Series
Additional features
USART/
4/4 4/4 4/4 No on STM32F7
UART
Series
Communication interfaces

Dedicated
USB OTG VDDUSB
Yes Yes Yes No
FS More endpoints on
STM32F7 Series
More endpoints
and host channels
USB OTG
Yes Yes Yes No with an embedded
HS
HS PHY in the
STM32F7x3 line
CAN 2 2 3 1 Yes -
SAI 1 2 Yes -
New clock source
for SDMMC1 on
SDIO/ STM32F7 Series
Yes Yes 2x 2x Yes
SDMMC1 with dedicated
supply for SDM-
MC2
SPDIFRX No 4 inputs NA NA -
RNG Yes Yes Yes Yes -
FMC memory con-
Yes Yes Yes Yes -
troller
Ethernet Yes Yes NA Yes -
MDIOS No No Yes NA NA -
HDMI-CEC No Yes NA NA -
DCMI Yes Yes NA Yes -
WWDG Yes Yes Yes Yes -
IWDG Yes Yes Yes Yes -
Additional features
CRC Yes Yes Yes Yes on STM32F7
Series
LCD-TFT No | Yes(3) Yes NA Yes -

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 Peripheral migration

Table 8. STM32 peripheral compatibility analysis between the STM32F42xxx/F43xxx and

STM32F7 Series devices (continued)
STM32F42xxx STM32F74xxx STM32F76xxx STM32F72xxx
Peripherals Compatibility
/F43xxx /F75xxx /F77xxx /F73xxx

New feature on
DSI-HOST No No Yes NA NA STM32F7x9xx/
Fx8xx
New feature on
JPEG No No Yes NA NA STM32F76xxx/
F77xxx
DMA DMA1-DMA2 (8 stream each) Yes -
Chrom-ART-Acc
Yes Yes NA Yes -
(DMA2D)
Crypto Yes Yes Yes (AES256) Yes -
Hash Yes Yes NA Yes -
140 in
STM32F7x2xx
GPIO Up to 168 Up to 168 Yes -
138 in
STM32F7x3xx
New feature on
DFSDM1 No No 4 filters NA NA STM32F76xxx/
F77xxx

12 bits 3 3 3
ADC Timer Trigger
ADC Number of Yes
16|24 16|24 16|24 not compatible
channels

12 bits Yes Yes Yes

DAC Number of Yes -
2 2 2
channels
New EXTI line for
EXTI Yes Yes Yes Yes
LPTIM1
New LSE drive
RCC Yes Yes Yes Yes
modes.
Additional features
RTC Yes Yes Yes Yes on STM32F7
Series
New wakeup pins
with configurable
PWR Yes Yes Yes Yes
polarity on
STM32F7 Series
SYSCFG Yes Yes Yes Yes -
1. SPI / I2S: 4/3 for 100 pin package and 6/3 for other packages.
2. SPI / I2S: 3/3 for 64 pin package, 4/3 for 100 pin package and 5/3 for other packages.
3. LCD - TFT:
- No: not available for the STM32F437xx devices.
- Yes: available for the STM32F439xx devices.

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38
Peripheral migration

2.2 Memory mapping

Table 9 presents the peripheral address mapping differences between the
STM32F42xxx/F43xx and STM32F7 Series devices.

Table 9. IP bus mapping differences between the STM32F42xxx/F43xxx and

STM32F7 Series devices
STM32F42xxx STM32F74xxx STM32F76xxx STM32F72xxx
/F43xxx /F75xxx /F77xxx /F73xxx
Peripheral Bus
Base address Base address Base address

Quad-SPI control register AHB3 NA 0xA000 1000 - 0xA0001FFF

SAI2 APB2 NA 0x4001 5C00 - 0x4001 5FFF
HDMI-CEC NA 0x4000 6C00 - 0x4000 6FFF NA
I2C4 NA 0x4000 6000 - 0x4000 63FF NA
0x4000 4000 -
I2S3ext NA
0x4000 43FF
APB1
SPDIFRX NA 0x4000 4000 - 0x4000 43FF NA
0x4000 3400 -
I2S2ext NA
0x4000 37FF
LPTIM1 NA 0x4000 2400 - 0x4000 27FF
USB OTG PHY HS 0x4001 7C00 -
APB2 NA NA NA
controller 0x4001 7FFF(1)
SDMMC2 APB2 NA NA 0x4001 1C00 - 0x4001 1FFF
0x4001 6C00 -
DSI-HOST APB2 NA NA NA
0x4001 73FF
0x5005 1000 -
JPEG AHB2 NA NA NA
0x5005 1FFF
0x4000 3400 -
CAN3 APB1 NA NA NA
0x4000 37FF
0x4001 7400 -
DFSDM1 APB2 NA NA NA
0x4001 77FF
0x4001 7800 -
MDIOS APB2 NA NA NA
0x4001 7BFF
1. Only for the STM32F7x3xx devices.

2.3 Flash memory

Table 10 presents the differences between the Flash memory interface of the
STM32F42xxx/F43xxx and STM32F7 Series devices.
The STM32F74xxx/F75xxx devices instantiate a different Flash module both in terms of
architecture and interface. For more information on the programming, erasing and
protection of the STM32F74xxx/F75xxx Flash memory, refer to the STM32F74xxx and
STM32F75xxx reference manual (RM0385).

20/39 DocID027558 Rev 3

 Peripheral migration

For more information on programming, erasing and protection of the STM32F76xxx/F77xxx

Flash memory, refer to the STM32F76xxx and STM32F77xxx reference manual (RM0410).
For more information on programming, erasing and protection of the STM32F72xxx/F73xxx
Flash memory, refer to the STM32F72xxx and STM32F73xxx reference manual (RM0431).

Table 10. Flash memory differences between the STM32F42xxx/F43xxx

and STM32F7 Series devices
STM32F42xxx STM32F74xxx STM32F76xxx STM32F72xxx
Flash
/F43xxx /F75xxx /F77xxx /F73xxx

0x0800 0000 - 0x080F 0x0800 0000 - 0x080F

0x0800 0000 – 0x081F 0x0800 0000 -
FFFF FFFF
FFFF 0x0807 FFFF
(on AXIM interface) (on AXIM interface)
– Up to 2 Mbytes
– configurable in 1 (or
2) bank (s)
In single bank:
– 4 sectors of 32
– Up to 1 Mbyte Kbytes – Up to 512 Kbytes
Main/program – Up to 2 Mbytes – Split in 1 bank – 1 sector of 128 – Split in 1 bank
memory – Split in 2 banks – 4 sectors of Kbytes – 4 sectors of 16
– 4 sectors of 16 Kbytes 32 Kbytes – 7 sectors of 256 Kbytes
– 1 sector of 64 Kbytes – 1 sector of Kbytes – 1 sector of 64
– 6 sectors of 128 Kbytes In dual bank: Kbytes
128 Kbytes – 3 sectors of – Each bank is com- – 3 sectors of 128
256 Kbytes posed of: Kbytes
– 4 sectors of 16
Kbytes
– 1 sector of 64 Kbytes
– 7 sectors of 128
Kbytes
– 256 bit wide data
read in single Bank
– 128 bit wide data read
– 256 bit wide data mode – 128 bit wide data
Features – Read while Write
read – 128 bit wide data read
(RWW)
read in dual Bank
mode
Up to 8 (depending on
Wait State the supply voltage and Up to 9 (depending on the supply voltage and frequency)
frequency)
One time pro-
grammable 512 OTP bytes 1024 OTP bytes 528 OTP bytes
(OTP)
Flash interface
0x4002 3C00 - 0x4002 3FFF
register

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38
Peripheral migration

Table 10. Flash memory differences between the STM32F42xxx/F43xxx

and STM32F7 Series devices (continued)
STM32F42xxx STM32F74xxx STM32F76xxx STM32F72xxx
Flash
/F43xxx /F75xxx /F77xxx /F73xxx

0x1FFF C000 - 0x1FFF

Base C00F 0x1FFF 0000 - 0x1FFF 001F
address 0x1FFE C000 - 0x1FFE (on AXIM interface)
C00F
– Bit 31
IWDG_STOP
– Bit 31 IWDG_STOP
– Bit 31 IWDG_STOP – Bit 30
– Bit 30
– Bit 31 SPRMOD – Bit 30 IWDG_STDBY IWDG_STDBY
IWDG_STDBY
– Bit 30 DB1M – Bit 29 nDBANK – Bits 29:24
– Bits 29:24 Reserved
– Bit 28 nDBOOT Reserved
– Bits 29:28 Reserved – Bits 27:16
Option – Bits 23:16
– Bits 27:16 nWRP[11:0] – Bits 23:16
bytes nWRP[7:0]
nWRP[11:0] – Bits 15:8 RDP[7:0] nWRP[7:0]
– Bits 15:8 RDP[7:0]
FLASH_ – Bits 15:8 RDP – Bits 7:4 USER – Bits 15:8 RDP[7:0]
– Bits 7:4 USER
OPTCR – Bits 7:5 USER - Bit 7: – Bits 7:4 USER
register - Bit 7:
- Bit 7: nRST_STDBY nRST_STDBY - Bit 7:
nRST_STDBY
- Bit 6: nRST_STOP - Bit 6: nRST_STOP nRST_STDBY
- Bit 6: nRST_STOP
- Bit 5: WDG_SW - Bit 5: IWDG_SW - Bit 6:
- Bit 5: IWDG_SW
– Bit 4 BFB2 – Bit 4: WWDG_SW nRST_STOP
– Bit 4: WWDG_SW - Bit 5: IWDG_SW
– Bits 3:2 BOR_LEV – Bits 3:2
– Bits 3:2 – Bit 4: WWDG_SW
– Bit 1 OPTSTRT BOR_LEV[1:0]
BOR_LEV[1:0]
– Bit 0 OPTLOCK – Bit 1 OPTSTRT – Bits 3:2
– Bit 1 OPTSTRT BOR_LEV[1:0]
– Bit 0 OPTLOCK
– Bit 0 OPTLOCK – Bit 1 OPTSTRT
– Bit 0 OPTLOCK
– Read protection – Read protection
(RDP) (RDP)
Memory – Write protections – Read protection (RDP) – Write protections
protection – Proprietary code – Write protections – Proprietary code
readout protection readout protection
(PCROP) (PCROP)

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 Peripheral migration

2.4 Embedded Flash memory

The main memory and information block organization are shown in Table 11.

Table 11. Flash module 1 Mbyte single bank organization (STM32F7 Series)
Bloc base addresses on Block base addresses
Block Name Sector size
AXIM interface on ITCM interface

STM32 STM32 STM32

F74xxx STM32 F74xxx STM32 F74xxx/ STM32
/F75xxx F72xxx /F75xxx F72xxx F75xxx F72xxx
/F76xxx /F73xxx /F76xxx /F73xxx /F76xxx /F73xxx
/F77xxx /F77xxx /F77xxx

0x0800 0000 - 0x0800 0000 - 0x0020 0000 - 0x0020 0000 - 32 16

Sector 0
0x0800 7FFF 0x0800 3FFF 0x0020 7FFF 0x0020 3FFF Kbytes Kbytes

0x0800 8000 - 0x0800 4000 - 0x0020 8000 - 0x0020 4000 - 32 16

Sector 1
0x0800 FFFF 0x0800 7FFF 0x0020 FFFF 0x0020 7FFF Kbytes Kbytes
0x0801 0000 - 0x0800 8000 - 0x0021 0000 - 0x0020 8000 - 32 16
Sector 2
0x0801 7FFF 0x0800 BFFF 0x0021 7FFF 0x0020 BFFF Kbytes Kbytes

Main 0x0801 8000 - 0x0800 C000 - 0x0021 8000 - 0x0020 C000 - 32 16

Sector 3
memory 0x0801 FFFF 0x0800 FFFF 0x0021 FFFF 0x0020 FFFF Kbytes Kbytes
block 0x0802 0000 - 0x0801 0000 - 0x0022 0000 - 0x0021 0000 - 128 64
Sector 4
0x0803 FFFF 0x0801 FFFF 0x0023 FFFF 0x0021 FFFF Kbytes Kbytes
0x0804 0000 - 0x0802 0000 - 0x0024 0000 - 0x0022 0000 - 256 128
Sector 5
0x0807 FFFF 0x0803 FFFF 0x0027 FFFF 0x0023 FFFF Kbytes Kbytes
0x0808 0000 - 0x0804 0000 - 0x0028 0000- 0x0024 0000 - 256 128
Sector 6
0x080B FFFF 0x0805 FFFF 0x002B FFFF 0x0025 FFFF Kbytes Kbytes
0x080C 0000 - 0x0806 0000 - 0x002C 0000 - 0x0026 0000 - 256 128
Sector 7
0x080F FFFF 0x0807 FFFF 0x02F FFFF 0x0027 FFFF Kbytes Kbytes

System 0x1FF0 0000 - 0x1FF0 0000 - 0x0010 0000- 0x0010 0000- 60 30

memory 0x1FF0 EDBF 0x1FF0 76D7 0x0010 EDBF 0x0010 76D7 Kbytes Kbytes
Information 0x1FF0 F000 - 0x1FF0 7800- 0x0010 F000 - 0x0010 7800 - 1024 528
block OTP
0x1FF0 F41F 0x1FF0 7A0F 0x0010 F41F 0x0010 7A0F bytes bytes
Option 32
0x1FFF 0000 - 0x1FFF 001F -
bytes bytes

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38
Peripheral migration

2.5 Flexible memory controller (FMC)

Table 12 presents the FMC differences between the STM32F42xxx/F43xxx and STM32F7
Series devices.

Table 12. FMC differences between the STM32F42xxx/F43xxx and STM32F7 Series
devices
FMC STM32F42xxx/F43xxx STM32F7 Series

– SRAM
– NOR/NAND memories – SRAM
– PSRAM – NOR/NAND memories
External memory interfaces – Two banks of NAND Flash – PSRAM
memory with ECC hardware – NAND Flash memory with
– 16-bit PC Card compatible ECC hardware
devices
Data bus width 8-,16- or 32-bit
Bank1
NOR/PSRAM/SRAM NOR/PSRAM/SRAM
4×64 Mbytes
Bank2
Reserved
4×64 Mbytes
NAND Flash memory
Bank3
NAND Flash memory
FMC Bank 4×64 Mbytes
memory mapping Bank4
PC Card Reserved
4×64 Mbytes
SDRAM bank1
4×64 Mbytes
SDRAM SDRAM
SDRAM bank2
4×64 Mbytes
NOR/PSRAM/SRAM SDRAM bank1
256 Mbytes 256 Mbytes
NAND bank1 SDRAM bank2
256 Mbytes 256 Mbytes
SDRAM bank1 NAND bank3
Memory mapping swap: 256 Mbytes 256 Mbytes
(SYSCFG_MEMRMP) SDRAM bank2
Reserved
Bits 11:10 SWP_FMC[1:0] = 01b 256 Mbytes
Reserved Reserved
NAND bank2 NOR/PSRAM/SRAM
256 Mbytes 256 Mbytes
PC card
Reserved
256 Mbytes

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 Peripheral migration

2.6 Interrupt vectors

Table 13 presents the interrupt vector differences between the STM32F42xxx/F43xxx and
STM32F7 Series devices.

Table 13. Interrupt vector differences between the STM32F42xxx/F43xxx and

STM32F7 Series devices
Position STM32F42xxx/F43xxx STM32F74xxx/F75xxx STM32F76xxx/F77xxx STM32F72xxx/F73xxx

91 NA SAI2
92 NA Quad-SPI
93 NA LPTIM1
94 NA HDMI-CEC NA
95 NA I2C4_EV NA
96 NA I2C4_ER NA
97 NA SPDIFRX NA
98 NA NA DSIHOST NA
99 NA NA DFSDM1_FLT0 NA
100 NA NA DFSDM1_FLT1 NA
101 NA NA DFSDM1_FLT2 NA
102 NA NA DFSDM1_FLT3 NA
103 NA NA SDMMC2 SDMMC2
104 NA NA CAN3_TX NA
105 NA NA CAN3_RX0 NA
106 NA NA CAN3_RX1 NA
107 NA NA CAN3_SCE NA
108 NA NA JPEG NA
109 NA NA MDIOS NA

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38
Peripheral migration

2.7 External interrupt lines (EXTI)

Table 14 presents the EXTI line differences between the STM32F42xxx/F43xxx and
STM32F7 Series devices.

Table 14. EXTI line differences between the STM32F42xxx/F43xxx and

STM32F7 Series devices
EXTI line STM32F42xxx/F43xxx STM32F74xxx/F75xxx STM32F76xxx/F77xxx STM32F72xxx/73xxx

0 to 15 16 external interrupt lines

16 PVD output
17 RTC alarm event
18 USB OTG FS wakeup event
19 Ethernet wakeup event NA
20 USB OTG HS (configured in FS) wakeup event
21 RTC tamper and TimeStamp events
22 RTC wakeup event
23 NA LPTIM1 asynchronous event
MDIO slave asynchro-
24 NA NA NA
nous event

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 Peripheral migration

2.8 RCC
Table 15 presents the main differences related to the RCC (Reset and Clock Controller)
between the STM32F42xxx/F43xxx and STM32F7 Series devices.

Table 15. RCC differences between the STM32F42xxx/F43xxx and

STM32F7 Series devices
STM32F74xxx/F75xxx/
STM32F42xxx/F43xxx STM32F7x3xx
F76xxx/F77xxx/F7x2xx
Peripherals
Clock sources

USB OTG FS – PLL48MHz derived from – PLL48MHz derived from

main PLL VCO (PLLQ main PLL VCO (PLLQ Clock)
RNG Clock) – PLLSAI VCO (PLLSAI clock)
– PLL48CLK
SDIO/SDMMC1 – PLL48CLK
– SYSCLK
– System clock (SYSCLK)
– APB1 or APB2 clock – HSI clock
U(S)ARTs
(PCLK1 or PCLK2) – LSE clock
– APB1 or APB2 clock (PCLK1 or PCLK2)
– System clock (SYSCLK)
I2Cs – APB1 clock (PCLK1) – HSI clock
– APB1 or APB2 clock (PCLK1 or PCLK2)
– PLLI2S
I2S
– External clock mapped on I2S_CKIN pin
– PLLI2S_Q
SAI1 – PLLSAI_Q
– External clock mapped on the I2S_CKIN pin.
– PLLI2S_Q
SAI2 NA – PLLSAI_Q
– External clock mapped on the I2S_CKIN pin.
LTDC – PLLSAI_R NA
– LSI clock
– LSE clock
LPTIM1 NA
– HSI clock
– APB1 clock (PCLK1)
The STM32F7x3xx devices embed
an USB OTG PHY HS. The PHY
HS has two PLLs: PLL1 and PLL2.
The PLL1 allows to output 60 MHz
USB OTG HS – 24 to 60 MHz to external PHY used as an input for PLL2 which
itself allows to generate the 480
Mbps in the USB OTG High Speed
mode.
The PLL1 has as input HSE clock.
ETHERNET MAC – 25 to 50 MHz external PHY NA

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38
Peripheral migration

Table 15. RCC differences between the STM32F42xxx/F43xxx and

STM32F7 Series devices (continued)
STM32F74xxx/F75xxx/
STM32F42xxx/F43xxx STM32F7x3xx
F76xxx/F77xxx/F7x2xx
Peripherals
Clock sources

SPDIFRX NA – PLLI2SP VCO NA

– LSE clock
HDMI-CEC NA – HSI clock divided by NA
488
– LSE clock
RTC – LSI clock
– HSE clock divided by 32
IWDG LSI
Configurable LSE drive in RCC_BDCR register: LSEDRV[1:0]:
– 00: Low drive
LSE NA – 10: Medium low drive
– 01: Medium high drive
– 11: High drive
RCC dedicated – RCC_DKCFGR1
clock configuration – RCC_DCKCFGR
– RCC_DKCFGR2
register

2.8.1 Maximum frequency according to power scale parameter

Table 16 shows the comparison of maximum frequency that the MCU can reach between
the STM32F42xxx/F43xxx and STM32F7 Series devices.

Table 16. Maximum frequency comparison between the STM32F42xxx/F43xxx and

STM32F7 Series devices
F4 max F7 max
Symbol Parameter Conditions Unit
Freq Freq

Power scale 3 (Over-drive OFF) 120 144

Over-drive OFF 144 168
Internal AHB clock Power scale 2
fHCLK Over-drive ON 168 180
frequency
Over-drive OFF 168 180
Power scale 1
Over-drive ON 180 216 MHz

Internal APB1 clock Over-drive OFF 42 45

fPCLK1
frequency Over-drive ON 45 54

Internal APB2 clock Over-drive OFF 84 90

fPCLK2
frequency Over-drive ON 90 108

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2.9 PWR
Table 17 presents the PWR controller differences between the STM32F42xxx/F43xxx and
STM32F7 Series devices.

Table 17. PWR differences between the STM32F42xxx/F43xxx and STM32F7 Series
devices
PWR STM32F42xxx/F43xxx STM32F7 Series

– Independent USB transceivers

supply:
VDDUSB: range is from 3.0 V to 3 6 V and is
completely independent from VDD or VDDA
Power supplies NA
– VDDSDMMC2 supply: range is from 1.7 V to
3.6 V and it can be independent from VDD
(only on STM32F76xxx/F77xxx and
STM32F72xxx/F73xxx devices).
– WKUP pin with configurable polarity on rising
or falling edge:
– PA0
– WKUP pin PA0 on rising – PA2
edge
– PC1
– RTC event (RTC ALARM,
Standby mode – PC13
Tamper event,Time stamp
wakeup sources – PI8
event)
– IWDG reset – PI11
– External reset in NRST pin – RTC event (RTC ALARM, tamper event, time
stamp event)
– IWDG reset
– External reset in NRST pin

PWR_CR PWR_CR1
PWR_CSR PWR_CSR1
PWR_CR2
PWR_CSR2
Power control Comment :
registers – PWR_CR2:
NA Used to configure the wakeup pin polarity, or to
clear the wakeup pins flags.
– PWR_CSR2:
Used either to enable the wakeup pins or used to
detect an event on the wakeup pin

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2.10 RTC
Table 18 shows the RTC comparison between the STM32F42xxx/F43xxx and STM32F7
Series devices.

Table 18. RTC comparison between the STM32F42xxx/F43xxx and STM32F7 Series
devices
RTC STM32F42xxx/F43xxx STM32F7 Series

Calendar in BCD Yes

Yes
Calendar sub seconds access
Resolution down to RTCCLK
Calendar synchronization on-
Yes
the-fly
Alarm on calendar 2 w/ sub second
Calibration window: 8s/16s/32s
Calendar calibration Calibration step: 3.81ppm/1.91ppm/0.95 ppm
Range [-480ppm +480ppm]
Synchronization on mains Yes
Periodic wakeup Yes
Yes
Timestamp
Sec, Min, Hour, Date, Sub seconds
Timestamp on VBAT switch No Yes
2 pins/ 2 events 3 pins/ 3 events
Tamper
Edge or level detection with configurable filtering
External interrupt and trigger
No Yes
with filtering
32-bit backup registers 20 32
RTC in VBAT Yes

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2.11 U(S)ART
The U(S)ART is not SW compatible with the STM32F42xxx/F43xxx devices and includes
new additional features detailed in Table 19.

Table 19. U(S)ART differences between the STM32F42xxx/F43xxx and

STM32F7 Series devices
U(S)ART STM32F42xxx/F43xxx STM32F7 Series

UART/USART 4/4
– Up to 27 Mbit/s
Baud rate – Up to 4x11.25 Mbit/s – (clock frequency is 100 MHz and
oversampling is by 8)
– Dual clock domain:
Convenient baud rate programming
Clock – Single clock domain
independent from the PCLK
reprogramming
– Word length: Programmable (7, 8 or 9
– Word length: Programmable (8 or 9 bits)
Data
bits) – Programmable data order with MSB-
first or LSB-first shifting
interrupt – 10 interrupt sources with flags – 14 interrupt sources with flags
– LIN mode
– SPI Master
– IrDA SIR ENDEC block
– Hardware flow control (CTS/RTS)
– Continuous communication using DMA
– Multiprocessor communication
– Single-wire half-duplex communication
Support the T=0 and T=1 asynchronous
Smartcard mode T = 0 and T= 1 has to
protocols.
Features be implemented by software.
Number of stop bits: 0.5, 1, 1.5, 2
Number of stop bits: 0.5, 1, 1.5, 2
smartcard operation.
– Support for ModBus communication
- Timeout feature
- CR/LF character recognition
NA – Receiver timeout interrupt
– Auto baud rate detection
– Driver Enable
– Swappable Tx/Rx pin configuration
U(S)ART
– Software not compatible
registers

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2.12 I2C
The STM32F42xxx/F43xxx and STM32F7 Series devices share the same features on the
I2C, but the software and register configuration are not compatible.
Table 20 presents the I2C differences between the STM32F42xxx/F43xxx and STM32F7
Series devices.

Table 20. I2C differences between the STM32F42xxx/F43xxx and STM32F7 Series devices
STM32F74xxx/F75xxx/
I2C STM32F42xxx/F43xxx STM32F72xxx/F73xxx
F76xxx/F77xxx

Instances – x3 (I2C1, I2C2, I2C3) – x4 (I2C1, I2C2, I2C3, I2C4) – x3 (I2C1, I2C2, I2C3)
– 7-bit and 10-bit addressing mode
– SMBus
– Standard mode (up to 100 kbit/s)
Features – Fast-mode (up to 400 kbit/s)
- – Fast-mode plus (up to 1 Mbit/s)(1)
– Single clock source – Programmable clock source
I2C registers – Software not compatible.
1. On the STM32F77xxx/F76xxx/F72xxx/F73xxx devices, the I2C I/Os support the 20mA drive needed in Fast-mode Plus.

2.13 SPI
The STM32F42xxx/F43xxx and STM32F7 Series implement different features on the SPI.
Table 21 presents the SPI differences between the STM32F42xxx/F43xxx and STM32F7
Series devices.

Table 21. SPI differences between the STM32F42xxx/F43xxx and STM32F7 Series devices
STM32F74xxx/F75xxx/
SPI STM32F42xxx/F43xxx STM32F72xxx/F73xxx
F76xxx/F77xxx

Instances x6 x4 | x6 x3 | x5
Features SPI + I2S
Fixed, configurable to 8 or
Data size Programmable from 4 to 16-bit
16 bits
Tx & Rx 16-bit buffers Two 32-bit embedded Rx and Tx FIFOs
Data buffer
(single data frame) (up to 4 data frames)
No
Data packing Yes
(16-bit access only)
SPI TI
SPI TI mode
Mode SPI Motorola mode
SPI Motorola mode
NSSP mode
Speed Up to 45 Mbit/s Up to 54 Mbit/s
SPI registers Software not compatible

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2.14 CRC
The STM32F7 Series devices implements a similar CRC (Cyclic redundancy check)
calculation unit as the STM32F42xxx/F43xxx devices.
Table 22 presents the CRC differences between the STM32F42xxx/F43xxx and STM32F7
Series devices.

Table 22. CRC differences between the STM32F42xxx/F43xxx and STM32F7 Series
devices
CRC STM32F42xxx/F43xxx STM32F7 Series

– Single input/output 32-bit data register

– CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
– General-purpose 8-bit register (can be used for temporary storage)
– Fully programmable polynomial with
Features programmable size (7, 8, 16, 32bits)
– Uses CRC-32 (Ethernet) polynomial: – Handles 8-,16-, 32-bit data size
0x4C11DB7 – Programmable CRC initial value
– Handles 32-bit data size – Input buffer to avoid bus stall during
calculation
– Reversibility option on I/O data
– Software compatible.
CRC registers
– STM32F7 Series includes new features.

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2.15 USB OTG

Table 23 presents the USB OTG differences between the STM32F42xxx/F43xxx and
STM32F7 Series devices.

Table 23. USB OTG differences between the STM32F42xxx/F43xxx and

STM32F7 Series devices
USB STM32F42xxx/F43xxx STM32F7 Series

– Universal Serial Bus revision 2.0

– Full support for the USB On-The-Go (USB OTG).
FS mode: FS mode:
– 1 bidirectional control endpoint – 1 bidirectional control endpoint
– 3 IN endpoints (bulk, interrupt, – 5 IN endpoints (bulk, interrupt,
isochronous) isochronous)
– 3 OUT endpoints (bulk, interrupt, – 5 OUT endpoints (bulk, interrupt,
isochronous isochronous)
– HS mode:(1)
Features
HS mode: – 9 bidirectional endpoints
– 6 bidirectional endpoints (including (including EP0)
EP0) – 16 host channels with periodic
– 12 host mode channels OUT support
– USB internal connect/disconnect feature with an internal pull-up resistor on
the USB D + (USB_DP) line.
– Independent VDDUSB power
NA supply allowing lower VDDCORE
while using USB.
FS mode:
FS mode:
– 1.25 Kbytes data FIFOs
– 1.25 Kbytes data FIFOs
– Management of up to 6 Tx FIFOs
– Management of up to 4 Tx FIFOs (1 for
Buffer memory (1 for each IN end point) + 1 Rx
each IN end point) + 1 Rx FIFO.
FIFO.
HS mode:
HS mode:
– 4 Kbytes total RAM
– 4 Kbytes total RAM
FS mode:
FS mode:
– USB suspend and resume
– USB suspend and resume
– Link power management (LPM)
Low-power modes
support
HS mode:
HS mode:
– No LPM supported
– Yes LPM supported
Configuration – SW not compatible
1. In the STM32F42xxx/43xxx and STM32F74xxx/F75xxx/F76xxx/F77xxx/F7x2xx devices, the HS mode is
supported via ULPI interface.
In the STM32F7x3xx devices, the HS mode is supported based on an embedded PHY high speed.

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2.16 ADC
The STM32F7 Series devices embed the same ADC peripherals with the same features
except for external triggers in regular and injected channels.
Table 24 and Table 25 present the differences of external trigger for regular channels and
injected channels between the STM32F42xxx/F43xxx and STM32F7 Series devices.

2.16.1 External trigger for regular channels

Table 24. External trigger for regular channel differences between the
STM32F42xxx/F43xxx and STM32F7 Series devices
Source
Type EXTSEL[3:0]
STM32F42xxx/F43xxx STM32F7 Series

0000 TIM1_CH1 event TIM1_CC1 event

0001 TIM1_CH2 event TIM1_CC2 event
0010 TIM1_CH3 event TIM1_CC3 event
0011 TIM2_CH2 event TIM2_CC2 event
0100 TIM2_CH3 event TIM5_TRGO event
0101 TIM2_CH4 event TIM4_CC4 event
0110 TIM2_TRGO event TIM3_CC4
Internal signal
from on-chip 0111 TIM3_CH1 event TIM8_TRGO event
timers
1000 TIM3_TRGO event TIM8_TRGO(2) event
1001 TIM4_CH4 event TIM1_TRGO event
1010 TIM5_CH1 event TIM1_TRGO(2) event
1011 TIM5_CH2 event TIM2_TRGO event
1100 TIM5_CH3 event TIM4_TRGO event
1101 TIM8_CH1 event TIM6_TRGO event
1110 TIM8_TRGO event NA
External pin 1111 EXTI line11

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2.16.2 External trigger for injected channels

Table 25. External trigger for injected channel differences between the
STM32F42xxx/F43xxx and STM32F7 Series devices
Source
Type EXTSEL[3:0]
STM32F42xxx/F43xxx STM32F7 Series

0000 TIM1_CH4 event TIM1_TRGO event

0001 TIM1_TRGO event TIM1_CC4 event
0010 TIM2_CH1 event TIM2_TRGO event
0011 TIM2_TRGO event TIM2_CC1 event
0100 TIM3_CH2 event TIM3_CC4 event
0101 TIM3_CH4 event TIM4_TRGO event
0110 TIM4_CH1 event NA
Internal signal from
0111 TIM4_CH2 event TIM8_CC4 event
on-chip timers
1000 TIM4_CH3 event TIM1_TRGO(2) event
1001 TIM4_TRGO event TIM8_TRGO event
1010 TIM5_CH4 event TIM8_TRGO(2) event
1011 TIM5_TRGO event TIM3_CC3 event
1100 TIM8_CH2 event TIM5_TRGO event
1101 TIM8_CH3 event TIM3_CC1 event
1110 TIM8_CH4 event TIM6_TRGO event
External pin 1111 EXTI line15 NA

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 Conclusion

3 Conclusion

This application note is a useful complement to the datasheets and reference manuals,
which gives a simple guideline to migrate from an existing STM32F42xxx/F43xxx device to
a STM32F7 Series device.

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Revision history

4 Revision history

Table 26. Document revision history

Date Revision Changes

31-Mar-2015 1 Initial release.

Updated:
– Section 2.1: STM32 product cross-compatibility with a new
paragraph about software compatibility,
– Table 8: STM32 peripheral compatibility analysis between the
STM32F42xxx/F43xxx and STM32F7 Series devices for RNG,
29-May-2015 2
ADC, and DAC peripherals,
– Section 2.8.1: Maximum frequency according to power scale
parameter setting F7 max at 216 MHz, 108 MHz and 54 MHz in
over-drive ON conditions,
– Section 2.11: U(S)ART with baud rate up to 13.5 Mbit/s.
Updated whole document to address the STM32F7 Series devices.
Added:
– Section 1.1.2: LQFP208 package.
– Section 1.1.3: LQFP176 package.
– Section 1.1.4: TFBGA216 package.
Updated:
– Table 8: STM32 peripheral compatibility analysis between the
13-Feb-2017 3 STM32F42xxx/F43xxx and STM32F7 Series devices.
– Table 9: IP bus mapping differences between the
STM32F42xxx/F43xxx and STM32F7 Series devices.
– Table 10: Flash memory differences between the
STM32F42xxx/F43xxx and STM32F7 Series devices.
– Table 13: Interrupt vector differences between the
STM32F42xxx/F43xxx and STM32F7 Series devices.
– Table 14: EXTI line differences between the
STM32F42xxx/F43xxx and STM32F7 Series devices.

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AN4660

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