Unit6dspprocessor 140207205522 Phpapp02
Unit6dspprocessor 140207205522 Phpapp02
Unit6dspprocessor 140207205522 Phpapp02
BY
Prof L.S.Kalkonde
Department of Electronics & Telecommunication
Prof Ram Meghe College of Engineering & Technology,Badnera
Digital Signal Processor---- Definition
4. Our ears are sensitive to sound, our eyes are sensitive to light,
and so on.
7. Our brains not only analyze the information received, but also
make decisions using this data.
· Digitize these signals (i.e., convert them from analog to digital using an
analog-to-digital converter (ADC)), as shown in the diagram.
Why Do We Need Digital Signal Processors?
Why Do We Need Digital Signal Processors?
• Data Memory:
– Stores the information to be processed
• Compute Engine:
– Performs the math processing, accessing the program from the Program Memory and
the data from the Data Memory
• Input / Output:
– Serves a range of functions to connect to the outside world
Types of Architecture
Super/ Modified
Harvard Harvard Architecture
Architecture
Von
Neumann
Architecture
Von Neumann Architecture
Instruction
CPU
&
Data Data Bus
Harvard Architecture
Address
Address Bus
Bus
Program Data
Memory CPU Memory
Data Bus Data Bus
Which Architecture is Best Suited for DSP?
2. DSPs typically use Harvard architecture, although von Neuman DSPs also exist.
3. Many signal and image processing applications require fast, real-time machines.
4. The drawback to using a true Harvard architecture is that since it uses separate
program and data memories, it needs twice as many address and data pins on the chip
and twice as much external memory. Unfortunately, as the number of pins or chips
increases, so does the price.
Which Architecture is Best Suited for DSP?
An elegant solution:
Two (or more) separate buses for program and data are used internally.
In one clock cycle, the program information flows on the pins, and
In the second cycle, data follows on the same pins.
Program and data information is then routed onto separate internal program and
data buses. Such machines are called modified Harvard architecture processors
because
the internal architecture is Harvard
external architecture is von Neuman.
Also Multiple internal RAM/ROM cells for high-use instructions and data.
Fixed vs. Floating Point
• 16 bit CPU
• Can execute 40 to 120 Million Instructions Per Second
• 17×17 bit MAC
• 64k × 16 bit physical program memory address space
• 64k × 16 bit external data memory address space
• 64k × 16 bit external IO address space
• Programmable timer & PLL
• DMA interface
• 100/128/144 TQFP & BGA packages
Functional Units
• 40 bit ALU
• 2- 40 bit accumulators ACCA & ACCB
• Barrel shifter
• 17X17 bit multiplier
• 40 bit adder
• CSSU-Compare, Select & store unit
• Exponent Encoder
• Data Address generation
• Program & address generation unit
TMS32054XX
•Uses an advanced , Modified Harvard
architecture
•Maximizes processing power by providing
4 pairs
Bus Structure
3 Pairs 1 Pair
Data Memory Program Memory
ALU
• 40 Bit ALU
• Wide range of Arithmetic & Logic Operation in
single clock cycle.
• After ALU operation destination of result
– Accumulator or
– Memory
Accumulators
• 40 bit ACCA & ACCB
• To store result for ALU & Multiply/Add.
• Temporary storage for other.
Barrel Shifter
• The barrel shifter can produce a left shift of 0 to 31
bits and a right shift of 0 to 16 bits on the input data.
• The shift requirements are defined in
– the shift count field of the instruction, the shift count field
(ASM) of status register ST1, or
– In the temporary register T.
Multiplier/Adder Unit
• The multiplier/adder block consists of several elements:
2. Program Fetch
3.Decode
The opcode is decoded to determiine access operation
Instruction Pipelining in TMS320C54X Processors
4.Access
Operand address is loaded on data DAB – Data Address Bus. If 2nd operand
is required , then another address is loaded into CAB
5. Read
6.Execute
Perform the task specified by the instruction
Sr no Parameter DSP Processor GPP Processor
3 Operand fetched from Multiple operands are fetch simultaneously Operands are fetch sequentially
memory
4 Memories Separate program memory and data Normally no such separate memories are
memory present
5 On-chip/off-chip Program memory and data memory are Normally on-chip cache memory is present
memories present on-chip and expandable off-chip. .Main memory is off-chip.
6 Address generation Addresses are generated combinely by Program counter is incremented
DAGs and program sequencer. sequentially to generate addresses.
7 Address/data bus Address and data buses are not multiplexed. Address/data buses can be separate on the
multiplexing They are separate on chip as well as off chip. chip but usually multiplexed off-chip.
8 Computational units Three separate computational units: ALU is the main computational unit.
ALU,MAC and shifter.
9 Suitable for Array processing operations Genral purpose processing
10 Queuing/Pipelining Queuing is implemented through instruction Queuing is performed explicitly by queuing
register and instruction cache register for pipelining of instructions