LIST OF CONTENTS

CHAPTER NO CONTENTS PAGE NO

ABSTRACT (i)

LIST OF TABLE (ii)

LIST OF FIGURE (iii)

1. INTRODUCTION
2. BLOCK DIAGRAM
2.1 BLOCK DIAGRAM EXPLANATION
3. CIRCUIT DIAGRAM
4. SOFTWARE REQUIREMENT
4.1 KEIL COMPILER
4.1.1 FEATURES
4.2 EMBEDDED C
5. HARD WARE REQUIREMENT
5.1 8051 MIC ROCONTROLLER
5.2 POWER SUPPLY
5.3 KEYPAD
5.4 RELAY
5.5 RF MODULE WITH ENCODER & DECODER
5.6 CCTV CAMERA
5.7 MOTOR
6. ADVANTAGE
7. APPLICATION
8. CONCLUSION
9. REFERENCE

1
 ABSTRACT

The objective of this project is to provide security to the border which needs
surveilence without manpower. To achieve this, a wireless based Border security robot is
designed. This robot is composed of a mechanical body fitted with DC motors with an 8051
MCU along with CCTV. The CCTV camera monitors the location continuously and the data is
sent to the control station. The data’s can be seen with the help of video display unit or monitor.
According to the image from the CCTV we can control the position of the arms.

2
LIST OF TABLE

3
LIST OF FIGURE

4
 INTRODUCTION

The mission of border security is to detect and prevent the entry of terrorists, weapons of
mass destruction, and illegal aliens into the country, and to interdict drug smugglers and other
criminals along the border. To achieve this mission a wireless based Border security robot is
designed. This robot is composed of a mechanical body fitted with DC motors with an 8051
MCU along with CCTV. The CCTV camera monitors the location continuously and the data is
sent to the control station. The data’s can be seen with the help of video display unit or monitor.
According to the image from the CCTV we can control the position of the arms.

The traditional design used to have limited intelligence and mainly operated by human
operator. This system requires human power to monitor the status of the border; the messages are
transferred through half-duplex mode. i.e., this mode allows transmission in only one direction at
a time; if one device is sending, the other must simply receive data until it's time for it to
transmit.

5
BLOCK DIAGRAM:

Transmitter Unit:

Power
supply

8051
Micro
Controller Keypad

RF Encoder
Transmitter HT12E

6
Receiver Unit

Power
supply

Relay with Motor

RF Decoder 8051
ULN 2003A
Receiver HT 12D Micro
controller

CCTV
Relay with Motor
ULN 2003A

BLOCK DIAGRAM EXPLANATION:

This proposed system presents the construction and design of wireless based border

security robot. This system is composed of transmitter section and receiver section. The robot

monitors the border continuously with the help of CCTV (Closed Circuit Television Camera),

the camera transmits AV signals to receiver section.

In receiver section, the small video display unit is used to display the current status of the

location According to the video information from the CCTV, the control operation has to be

7
performed. Keypad module is interfaced with the controller for controlling the direction of the

robot via RF modules.

The controlling data’s are transferred wireless way from the receiver section to the

transmitter section with the help of encoding and decoding devices.

8
4. SOFTWARE REQUIREMENT

4.1 KEIL C Compiler

The Keil C51 C Compiler for the 8051 microcontroller is the most popular 8051 C
compiler in the world. It provides more features than any other 8051 C compiler available today.

The C51 Compiler allows you to write 8051 microcontroller applications in C that, once
compiled, have the efficiency and speed of assembly language. Language extensions in the C51
Compiler give you full access to all resources of the 8051.

The C51 Compiler translates C source files into relocatable object modules which contain
full symbolic information for debugging with the µVision Debugger or an in-circuit emulator. In
addition to the object file, the compiler generates a listing file which may optionally include
symbol table and cross reference information.

4.1.1 Features
 Nine basic data types, including 32-bit IEEE floating-point,
 Flexible variable allocation with bit, data, b data, I data, x data, and p
data memory types,
 Interrupt functions may be written in C,
 Full use of the 8051 register banks,
 Complete symbol and type information for source-level debugging,
 Use of AJMP and ACALL instructions,
 Bit-addressable data objects,
 Built-in interface for the RTX51 Real-Time Kernel,
 Support for dual data pointers on Atmel, AMD, Cypress, Dallas
Semiconductor, Infineon, Philips, and Triscend microcontrollers,
 Support for the Philips 8xC750, 8xC751, and 8xC752 limited instruction sets,

Support for the Infineon 80C517 arithmetic unit

9
4.2 EMBEDDED C

The C programming language is perhaps the most popular programming language for
programming embedded systems we mentioned other popular programming languages).Most C
programmers are spoiled because they program in environments where not only is there a
standard library implementation, but there are frequently a number of other libraries available for
use. The cold fact is, that in embedded systems, there rarely are many of the libraries that
programmers have grown used to, but occasionally an embedded system might not have a
complete standard library, if there is a standard library at all. Few embedded systems have
capability for dynamic linking, so if standard library functions are to be available at all, they
often need to be directly linked into the executable. Oftentimes, because of space concerns, it is
not possible to link in an entire library file, and programmers are often forced to "brew their
own" standard c library implementations if they want to use them at all. While some libraries are
bulky and not well suited for use on microcontrollers, many development systems still include
the standard libraries which are the most common for C programmers.

C remains a very popular language for micro-controller developers due to the code
efficiency and reduced overhead and development time. C offers low-level control and is
considered more readable than assembly. Many free C compilers are available for a wide variety
of development platforms. The compilers are part of an IDEs with ICD support, breakpoints,
single-stepping and an assembly window. The performance of C compilers has improved
considerably in recent years, and they are claimed to be more or less as good as assembly,
depending on who you ask. Most tools now offer options for customizing the compiler
optimization. Additionally, using C increases portability, since C code can be compiled for
different types of processors.

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5. HARDWARE REQUIREMENT

5.1 MICROCONTROLLER

The generic 8031 architecture sports a Harvard architecture, which contains two separate
buses for both program and data. So, it has two distinctive memory spaces of 64K X 8 size for
both program and data. It is based on an 8 bit central processing unit with an 8 bit Accumulator
and another 8 bit B register as main processing blocks. Other portions of the architecture include
few 8 bit and 16 bit registers and 8 bit memory locations.Each 8031 device has some amount of
data RAM built in the device for internal processing. This area is used for stack operations and
temporary storage of data.This base architecture is supported with onchip peripheral functions
like I/O ports, timers/counters, versatile serial communication port. So it is clear that this 8031
architecture was designed to cater many real time embedded needs.

The following list gives the features of the 8051 architecture:

 Optimized 8 bit CPU for control applications.

 Extensive Boolean processing capabilities.
 64K Program Memory address space.
 64K Data Memory address space.
 128 bytes of onchip Data Memory.
 32 Bi-directional and individually addressable I/O lines.
 Two 16 bit timer/counters.
 Full Duplex UART, On-chip clock oscillator.
 6-source / 5-vector interrupt structure with priority levels.
Now you may be wondering about the non mentioning of memory space meant for the
program storage, the most important part of any embedded controller. Originally this 8031
architecture was introduced with onchip, ‘one time programmable’ version of Program Memory
of size 4K X 8. Intel delivered all these microcontrollers (8051) with user’s program fused inside
the device. The memory portion was mapped at the lower end of the Program Memory area. But,

11
after getting devices, customers couldn’t change any thing in their program code, which was
already made available inside during device fabrication.

Figure 1 - Block Diagram of the 8031 Core

So, very soon Intel introduced the 8031 devices (8751) with re-programmable type of Program
Memory using built-in EPROM of size 4K X 8. Like a regular EPROM, this memory can be re-
programmed many times. Later on Intel started manufacturing these 8031 devices without any
onchip Program Memory.Now I go ahead giving more information on the important functional
blocks of the 8031.

5.1.1 DIFFERENCES BETWEEN MICROCONTROLLER AND MICROPROCESSOR:

 Microprocessors have many instructions for moving data from external memory to internal
memory. But microcontrollers have a few such instructions.
 Microprocessors have less bit handling instructions, but microcontrollers have many such
instructions.
 Microprocessors are concerned with rapid movement of code and data from external
memory. But Microcontroller is concerned with that of bits within the chip.

12
 Of course Microprocessor needs additional chips for memory, parallel port, timer etc and
microcontroller needs no such external ports.

8031

Figure 2 - 8031 Microcomputer Pinout Diagram

13
 Figure 3 - 8031 Microcomputer logic symbol

5.1.2 OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier
which can be configured for use as an onchip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the device from an external clock source,
XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no
requirements on the duty cycle of the external clock signal, since the input to the internal
clocking circuitry is through a divide-by two flip-flop, but minimum and maximum voltage high
and low time specifications must be observed.

5.1.3 8051 CLOCK

 8051 has an on-chip oscillator

 It needs an external crystal
 Crystal decides the operating frequency of the 8051

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5.1.4 IDLE MODE

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active.
The mode is invoked by software. The content of the on-chip RAM and all the special functions
registers remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset. It should be noted that when idle is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to
internal RAM in this event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction
following the one that invokes Idle should not be one that writes to a port pin or to external
memory.

5.1.5 POWER DOWN MODE

In the power down mode the oscillator is stopped, and the instruction that invokes power
down is the last instruction executed. The on-chip RAM and Special Function Registers retain
their values until the power down mode is terminated. The only exit from power down is a
hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset
should not be activated before VCC is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and stabilize.

5.1.6 8051 RESET

 RESET is an active High input

15
  When RESET is set to High, 8051 goes back to the poweron state
 Power-On Reset
 Push PB and active High on RST
 Release PB, Capacitor discharges and RST goes low
 RST must stay high for a min of 2 machine cycles

5.1.7 CENTRAL PROCESSING UNIT

The CPU is the brain of the microcontrollers reading user’s programs and executing the
expected task as per instructions stored there in. Its primary elements are an 8 bit Arithmetic
Logic Unit (ALU), Accumulator (Acc), few more 8 bit registers, B register, Stack Pointer (SP),
Program Status Word (PSW) and 16 bit registers, Program Counter (PC) and Data Pointer
Register (DPTR).

5.1.8 THE ACCUMULATOR

If worked with any other assembly language you will be familiar with the concept of an
accumulator register. The Accumulator, as its name suggests, is used as a general register to
accumulate the results of a large number of instructions. It can hold an 8-bit (1-byte) value and is
the most versatile register the 8052 has due to the sheer number of instructions that make use of

16
the accumulator. More than half of the 8052ís 255 instructions manipulate or use the
Accumulator in some way.

For example, if you want to add the number 10 and 20, the resulting 30 will be stored in
the Accumulator. Once you have a value in the Accumulator you may continue processing the
value or you may store it in another register or in memory.

5.1.9 THE "R" REGISTERS

The "R" registers are sets of eight registers that are named R0, R1, through R7. These
registers are used as auxiliary registers in many operations. To continue with the above example,
perhaps you are adding 10 and 20. The original number 10 may be stored in the Accumulator
whereas the value 20 may be stored in, say, register R4. To process the addition you would
execute the command:As mentioned earlier, there are four sets of ‘R’ registers, register bank 0,
1, 2, and 3. When the 8052 is first powered up, register bank 0 (addresses 00h through 07h) is
used by default. In this case, for example, R4 is the same as Internal RAM address 04h.
However, your program may instruct the 8052 to use one of the alternate register banks; i.e.,
register banks 1, 2, or 3. In this case, R4 will no longer be the same as Internal RAM address
04h. For example, if your program instructs the 8052 to use register bank 1, register R4 will now
be synonymous with Internal RAM address 0Ch. If you select register bank 2, R4 is synonymous
with 14h, and if you select register bank 3 it is synonymous with address 1Ch. The concept of
register banks adds a great level of flexibility to the 8052, especially when dealing with
interrupts (we'll talk about interrupts later). However, always remember that the register banks
really reside in the first 32 bytes of Internal RAM.

5.1.10 THE "B" REGISTER

The "B" register is very similar to the Accumulator in the sense that it may hold an 8-bit
(1-byte) value. The "B" register is only used implicitly by two 8052 instructions: MUL AB and
DIV AB. Thus, if you want to quickly and easily multiply or divide A by another number, you
may store the other number in "B" and make use of these two instructions.Aside from the MUL

17
and DIV instructions, the "B" register is often used as yet another temporary storage register
much like a ninth "R" register.

5.1.11 THE PROGRAM COUNTER (PC)

The Program Counter (PC) is a 2-byte address that tells the 8052 where the next
instruction to execute is found in memory. When the 8052 is initialized PC always starts at
0000h and is incremented each time an instruction is executed. It is important to note that PC
isn’t always incremented by one. Since some instructions are 2 or 3 bytes in length the PC will
be incremented by 2 or 3 in these cases.The Program Counter is special in that there is no way to
directly modify its value. That is to say, you can’t do something like PC=2430h. On the other
hand, if you execute LJMP 2430h you’ve effectively accomplished the same thing.It is also
interesting to note that while you may change the value of PC (by executing a jump instruction,
etc.) there is no way to read the value of PC. That is to say, there is no way to ask the 8052
"What address are you about to execute?" As it turns out, this is not completely true: There is one
trick that may be used to determine the current value of PC.

5.1.12 THE DATA POINTER (DPTR)

The Data Pointer (DPTR) is the 8052ís only user-accessible 16-bit (2-byte) register. The
Accumulator, "R" registers, and "B" register are all 1-byte values. The PC just described is a 16-
bit value but isn’t directly user-accessible as a working register.DPTR, as the name suggests, is
used to point to data. It is used by a number of commands that allow the 8052 to access external
memory. When the 8052 accesses external memory it accesses the memory at the address
indicated by DPTR.While DPTR is most often used to point to data in external memory or code
memory, many developers take advantage of the fact that it’s the only true 16-bit register
available. It is often used to store 2-byte values that have nothing to do with memory locations.

5.1.13 THE STACK POINTER (SP)

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 The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte)
value. The Stack Pointer is used to indicate where the next value to be removed from the stack
should be taken from. When you push a value onto the stack, the 8052 first increments the value
of SP and then stores the value at the resulting memory location. When you pop a value off the
stack, the 8052 returns the value from the memory location indicated by SP, and then decrements
the value of SP.This order of operation is important. When the 8052 is initialized SP will be
initialized to 07h. If you immediately push a value onto the stack, the value will be stored in
Internal RAM address 08h. This makes sense taking into account what was mentioned two
paragraphs above: First the 8051 will increment the value of SP (from 07h to 08h) and then will
store the pushed value at that memory address (08h).SP is modified directly by the 8052 by six
instructions: PUSH, POP, ACALL, LCALL, RET, and RETI. It is also used intrinsically
whenever an interrupt is triggered (more on interrupts later. Don’t worry about them for now!).

5.1.14 INPUT / OUTPUT PORTS

The 8031’s I/O port structure is extremely versatile and flexible. The device has 32 I/O
pins configured as four eight bit parallel ports (P0, P1, P2 and P3). Each pin can be used as an
input or as an output under the software control. These I/O pins can be accessed directly by
memory instructions during program execution to get required flexibility.These port lines can be
operated in different modes and all the pins can be made to do many different tasks apart from
their regular I/O function executions. Instructions, which access external memory, use port P0 as
a multiplexed address/data bus. At the beginning of an external memory cycle, low order 8 bits
of the address bus are output on P0. The same pins transfer data byte at the later stage of the
instruction execution.

Also, any instruction that accesses external Program Memory will output the higher order
byte on P2 during read cycle. Remaining ports, P1 and P3 are available for standard I/O
functions. But all the 8 lines of P3 support special functions: Two external interrupt lines, two
counter inputs, serial port’s two data lines and two timing control strobe lines are designed to use
P3 port lines. When you don’t use these special functions, you can use corresponding port lines
as a standard I/O.Even within a single port, I/O operations may be combined in many ways.
Different pins can be configured as input or outputs independent of each other or the same pin

19
can be used as an input or as output at different times. You can comfortably combine I/O
operations and special operations for Port 3 lines.

5.1.15 TIMERS / COUNTERS

8031 has two 16 bit Timers/Counters capable of working in different modes. Each
consists of a ‘High’ byte and a ‘Low’ byte which can be accessed under software. There is a
mode control register and a control register to configure these timers/counters in number of
ways.These timers can be used to measure time intervals, determine pulse widths or initiate
events with one microsecond resolution upto a maximum of 65 millisecond (corresponding to 65,
536 counts). Use software to get longer delays. Working as counter, they can accumulate
occurrences of external events (from DC to 500KHz) with 16 bit precision.

5.1.16 INTERRUPTS

The 8031 has five interrupt sources: one from the serial port when a transmission or
reception operation is executed; two from the timers when overflow occurs and two come from
the two input pins INT0, INT1. Each interrupt may be independently enabled or disabled to

20
allow polling on same sources and each may be classified as high or low priority.A high priority
source can override a low priority service routine. These options are selected by interrupt enable
and priority control registers, IE and IP.When an interrupt is activated, then the program flow
completes the execution of the current instruction and jumps to a particular program location
where it finds the interrupt service routine. After finishing the interrupt service routine, the
program flows return to back to the original place.The Program Memory address, 0003H is
allotted to the first interrupt and next seven bytes can be used to do any task associated with that
interrupt.

Interrupt Source Service routine starting address

External 0 0003H

Timer/Counter 0 000BH

External 1 0013H

Timer/counter 1 001BH

Serial port 0023H

5.1.17 SERIAL PORT

Each 8031 microcomputer contains a high speed full duplex (means you can
simultaneously use the same port for both transmitting and receiving purposes) serial port which
is software configurable in 4 basic modes: 8 bit UART; 9 bit UART; Interprocessor
Communications link or as shift register I/O expander.For the standard serial communication
facility, 8031 can be programmed for UART operations and can be connected with regular
personal computers, teletype writers, modem at data rates between 122 bauds and 31 kilobauds.
Getting this facility is made very simple using simple routines with option to select even or odd
parity. You can also establish a kind of Interprocessor communication facility among many
microcomputers in a distributed environment with automatic recognition of address/data.Apart
from all above, you can also get super fast I/O lines using low cost simple TTL or CMOS shift
registers.

5.1.18 8051 PIN FUNCTIONS

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I/O PORTS (P0, P1, P2, P3)

Of the 40 pins of the typical 8052, 32 of them are dedicated to I/O lines that have a one-
to-one relation with SFRs P0, P1, P2, and P3. The developer may raise and lower these lines by
writing 1s or 0s to the corresponding bits in the SFRs. Likewise, the current state of these lines
may be read by reading the corresponding bits of the SFRs.

All of the ports have internal pull-up resistors except for port 0.

PORT 0

Port 0 is dual-function in that it in some designs port 0ís I/O lines are available to the
developer to access external devices while in other designs it is used to access external memory.
If the circuit requires external RAM or ROM, the microcontroller will automatically use port 0 to
clock in/out the 8-bit data word as well as the low 8 bits of the address in response to a MOVX
instruction and port 0 I/O lines may be used for other functions as long as external RAM isn’t
being accessed at the same time. If the circuit requires external code memory, the
microcontroller will automatically use the port 0 I/O lines to access each instruction that is to be
executed. In this case, port 0 cannot be utilized for other purposes since the state of the I/O lines
are constantly being modified to access external code memory.Note that there are no pull-up
resistors on port 0, so it may be necessary to include your own pull-up resistors depending on the
characteristics of the parts you will be driving via port 0.

PORT 1

Port 1 consists of 8 I/O lines that you may use exclusively to interface to external parts.
Unlike port 0, typical derivatives do not use port 1 for any functions themselves. Port 1 is
commonly used to interface to external hardware such as LCDs, keypads, and other devices.
With 8052 derivatives, two bits of port 1 are optionally used as described forextended timer 2
functions. These two lines are not assigned these special functions on 8051ís since 8051ís don’t
have a timer 2. Further, these lines can still be used for your own purposes if you don’t need
these features of timer 2.P1.0 (T2): If T2CON.1 is set (C/T2), then timer 2 will be incremented
whenever there is a 1-0 transition on this line. With C/T2 set, P1.0 is the clock source for timer 2.
P1.1 (T2EX): If timer 2 is in auto-reload mode and T2CON.3 (EXEN2) is set, a 1-0 transition on

22
this line will cause timer 2 to be reloaded with the auto-reload value. This will also cause the
T2CON.6 (EXF2) external flag to be set, which may cause an interrupt if so enabled.

PORT 2

Like port 0, port 2 is dual-function. In some circuit designs it is available for accessing
devices while in others it is used to address external RAM or external code memory. When the
MOVX @DPTR instruction is used, port 2 is used to output the high byte of the memory address
that is to be accessed. In these cases, port 2 may be used to access other devices as long as the
devices are not being accessed at the same time a MOVX instruction is using port 2 to address
external RAM. If the circuit requires external code memory, the microcontroller will
automatically use the port 2 I/O lines to access each instruction that is to be executed. In this
case, port 2 cannot be utilized for other purposes since the state of the I/O lines are constantly
being modified to access external code memory.

PORT 3

Port 3 consists entirely of dual-function I/O lines. While the developer may access all
these lines from their software by reading/writing to the P3 SFR, each pin has a pre-defined
function that the microcontroller handles automatically when configured to do so and/or when
necessary. P3.0 (RXD): The UART/serial port uses P3.0 as the receive line. In circuit designs
that will be using the microcontroller’s internal serial port, this is the line into which serial data
will be clocked. Note that when interfacing an 8052 to an RS-232 port that you may not connect
this line directly to the RS-232 pin; rather, you must pass it through a part such as the MAX232
to obtain the correct voltage levels. This pin is available for any use the developer may assign it
if the circuit has no need to receive data via the integrated serial port.P3.1 (TXD): The
UART/serial port uses P3.1 as the ‘transmit line.’ In circuit designs that will be using the
microcontroller’s internal serial port, this is the line that the microcontroller will clock out all
data which is written to the SBUF SFR. Note that when interfacing an 8052 to an RS-232 port
that you may not connect this line directly to the RS-232 pin; rather, you must pass it through a
part such as the MAX232 to obtain the correct voltage levels. This pin is available for any use
the developer may assign it if the circuit has no need to transmit data via the integrated serial

23
port.P3.2 (-INT0): When so configured, this line is used to trigger an ‘External 0 Interrupt.’ This
may either be low-level triggered or may be triggered on a 1-0 transition. Please see the chapter
on interrupts for details. This pin is available for any use the developer may assign it if the circuit
does not need to trigger an external 0 interrupt.P3.3 (-INT1): When so configured, this line is
used to trigger an ‘External 1 Interrupt.’ This may either be low-level triggered or may be
triggered on a 1-0 transition. Please see the chapter on interrupts for details. This pin is available
for any use the developer may assign it if the circuit does not need to trigger an external 1
interrupt.P3.4 (T0): When so configured, this line is used as the clock source for timer 0. Timer 0
will be incremented either every instruction cycle that T0 is high or every time there is a 1-0
transition on this line, depending on how the timer is configured. Please see the chapter on timers
for details. This pin is available for any use the developer may assign it if the circuit does not to
control timer 0 externally.

P3.5 (T1): When so configured, this line is used as the clock source for timer 1. Timer 1 will be
incremented either every instruction cycle that T1 is high or every time there is a 1-0 transition
on this line, depending on how the timer is configured. Please see the chapter on timers for
details. This pin is available for any use the developer may assign it if the circuit does not to
control timer 1 externally.P3.6 (-WR): This is external memory write strobe line. This line will
be asserted low by the microcontroller whenever a MOVX instruction writes to external RAM.
This line should be connected to the RAM’s write (-W) line. This pin is available for any use the
developer may assign it if the circuit does not write to external RAM using MOVX.P3.7 (-RD):
This is external memory write strobe line. This line will be asserted low by the microcontroller
whenever a MOVX instruction writes to external RAM. This line should be connected to the
RAM’s write (-W) line. This pin is available for any use the developer may assign it if the circuit
does not read from external RAM using MOVX.

5.1.19 OSCILLATOR INPUTS (XTAL1, XTAL2)

The 8052 is typically driven by a crystal connected to pins 18 (XTAL2) and 19 (XTAL1).
Common crystal frequencies are 11.0592Mhz as well as 12Mhz, although many newer
derivatives are capable of accepting frequencies as high as 40Mhz.While a crystal is the normal
clock source, this isn’t necessarily the case. A TTL clock source may also be attached to XTAL1
and XTAL2 to provide the microcontroller’s clock.

24
5.1.20 RESET LINE (RST)

Pin 9 is the master reset line for the microcontroller. When this pin is brought high for
two instruction cycles, the microcontroller is effectively reset. SFRs, including the I/O ports, are
restored to their default conditions and the program counter will be reset to 0000h. Keep in mind
that Internal RAM is not affected by a reset. The microcontroller will begin executing code at
0000h when pin 9 returns to a low state.

The reset line is often connected to a reset button/switch that the user may press to reset the
circuit. It is also common to connect the reset line to a watchdog IC or a supervisor IC (such as
MAX707). The latter is highly recommended for commercial and professional designs since
traditional resistor-capacitor networks attached to the reset line, while often sufficient for
students or hobbyists, are not terribly reliable.

5.1.21 ADDRESS LATCH ENABLE (ALE)

The ALE at pin 30 is an output-only pin that is controlled entirely by the microcontroller
and allows the microcontroller to multiplex the low-byte of a memory address and the 8-bit data
itself on port 0. This is because, while the high-byte of the memory address is sent on port 2, port
0 is used both to send the lowbyte of the memory address and the data itself. This is
accomplished by placing the low-byte of the address on port 0, exerting ALE high to latch the
low-byte of the address into a latch IC (such as the 74HC573), and then placing the 8 data-bits
on port 0. In this way the 8052 is able to output a 16-bit address and an 8-bit data word with 16
I/O lines instead of 24.The ALE line is used in this fashion both for accessing external RAM
with MOVX @DPTR as well as for accessing instructions in external code memory. When your
program is executed from external code memory, ALE will pulse at a rate of 1/6th that of the
oscillator frequency. Thus if the oscillator is operating at 11.0592Mhz, ALE will pulse at a rate
of 1,843,200 times per second. The only exception is when the MOVX instruction is executed
one ALE pulse is missed in lieu of a pulse on WR or RD.

5.1.22 PROGRAM STORE ENABLE (-PSEN)

25
 The Program Store Enable (PSEN) line at pin 29 is exerted low automatically by the
microcontroller whenever it accesses external code memory. This line should be attached to the
Output Enable (-OE) pin of the EPROM that contains your code memory.

PSEN will not be exerted by the microcontroller and will remain in a high state if your program
is being executed from internal code memory.

5.1.23 EXTERNAL ACCESS (-EA)

The External Access (-EA) line at pin 31 is used to determine whether the 8052 will execute
your program from external code memory or from internal code memory. If EA is tied high
(connected to +5V) then the microcontroller will execute the program it finds in internal/on-chip
code memory. If EA is tied low (to ground) then it will attempt to execute the program it finds in
the attached external code memory EPROM. Of course, your EPROM must be properly
connected for the microcontroller to be able to access your program in external code memory.

5.1.24 MEMORY ORGANIZATION

The 8051 architecture provides both onchip memory as well as off chip memory expansion
capabilities. It supports several distinctive ‘physical’ address spaces, functionally separated at the
hardware level by different addressing mechanisms, read and write controls signals or both:

 On chip Program Memory

 On chip Data Memory
 Off chip Program Memory
 Off chip Data Memory
 On chip Special Function Registers
The Program Memory area (EPROM incase of external memory or Flash/EPROM incase of
internal one) is extremely large and never lose information when the power is removed. Program
Memory is used for information needed each time power is applied: Initialization values,
Calibration data, Keyboard lookup tables etc along with the program itself. The Program
Memory has a 16 bit address and any particular memory location is addressed using the 16 bit
Program Counter and instructions which generate a 16 bit address.Onchip Data memory is
smaller and therefore quicker than Program Memory and it goes into a random state when power

26
is removed. Onchip RAM is used for variables which are calculated when the program is
executed.In contrast to the Program Memory, On chip Data Memory accesses need a single 8 bit
value (may be a constant or another variable) to specify a unique location. Since 8 bits are more
than sufficient to address 128 RAM locations, the onchip RAM address generating register is
single byte wide.Different addressing mechanisms are used to access these different memory
spaces and this greatly contributes to microcomputer’s operating efficiency.

The 64K byte Program Memory space consists of an internal and an external memory
portion. If the EA pin is held high, the 8051 executes out of internal Program Memory unless the
address exceeds 0FFFH and locations 1000H through FFFFH are then fetched from external
Program Memory. If the EA pin is held low, the 8031 fetches all instructions from the external
Program Memory. In either case, the 16 bit Program Counter is the addressing mechanism.

Figure 4 - Program Memory

The Data Memory address space consists of an internal and an external memory space.
External Data Memory is accessed when a MOVX instruction is executed.Apart from onchip

27
Data Memory of size 128/256 bytes, total size of Data Memory can be expanded upto 64K using
external RAM devices.

Total internal Data Memory is divided into three blocks:

Lower 128 bytes.

Higher 128 bytes

Special Function Register space.

Higher 128 bytes are available only in 8032/8052 devices.

Even though the upper RAM area and SFR area share same address locations, they are
accessed through different addressing modes. Direct addresses higher than 7FH access SFR
memory space and indirect addressing above 7FH access higher 128 bytes (in 8032/8052).

28
 Figure 5 - Internal Data Memory

The next figure indicates the layout of lower 128 bytes. The lowest 32 bytes (from
address 00H to 1FH) are grouped into 4 banks of 8 registers. Program instructions refer these
registers as R0 through R7. Program Status Word indicates which register bank is being used at
any point of time.

29
 Figure 6 - Lower 128 Bytes of Internal RAM

The next 16 bytes above these register banks form a block of bit addressable memory
space. The instruction set of 8031 contains a wide range of single bit processing instructions and
these instructions can directly access the 128 bits of this area.The SFR space includes port
latches, timer and peripheral control registers. All the members of 8031 family have same SFR at
the same SFR locations. There are some 16 unique locations which can be accessed as bytes and
as bits.

5.1.25 COMMON MEMORY SPACE

The 8031’s Data Memory may not be used for program storage. So it means you can’t
execute instructions out of this Data Memory.But, there is a way to have a single block of
offchip memory acting as both Program and Data Memory. By gating together both memory
read controls (RD and PSEN) using an AND gate, a common memory read control signal can be

30
generated.In this arrangement, both memory spaces are tied together and total accessible memory
is reduced from 128 Kbytes to 64 Kbytes.The 8031 can read and write into this common memory
block and it can be used as Program and Data Memory.You can use this arrangement during
program development and debugging phase. Without taking Microcontroller off the socket to
program its internal ROM (EPROM/Flash ROM), you can use this common memory for frequent
program storage and code modifications.

5.1. 25 ADDRESSING MODES

8031’s assembly language instruction set consists of an operation mnemonic and zero to
three operands separated by commas. In two byte instructions the destination is specified first,
and then the source. Byte wide mnemonics like ADD or MOV use the Accumulator as a source
operand and also to receive the result.

The 8031 supports five types of addressing modes:

 Register Addressing
 Direct Addressing
 Register Indirect Addressing
 Immediate Addressing
 Index Addressing

5.1.26 REGISTER ADDRESSING

Register Addressing accesses the eight working registers (R0-R7) of the selected register
bank. The least significant three bits of the instruction opcode indicate which register is to be
used for the operation. One of the four banks of registers is to be predefined in the PSW before
using register addressing instruction. ACC, B, DPTR and CY, (the Boolean Accumulator) can
also be addressed in this mode.

5.1.27 DIRECT ADDRESSING

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 Direct addressing can access any onchip variables or hardware register. To indicate the
address of the location, an additional byte is attached to the opcode. Depending on the highest
order bit of the direct address byte one of two physical memory space is selected.

DIRECT ADDRESSING

When the direct address range is between 0 and 127 (00H - 7FH) one of the 128 low
order onchip RAM location is accessed. All I/O ports, special function, control registers are
assigned between 128 and 255 (80H - FFH). When direct addressing indicates any location in
this range, corresponding hardware register is accessed.

This is the only method available for accessing I/O ports and special function registers.

5.1. 28REGISTER INDIRECT ADDRESSING

Register indirect addressing uses the contents of either R0 or R1 (in the pre selected
register bank) as a address pointer to locate in a 256 byte block (the lower 128 bytes of internal
RAM in 8031 or 256 bytes in 8032) or the lower 256 bytes of external data memory. Note that
the special function registers are not accessible in this mode. Access to full 64K external data
memory address space is indicated by the 16 bit Data Pointer register, DPTR.Execution of PUSH
and POP instructions also involve indirect register addressing. The Stack Pointer indicates the
correct stack location anywhere in the internal RAM.

5.1.29 IMMEDIATE ADDRESSING

When a source operand is a constant rather than a variable, then the constant can be
embedded into the instruction itself. This kind of instructions take two bytes and first one
specifies the opcode and second byte gives the required constant.

5.1.30 INDEX ADDRESSING

Only the Program Memory can be accessed by this mode. This mode is intended for
reading lookup tables in the Program Memory. A 16 bit base register (either DPTR or the
Program Counter) points to the base of the lookup tables and the Accumulator carries the

32
constant indicating table entry number.The address of the exact location of the table is formed by
adding the Accumulator data to the base pointer.

5.1.31 INSTRUCTION SET

8031 architecture sports a powerful and versatile instruction set that enables the user to
develop a compact program. There is a facility to manipulate both byte data and 1 bit binary
data. The table gives complete information on the instruction set.

5.1.32 1 - DATA TRANSFER INSTRUCTIONS

The above table gives the instructions that can be used to move data around internal memory
spaces and the addressing modes that can be used with each one.The MOV <dest>, <src>
instruction allows data to be transferred between any two internal RAM locations without
disturbing the Accumulator. The upper 128 bytes of the data RAM can be accessed only by

33
indirect addressing and SFR space by direct addressing.In all 8031 devices, the stack resides in
onchip RAM, and grows upwards. The PUSH instruction first increments the Stack Pointer (SP),
then copies the byte into the stack. PUSH and POP use only direct addressing to identify the byte
being saved or restored. But the stack itself is accessed by indirect addressing using the SP
register. This means the stack can go into the upper 128 bytes if they are implemented but not
into SFR space.In devices that don’t have upper 128 bytes, if the SP points to anywhere in upper
128 bytes, pushed bytes are lost and popped bytes are indeterminate.The data transfer
instructions include a 16 bit MOV that can be used to initialize the Data Pointer (DPTR) for
lookup tables in Program Memory or for 16 bit external Data Memory accesses.The XCH A,
<byte> instruction causes the Accumulator and the addressed byte to exchange the data. The
XCHD A,@Ri instruction exchange only low nibble between the Accumulator and the addressed
byte.

5.1.33 2 - DATA TRANSFER IN EXTERNAL RAM

This following table gives possible data transfer operations in external data memory
space. Only indirect addressing can be used. The choice is whether to use a one byte address by
@Ri, where Ri can be either R0 or R1 of the selected register bank or a two byte address,
@DPTR.

Note that in all external data RAM accesses the Accumulator is always either the
destination or source of data.The read and write strobes to external RAM are activated only
during the execution of a MOVX instruction. Normally these signals are inactive and infact if
they are not going to be used at all, then their pins are available as extra I/O lines.

34
5.1.34 LOOKUP TABLES

This table shows the two instructions that are available for reading lookup tables from
Program Memory. Since they access only Program Memory, the lookup tables can only be read
not updated. The mnemonic MOVC is for ‘move constant’. If the table access is to external
Program Memory, then the read strobe is PSEN.The first MOVC instruction of the table can read
a byte from 256 entries, numbered 0 through 255. The number of the desired entry loaded into
the Accumulator and the Data Pointer is set up to point to beginning of the table.

The other MOVC instruction works with the Program Counter (PC). Hence PC acts as
the table base and the Accumulator should carry the table entry value.

5.1.35 ARITHMETIC INSTRUCTIONS

Note that most of the operations use Accumulator and any byte in the internal data
memory space can be increased or decrease without using Accumulator.

35
 The instruction MUL AB multiplies the unsigned eight bit integer values held in the
Accumulator and B registers. The lower order byte of the 16 bit product is left in the
Accumulator and the higher order byte in B.

DIV AB divides the unsigned eight bit integer in the Accumulator by the unsigned eight
bit integer in the B register. The integer part of quotient stays with the Accumulator and the
remainder in the B register. The DAA instruction is for BCD arithmetic operations. In BCD
arithmetic, ADD and ADD C instructions should always be followed by a DAA operation, to
ensure that the result is also in BCD. The DAA operation produces a meaningful result only in
the second step when adding two BCD bytes.

36
5.1.36 LOGICAL INSTRUCTIONS

The following table gives the list of 8031’s logical instructions. The instructions that perform
Boolean operations (AND, OR, Exclusive OR, NOT) on bytes perform the operation on a bit by
bit basis. All of the logical instructions that are Accumulator specific execute in 1µs (using a
12MHz clock). Others take 2µs.

Boolean operations can be performed on any byte in the lower 128 internal data memory space
or the SFR space using direct addressing without having to use the Accumulator. If the operation
is in response to an interrupt, not using the Accumulator saves time and effort in the interrupt
service routine.

37
The Rotate instructions (RL A, RLC A, etc.) shift the Accumulator 1 bit to the left or right. For a
left rotation, the MSB rolls into the LSB position and for a right rotation, the LSB rolls into MSB
position.

The SWAP A instruction interchanges the high and low nibbles within the Accumulator. This is
a useful operation in BCD manipulation.

38
5.1.37 PROGRAM CONTROL – JUMPS, CALLS, AND RETURNS

LJMP (long jump) encodes a 16 bit address in the 2nd and 3rd instruction bytes. The
destination may be anywhere in the 64K byte Program Memory address space.The two byte
AJMP (Absolute jump) instruction encodes its destination using a 11 bit address which is
embedded in the instruction itself. Address bits 10 through 8 form a 3 bit field in the opcode and
address bits 7 through 0 form a second byte.Address bits 15-11 remain unchanged from the
incremented contents of the PC, so AJMP can only be used when the destination is known to be
within the same 2K memory block.

5.1.38 JUMP INSTRUCTIONS

Following table gives a list of unconditional jumps.

As you can see, there are three types of jump operations:

SJMP – Short Jump

LJMP – Long Jump

39
AJMP – Absolute Jump

Basically these jump operations differ from each other by the way of address generation meant
for that jump operation.

SJMP (Short Jump) determines the destination with a Program Counter relative address
mentioned in the second byte. The CPU calculates the destination at run time by adding the
signed 8 bit displacement value to the incremented PC. Negative offset values will cause jumps
upto 128 bytes backwards; positive values upto 127 bytes forward.

In contrast, LJMP instructions jump into any place in the 64K bytes program space. The
instruction is three bytes long, first byte is the opcode and next two bytes give destination
address.Like SJMP, AJMP instructions jump into much longer space, anywhere into 2K block.
The instruction is 2 bytes long, containing the opcode in the first byte and the second byte holds
low byte of the destination address. The opcode itself carries higher order bits of 2K space (bits 8
– 10). During the instruction execution, these 11 bits are simply substituted for the low 11 bits in
the PC. Hence, the destination has to be within the same 2K block as the instruction following
the AJMP.The JMP @A+DPTR instruction supports case jumps. The destination address is
calculated during run time as the sum of the 16 bit DPTR register and the Accumulator.Typical
application for this case jump is the facility to jump to the exact location in a lookup table. This
particular type of jumps is one of the most wanted operations. Normally, the DPTR holds the
address of a lookup table. During runtime, the Accumulator is made to calculate the exact
position of the required byte. This instruction sums up both DPTR and the Accumulator and then
jumps to that specific byte.

These are two CALL instructions: LCALL and ACALL. These instructions are used to call
subroutine and they differ in a way the subroutine address is determined.Each instruction
increments the PC to the first byte of the following instruction and then pushes it onto the stack
(low byte first). Saving both bytes increments the Stack Pointer by two. LCALL instruction is for
the long subroutine call operation and the instruction is a 3 byte long one and second and third
bytes carry the address of the subroutine. So the subroutine can be anywhere in the 64K Program
Memory space.But the ACALL instruction drives an absolute subroutine call operation and uses

40
the 11 bit address format. The subroutine should be within the 2K block as the instruction
following the ACALL.Subroutines should end with a RET instruction that pops the high and low
order bytes of the PC successively from the stack, decreasing the Stack Pointer by two and
program execution continues at the address pushed, the first byte of the instruction immediately
following the call.RETI can be used to return from an interrupt service routine. The only
difference between RET and RETI is that RETI tells the interrupt control system that the
interrupt in progress is done. If there is no active interrupt operation, then the RETI is
functionally same as RET.

5.1.39 CONDITIONAL JUMP INSTRUCTIONS

Like SJMP, all conditional jump instructions use relative addressing: JZ (jump if Zero)
and JNZ (jump if not Zero) monitor the state of the Accumulator as implied by their names while
JC (jump on carry) and JNC (jump on no carry) test whether or not the carry flag is set. All these
4 instructions are two byte instructions.

The 8031 instruction set supports another set of conditional jump instruction using Boolean
processing. They are covered separately.

5.1.40 OPERATE AND BRANCH INSTRUCTIONS

CJNE, DJNZ - This group of instructions combine a byte operation with a conditional jump
based on the results. CJNE (Compare and Jump if Not Equal) compares two byte operands and
execute a jump if they disagree. The carry flag is set following the rules of subtraction. If the

41
unsigned integer value of the first operand is less than that of second, then it is set. Otherwise, it
is cleared. The CJNE instruction can also be used for loop control. Two bytes are specified in the
operand field of the instruction. The jump is executed only if the two bytes are not equal.DJNZ
(Decrement and Jump if not Zero) decrements the register or direct address indicated and jumps
if the result is not zero, without affecting any flags. This provides a simple means of executing a
program loop a given number of times, or for adding a moderate time delay (from 2 to 512
machine cycles) using a single instruction. CJNE and DJNZ, like all conditional jumps use
Program Counter relative addressing for the destination address.

5.1.41 BOOLEAN INSTRUCTIONS

The 8031 devices contain a complete Boolean (single bit) processor. The internal RAM
contains 128 addressable bits and the SFR space can support upto 128 other addressable bits. All
of the port lines are bit addressable and each one can be treated as a separate single bit port.

The instructions that access these bits are not just conditional branches, but a complete menu of
MOVE, SET, CLEAR, COMPLEMENT, OR, AND instructions. This range of bit operations are
not easily obtained in other architectures with any amount of byte oriented software.The
instruction set for the Boolean processor is shown here. All bit accesses are direct addressing. Bit
addresses 00H through 7FH are in the lower 128 bytes and bit addresses 80H through FFH are in
SFR space.The carry bit is used as the Boolean processor. Bit instructions that refer to the carry

42
bit as C assemble as carry specific instructions. The carry bit also has a direct address, since it
resides in the PSW register which is bit addressable.Boolean instructions support JB (Jump on
Bit), JNB (Jump on No Bit), JBC (Jump on Bit and Clear), JC (Jump on Carry) and JNC (Jump
on No Carry) operations.The destination address for these jumps is specified in the second byte
of the instruction. This is a signed (two’s complement) offset byte that is added to the PC if the
jump is executed. The range of jump is therefore –128 to +127 Program Memory bytes relative
to the first byte following the jump instruction.

43
44
5.2 POWER SUPPLY

Block Diagram

The ac voltage, typically 220V rms, is connected to a transformer, which steps that ac voltage
down to the level of the desired dc output. A diode rectifier then provides a full-wave rectified
voltage that is initially filtered by a simple capacitor filter to produce a dc voltage. This resulting
dc voltage usually has some ripple or ac voltage variation.

A regulator circuit removes the ripples and also remains the same dc value even if the input dc
voltage varies, or the load connected to the output dc voltage changes. This voltage regulation is
usually obtained using one of the popular voltage regulator IC units.

TRANSFORMER RECTIFIER FILTER IC REGULATOR LOAD

Fig 7 Block Diagram of Power supply

Working principle

Transformer

The potential transformer will step down the power supply voltage (0-230V) to (0-6V) level.
Then the secondary of the potential transformer will be connected to the precision rectifier,
which is constructed with the help of op–amp. The advantages of using precision rectifier are it
will give peak voltage output as DC, rest of the circuits will give only RMS output.

45
Bridge rectifier

When four diodes are connected as shown in figure, the circuit is called as bridge rectifier. The
input to the circuit is applied to the diagonally opposite corners of the network, and the output is
taken from the remaining two corners.
Let us assume that the transformer is working properly and there is a positive potential, at point
A and a negative potential at point B. the positive potential at point A will forward bias D3 and
reverse bias D4.
The negative potential at point B will forward bias D1 and reverse D2. At this time D3 and D1
are forward biased and will allow current flow to pass through them; D4 and D2 are reverse
biased and will block current flow.

The path for current flow is from point B through D1, up through RL, through D3, through the
secondary of the transformer back to point B. this path is indicated by the solid arrows.
Waveforms (1) and (2) can be observed across D1 and D3.

One-half cycle later the polarity across the secondary of the transformer reverse, forward biasing
D2 and D4 and reverse biasing D1 and D3. Current flow will now be from point A through D4,
up through RL, through D2, through the secondary of T1, and back to point A. This path is
indicated by the broken arrows. Waveforms (3) and (4) can be observed across D2 and D4. The
current flow through RL is always in the same direction. In flowing through RL this current
develops a voltage corresponding to that shown waveform (5). Since current flows through the
load (RL) during both half cycles of the applied voltage, this bridge rectifier is a full-wave
rectifier.

One advantage of a bridge rectifier over a conventional full-wave rectifier is that with a given
transformer the bridge rectifier produces a voltage output that is nearly twice that of the
conventional full-wave circuit.

46
This may be shown by assigning values to some of the components shown in views A and B.
assume that the same transformer is used in both circuits. The peak voltage developed between
points X and y is 1000 volts in both circuits. In the conventional full-wave circuit shown—in
view A, the peak voltage from the center tap to either X or Y is 500 volts. Since only one diode
can conduct at any instant, the maximum voltage that can be rectified at any instant is 500 volts.

The maximum voltage that appears across the load resistor is nearly-but never exceeds-500 v0lts,
as result of the small voltage drop across the diode. In the bridge rectifier shown in view B, the
maximum voltage that can be rectified is the full secondary voltage, which is 1000 volts.
Therefore, the peak output voltage across the load resistor is nearly 1000 volts. With both
circuits using the same transformer, the bridge rectifier circuit produces a higher output voltage
than the conventional full-wave rectifier circuit.

IC voltage regulators

Voltage regulators comprise a class of widely used ICs. Regulator IC units contain the circuitry
for reference source, comparator amplifier, control device, and overload protection all in a single
IC. IC units provide regulation of either a fixed positive voltage, a fixed negative voltage, or an
adjustably set voltage. The regulators can be selected for operation with load currents from
hundreds of milli amperes to tens of amperes, corresponding to power ratings from milli watts to
tens of watts.

47
 Fig 8 Circuit Diagram Of Power Supply

A fixed three-terminal voltage regulator has an unregulated dc input voltage, Vi, applied to one
input terminal, a regulated dc output voltage, Vo, from a second terminal, with the third terminal
connected to ground.

The series 78 regulators provide fixed positive regulated voltages from 5 to 24 volts. Similarly,
the series 79 regulators provide fixed negative regulated voltages from 5 to 24 volts.
 For ICs, microcontroller, LCD --------- 5 volts
 For alarm circuit, op-amp, relay circuits ---------- 12 volts

48
5.3 KEYPAD

Keyboards and LCDs are the most widely used input/output devices of the 8051, and a
basic understanding of them is essential. In this section, we first discuss keyboard fundamentals,
along with key press and key detection mechanisms, Then we show how a keyboard is interfaced
to an
8051.

Fig 9 Typical Keypad

5.3.1 Interfacing the keyboard to the microcontroller:

At the lowest level, keyboards are organized in a matrix of rows and columns. The CPU accesses
both rows and column through ports; therefore, with two 8-bit ports, an 8*8 matrix of keys can
be connected to a microprocessor. When a key pressed, a row and column make a connect;
otherwise, there is no connection between row and column. In IBM PC keyboards, a single
microcontroller (consisting of microprocessor, RAM and EPROM, and several ports all on a
single chip) takes care of software and hardware interfacing of keyboard. In such systems it is
the function of programs stored in the EPROM of microcontroller to scan the keys continuously,
identify which one has been activated, and present it to the motherboard. In this section we look
at the mechanism by which the 8051 scans and identifies the key.

49
Scanning and identifying the key:

Figure10 shows a 4*4 matrix connected to two ports. The rows are connected to an output port
and the columns are connected to an input port. If no key has been pressed, reading the input port
will yield 1s for all columns since they are all connected to high (Vcc) If all the rows are
grounded and a key is pressed, one of the columns will have 0 since the key pressed provides the
path to ground. It is the function of the microcontroller to scan the keyboard continuously to
detect and identify the key pressed. How it is done is explained next.
...................................................................................................................................

fig 10 Keypad Interfacing

Grounding rows and reading columns:

50
To detect a pressed key, the microcontroller grounds all rows by providing 0 to the output latch,
and then it reads the columns. If the data read from the columns is D3-D0=1111, no key has been
pressed and the process continues until a key press is detected. However, if one of the column
bits has a zero, this means that a key press has occurred. For example, if D3-D0=1101, this
means that a key in the D1 column has been pressed. After a key press is detected, the
microcontroller will go through the process of identifying the key. Starting with the top row, the
microcontroller grounds it by providing a low to row D0 only; then it reads the columns. If the
data read is all1s, no key in that row is activated and the process is moved to the next row. It
grounds the next row, reads the columns, and checks for any zero. This process continues until
the row is identified. After identification of the row in which the key has been pressed, the next
task is to find out which column the pressed key belongs to. This should be easy since the
microcontroller knows at any time which row and column are being access

5.4 Relay

A relay is an electrically operated switch. Many relays use anelectromagnet to operate a

switching mechanism mechanically, but other operating principles are also used. Relays are used
where it is necessary to control a circuit by a low-power signal (with complete electrical isolation
between control and controlled circuits), or where several circuits must be controlled by one
signal. The first relays were used in long distance telegraph circuits, repeating the signal coming
in from one circuit and re-transmitting it to another. Relays were used extensively in telephone
exchanges and early computers to perform logical operations.

A type of relay that can handle the high power required to directly control an electric
motor is called a contactor. Solid-state relayscontrol power circuits with no moving parts, instead
using a semiconductor device to perform switching. Relays with calibrated operating
characteristics and sometimes multiple operating coils are used to protect electrical circuits from
overload or faults; in modern electric power systems these functions are performed by digital
instruments still called "protective relay

51
 Figure 11 Simple electromechanical Relay

Small "cradle" relay often used in electronics. The "cradle" term refers to the shape of the relay's
armature.

A simple electromagnetic relay consists of a coil of wire wrapped around a soft iron core,
an iron yoke which provides a low reluctance path for magnetic flux, a movable ironarmature,
and one or more sets of contacts (there are two in the relay pictured). The armature is hinged to
the yoke and mechanically linked to one or more sets of moving contacts. It is held in place by
a spring so that when the relay is de-energized there is an air gap in the magnetic circuit. In this
condition, one o f the two sets of contacts in the relay pictured is closed, and the other set is
open. Other relays may have more or fewer sets of contacts depending on their function. The
relay in the picture also has a wire connecting the armature to the yoke. This ensures continuity
of the circuit between the moving contacts on the armature, and the circuit track on the printed
circuit board (PCB) via the yoke, which is soldered to the PCB.When an electric current is
passed through the coil it generates a magnetic field that activates the armature, and the
consequent movement of the movable contact(s) either makes or breaks (depending upon
construction) a connection with a fixed contact. If the set of contacts was closed when the relay
was de-energized, then the movement opens the contacts and breaks the connection, and vice
versa if the contacts were open. When the current to the coil is switched off, the armature is
returned by a force, approximately half as strong as the magnetic force, to its relaxed position.
Usually this force is provided by a spring, but gravity is also used commonly in industrial motor

52
starters. Most relays are manufactured to operate quickly. In a low-voltage application this
reduces noise; in a high voltage or current application it reduces arcing.

When the coil is energized with direct current, a diode is often placed across the coil to
dissipate the energy from the collapsing magnetic field at deactivation, which would otherwise
generate a spike dangerous to semiconductor circuit components. Some automotive relays
include a diode inside the relay case. Alternatively, a contact protection network consisting of a
capacitor and resistor in series (snubbercircuit) may absorb the surge. If the coil is designed to be
energized with alternating current (AC), a small copper "shading ring" can be crimped to the end
of the solenoid, creating a small out-of-phase current which increases the minimum pull on the
armature during the AC cycle.[1]

A solid-state relay uses a thyristor or other solid-state switching device, activated by the control
signal, to switch the controlled load, instead of a solenoid. An optocoupler (a light-emitting
diode (LED) coupled with a photo transistor) can be used to isolate control and controlled
circuits.In this Relay with ULN 2003A is used.ULN 20XX series are High Voltage, High current
Darlington arrays.

Ideally suited for interfacing between low-level logic circuitry and multiple peripheral
power loads, the Series ULN20xxA/L high-voltage, high-current Darlington arrays feature
continuous load current ratings to 500 mA for each of the seven drivers. At an appropriate duty
cycle depending on ambient temperature and number of drivers turned ON simultaneously,
typical power loads totaling over 230 W (350 mA x 7, 95 V) can be controlled. Typical loads
include relays, solenoids, stepping motors, magnetic print hammers, multiplexed LED and
incandescent displays, and heaters. All devices feature open-collector outputs with integral
clamp diodes.

The ULN2003A/L and ULN2023A/L have series input resistors selected for operation
directly with 5 V TTL or CMOS. These devices will handle numerous interface needs —
particularly those beyond the capabilities of standard logic buffers. The ULN2004A/L and
ULN2024A/L have series input resistors for operation directly from 6 to 15 V CMOS or PMOS
logic outputs. The ULN2003A/L and ULN2004A/L are the standard Darlington arrays. The
outputs are capable of sinking 500 mA and will withstand at least 50 V in the OFF state. Outputs

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may be paralleled for higher load current capability. The ULN2023A/L and ULN2024A/L will
withstand 95 V in the OFF state.

Fig 12 ULN2003 pin diagram

These Darlington arrays are furnished in 16-pin dual in-line plastic packages (suffix “A”)
and 16-lead surface-mountable SOICs (suffix “L”). All devices are pinned with outputs opposite
inputs to facilitate ease of circuit board layout. All devices are rated for operation over the
temperature range of -20°C to +85°C.

FEATURES

o TTL, DTL, PMOS, or CMOS-Compatible Inputs

o Output Current to 500 mA

o Output Voltage to 95 V

o Transient-Protected Outputs

o Dual In-Line Plastic Package or Small-Outline IC Package

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5.5 RF MODULE

Fig 13 RF Transmitter and Receiver

The RF module, as the name suggests, operates at Radio Frequency. The corresponding
frequency range varies between 30 kHz & 300 GHz. In this RF system, the digital data is
represented as variations in the amplitude of carrier wave. This kind of modulation is known as
Amplitude Shift Keying (ASK).

Transmission through RF is better than IR (infrared) because of many reasons. Firstly,

signals through RF can travel through larger distances making it suitable for long range
applications. Also, while IR mostly operates in line-of-sight mode, RF signals can travel even
when there is an obstruction between transmitter & receiver. Next, RF transmission is more
strong and reliable than IR transmission. RF communication uses a specific frequency unlike IR
signals which are affected by other IR emitting sources.

This RF module comprises of an RF Transmitter and an RF Receiver. The

transmitter/receiver (Tx/Rx) pair operates at a frequency of 434 MHz. An RF transmitter
receives serial data and transmits it wirelessly through RF through its antenna connected at pin4.
The transmission occurs at the rate of 1Kbps - 10Kbps.The transmitted data is received by an RF
receiver operating at the same frequency as that of the transmitter.The RF module is often used
alongwith a pair of encoder/decoder. The encoder is used for encoding parallel data for
transmission feed while reception is decoded by a decoder. HT12E-HT12D, HT640-HT648, etc.
are some commonly used encoder/decoder pair ICs.

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5.5.1 Pin Diagram: 

Fig 14 Pin Diagram of RF Transmitter and Receiver

Pin Description: 

RF Transmitter

Pin No Function Name

1 Ground (0V) Ground
2 Serial data input pin Data
3 Supply voltage; 5V Vcc
4 Antenna output pin ANT
 
RF Receiver

Pin No Function Name

1 Ground (0V) Ground
2 Serial data output pin Data
3 Linear output pin; not connected NC
4 Supply voltage; 5V Vcc
5 Supply voltage; 5V Vcc
6 Ground (0V) Ground
7 Ground (0V) Ground
8 Antenna input pin ANT

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5.5.2 Encoder and decoder

The radio frequency spectrum is filled with noise and other signals, especially those
frequencies where unlicensed transmitter operation under FCC part 15 rules is allowed. When
using a wireless remote control system it is desirable to have a way of filtering out or ignoring
those unwanted signals to prevent false data from being received.A simple way to accomplish
this is to use an encoder IC at the transmitter and a decoder IC at the receiver. The
encoder generates serial codes that are automatically sent three times and must be received at
least twice before data is accepted as valid by the decoder circuit.In the early days of  "radio
control", before these coding ICs were available, radio controlled garage doors sometimes
opened themselves when they received transmissions from a plane passing overhead or a two-
way radio operating in the area. Encoding and decoding is now used in most wireless control
systems to prevent this type of interference. A GL-104 IC in an 18 pin DIP package available
from Glolab can be used as an either an encoder or decoder just by changing the connection to
one pin. These devices also offer more flexibility than the usual encoder and decoder ICs. One
GL-104 that is configured as an encoder is needed for each transmitter and one that is configured
as a decoder for each receiver. You will also need one 4 MHz ceramic resonator (CR) and one
voltage detector/reset (VDR) device for use with each GL-104.  The GL-104 will be used in the
following application examples. These devices have four data channels. See GL-104 for a
description of pin functions.

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5.6 CCTV Camera

Closed-circuit television (CCTV) cameras can produce images or recordings

for surveillance purposes, and can be either video cameras, or digital stills cameras.It is
used to capture visual scene infront of it. The CCTV camera monitors the location
continuously and the data is sent to the control station. The data’s can be seen with the help
of video display unit or monitor. According to the image from the CCTV we can control the
position of the arms.

Fig 15 Typical CCTV Camera

Closed Circuit Television (CCTV) brings benefits to the campus community through a
variety of initiatives including the following:

• Acts as a deterrent to crime.

• Provides a potential opportunity to aid in the investigation and follow up of
criminal activities.
• Enhances UOW Security’s capacity to increase surveillance of a larger area.
• Enhances the perception of safety.
• Aids in surveillance of traffic and parking activities.
• Helps to protect infrastructure and assets.
• Provides opportunity for surveillance of emergencies in particular events.

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5.7 Motor

A DC motor is designed to run on DC electric power. Two examples of pure DC designs

are Michael Faraday's homopolar motor (which is uncommon), and the ball bearing motor,
which is (so far) a novelty.

By far the most common DC motor types are the brushed and brushless types, which use
internal and external commutation respectively to create an oscillating AC current from the DC
source—so they are not purely DC machines in a strict sense.

We in our project are using brushed DC Motor, which will operate in the ratings of 12v
DC 0.6A which will drive the flywheels in order to make the robot move.

Fig 16 Typical DC Motor

6. ADVANTAGES

 Provide high strength and security in borders

 Secured way of seeing locations using CCTV

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7. APPLICATIONS

 It can be used mainly in military applications for security purpose.

 Also be used in industries for spying purpose.

8. Conclusion

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