DATASHEET

ICL7660 FN3072
CMOS Voltage Converters Rev. 8.00
Feb 13, 2020

The ICL7660 is a monolithic CMOS power supply circuit that Features

offers unique performance advantages over previously
available devices. The ICL7660 performs supply voltage • Simple Conversion of +5V Logic Supply to ±5V Supplies
conversions from positive to negative for an input range of • Simple Voltage Multiplication (VOUT = (-) nVIN)
+1.5V to +10.0V resulting in complementary output voltages
• Typical Open Circuit Voltage Conversion Efficiency 99.9%
of -1.5V to -10.0V. Only two noncritical external capacitors
are needed for the charge pump and charge reservoir • Typical Power Efficiency 98%
functions. The ICL7660 can also be connected to function as • Wide Operating Voltage Range of 1.5V to 10.0V
voltage doublers and can generate output voltages up to
• Easy to Use - Requires Only Two External Non-Critical
+18.6V with a +10V input. Passive Components
Contained on the chip are a series DC supply regulator, RC • No External Diode Over Full Temperature and Voltage
oscillator, voltage level translator, and four output power Range
MOS switches. A unique logic element senses the most
• Pb-Free Plus Anneal Available (RoHS Compliant)
negative voltage in the device and ensures that the output
N-Channel switch source-substrate junctions are not forward
Applications
biased. This assures latchup free operation.
• On Board Negative Supply for Dynamic RAMs
The oscillator, when unloaded, oscillates at a nominal
frequency of 10kHz for an input supply voltage of 5.0V. This • Localized µProcessor (8080 Type) Negative Supplies
frequency can be lowered by the addition of an external • Inexpensive Negative Supplies
capacitor to the OSC terminal, or the oscillator may be
overdriven by an external clock. • Data Acquisition Systems

The LV terminal may be tied to GROUND to bypass the Related Literature

internal series regulator and improve low voltage (LV)
For a full list of related documents, visit our website:
operation. At medium to high voltages of +3.5V to +10.0V,
the LV pin is left floating to prevent device latchup. • ICL7660 device page

Pinouts
ICL7660
(8 LD PDIP, SOIC)
TOP VIEW

NC 1 8 V+

CAP+ 2 7 OSC

GND 3 6 LV

CAP- 4 5 VOUT

FN3072 Rev. 8.00 Page 1 of 12

Feb 13, 2020
ICL7660

Ordering Information
PART NUMBER PART TEMP. RANGE PKG.
(Note 3) MARKING (°C) PACKAGE DWG. #
ICL7660CBA (No longer available, recommended 7660CBA 0 to 70 8 Ld SOIC (N) M8.15
replacement: ICL7660CBAZ, ICL7660CBAZ-T)
ICL7660CBAZ (Note 1) 7660CBAZ 0 to 70 8 Ld SOIC (N) (Pb-free) M8.15
ICL7660CBAZA (Note 1) 7660CBAZ 0 to 70 8 Ld SOIC (N) (Pb-free) M8.15
ICL7660CPA (No longer available, recommended 7660CPA 0 to 70 8 Ld PDIP E8.3
replacement: ICL7660CPAZ)
ICL7660CPAZ 7660CPAZ 0 to 70 8 Ld PDIP (Pb-free) (Note 2) E8.3
NOTES:
1. Add “-T” suffix to part number for tape and reel packaging. See TB347 for details about reel specifications.
2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
3. Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020.

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ICL7660

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +10.5V Thermal Resistance (Typical, Note 4) JA (°C/W) JC (°C/W)
LV and OSC Input Voltage . . . . . . -0.3V to (V+ +0.3V) for V+ < 5.5V PDIP Package (Note 5) . . . . . . . . . . . . 110 N/A
(Note 6) . . . . . . . . . . . . . . (V+ -5.5V) to (V+ +0.3V) for V+ > 5.5V SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A
Current into LV (Note 6) . . . . . . . . . . . . . . . . . . . .20µA for V+ > 3.5V Maximum Storage Temperature Range. . . . . . . . . . . -65°C to 150°C
Output Short Duration (VSUPPLY ≤ 5.5V) . . . . . . . . . . . . Continuous Pb-Free Reflow Profile (Note 5). . . . . . . . . . . . . . . . . . . . . . . TB493

Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and
result in failures not covered by warranty.

NOTES:
4. JA is measured with the component mounted on an evaluation PC board in free air.
5. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

Electrical Specifications V+ = 5V, TA = 25°C, COSC = 0, Test Circuit Note 7, Figure 11 on page 6 unless otherwise specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Supply Current I+ RL = ∞ - 170 500 µA
Supply Voltage Range - Lo VL+ MIN ≤ TA ≤ MAX, RL = 10kΩ, LV to GND 1.5 - 3.5 V
Supply Voltage Range - Hi VH+ MIN ≤ TA ≤ MAX, RL = 10kΩ, LV to Open 3.0 - 10.0 V
Output Source Resistance ROUT IOUT = 20mA, TA = 25°C - 55 100 Ω
IOUT = 20mA, 0°C ≤ TA ≤ 70°C - - 120 Ω
IOUT = 20mA, -55°C ≤ TA ≤ 125°C - - 150 Ω
IOUT = 20mA, -40°C ≤ TA ≤ 85°C - - - Ω
V+ = 2V, IOUT = 3mA, LV to GND 0°C ≤ TA ≤ 70°C - - 300 Ω
V+ = 2V, IOUT = 3mA, LV to GND, -55°C ≤ TA ≤ 125°C - - 400 Ω
Oscillator Frequency fOSC - 10 - kHz
Power Efficiency PEF RL = 5kΩ 95 98 - %
Voltage Conversion Efficiency VOUT EF RL = ∞ 97 99.9 - %
Oscillator Impedance ZOSC V+ = 2V - 1.0 - MΩ
V = 5V - 100 - kΩ
NOTES:
6. Connecting any input terminal to voltages greater than V+ or less than GND may cause destructive latchup. It is recommended that no inputs
from sources operating from external supplies be applied prior to “power up” of the ICL7660.
7. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very
small but finite stray capacitance present, of the order of 5pF.

FN3072 Rev. 8.00 Page 3 of 12

Feb 13, 2020
ICL7660

Functional Block Diagram

V+

CAP+
VOLTAGE
RC LEVEL
OSCILLATOR ÷2
TRANSLATOR
CAP-

VOUT

OSC LV

VOLTAGE LOGIC
REGULATOR NETWORK

Typical Performance Curves (Test Circuit of Figure 11 on page 6)

10 10k
TA = 25°C
OUTPUT SOURCE RESISTANCE (Ω)

8
SUPPLY VOLTAGE RANGE
SUPPLY VOLTAGE (V)

(NO DIODE REQUIRED)

1000
6

4
100

0 10
-55 -25 0 25 50 100 125 0 1 2 3 4 5 6 7 8
TEMPERATURE (°C) SUPPLY VOLTAGE (V+)

FIGURE 1. OPERATING VOLTAGE AS A FUNCTION OF FIGURE 2. OUTPUT SOURCE RESISTANCE AS A FUNCTION

TEMPERATURE OF SUPPLY VOLTAGE

FN3072 Rev. 8.00 Page 4 of 12

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ICL7660

Typical Performance Curves (Test Circuit of Figure 11 on page 6) (Continued)

350 100
IOUT = 1mA TA = 25°C

POWER CONVERSION EFFICIENCY (%)

98
OUTPUT SOURCE RESISTANCE (Ω)

300 IOUT = 1mA

96
250 94
92
200
IOUT = 15mA
90
150 V+ = +2V
88

100 86
84
50
V+ = 5V 82
V+ = +5V
0 80
-55 -25 0 25 50 75 100 125 100 1K 10K

TEMPERATURE (°C) OSC. FREQUENCY fOSC (Hz)

FIGURE 3. OUTPUT SOURCE RESISTANCE AS A FUNCTION FIGURE 4. POWER CONVERSION EFFICIENCY AS A

OF TEMPERATURE FUNCTION OF OSC. FREQUENCY

10K 20

OSCILLATOR FREQUENCY fOSC (kHz)

OSCILLATOR FREQUENCY fOSC (Hz)

18

16
1K
14

12

100 10

8
V+ = 5V
V+ = +5V
TA = 25°C 6
10
1.0 10 100 1000 10K -50 -25 0 25 50 75 100 125
COSC (pF) TEMPERATURE (°C)

FIGURE 5. FREQUENCY OF OSCILLATION AS A FUNCTION FIGURE 6. UNLOADED OSCILLATOR FREQUENCY AS A

OF EXTERNAL OSC. CAPACITANCE FUNCTION OF TEMPERATURE

5 100 100
TA = 25°C
POWER CONVERSION EFFICIENCY (%)

4 90 PEFF 90
V+ = +5V I+
3 80 80
SUPPLY CURRENT I+ (mA)
2 70 70
OUTPUT VOLTAGE

1 60 60

0 50 50

-1 40 40

-2 30 30

20 20
-3
TA = 25°C
10 10
-4 V+ = +5V
SLOPE 55Ω 0 0
-5 0 10 20 30 40 50 60
0 10 20 30 40 50 60 70 80
LOAD CURRENT IL (mA) LOAD CURRENT IL (mA)

FIGURE 7. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT FIGURE 8. SUPPLY CURRENT AND POWER CONVERSION
CURRENT EFFICIENCY AS A FUNCTION OF LOAD
CURRENT

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Feb 13, 2020
ICL7660

Typical Performance Curves (Test Circuit of Figure 11 on page 6) (Continued)

+2 100 20.0
TA = 25°C

POWER CONVERSION EFFICIENCY (%)

V+ = 2V 90 18.0

SUPPLY CURRENT (mA) (NOTE 5)

I+
80 16.0
+1 PEFF
70 14.0
OUTPUT VOLTAGE

60 12.0

0 50 10.0
40 8.0
30 6.0
-1
20 4.0
SLOPE 150Ω TA = 25°C
10 2.0
V+ = 2V
0 0
-2 0 1.5 3.0 4.5 6.0 7.5 9.0
0 1 2 3 4 5 6 7 8
LOAD CURRENT IL (mA) LOAD CURRENT IL (mA)

FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION
CURRENT EFFICIENCY AS A FUNCTION OF LOAD
CURRENT
NOTE:
8. These curves include in the supply current that current fed directly into the load RL from the V+ (See Figure 11). Thus, approximately half the
supply current goes directly to the positive side of the load, and the other half, through the ICL7660, to the negative side of the load. Ideally,
VOUT 2VIN, IS  2IL, so VIN x IS  VOUT x IL.

IS V+
1 8 (+5V)

2 7 IL
C1 + ICL7660
10µF 3 6
-
4 5 RL
COSC
(NOTE)
-VOUT

C2 -
10µF +

NOTE: For large values of COSC (>1000pF) the values of C1 and C2 should be increased to 100µF.
FIGURE 11. ICL7660 TEST CIRCUIT

Detailed Description approaches this ideal situation more closely than existing non-
mechanical circuits.
The ICL7660 contains all the necessary circuitry to complete a
negative voltage converter, with the exception of two external In the ICL7660, the four switches of Figure 12 are MOS power
capacitors which may be inexpensive 10µF polarized switches; S1 is a P-Channel device and S2 , S3 and S4 are
electrolytic types. The mode of operation of the device may be N-Channel devices. The main difficulty with this approach is
best understood by considering Figure 12 on page 7, which that in integrating the switches, the substrates of S3 and S4
shows an idealized negative voltage converter. Capacitor C1 is must always remain reverse biased with respect to their
charged to a voltage, V+, for the half cycle when switches S1 sources, but not so much as to degrade their ON resistances.
and S3 are closed. (Note: Switches S2 and S4 are open during In addition, at circuit start-up, and under output short circuit
this half cycle.) During the second half cycle of operation, conditions (VOUT = V+), the output voltage must be sensed
switches S2 and S4 are closed, with S1 and S3 open, thereby and the substrate bias adjusted accordingly. Failure to
shifting capacitor C1 negatively by V+ volts. Charge is then accomplish this would result in high power losses and probable
transferred from C1 to C2 such that the voltage on C2 is exactly device latchup.
V+, assuming ideal switches and no load on C2 . The ICL7660

FN3072 Rev. 8.00 Page 6 of 12

Feb 13, 2020
ICL7660

This problem is eliminated in the ICL7660 by a logic network that The ICL7660 approaches these conditions for negative
senses the output voltage (VOUT) together with the level voltage conversion if large values of C1 and C2 are used.
translators, and switches the substrates of S3 and S4 to the ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE
correct level to maintain necessary reverse bias. BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS. The energy lost is defined by:
The voltage regulator portion of the ICL7660 is an integral part of
the anti-latchup circuitry, however its inherent voltage drop can E = 1/2 C1 (V12 - V22)
degrade operation at low voltages. Therefore, to improve low
where V1 and V2 are the voltages on C1 during the pump and
voltage operation the LV pin should be connected to GROUND,
transfer cycles. If the impedances of C1 and C2 are relatively
disabling the regulator. For supply voltages greater than 3.5V the
high at the pump frequency (refer to Figure 12) compared to the
LV terminal must be left open to insure latchup proof operation,
value of RL , there will be a substantial difference in the voltages
and prevent device damage.
V1 and V2 . Therefore it is not only desirable to make C2 as large
8 S1 2 S2
as possible to eliminate output voltage ripple, but also to employ
VIN a correspondingly large value for C1 in order to achieve
maximum efficiency of operation.
C1
3 3
Do’s and Don’ts
C2 1. Do not exceed maximum supply voltages.
S3 S4 5 2. Do not connect LV terminal to GROUND for supply voltages
VOUT = -VIN
greater than 3.5V.
3. Do not short circuit the output to V+ supply for supply
7 voltages above 5.5V for extended periods, however,
transient conditions including start-up are okay.
FIGURE 12. IDEALIZED NEGATIVE VOLTAGE CONVERTER
4. When using polarized capacitors, the + terminal of C1 must
be connected to pin 2 of the ICL7660, and the + terminal of
Theoretical Power Efficiency C2 must be connected to GROUND.
Considerations 5. If the voltage supply driving the ICL7660 has a large source
In theory a voltage converter can approach 100% efficiency if impedance (25Ω - 30Ω), then a 2.2µF capacitor from pin 8
certain conditions are met. to ground may be required to limit rate of rise of input
voltage to less than 2V/µs.
1. The driver circuitry consumes minimal power. 6. User should insure that the output (pin 5) does not go more
2. The output switches have extremely low ON resistance and positive than GND (pin 3). Device latch up will occur under
virtually no offset. these conditions. A 1N914 or similar diode placed in parallel
3. The impedances of the pump and reservoir capacitors are with C2 will prevent the device from latching up under these
negligible at the pump frequency. conditions. (Anode pin 5, Cathode pin 3).

V+

1 8
RO
2 7 VOUT
+ ICL7660 -
10µF 3 6
- V+
+
4 5
VOUT = - V+
-
10µF
+

FIGURE 13A. CONFIGURATION FIGURE 13B. THEVENIN EQUIVALENT

FIGURE 13. SIMPLE NEGATIVE CONVERTER

FN3072 Rev. 8.00 Page 7 of 12

Feb 13, 2020
ICL7660

t2 t1

V
A
-(V+)

FIGURE 14. OUTPUT RIPPLE

V+
1 8

2 ICL7660 7
1 8
“1”
C1 3 6 RL
2 ICL7660 7
4 5 “n”
C1 3 6

4 5

-
C2
+

FIGURE 15. PARALLELING DEVICES

V+
1 8

2 ICL7660 7
+ “1” 1 8
10µF 3 6
- 2 ICL7660 7
4 5 + “n”
10µF 3 6
-
4 5 VOUT = - nV+
-
- 10µF
+
10µF
+

FIGURE 16. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE

Typical Applications RO  2(RSW1 + RSW3 + ESRC1) +

1
Simple Negative Voltage Converter + ESRC2
(fPUMP) (C1)
The majority of applications will undoubtedly utilize the ICL7660 fOSC
for generation of negative supply voltages. Figure 13 on page 7 (fPUMP = , RSWX = MOSFET switch resistance)
2
shows typical connections to provide a negative supply negative Combining the four RSWX terms as RSW, we see that:
(GND) for supply voltages below 3.5V. 1
RO  2 (RSW) + + 4 (ESRC1) + ESRC2
The output characteristics of the circuit in Figure 13A on (fPUMP) (C1)
page 7 can be approximated by an ideal voltage source in
series with a resistance as shown in Figure 13B on page 7. RSW, the total switch resistance, is a function of supply voltage
The voltage source has a value of -V+. The output impedance and temperature (See the Output Source Resistance graphs),
(RO) is a function of the ON resistance of the internal MOS typically 23Ω at 25°C and 5V. Careful selection of C1 and C2
switches (shown in Figure 12 on page 7), the switching will reduce the remaining terms, minimizing the output
frequency, the value of C1 and C2 , and the ESR (equivalent impedance. High value capacitors will reduce the
series resistance) of C1 and C2. A good first order 1/(fPUMP • C1) component, and low ESR capacitors will lower
approximation for RO is: the ESR term. Increasing the oscillator frequency will reduce
the 1/(fPUMP • C1) term, but may have the side effect of a net
RO  2(RSW1 + RSW3 + ESRC1) + increase in output impedance when C1 > 10µF and there is no
2(RSW2 + RSW4 + ESRC1) + longer enough time to fully charge the capacitors every cycle.

FN3072 Rev. 8.00 Page 8 of 12

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ICL7660

In a typical application where fOSC = 10kHz and C = C1 = C2 = Cascading Devices

10µF: The ICL7660 can be cascaded as shown to produce larger
1 negative multiplication of the initial supply voltage. However,
RO  2 (23) + + 4 (ESRC1) + ESRC2 due to the finite efficiency of each device, the practical limit is
(5 • 103) (10-5)
10 devices for light loads. The output voltage is defined by:
RO  46 + 20 + 5 (ESRC)
VOUT = -n (VIN),
Because the ESRs of the capacitors are reflected in the output
where n is an integer representing the number of devices
impedance multiplied by a factor of 5, a high value could
cascaded. The resulting output resistance would be
potentially swamp out a low 1/(fPUMP • C1) term, rendering an
approximately the weighted sum of the individual ICL7660
increase in switching frequency or filter capacitance ineffective.
ROUT values.
Typical electrolytic capacitors can have ESRs as high as 10Ω.
Changing the ICL7660 Oscillator Frequency
1
RO  2 (23) + + 4 (ESRC1) + ESRC2 It can be required in some applications (due to noise or other
(5 • 103) (10-5)
considerations) to increase the oscillator frequency. This is
RO/  46 + 20 + 5 (ESRC) achieved by overdriving the oscillator from an external clock,
as shown in Figure 17. In order to prevent possible device
Because the ESRs of the capacitors are reflected in the output latchup, a 1kΩ resistor must be used in series with the clock
impedance multiplied by a factor of 5, a high value could output. In a situation where the designer has generated the
potentially swamp out a low 1/(fPUMP • C1) term, rendering an external clock frequency using TTL logic, the addition of a
increase in switching frequency or filter capacitance ineffective. 10kΩ pullup resistor to V+ supply is required. Note: The pump
Typical electrolytic capacitors can have ESRs as high as 10Ω. frequency with external clocking, as with internal clocking, will
Output Ripple be 1/2 of the clock frequency. Output transitions occur on the
positive-going edge of the clock
ESR also affects the ripple voltage seen at the output. The total
ripple is determined by 2 voltages, A and B, as shown in
Figure 14 on page 8. Segment A is the voltage drop across the V+ V+

ESR of C2 at the instant it goes from being charged by C1 1 8

(current flow into C2) to being discharged through the load 1kΩ
CMOS
2 7 GATE
(current flowing out of C2). The magnitude of this current + ICL7660
change is 2• IOUT , hence the total drop is 2 • IOUT • ESRC2V. 10µF 3 6
-
Segment B is the voltage change across C2 during time t2 , the 4 5 VOUT
-
half of the cycle when C2 supplies current to the load. The drop +
10µF
at B is lOUT • t2/C2V. The peak-to-peak ripple voltage is the
sum of these voltage drops: FIGURE 17. EXTERNAL CLOCKING
1
VRIPPLE
 [ 2 (fPUMP) (C2) + 2 (ESR )
C2 ] IOUT It is also possible to increase the conversion efficiency of the
ICL7660 at low load levels by lowering the oscillator frequency.
This reduces the switching losses, and is shown in Figure 18 on
Again, a low ESR capacitor resets in a higher performance
page 10. However, lowering the oscillator frequency will cause
output.
an undesirable increase in the impedance of the pump (C1) and
Paralleling Devices reservoir (C2) capacitors; this is overcome by increasing the
Any number of ICL7660 voltage converters can be paralleled values of C1 and C2 by the same factor that the frequency has
to reduce output resistance. The reservoir capacitor, C2 , been reduced. For example, the addition of a 100pF capacitor
serves all devices while each device requires its own pump between pin 7 (OSC) and V+ will lower the oscillator frequency
capacitor, C1 . The resultant output resistance would be to 1kHz from its nominal frequency of 10kHz (a multiple of 10),
approximately: and thereby necessitate a corresponding increase in the value
of C1 and C2 (from 10µF to 100µF).
ROUT (of ICL7660)
ROUT =
n (number of devices)

FN3072 Rev. 8.00 Page 9 of 12

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ICL7660

V+ V+ VOUT =
- (nVIN - VFDX)
1 8
1 8
COSC
2 7
2 7 -
+ ICL7660 D1 C3
C1 + ICL7660 +
3 6
- 3 6
C1 -
4 5 VOUT
- 4 5
C2 VOUT = (2V+) -
+ D2 (VFD1) - (VFD2)
- +
+
FIGURE 18. LOWERING OSCILLATOR FREQUENCY C2 - C4

Positive Voltage Doubling FIGURE 20. COMBINED NEGATIVE VOLTAGE CONVERTER

The ICL7660 can be employed to achieve positive voltage AND POSITIVE DOUBLER
doubling using the circuit shown in Figure 19. In this
Voltage Splitting
application, the pump inverter switches of the ICL7660 are
The bidirectional characteristics can also be used to split a
used to charge C1 to a voltage level of V+ -VF (where V+ is the
higher supply in half, as shown in Figure 21. The combined
supply voltage and VF is the forward voltage drop of diode D1).
load will be evenly shared between the two sides. Because the
On the transfer cycle, the voltage on C1 plus the supply voltage
switches share the load in parallel, the output impedance is
(V+) is applied through diode D2 to capacitor C2 . The voltage
much lower than in the standard circuits, and higher currents
thus created on C2 becomes (2V+) - (2VF) or twice the supply
can be drawn from the device. By using this circuit, and then
voltage minus the combined forward voltage drops of diodes
the circuit of Figure 16 on page 8, +15V can be converted (via
D1 and D2 .
+7.5, and -7.5) to a nominal -15V, although with rather high
The source impedance of the output (VOUT) will depend on the series output resistance (~250Ω).
output current, but for V+ = 5V and an output current of 10mA it
will be approximately 60Ω. V+
+
V+ RL1 50µF
1 8
-
1 8
2 7 D1 VOUT = V+ - V- 2 7
ICL7660 2
3 6 VOUT = + ICL7660
D2 (2V+) - (2VF) 50µF 3 6
RL2 -
4 5
4 5
+ + +
C1 C2 50µF
- - -
V-

FIGURE 19. POSITIVE VOLT DOUBLER FIGURE 21. SPLITTING A SUPPLY IN HALF

Combined Negative Voltage Conversion Regulated Negative Voltage Supply

and Positive Supply Doubling In some cases, the output impedance of the ICL7660 can be a
Figure 20 combines the functions shown in Figure 13 on problem, particularly if the load current varies substantially. The
page 7 and Figure 19 to provide negative voltage conversion circuit of Figure 22 on page 11 can be used to overcome this by
and positive voltage doubling simultaneously. This approach controlling the input voltage, using an ICL7611 low-power
would be, for example, suitable for generating +9V and -5V CMOS op amp, in such a way as to maintain a nearly constant
from an existing +5V supply. In this instance capacitors C1 and output voltage. Direct feedback is inadvisable, since the output
C3 perform the pump and reservoir functions respectively for of the ICL7660 does not respond instantaneously to change in
the generation of the negative voltage, while capacitors C2 and input, but only after the switching delay. The circuit shown
C4 are pump and reservoir respectively for the doubled supplies enough delay to accommodate the ICL7660, while
positive voltage. There is a penalty in this configuration which maintaining adequate feedback. An increase in pump and
combines both functions, however, in that the source storage capacitors is desirable, and the values shown provides
impedances of the generated supplies will be somewhat higher an output impedance of less than 5Ω to a load of 10mA.
due to the finite impedance of the common charge pump driver
at pin 2 of the device.

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ICL7660

Other Applications
Further information on the operation and use of the ICL7660
see the ICL7660 device page.

+8V 50k

56k
+8V
100Ω
-
50k 10µF
- +
100k ICL7611
+
1 8

2 7
ICL8069 + ICL7660
100µF 3 6
-
4 5 VOUT

800k -
250k 100µF
VOLTAGE +
ADJUST

FIGURE 22. REGULATING THE OUTPUT VOLTAGE

+5V LOGIC SUPPLY

12 11

TTL DATA 16 1
INPUT
4 3 RS232 +5V
DATA
15 OUTPUT -5V
1 8

2 7 IH5142
+ ICL7660
10µF 3 6 13 14
-
4 5
-
10µF
+

FIGURE 23. RS232 LEVELS FROM A SINGLE 5V SUPPLY

Revision History
Rev. Date Description

8.00 Feb 13, 2020 Removed ICL7660A from datasheet. This has been added to the ICL7660S datasheet.
Updated Ordering Information table - Removed ICL7660A parts and stamped CBA and CPA parts ”No longer
available” with recommended replacement.
Added Related Literature
Added Revision History
Updated Disclaimer.

FN3072 Rev. 8.00 Page 11 of 12

Feb 13, 2020
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