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    EE477L-Final Project Phase 3

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    Amandeep Vaish
    The document provides instructions for the final project phase 3 of the EE-477L course. Students are to implement a 12-bit Kogge-Stone adder (KSA) by designing the schematic, symbol, and layout. Functional testing is required to show the KSA performs addition correctly on different input test cases. Screenshots of the schematic, layout, testbench, and waveforms must be submitted along with identifying the critical path and propagation delay for different test cases. The submission is one PDF file with all required materials.

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    © All Rights Reserved
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    EE477L-Final Project Phase 3

    Uploaded by

    Amandeep Vaish
    64 views3 pages
    The document provides instructions for the final project phase 3 of the EE-477L course. Students are to implement a 12-bit Kogge-Stone adder (KSA) by designing the schematic, symbol, and layout. Functional testing is required to show the KSA performs addition correctly on different input test cases. Screenshots of the schematic, layout, testbench, and waveforms must be submitted along with identifying the critical path and propagation delay for different test cases. The submission is one PDF file with all required materials.

    Original Title

    EE477L-Final_Project_Phase_3

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    The document provides instructions for the final project phase 3 of the EE-477L course. Students are to implement a 12-bit Kogge-Stone adder (KSA) by designing the schematic, symbol, and layout. Functional testing is required to show the KSA performs addition correctly on different input test cases. Screenshots of the schematic, layout, testbench, and waveforms must be submitted along with identifying the critical path and propagation delay for different test cases. The submission is one PDF file with all required materials.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    64 views3 pages

    EE477L-Final Project Phase 3

    Uploaded by

    Amandeep Vaish
    The document provides instructions for the final project phase 3 of the EE-477L course. Students are to implement a 12-bit Kogge-Stone adder (KSA) by designing the schematic, symbol, and layout. Functional testing is required to show the KSA performs addition correctly on different input test cases. Screenshots of the schematic, layout, testbench, and waveforms must be submitted along with identifying the critical path and propagation delay for different test cases. The submission is one PDF file with all required materials.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    EE-477L – Final Project Phase 3

    Spring 2020
    Due: 05/06/2020 (11:59pm)
    Notes:
    o Final Project is based on individual work. No collaboration is allowed.
    o The cells you design in this phase are going to be used in your final project.
    o Your final project report must be a pdf file, which include all the materials of the
    corresponding parts. Other file formats will not be graded.
    o Submit electronically to DEN→Assignments→ Final Project.
    o Ask your questions ONLY in DEN discussion section or use office hours. Do NOT
    send emails asking technical
    questions.
    o TA: Sriharsha Ankathi & Zeming
    Introduction
    The main goal of this phase is to help you understand basic adder design.
    1) Use VDD=1.8 V in this lab. Use rise time = fall time = 0.1ns for all the input
    signals in stimulus;
    2) β = 4 for all gates;
    3) The two inverters working as buffer are required to set WPMOS= 1200 nm, WNMOS= 300
    nm, LNMOS= LPMOS = 200 nm;
    4) The load of every gate is required to be an inverter with WPMOS = 4800 nm, WNMOS =
    1200 nm, LNMOS= LPMOS = 200 nm;
    5) VDD and GND should be drawn with metal 1 and have 6λ width.

    Kogge-Stone Adder
    This is a 12-bit addition. Therefore, the input of addition is a 10-bit unsigned number and 12-bit
    unsigned number, and the output is a 12-bit unsigned number.
    Implement the KSA
    1) Draw the schematic, symbol, and layout for following gates:
    Definition: input A_0 to A_9, B_0 to B_11; output S_0 to S_11
    Cell name: KSA
    All transistor widths of transmission gates are 300nm
    Testbench is not required
    2) Perform functional test
    Design input patterns to show correct functionality
    Waveform includes all inputs and outputs
    Testbench is required
    In this phase, the architecture of adder is specified as KSA. You cannot change it to ripple
    carry adder or carry select adder.
    The structure of KSA is as the same as the slide of PPT.
    4-bit KSA as an example.

    12-bit group PG logic

    11 10 9 8 7 6 5 4 3 2 1 0

    11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

    Test cases for function test:


    1. 90+30
    2. 500+600
    3. 2+4095
    4. 897+0
    For the full credits, you could choose any size you want, once the function is correct.

    Bonus of final project:


    For the size of HA and FA, you need to determine it based on the trade-off between the
    performance and area, since we need to compare the product of period and the area after you
    finish all phases of your final project.
    (Hint: you could choose the size based on the delay result of schematic and the approximate
    delay calculation)
    Submission
    1) Submit the screenshot of schematic, layout, layout testbench.
    2) Submit the screenshot of waveform of function test for all test cases on the schematic.
    3) Drawing the critical path of the addition by analyzing on your schematic. (case by case)
    (Hint: For different cases, the critical paths are different)
    4) State the propagation delay of longest path. (It needs to be measured based on the
    extracted view of your layout) (Hint: For different cases, the critical paths are different)
    You only need to combine these screenshots into one pdf file. (No need for zip file)

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