Analog Design Assignment

Analog and Digital VLSI Design - EEE C443 February 1, 2012

Introduction

For this assignment, you are required to design a simple analog subsystem with the operational amplier as the basic building block. You will be given a few classes of circuits to choose from. Each class of circuit will have some associated specications with it. These specications in turn will place design specications on the basic building block - namely the operational amplier. You need to make the choice and then decide numerical values for each of the system specs that will be enumerated for you. For this job, you might need to refer to journals and other publications. The library IEEE site is a good place to start. The Internet is of course an excellent place to scrounge around for information. In real life the specications would be provided to you by a customer. As a designer your job is to meet those specications. The ability to look at system specications and translate them to specs for individual building blocks is an important aspect of design. This assignment will help you get a feel for this.

Assignment Requirements

You may work on this assignment alone or in groups of two. Groups of three or more are strictly forbidden. Each group is required to submit one copy of the assignment report, strictly adhering to the format provided in a write-up following this document. You are encouraged to discuss the problem with other people who have chosen assignments from the same class of circuits but this does not imply sharing of netlists or design specs. You are advised to use the gm /ID method for meeting gain requirements, while simultaneously using the OCTC method for meeting bandwidth requirements. There will be no deadline extensions or other considerations based on server or software issues. You are being given ample time and it is expected that you partition your work well into that time and not just turn up in the O-Lab on the last couple of days to complete the same. 1

This will be a complex assignment and you will require deep thought and possibly multiple iterations before you can arrive at your nal schematic.

Suggested Design Procedure

As mentioned earlier, you need to look around the IEEE site in the library and also the Internet to get an idea for typical specs for your chosen design block. It is suggested that you make these specs slightly more challenging as the grading that will be done will take into consideration the diculty in meeting specs. Next you will need to decide how each of those specs will aect your operational amplier design. As an extremely simple example, if you are building a closed loop amplier, there might be a system level spec like accuracy of the closed loop gain expressed as x%. This means that A/(1 + A) needs to be related to this gure of x. This in turn will place a requirement on A, the open loop gain of the amplier. (See Ex. 9.1, pg. 292, Razavi ) This is how you need to relate all system level specs to the opamp specs. This is where the rst major challenge of the assignment lies. Once you have the opamp specs, you will need to decide which opamp architecture will help you meet the specs most easily. For example, if a large bandwidth is required it might be inadvisable to use a two-stage opamp since the compensation capacitance reduces the bandwidth heavily. At the same time trying to use a large bandwidth opamp architecture when a moderate or small bandwidth is required is considered overkill and will result in penalisation in terms of marks. Once the opamp architecture is decided upon and its specs extracted from the system level specs, what remains is to decide the level of overestimation at the schematic level of simulation. Remember, as taught in class, once on layout a circuit is going to incur a pretty heavy penalty in terms of speed because of parasitic capacitances which are fairly impossible to estimate at the schematic stage. Hence, please overestimate all your design specs by a factor of 1.5 when they involve capacitances (e.g. bandwidth) because they will be slower on layout by approximately that gure. This essentially means that, for schematic simulation, the relevant specs should all be higher.

Specications

There will be some common specications which any and all of the assignment classes will have to meet or follow. Apart from this, for each class there will be a set of four (barring the opamp which has ve) specications unique to the design. Apart from the specs, for each class there will be a set of simulations that need to be calculated. You need not be bothered about meeting any specs for this section. It is just required that you do the simulations and tabulate your results. This does not mean that you can be careless in the simulations and/or tabulations. They come under the purview of the marks awarded as well! Finally, there will be simulations whose results you have to tabulate for all classes of circuits. These have to be done by everyone.

Common Specications

These are the common specications for all classes of assignments. Parameter Specication Technology TSMC 0.18m technology VDD 3.3V CL 1pF Current Mirror Ratios 20 Reference Current Single ideal current source of arbitrary value, with the positive node tied to VDD or negative node tied to ground Power Dissipation As small as possible * Although the technology is 0.18m, you are to use the 0.35m transistors which are in the design kit for analog design. The 0.18m transistors specically refer to the digital transistors and will not be able to sustain the power supply of 3.3V. You will be given a zero in your assignment if you fail to follow this particular directive.

Classes of Circuits
1. Voltage Regulator 2. Filter 3. Sample and Hold Amplier 4. Switched Capacitor Amplier (Simplied) 5. Fully Dierential Opamp

Here are the classes of circuits that you are to choose from for this assignment:

In case you are confused about (5) turning up as a separate class, then let it be known that the rst four classes are all to be single ended implementations of opamps. The last will be a standalone opamp but since it is fully dierential it will need common-mode feedback (CMFB) circuitry to stabilise its output dc bias. This will be covered in class.

6.1

Voltage Regulator

The circuit for this class is given as follows:

6.1.1

Voltage Regulator Specs

1. Load Regulation 2. Line Regulation 3. Maximum Load Current 4. PSRR @ DC/low frequencies Remember that the regulator output is used as a regulated (obviously!) supply for a large number of circuit blocks. This means that the output needs to be as close to the supply as possible. 6.1.2 Simulations

These are the simulations which are to be carried out for the voltage regulator in particular. These simulation results need to be tabulated along with the design specs: 1. PSRR transient simulations 2. Settling time with supply ramped from 0 to VDD in i) 10ps ii) 10 ms For the PSRR transient simulations use a pulse train of 100mV p-p superimposed on VDD .

6.2

Second Order Filter

The circuit for this class is given as follows:

You may choose the lter to be either low or high pass. Note that appropriate choice of the impedances Z1 through Z4 will determine the nature of the frequency response. Also note that either kind of lter will be of the second order. 6.2.1 Filter Specs

1. Cuto Frequency 2. Passband Gain 3. Passband Ripple 4. PSRR Decide on the lter type and class (e.g. Butterworth, Chebyshev etc.) before you start your design. Note that the PSRR simulations need to be done in exactly the same way as in the case of the voltage regulator. 6.2.2 Simulations

These are the simulations which are to be carried out for the lter in particular. These simulation results need to be tabulated along with the design specs: 1. Initial Roll-o Rate (has to be 40 dB/dec) 2. Frequency Response Peaking 3. Peak Overshoot (for 1V step input)

6.3

Sample and Hold Amplier

The circuit for this class is given as follows:

As you can see this class uses two operational ampliers. Needless to say, to enable design reuse you should carefully choose the opamp topology and specs so that both the functions demonstrated above can be met with a single design. 6.3.1 S/H Specs

1. Maximum Frequency of Operation 2. Allowable Input Voltage Range 3. Sample-to-Hold Transient Settling Time (for Max i/p voltage) 4. PSRR Please note that the PSRR needs to be simulated in the exact same manner as mentioned for the voltage regulator. The clock which is to be used for this simulation is to have the time period corresponding to the maximum frequency and equal rise and fall times of 1 ns each. 6.3.2 Simulations

These are the simulations which are to be carried out for the S/H amplier in particular. These simulation results need to be tabulated along with the design specs: 1. Aperture Time (S-to-H) 2. Acquisition Time (H-to-S)

6.4

Switched Capacitor Amplier

The circuit for this class is given as follows:

Note that the 10 G resistor is used to set the dc bias point at the input terminal of the opamp since capacitors will not allow any dc bias current through. It is not part of the actual design. However, you will have to use it for your simulations. 6.4.1 SC Amp Specs

1. Frequency of Operation 2. Settling Time 3. Output Error 4. PSRR The output error refers to the dierence between the anticipated charge transfer to the output as against the actual charge transfer to the output. The PSRR needs to be simulated as described in the section on voltage regulators. 6.4.2 Simulations

This is the simulation which are to be carried out for the SC amplier in particular. This simulation result needs to be tabulated along with the design specs: 1. Output Drift For the single ended variant shown in the circuit diagram, there might be a drift in the output dc level drift with time. You will be required to run a transient simulation to discover the drift.

6.5

Fully Dierential Operational Amplier

For obvious reasons, no circuit diagram will be provided to you. If you opt for this class for your assignment, then note that the opamp that you need to build is no longer tailored to meet a certain type of operation for a specic circuit. This means that the specs for the opamp need to be as close to those of an ideal opamp as possible since this design will be general purpose and should work fairly well for any application that it is used for. Since this implementation will be fully dierential, you will need to design CMFB circuitry too. 6.5.1 Opamp Specs

1. Low frequency Open Loop Gain 2. Unity Gain Bandwidth 3. Input Referred Oset 4. Phase Margin 5. Slew Rate 6.5.2 Simulations

These are the simulations which are to be carried out for the SC amplier in particular. These simulation results need to be tabulated along with the design specs: 1. CMFB circuitry gain 2. Input Transistor Mismatch Analysis 3. Settling time in Unity Feedback (for 1V step i/p) For the input transistor mismatch analysis, you will be required to simulate the opamp by changing the (W/L) ratios of the input transistors by 10% in opposite directions. As you can gure out, there will have to be two simulations for this.

Common Simulations
1. Performance Evaluation at: VDD +10%, FF Corner, Minimum Resistance Corner, 0 C VDD -10%, SS Corner, Maximum Resistance Corner, 100 C 2. Noise Analysis

The following simulations need to be done for all classes of circuits:

The rst set of simulations will give you an idea of what sort of havoc, PVT variations can wreak on the operation of a circuit. When you tabulate your nal results, every parameter mentioned for each class of circuit - specic and nonspecic - need to be tabulated as three columns; one for TT, Typical Resistance, 27 C and the other two as the PVT corners mentioned in this section. You are not required to meet the specications at all corners. The minimum requirement is meeting it at the TT, Typical Resistance, 27 C corner. However, let it be stated that whosoever can meet the performance criteria at all three corners will be awarded 15 marks (out of 75) as a bonus even if his or her total has to cross the stipulated 75 marks as a result! The noise simulation will give you an idea of a theoretical topic that you have studied in class. You will be required to submit some back of the envelope calculations to quantify the noise causing elements in your circuit. This will be further claried in a subsequent document.

Footnote

I know it looks a little scary, but you need to get your teeth into it. As I have often said, I will push you always out of your comfort zone. May you realise the Innite Potential that Lies Within. A This document was prepared using L TEX. Switch to Linux. Switch to a better world...Im obviously sleepy...