Cortex - M1: Technical Reference Manual
Cortex - M1: Technical Reference Manual
Cortex - M1: Technical Reference Manual
Revision: r1p0
Change History
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Preface
About this manual ........................................................................................ xiv
Feedback ..................................................................................................... xix
Chapter 1 Introduction
1.1 About the processor .................................................................................... 1-2
1.2 Components, hierarchy, and implementation .............................................. 1-4
1.3 Configurable options ................................................................................. 1-10
1.4 About the architecture ............................................................................... 1-11
1.5 Binary compatibility with Cortex-M3 processor ......................................... 1-12
1.6 Product revisions ...................................................................................... 1-13
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. iii
Contents
Chapter 4 Exceptions
4.1 About the exception model ......................................................................... 4-2
4.2 Exception types .......................................................................................... 4-3
4.3 Exception priority ........................................................................................ 4-5
4.4 Stacks ......................................................................................................... 4-7
4.5 Pre-emption ................................................................................................ 4-8
4.6 Exception exit ........................................................................................... 4-10
4.7 Late-arrival ................................................................................................ 4-12
4.8 Exception control transfer ......................................................................... 4-13
4.9 Activation levels ........................................................................................ 4-14
4.10 Lock-up ..................................................................................................... 4-16
Chapter 8 Debug
8.1 About debug ............................................................................................... 8-2
8.2 Debug control ............................................................................................. 8-5
8.3 ROM table ................................................................................................ 8-13
8.4 BPU .......................................................................................................... 8-16
8.5 DW unit ..................................................................................................... 8-19
8.6 Debug TCM interface ............................................................................... 8-24
8.7 Examples of debug register halt, access, and step .................................. 8-25
8.8 Data address watchpoint matching .......................................................... 8-28
8.9 Semiprecise watchpoints .......................................................................... 8-29
Glossary
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. vii
List of Tables
Table 6-5 SysTick Current Value Register bit assignments ...................................................... 6-7
Table 6-6 SysTick Calibration Value Register bit assignments ................................................ 6-8
Table 6-7 CPUID Base Register bit assignments ..................................................................... 6-9
Table 6-8 Interrupt Control State Register bit assignments .................................................... 6-10
Table 6-9 Application Interrupt and Reset Control Register bit assignments ......................... 6-12
Table 6-10 Configuration and Control Register bit assignments .............................................. 6-14
Table 6-11 System Handler Priority Register 2 bit assignments ............................................... 6-15
Table 6-12 System Handler Priority Register 3 bit assignments ............................................... 6-16
Table 6-13 System Handler Control and State Register bit assignments ................................. 6-17
Table 7-1 NVIC registers .......................................................................................................... 7-3
Table 7-2 Interrupt Set-Enable Register bit assignments ......................................................... 7-4
Table 7-3 Interrupt Clear-Enable Register bit assignments ...................................................... 7-5
Table 7-4 Interrupt Set-Pending Register bit assignments ....................................................... 7-6
Table 7-5 Interrupt Clear-Pending Registers bit assignments .................................................. 7-7
Table 7-6 Interrupt Priority Registers 0-31 bit assignments ...................................................... 7-8
Table 8-1 Core debug registers summary ................................................................................ 8-3
Table 8-2 BPU register summary .............................................................................................. 8-3
Table 8-3 DW register summary ............................................................................................... 8-4
Table 8-4 Debug Fault Status Register bit assignments ........................................................... 8-6
Table 8-5 Debug Halting Control and Status Register .............................................................. 8-8
Table 8-6 Debug Core Register Selector Register ................................................................. 8-10
Table 8-7 Debug Exception and Monitor Control Register ..................................................... 8-12
Table 8-8 ROM memory ......................................................................................................... 8-13
Table 8-9 Breakpoint Control Register bit assignments .......................................................... 8-17
Table 8-10 Breakpoint Comparator Registers bit assignments ................................................ 8-18
Table 8-11 DW Control Register bit assignments ..................................................................... 8-20
Table 8-12 Control Register bit assignments ............................................................................ 8-20
Table 8-13 DW Comparator Registers bit assignments ............................................................ 8-21
Table 8-14 DW Mask Registers bit assignments ...................................................................... 8-22
Table 8-15 DW Function Registers bit assignments ................................................................. 8-23
Table 8-16 Settings for DW Function Registers ........................................................................ 8-23
Table 9-1 Other AHB-AP ports ................................................................................................. 9-5
Table 9-2 AHB access port registers ........................................................................................ 9-6
Table 9-3 AHB-AP Control/Status Word Register bit assignments ........................................... 9-7
Table 9-4 AHB-AP Transfer Address Register bit assignments ............................................... 9-8
Table 9-5 AHB-AP Data Read/Write Register bit assignments ................................................ 9-9
Table 9-6 Banked Data Register bit assignments ..................................................................... 9-9
Table 9-7 ROM Address Register bit assignments ................................................................. 9-10
Table 9-8 AHB-AP Identification Register bit assignments ..................................................... 9-10
Table 10-1 HPROT[3:0] encoding ............................................................................................. 10-5
Table 10-2 Byte-write size ........................................................................................................ 10-6
Table 10-3 Instruction and Data TCM sizes .............................................................................. 10-7
Table A-1 Reset signals ............................................................................................................ A-2
Table A-2 Miscellaneous signals ............................................................................................... A-3
Table A-3 Interrupt interface ...................................................................................................... A-4
Table A-4 External AHB-Lite interface ...................................................................................... A-5
Table A-5 ITCM interface .......................................................................................................... A-6
viii Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
List of Tables
Figure 6-12 System Handler Control and State Register bit assignments ................................. 6-16
Figure 7-1 Interrupt Priority Registers 0-7 bit assignments ........................................................ 7-8
Figure 8-1 Debug Fault Status Register bit assignments ........................................................... 8-6
Figure 8-2 Debug Halting Control and Status Register bit assignments .................................... 8-8
Figure 8-3 Debug Core Register Selector Register bit assignments ....................................... 8-10
Figure 8-4 Debug Exception and Monitor Control Register bit assignments ........................... 8-12
Figure 8-5 Breakpoint Control Register bit assignments .......................................................... 8-16
Figure 8-6 Breakpoint Comparator Registers bit assignments ................................................ 8-18
Figure 8-7 DW Control Register bit assignments ..................................................................... 8-19
Figure 8-8 DW Mask Registers 0-1 format ............................................................................... 8-21
Figure 8-9 DW Function Registers bit assignments ................................................................. 8-22
Figure 9-1 DAP configuration ..................................................................................................... 9-2
Figure 9-2 AHB access port internal structure. .......................................................................... 9-5
Figure 9-3 AHB-AP Control/Status Word Register bit assignments ........................................... 9-7
Figure 9-4 AHB-AP Identification Register bit assignments ..................................................... 9-10
Figure 10-1 ITCM write signal timings ........................................................................................ 10-6
Figure 10-2 ITCM read signal timings ........................................................................................ 10-7
xii Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Preface
This preface introduces the Cortex-M1 r0p1 Technical Reference Manual (TRM). It
contains the following sections:
• About this manual on page xiv
• Feedback on page xix.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. xiii
Preface
The rnpn identifier indicates the revision status of the product described in this manual,
where:
rn Identifies the major revision of the product.
pn Identifies the minor revision or modification status of the product.
Intended audience
Chapter 1 Introduction
Read this chapter for an introduction to the components of the processor
and the processor instruction set.
Chapter 4 Exceptions
Read this chapter for a description of the processor exception model.
xiv Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Preface
Chapter 8 Debug
Read this chapter for a description of the processor system debug
components, and debugging and testing the processor.
Glossary Read the Glossary for definitions of terms used in this manual.
Conventions
Typographical
monospace Denotes text that you can enter at the keyboard, such as
commands, file and program names, and source code.
monospace bold Denotes language keywords when used outside example code.
< and > Enclose replaceable terms for assembler syntax where they appear
in code or code fragments. For example:
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
Timing diagrams
The figure named Key to timing diagram conventions explains the components used in
timing diagrams. Variations, when they occur, have clear labels. You must not assume
any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value
within the shaded area at that time. The actual level is unimportant and does not affect
normal operation.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus change
Signals
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means:
• HIGH for active-HIGH signals
xvi Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Preface
Numbering
<size in bits>'<base><number>
This is a Verilog method of abbreviating constant numbers. For example:
• 'h7B4 is an unsized hexadecimal value.
• 'o7654 is an unsized octal value.
• 8'd9 is an eight-bit wide decimal value of 9.
• 8'h3F is an eight-bit wide hexadecimal value of 0x3F. This is
equivalent to b00111111.
• 8'b1111 is an eight-bit wide binary value of b00001111.
Additional reading
ARM publications
This manual contains information that is specific to the Cortex-M1 processor. See the
following documents for other relevant information:
• ARMv6-M Architecture Reference Manual (ARM DDI 0419)
• ARMv6-M Instruction Set Quick Reference Guide (ARM QRC 0011)
• ARM AMBA® 3 AHB-Lite Protocol Specification (ARM IHI 0033)
• ARM CoreSight™ Components Technical Reference Manual (ARM DDI 0314)
• ARM Debug Interface v5, Architecture Specification (ARM IHI 0031)
• Application Binary Interface for the ARM Architecture (The Base Standard)
(IHI0036)
• Cortex-M1 Configuration and Sign-off Guide (ARM DII 0166)
• Cortex-M1 Integration Manual (ARM DII 0167).
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. xvii
Preface
Other publications
xviii Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Preface
Feedback
ARM welcomes feedback on the Cortex-M1 processor and its documentation.
If you have any comments or suggestions about this product, contact your supplier
giving:
• the product name
• a concise explanation of your comments.
If you have any comments on this manual, send an email to [email protected] giving:
• the title
• the number
• the page number(s) to which your comments refer
• a concise explanation of your comments.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. xix
Preface
This chapter introduces the processor and instruction set. It contains the following
sections:
• About the processor on page 1-2
• Components, hierarchy, and implementation on page 1-4
• Configurable options on page 1-10
• About the architecture on page 1-11
• Binary compatibility with Cortex-M3 processor on page 1-12
• Product revisions on page 1-13.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 1-1
Introduction
1-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Introduction
• 32-bit hardware multiplier. You can choose either the standard multiplier or a
smaller, lower performance multiplier implementation.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 1-3
Introduction
DTCM
ITCM
Processor with debug
Debug subsystem
ITCM DTCM
Debug TCM interface interface interface
Breakpoint unit
Core
Data watchpoint unit Dbg
AHB Decoder Debug control
AHB Multiplexer ROM table
NVIC
SW/JTAG interface
1-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Introduction
ITCM DTCM
AHB-PPB Core
External
AHB Master
interface
1.2.1 Core
• 3-stage pipeline
• multiply cycles:
— three cycles for normal multiplier
— 33 cycles for small multiplier.
• Thumb state
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 1-5
Introduction
Registers
Because reads are speculatively fetched from TCMs, Device and Strongly-Ordered
memory types are not supported, for example FIFOs in TCM space. You must ensure
that any Flash memory in this space is tolerant of extra accesses at all times. The TCM
interface does not support wait states.
1.2.3 NVIC
The NVIC is tightly coupled to the processor core. This facilitates low-latency
exception processing. The main features include:
• a configurable number of external interrupts, 1, 8, 16, or 32
• a fixed number of bits of priority, 2 bits, providing four levels of configurable
priority
• both level and pulse interrupt support
• processor state automatically saved on interrupt entry and restored on interrupt
exit, with no instruction overhead.
The Bus master provides a maximum of two interfaces. One master interface connects
the internal Private Peripheral Bus (PPB) signals to the AHB PPB. The other master
interface connects external bus signals to the AHB port.
1-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Introduction
1.2.5 AHB-PPB
1.2.6 Debug
• The full debug configuration has four breakpoint comparators and two watchpoint
comparators. This is the default configuration.
• The reduced debug configuration has two breakpoint comparators and one
watchpoint comparator.
AHB decoder Decodes the AHB address lines to create selects for the
peripherals in the debug system.
AHB multiplexer Combines the debug slave responses for all debug blocks.
AHB matrix The AHB Matrix arbitrates between the processor and debug
accesses to the internal PPB and the AHB-Lite external interface.
See Chapter 10 External and Memory Interfaces for more
information.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 1-7
Introduction
1-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Introduction
Debug control A debugger can access the debug control registers through the
PPB to halt and step the processor. The debugger can also access
processor registers when the processor is halted.
See Chapter 8 Debug for more information.
ROM table The ROM table enables standard debug tools to recognize the
processor and the debug peripherals available, and to find the
addresses required to access those peripherals.
See Chapter 8 Debug for more information.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 1-9
Introduction
Table 1-1 shows the features you can configure using parameters and the default for the
processors.
Table 1-2 shows the features you can configure by setting processor pin values.
Instruction TCM sizea 0KB (no Instruction TCM), 1KB, 2KB, and powers of 2 to 1MB.
Data TCM sizea 0KB (no Data TCM), 1KB, 2KB, and powers of 2 to 1MB.
a. TCM size might be limited by the memory available on your FPGA. Contact your implementation
team for more information.
1-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Introduction
For complete descriptions of all instruction sets, see the ARMv6-M Instruction Set
Quick Reference Guide.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 1-11
Introduction
To ensure a smooth transition, ARM recommends that code designed to operate on both
processor architectures obey the following rules and configure the Configuration
Control Register (CCR) appropriately:
• Use word transfers only to access all registers in the NVIC and System Control
Space (SCS)
• Treat all unused SCS registers and bit fields on the Cortex-M1processor as
do-not-modify
• As soon as possible after reset, manually configure the following fields in the
CCR on the Cortex-M3 processor:
— STKALIGN bit to one
— UNALIGN_TRP bit to one
— Leave all other bits in the CCR register as their original value.
1-12 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Introduction
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 1-13
Introduction
1-14 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Chapter 2
Programmer’s Model
This chapter describes the processor programmer’s model. It contains the following
sections:
• About the programmer’s model on page 2-2
• Registers on page 2-4
• Data types on page 2-10
• Memory formats on page 2-11
• Instruction set on page 2-13.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 2-1
Programmer’s Model
2.1.1 Privilege
The processor does not support differentiated User and Privileged modes. The processor
is always in Privileged mode.
Thread mode
Is entered on Reset and can be re-entered as a result of an exception
return.
Handler mode
Is entered as a result of an exception.
Thumb state
This is normal execution running the set of 16-bit and 32-bit halfword
aligned Thumb and Thumb-2 instructions.
Debug state
This is the state when in halting debug.
Out of reset, all code uses the main stack. An exception handler such as SVCall can
change the stack used by Thread mode from the main stack to the process stack by
changing the EXC_RETURN value it uses on exit. All exceptions continue to use the
main stack. The stack pointer, R13, is a banked register that switches between the main
stack and the process stack. Only one stack, the process stack or the main stack, is
visible through R13 at any one time.
2-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Programmer’s Model
It is also possible to switch from main stack to process stack while in Thread mode by
writing to the Special-Purpose Control Register using the MSR instruction. See
Special-Purpose Control Register on page 2-9 for more information.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 2-3
Programmer’s Model
2.2 Registers
The processor has the following 32-bit registers:
• 13 general-purpose registers, R0-R12
• Stack Pointer (SP) (SP, R13) and banked register aliases, SP_process and
SP_main
• Link Register (LR, R14)
• Program Counter (PC, R15)
• Program status registers, xPSR.
r0
r1
r2
r3
low registers
r4
r5
r6
r7
r8
r9
high registers r10
r11
r12
r13 (SP) SP_process SP_main
r14 (LR)
r15 (PC)
Program Status Register xPSR
Low registers Registers R0-R7 are accessible by all instructions that specify a
general-purpose register.
High registers Registers R8-R12 are not accessible by all 16-bit instructions.
2-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Programmer’s Model
The R13, R14, and R15 registers have the following special functions:
Stack pointer Register R13 is used as the Stack Pointer (SP). Because the SP
ignores writes to bits [1:0], it is autoaligned to a word, four-byte,
boundary.
Note
SP[1:0] must be treated as SBZP.
Handler mode always uses SP_main, Thread mode can use either
SP_main or SP_process.
This section describes the break down of the processor status register at the system
level:
• Application PSR
• Interrupt PSR on page 2-6
• Execution PSR on page 2-7.
They can be accessed as individual registers, a combination of any two from three, or a
combination of all three using the MRS and MSR instructions.
Application PSR
The Application PSR (APSR) contains the condition code flags. Before entering an
exception, the processor saves the condition code flags on the stack. You can access the
APSR using the MSR and MRS instructions.
Figure 2-2 on page 2-6 shows the bit assignments of the APSR.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 2-5
Programmer’s Model
31 30 29 28 27 0
N Z C V Reserved
[27:0] - Reserveda
a. The bits are defined as UNK/SBZP.
Interrupt PSR
The Interrupt PSR (IPSR) contains the Interrupt Service Routine (ISR) number of the
current exception activation.
31 6 5 0
2-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Programmer’s Model
[31:6] - Reserved
Execution PSR
The Execution PSR (EPSR) contains the Thumb state bit (T-bit).
31 25 24 23 0
Reserved T Reserved
Note
Unless the processor is in Debug state, the EPSR is not directly accessible and all fields
read as zero using an MRS instruction. MSR instruction writes are ignored.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 2-7
Programmer’s Model
[31:25] - Reserved.
[24] T The T-bit is set according to the reset vector when the processor comes out of reset. The execution
of an instruction with the EPSR T-bit clear causes a Hard Fault. This ensures that attempts to switch
to ARM state fail in a predictable way.
[23:0] - Reserved.
On entering an exception, the processor saves the combined information from the three
status registers on the stack.
Note
Bit [9] of the stacked xPSR contains the alignment status of the active SP when the
exception processing begins.
Figure 2-5 shows the bit assignments of the Special-Purpose Priority Mask Register.
31 1 0
Reserved
PRIMASK
2-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Programmer’s Model
Table 2-4 lists the bit assignments of the Special-Purpose Priority Mask Register.
[31:1] - Reserved
You can access the Special-Purpose Priority Mask Register using the MSR and MRS
instructions. You can also use the CPS instruction to set or clear PRIMASK.
Figure 2-6 shows the bit assignments of the Special-purpose Control Register.
31 2 1 0
Reserved
[31:2] - Reserved
[0] - Reserved
For writes from Handler mode occurring as part of an exception return, see the
ARMv6-M Architecture Reference Manual.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 2-9
Programmer’s Model
Note
Unless otherwise stated the core can access all regions of the memory map, including
the code region, with all data types. To support this, the system, including memories,
must support subword writes without corrupting neighboring bytes in that word.
2-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Programmer’s Model
Table 2-6 shows the required mapping for an AHB-Lite interface. Table 2-6 also shows
how the slaves use the HSIZE and the HADDR signals to determine which byte lanes
are active on the data buses HWDATA and HRDATA.
Word 0 x x x x
Halfword 0 - - x x
Halfword 2 x x - -
Byte 0 - - - x
Byte 1 - - x -
Byte 2 - x - -
Byte 3 x - - -
On the TCM interface, the byte write enables are to be used for writes to ensure the
correct byte lanes on the write data bus are written. All TCM reads are performed as
word accesses and the processor will select the appropriate byte lanes depending on the
requested access size and the address alignment.
Note
These properties are endian-independent.
Endianness affects the numeric significance given to the bytes within the word or
halfword, by the master performing the access. For a little-endian access, the byte with
the highest address within the word or halfword has the highest numerical significance.
For a big-endian access, the byte with the lowest address has the highest numerical
significance.
For more details on endianness, see the ARMv6-M Architecture Reference Manual.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 2-11
Programmer’s Model
Accesses to the PPB space are always in little-endian format. The processor correctly
interprets PPB data even when configured for big-endian operation.
2-12 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Programmer’s Model
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 2-13
Programmer’s Model
2-14 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Chapter 3
Memory Map
This chapter describes the processor fixed memory map. It contains the following
section:
• About the memory map on page 3-2.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 3-1
Memory Map
0xE00FFFFF 0xFFFFFFFF
ROM Table
0xE00FF000
Reserved Reserved
0xE0042000
Reserved
0xE0041000 0xE0100000
Reserved private peripheral bus
0xE0000000
0xE0040000 0xDFFFFFFF
Reserved
0xE000F000
External device 1GB
Debug control
0xE000ED00
NVIC 0xA0000000
0xE000E000 0x9FFFFFFF
Reserved
0xE0003000
BP SRAM 1GB
0xE0002000
DW
0xE0001000
0x60000000
Reserved 0x5FFFFFFF
0xE0000000
Peripheral 0.5GB
0x40000000
0x3FFFFFFF 0x3FFFFFFF
511MB External
0x20100000 SRAM 0.5GB
0x20000000 1MB DTCM
0x20000000
0x1FFFFFFF
0.5GB
0x1FFFFFFF Code
External
0x10010000 0x00000000
0x1000FFFF
ITCM (Upper Alias)
0x10000000
0x0FFFFFFF
External
0x00100000
0x00000000 1MB ITCM (Lower Alias)
3-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Memory Map
Device
Region Name XNa Interface accessed
type
0x00000000- Code, ITCM, Lower Normal - If the ITCM Lower Alias is enabled, instruction fetches and
0x000FFFFF Alias data accesses are performed to ITCM. Data accesses include
data literal accesses. The region shown here is for the
maximum supported size of ITCM. If there is less ITCM, this
region ends at a lower address and the next starts at the
following address.
0x00100000- Code, external Normal - Instruction fetches and data accesses are performed to the
0x0FFFFFFF external system bus. Data accesses include data literal
accesses.
0x10000000- Code, ITCM, Upper Normal - If the ITCM Upper Alias is enabled, instruction fetches and
0x1000FFFF Alias data accesses are performed to ITCM. Data accesses include
data literal accesses. The region shown here is for the
maximum supported size of ITCM. If there is less ITCM, this
region ends at a lower address and the next starts at the
following address.
0x10010000- Code, external Normal - Instruction fetches and data accesses are performed to the
0x1FFFFFFF external system bus. Data accesses include data literal
accesses.
0x20000000- SRAM, DTCM Normal XN Instruction fetches are faulted. Data accesses are performed
0x200FFFFF to DTCM. The region shown here is for the maximum
supported size of DTCM. If there is less DTCM, this region
ends at a lower address and the next starts at the following
address.
0x20100000- SRAM, external Normal - Instruction fetches are performed to the external system bus.
0x3FFFFFFF Data accesses are performed to the external system bus.
0x40000000- Peripheral Device XN Data accesses are performed to the external system bus.
0x5FFFFFFF Instruction accesses are prevented and faulted.
0x60000000- SRAM Normal - Instruction and Data accesses are performed to the external
0x9FFFFFFF system bus.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 3-3
Memory Map
Device
Region Name XNa Interface accessed
type
0xA0000000- External Device Device XN Data accesses are performed to the external system bus.
0xDFFFFFFF Instruction accesses are prevented and faulted.
0xE0000000- Private Peripheral Bus SO XN Data accesses are performed over the PPB. Instruction
0xE00FFFFF accesses are prevented and faulted.
a. Execute Never. A region is marked as XN to prevent instructions being fetched from that region.
See Chapter 10 External and Memory Interfaces for a description of the processor bus
interfaces. See Chapter 8 Debug for information on ROM memory.
3-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Chapter 4
Exceptions
This chapter describes the exception model of the processor. It contains the following
sections:
• About the exception model on page 4-2
• Exception types on page 4-3
• Exception priority on page 4-5
• Stacks on page 4-7
• Pre-emption on page 4-8
• Exception exit on page 4-10
• Late-arrival on page 4-12
• Exception control transfer on page 4-13
• Activation levels on page 4-14
• Lock-up on page 4-16.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 4-1
Exceptions
• Automatic state saving and restoring. The processor pushes state registers on the
stack when entering the exception and pops them when exiting the exception with
no instruction overhead.
For information on what content is stacked, see Pre-emption on page 4-8.
• Automatic reading of the vector table entry that contains the exception handler
address.
Note
Vector table entries are ARM or Thumb interworking compatible values.
Bit[0] of the vector value is loaded into the EPSR T-bit on exception entry.
Creating a table entry with bit [0] clear generates a Hard Fault on the first
instruction of the handler corresponding to this vector.
• Closely-coupled interface between the processor and the NVIC to enable efficient
processing of interrupts and processing of late-arriving interrupts with higher
priority.
• Separate stacks for Handler and Thread modes if the Operating System (OS)
extension is implemented.
• Exception control transfer using the calling conventions of the C/C++ standard
ARM Architecture Procedure Call Standard (AAPCS). For more information, see
the Application Binary Interface for the ARM Architecture (The Base Standard).
Note
The number of interrupts are configured during implementation. Software can choose
to enable a subset of the configured number of hardware interrupts.
4-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Exceptions
For more information on exceptions, see the ARMv6-M Architecture Reference Manual.
Table 4-1 shows the exception type, position, and priority. Position refers to the word
offset of the exception vectors from the start of the vector table, which is always at
address 0x0. The lower numbers shown in the Priority column of the table are higher
priority. How the types are activated, synchronously or asynchronously, is also shown.
The exact meaning and use of priorities is explained in Exception priority on page 4-5.
4-10 - - Reserved. -
11 SVC Configurable System service call using the SVC instruction. Synchronous
12-13 - - Reserved. -
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Exceptions
14 PendSV Configurable Pendable request for system service. This is only Asynchronous
pended by software.
16-47 External Interrupt Configurable Asserted from outside the processor or pended by Asynchronous
software.
4-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Exceptions
Scenario Description
Pre-emption A pended exception can interrupt the current execution thread if the priority of the pended exception is
higher than the current execution priority.
When one exception pre-empts another, the exceptions are nested.
On exception entry the processor automatically saves processor state, which is pushed on to the stack.
The vector corresponding to the exception is fetched. Execution begins at the address pointed to by the
vector table value. Execution of the first instruction of the exception starts when the processor state has
been saved. The state saving is performed over the ITCM, DTCM, or external AHB-Lite interface
depending on:
• the value of the stack pointer when the processor registered the exception
• the size of the TCMs implemented.
The vector fetch is performed over the external AHB-Lite interface or the ITCM memory interface
depending on the configuration of ITCM size.
Return When a valid return instruction is executed, the processor pops the stack and returns to a stacked
exception or Thread mode.
On completion of an exception handler the processor automatically restores the processor state by
popping the stack to restore the state prior to the exception.
Late-arriving A mechanism used by the processor to speed up pre-emption. If a higher priority exception arrives during
state saving for a previous pre-emption, the processor switches to handling the higher priority exception
instead and initiates the vector fetch for that exception. The state saving is not affected by late arrival,
because the state that is saved is the same for both exceptions and the state saving continues uninterrupted.
Late arriving exceptions are recognized up to the point where the vector fetch has been initiated. If a high
priority exception is recognized too late to be handled as a late arrival, it is pended and subsequently
pre-empts the original exception handler.
In the processor exception model, priority determines when and how the processor takes
exceptions. You can assign priority levels to interrupts.
The NVIC supports software-assigned priority levels. You can assign a priority level
from 0 to 3 to an interrupt by writing to the two-bit IP_N field in an Interrupt Priority
Register, see Interrupt Priority Registers on page 7-7. Priority level 0 is the highest
priority level and priority level 3 is the lowest. For example, if you assign priority level
1 to IRQ[0] and priority level 0 to IRQ[31], then IRQ[31] has priority over IRQ[0].
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 4-5
Exceptions
Note
Software prioritization does not affect reset, Non-Maskable Interrupt (NMI), and Hard
Fault. They always have higher priority than the external interrupts.
When multiple exceptions have the same priority number, the pending exception with
the lowest exception number takes precedence. For example, if both IRQ[0] and
IRQ[1] are priority level 1, then IRQ[0] has precedence over IRQ[1].
For more information on the IP_N fields, see Interrupt Priority Registers on page 7-7.
4-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Exceptions
4.4 Stacks
The processor supports two separate stacks:
Process stack
You can configure Thread mode to use either SP_process or SP_main for
its Stack Pointer (SP).
Note
This is only available if the OS extension option is implemented. Contact
your implementation team for information.
Main stack Handler mode uses the main stack. SP_main is the SP register for the
main stack. Thread mode uses SP_main out of reset.
Only one Stack Pointer register, SP_process or SP_main, is visible at any time, using
R13.
When a thread is pre-empted, its context is automatically saved onto the stack that was
active at the time the exception was recognized.
If an exception pre-empts Thread mode, the context of the pre-empted thread can be
stacked using SP_process or SP_main depending on the value of the CONTROL[1] bit.
On exception return, the EXC_RETURN value determines which stack is used for the
unstacking of context. The EXC_RETURN value loaded into R14 during exception
entry points to the same stack that was used to stack the context. If your exception
handler code moves the stack, you must ensure that the EXC_RETURN value used for
exception return is correctly updated.
All exception handlers must use SP_main for their local variables.
Note
MSR and MRS instructions have visibility of both stack pointers.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 4-7
Exceptions
4.5 Pre-emption
This section describes the behavior of the processor when it takes an exception.
When the processor takes an exception, it automatically pushes the following eight
registers to the stack:
• xPSR
• ReturnAddress( )
• Link Register (LR)
• R12
• R3
• R2
• R1
• R0.
The SP is decremented by eight words on the completion of the stack push. Figure 4-1
shows the contents of the stack after an exception pre-empts the current program flow.
Old SP <previous>
xPSR
ReturnAddress()
LR
r12
r3
r2
r1
SP r0
Note
• Figure 4-1 shows the order on the stack.
• Doubleword alignment of the stack pointer is enforced when stacking
commences. Bit [2] of the stack pointer is saved as bit [9] of the stacked xPSR.
After returning from the exception, the processor automatically pops the eight registers
from the stack. The exception return value, EXC_RETURN, is automatically loaded
into the LR on exception entry to enable exception handlers to be written as normal
C/C++ functions without the requirement for a veneer. See the ARMv6-M Architecture
Reference Manual for more information.
4-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Exceptions
Table 4-3 describes the steps that the processor takes before it enters an exception.
Action Description
Push eight registers Pushes xPSR, ReturnAddress(), LR, R12, R3,R2, R1, and R0 on selected stack.
Read vector table Reads vector from the appropriate vector table entry:
(0x0) + (exception_number *4).
The vector table read is done after all eight registers are pushed on to the stack.
Read SP_main On Reset only, SP_main is updated from the first entry in the vector table. Other exceptions do not
from vector table modify SP_main in this manner.
Update LR The LR is set to the appropriate EXC_RETURN to enable correct return from the exception.
EXC_RETURN is one of 16 values as defined in ARMv6-M Architecture Reference Manual.
Update PC Updates PC with the read data from the vector table. No other late-arriving exceptions can be
processed until the first instruction of the exception starts to execute.
Load pipeline Pipeline is filled with sequential instructions at the vector address.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 4-9
Exceptions
Action Description
Pop eight registers Pops R0, R1, R2, R3, R12, LR, PC, and xPSR from stack selected by EXC_RETURN.
The value of xPSR[5:0] loaded off the stack determines the exception number that defines
the priority of the thread to be returned to.
The value of EXC_RETURN determines which mode is returned to.
Exception returns occur when one of the following instructions executed in Handler
mode loads a value of 0xFXXXXXXX into the PC:
• POP that includes loading the PC
• BX with any register.
4-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Exceptions
When used in this way, the value written to the PC is intercepted and is referred to as
the EXC_RETURN value. Table 4-5 lists the EXC_RETURN[3:0] values with a description
of the exception return behavior.
EXC_RETURN[3:0] Description
0bXXX0 Reserved.
0b0011 Reserved.
0b01X1 Reserved.
0b1X11 Reserved.
If an EXC_RETURN value is loaded into the PC when in Thread mode, or from the
vector table, or by any other instruction, the value is treated as an address, not as a
special value. This address range is defined to have Execute Never (XN) permissions
and results in a Hard Fault.
Note
Exception handlers must preserve the value of EXC_RETURN[28:4] or write them as
all ones (1s).
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 4-11
Exceptions
4.7 Late-arrival
A late-arriving exception can be handled in preference to a previous exception if the
vector fetch has not started and the late-arriving exception has:
• a higher priority than the previous exception
• the same priority but a lower exception number than the previous exception.
If a high priority exception is recognized after the vector fetch of the original exception
has started, the late-arriving exception cannot use the context already stacked for the
original exception. In this case, the original exception handler is pre-empted and its
context is saved onto the stack.
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Exceptions
Processor activity at
recognition of exception Transfer to exception processing
Instruction Instruction completes and exception is taken before the next instruction.
Exception entry This is classified as a late arriving exception. If the new exception is of higher priority or
the same priority and lower exception number than the first exception, the core might
service the late arriving exception first as a late arrival case. If not, the late arriving
exception remains pending and normal pre-emption rules apply.
If the late arriving exception arrives early enough in the core stacking phase it is taken as
a late arrival. In this case, the core fetches the vector for the late arriving exception instead
of the vector for the first exception. Execution begins at the late arriving exception vector
and the first exception remains pending.
If the late arriving exception arrives too late in the stacking phase it cannot be handled as
a late arrival. Instead, the first exception vector is fetched, execution commences at the
first exception vector address and the late arriving exception is pended and normal
pre-emption rules apply.
Exception postamble Exception return sequence is completed and execution resumes at the target of the return.
Normal pre-emption rules then apply.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 4-13
Exceptions
Table 4-8 lists the transition rules for all exception types and how they relate to the
access rules and stack model.
ISR or NMIa Set-pending software instruction or hardware signal Asynchronous pre-emption Main
a. Nonmaskable interrupt.
b. Supervisor Call.
4-14 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Exceptions
Intended
activation subtype Triggering event Activation Priority effect
SVC SVC instruction Synchronous If the priority programmed for the SVCall exception
is higher than the currently executing priority, the
SVCall exception is taken. If not, the SVC escalates
to a HardFault.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 4-15
Exceptions
4.10 Lock-up
The processor has a lock-up state that is entered when an unrecoverable condition
occurs. The cause of unrecoverable conditions are asynchronous or synchronous faults,
including an escalated SVC instruction. For more information on unrecoverable
conditions, see the ARMv6-M Architecture Reference Manual.
The processor can enter the lock-up state at a priority of -1 or -2. An NMI can be taken
and cause the processor to leave the lock-up state if it was at a priority of -1.
A debugger can also cause the processor to exit the lock-up state.
The LOCKUP pin from the processor indicates the that the processor is in the lock-up
state.
4-16 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Chapter 5
Clocks and Resets
This chapter describes the processor clocking and resets. It contains the following
section:
• About clocks and resets on page 5-2.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 5-1
Clocks and Resets
The SYSRESETn signal resets the entire processor system with the exception of
debug, and must be used to reset the external AHB bus. The DBGRESETn signal resets
all the debug logic in the processor, when present.
Processor
SYSRESETREQ
DAPCLK
DAPRESETn
DBGRESETn
5-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Clocks and Resets
Note
Both DBGRESETn and SYSRESETn must be asserted at power on reset.
Depending on your requirements, you might want to reset the system outside the
processor independent of the state of SYSRESETREQ. If this is the case, ensure that:
Note
If you do not reset the system at the same time as the processor, you must also ensure
accesses that might be in progress as reset occurs do not disrupt the system.
You can stop all of the processor clocks indefinitely without loss of state.
Note
• When the External AHB system and the processor are held in reset by
SYSRESETn, the debugger can only access the debug portion of the PPB space
of the processor and the TCMs. The debugger cannot access external memory
space.
• You must ensure that DAPRESETn is held LOW for a minimum of two cycles
and deasserted synchronously to DAPCLK.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 5-3
Clocks and Resets
5-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Chapter 6
System Control
This chapter describes the registers that program the processor. It contains the following
sections:
• About system control on page 6-2
• System control register descriptions on page 6-4.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 6-1
System Control
SysTick Control and Status Register R/W 0xE000E010 0x00000004 page 6-5
SysTick Current Value Register R/W clear 0xE000E018 0x00000000 page 6-7
Application Interrupt and Reset Control Register -b 0xE000ED0C 0xFA050000c page 6-12
0xFA058000d
System Handler Control and State Register R/W 0xE000ED24 0x00000000 page 6-16
a. Access type depends on the individual bit. For more information see Table 6-8 on page 6-10
b. Access type depends on the individual bit. For more information see Table 6-9 on page 6-12
c. Reset value for little-endian.
d. Reset value for BE-8 big-endian.
Note
• All system control registers are only accessible using word transfers. Any attempt
to write a halfword or byte causes corruption of register bits.
6-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
System Control
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 6-3
System Control
Use the Auxiliary Control Register to control the Instruction TCM Upper and Lower
Alias Enables.
Figure 6-1 shows the bit assignments of the Auxiliary Control Register
31 5 4 3 2 0
Reserved 0 0
ITCMUAEN
ITCMLAEN
Reserved
Table 6-2 lists the bit assignments of the Auxiliary Control Register.
[31:5] - Reserved.
[2:0] - Reserved.
When the ITCMLAEN bit is set, all valid instruction and data accesses to the address
region 0x00000000 to (maximum ITCM size) are mapped onto the ITCM interface.
When the ITCMLAEN bit is clear, these accesses are mapped onto the external
AHB-Lite interface.
6-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
System Control
When the ITCMUAEN bit is set, all valid instruction and data accesses to the address
region 0x10000000 to (0x10000000 + maximum ITCM size) are mapped onto the ITCM
interface. When the ITCMUAEN bit is clear, these accesses are mapped onto the
external AHB-Lite interface.
Use the SysTick Control and Status Register to enable the SysTick features.
Figure 6-2 shows the bit assignments of the SysTick Control and Status Register.
31 17 16 15 3 2 1 0
Reserved Reserved 0 0 0
COUNTFLAG CLKSOURCE
TICKINT
ENABLE
Table 6-3 lists the bit assignments of the SysTick Control and Status register.
[31:17] - Reserved.
[16] COUNTFLAG Returns 1 if timer counted to 0 since last time this was read. Clears on read by application
or debugger.
[15:3] - Reserved.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 6-5
System Control
Table 6-3 SysTick Control and Status Register bit assignments (continued)
[0] ENABLE 1 = counter operates in a multi-shot way. That is, counter loads with the Reload value and
then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally
pends the SysTick handler, based on TICKINT. It then loads the Reload value again and
begins counting.
0 = counter disabled.
Use the SysTick Reload Value Register to specify the start value to load into the SysTick
Current Value Register when the counter reaches 0. It can be any value in range
0x00000001-0x00FFFFFF. A start value of 0 is possible, but has no effect because the
SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0.
The RELOAD value can be calculated according to its use. For example:
Figure 6-3 on page 6-7 shows the bit assignments of the SysTick Reload Value Register.
6-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
System Control
31 24 23 0
Reserved RELOAD
Table 6-4 lists the bit assignments of the SysTick Reload Value Register.
[31:24] - Reserved
[23:0] RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0
Use the SysTick Current Value Register to find the current value in the register.
Figure 6-4 shows the bit assignments of the SysTick Current Value Register.
31 24 23 0
Reserved CURRENT
Table 6-5 lists the bit assignments of the SysTick Current Value Register.
[31:24] - Reserved.
[23:0] CURRENT Reads return the current value of the SysTick counter.
This register is write-clear. Writing to it with any value clears the register to 0. Clearing this
register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 6-7
System Control
Use the SysTick Calibration Value Register to enable software to scale to any required
speed using divide and multiply.
Figure 6-5 shows the bit assignments of the SysTick Calibration Value Register.
31 30 29 24 23 0
Reserved TENMS
SKEW
NOREF
Table 6-6 lists the bit assignments of the SysTick Calibration Value Register.
[31] NOREF Reads as one. Indicates that no separate reference clock is provided.
[30] SKEW Reads as zero. Calibration value for the 10ms inexact timing is not known because TENMS is not
known. This can affect its suitability as a software real time clock.
[29:24] - Reserved.
6-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
System Control
Figure 6-6 shows the bit assignments of the CPUID Base Register.
31 24 23 20 19 16 15 4 3 0
Table 6-7 lists the bit assignments of the CPUID Base Register.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 6-9
System Control
Access Access type depends on the individual bit. For more information see
Table 6-8.
Reset value 0x00000000.
Figure 6-7 shows the bit assignments of the Interrupt Control State Register.
31 30 29 28 27 26 25 24 23 22 21 18 17 12 11 6 5 0
ISRPENDING
ISRPREEMPT
Reserved
PENDSTCLR
PENDSTSET
PENDSVCLR
PENDSVSET
Reserved
NMIPENDSET
Table 6-8 lists the bit assignments of the Interrupt Control State Register.
[30:29] - - Reserved.
6-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
System Control
[24] - - Reserved.
[23] ISRPREEMPTb RO You must only use this at debug time. It indicates that a pending interrupt
becomes active in the next running cycle. If C_MASKINTS is clear in the Debug
Halting Control and Status Register, the interrupt is serviced:
1 = a pending exception is serviced on exit from the debug halt state
0 = a pending exception is not serviced.
[21:18] - - Reserved.
[17:12] VECTPENDINGa RO Indicates the exception number for the highest priority pending exception:
0 = no pending exceptions
Non zero = The pending state includes the effect of memory-mapped enable and
mask registers. It does not include the PRIMASK special-purpose register
qualifier.
[11:6] - - Reserved.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 6-11
System Control
Figure 6-8 shows the bit assignments of the Application Interrupt and Reset Control
Register.
31 16 15 14 3 2 1 0
VECTKEY Reserved
ENDIANNESS SYSRESETREQ
Reserved
Figure 6-8 Application Interrupt and Reset Control Register bit assignments
Table 6-9 lists the bit assignments of the Application Interrupt and Reset Control
Register.
Table 6-9 Application Interrupt and Reset Control Register bit assignments
[31:16] VECTKEY WO Register key. To write to other parts of this register, you must ensure 0x5FA is
written into the VECTKEY field.
[15] ENDIANNESS RO Data endianness bit. The read value depends on the endian configuration
implemented:
0 = little-endian
1 = BE-8 big-endian.
[14:3] - - Reserved.
6-12 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
System Control
Table 6-9 Application Interrupt and Reset Control Register bit assignments (continued)
[2] SYSRESETREQ WO Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to
be asserted to request a reset. The intention is to force a large system reset of
all major components except for debug. The C_HALT bit in the DHCSR is
cleared as a result of the system reset requested. The debugger does not lose
contact with the device.
[1] VECTCLRACTIVE WO Clears all active state information for fixed and configurable exceptions.
This bit:
• is self-clearing
• can only be set by the DAP when the processor is halted.
When this bit is set:
• clears all active exception status of the processor
• forces a return to Thread mode
• forces an IPSR of 0.
A debugger must re-initialize the stack.
[0] - - Reserved.
The Configuration and Control Register permanently enables stack alignment and
causes unaligned accesses to result in a Hard Fault.
Figure 6-9 shows the bit assignments of the Configuration and Control Register.
31 10 9 8 4 3 2 0
Reserved Reserved
STKALIGN
UNALIGN_TRP
Reserved
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 6-13
System Control
Table 6-10 lists the bit assignments of the Configuration and Control Register.
[31:10] - Reserved.
[9] STKALIGN Always set to 1. On exception entry, all exceptions are entered with 8-byte stack alignment
and the context to restore it is saved. The SP is restored on the associated exception return.
[8:4] - Reserved.
[3] UNALIGN_TRP Indicates that all unaligned accesses results in a Hard Fault. Trap for unaligned access is
fixed at 1.
[2:0] - Reserved.
System handlers are a special class of exception handler that can have their priority set
to any of the priority levels.
There are two system handler priority registers for prioritizing the following system
handlers:
• SVCall, see System Handler Priority Register 2
• SysTick, see System Handler Priority Register 3 on page 6-15
• PendSV, see System Handler Priority Register 3 on page 6-15.
PendSV and SVCall are permanently enabled. You can enable or disable SysTick by
writing to the SysTick Control and Status Register.
Figure 6-10 on page 6-15 shows the bit assignments of the System Handler Priority
Register 2.
6-14 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
System Control
31 30 29 0
Reserved
PRI_11
Table 6-11 lists the bit assignments for the System Handler Priority Register 2.
[29:0] - Reserved
Figure 6-11 shows the bit assignments of the System Handler Priority Register 3.
31 30 29 24 23 22 21 0
Reserved Reserved
PRI_15 PRI_14
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 6-15
System Control
Table 6-12 lists the bit assignments of the System Handler Priority Registers.
[29:24] - Reserved
[21:0] - Reserved
Use the System Handler Control and State Register to read or write the pending status
of SVCall.
Figure 6-12 shows the bit assignments of the System Handler and State Control
Register.
31 16 15 14 0
Reserved Reserved
SVCALLPENDED
Figure 6-12 System Handler Control and State Register bit assignments
6-16 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
System Control
Table 6-13 lists the bit assignments of the System Handler Control Register.
Table 6-13 System Handler Control and State Register bit assignments
[31:16] - Reserved.
[14:0] - Reserved.
Note
This register is only accessible as part of debug and not through the processor memory
map.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 6-17
System Control
6-18 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Chapter 7
Nested Vectored Interrupt Controller
This chapter describes the Nested Vectored Interrupt Controller (NVIC). It contains the
following sections:
• About the NVIC on page 7-2
• NVIC programmer’s model on page 7-3
• Level versus pulse interrupts on page 7-9
• Resampling level interrupts on page 7-10
• Interrupts as general purpose input on page 7-11.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 7-1
Nested Vectored Interrupt Controller
All NVIC registers are only accessible using word transfers. Any attempt to write a
halfword or byte individually causes corruption of the register bits.
Processor accesses are correctly handled regardless of the endian configuration of the
processor.
7-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Nested Vectored Interrupt Controller
The sections that follow describe how to use the NVIC registers.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 7-3
Nested Vectored Interrupt Controller
Each bit in the register corresponds to one of 32 interrupts. Setting a bit in the Interrupt
Set-Enable Register enables the corresponding interrupt.
When the enable bit of a pending interrupt is set, the processor activates the interrupt
based on its priority. When the enable bit is clear, asserting the interrupt signal pends
the interrupt, but it is not possible to activate the interrupt, regardless of its priority.
Therefore, a disabled interrupt can serve as a latched general-purpose bit. You can read
it and clear it without invoking an interrupt.
Clear the enable state by writing a 1 to the corresponding bit in the Interrupt
Clear-Enable Register (see Interrupt Clear-Enable Register). This also clears the
corresponding bit in the Interrupt Set-Enable Register (see Interrupt Set-Enable
Register on page 7-3).
Table 7-2 lists the bit assignments of the Interrupt Set-Enable Register.
Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt
Clear-Enable Register bit disables the corresponding interrupt.
7-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Nested Vectored Interrupt Controller
Note
Writing a 1 to a Clear-Enable Register bit does not affect currently active interrupts. It
only prevents new activations.
Table 7-3 lists the bit assignments of the Interrupt Clear-Enable Register.
Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt
Set-Pending Register bit pends the corresponding interrupt. Writing a 0 to a pending bit
has no effect on the pending state of the corresponding interrupt.
Clear an interrupt pending pit by writing a 1 to the corresponding bit in the Interrupt
Clear-Pending Register (see Interrupt Clear-Pending Register on page 7-6).
Note
Writing to the Interrupt Set-Pending Register has no effect on an interrupt that is already
pending.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 7-5
Nested Vectored Interrupt Controller
Table 7-4 lists the bit assignments of the Interrupt Set-Pending Register.
Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt
Clear-Pending Register bit clears the pending state of the corresponding interrupt.
Note
Writing to the Interrupt Clear-Pending Register has no effect on an interrupt that is
active unless it is also pending.
7-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Nested Vectored Interrupt Controller
Table 7-5 lists the bit assignments of the Interrupt Clear-Pending Registers.
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the
available interrupts. 0 is the highest priority and 3 is the lowest.
The two bits of priority are stored in bits [7:6] of each byte.
Figure 7-1 on page 7-8 shows the bit assignments of Interrupt Priority Registers 0-7.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 7-7
Nested Vectored Interrupt Controller
31 30 29 24 23 22 21 16 15 14 13 8 7 6 5 0
Figure 7-1 shows fields for 32 interrupts using Interrupt Priority Registers 0-7. If your
implementation uses fewer interrupts, all unused registers are Reserved.
Table 7-6 lists the bit assignments of the Interrupt Priority Registers.
7-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Nested Vectored Interrupt Controller
For level interrupts, if the signal is not deasserted before the return from the interrupt
routine, the interrupt repends and re-activates. This is particularly useful for FIFO and
buffer-based devices because it ensures that they drain either by a single ISR or by
repeated invocations, with no extra work. This means that the device holds the interrupt
signal asserted until the device is empty.
A pulse interrupt must be asserted for at least one processor clock cycle to enable the
NVIC to observe it.
A pulse interrupt can be reasserted during the ISR so that the interrupt can be pended
and active at the same time. The application design must ensure that a second pulse does
not arrive before the interrupt caused by the first pulse is activated. If the second pulse
arrives before the interrupt is activated, the second pulse has no effect because it is
already pended. When the ISR is activated, the pend bit is cleared. If the interrupt asserts
again when the ISR is activated, the NVIC latches the pend bit again.
Pulse interrupts are mainly used for external signals and for rate or repeat signals.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 7-9
Nested Vectored Interrupt Controller
For Pulse interrupts, a bit that is set to 1 indicates that another interrupt has arrived since
the ISR started.
If the level interrupt is guaranteed to have been cleared and then asserted, the status bit
read from the Interrupt Pending Registers is set to 1, as for pulse interrupts.
For level interrupts, where the line might remain HIGH continuously from ISR entry,
write 1 to the appropriate bit of the:
• Interrupt Set-Pending Register
• Interrupt Clear-Pending Register.
The Interrupt Clear-Pending Register is not cleared if the interrupt line is HIGH, and
can be read again to determine the status.
7-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Nested Vectored Interrupt Controller
You can use the Interrupt Clear-Pending Register on page 7-6 to check if the input is
HIGH since it was last accessed.
To check the current status, write 1 to the appropriate bit of Interrupt Clear-Pending
Register. The value on the status bit is cleared if the interrupt line is LOW and the
Interrupt Clear-Pending Register can be read again to determine the status.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 7-11
Nested Vectored Interrupt Controller
7-12 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Chapter 8
Debug
This chapter describes the debug system and how to use it. It contains the following
sections:
• About debug on page 8-2
• Debug control on page 8-5
• ROM table on page 8-13
• BPU on page 8-16
• DW unit on page 8-19
• Debug TCM interface on page 8-24
• Examples of debug register halt, access, and step on page 8-25
• Data address watchpoint matching on page 8-28
• Semiprecise watchpoints on page 8-29.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-1
Debug
• The full debug configuration has four breakpoint comparators and two watchpoint
comparators. This is the default configuration.
• The reduced debug configuration has two breakpoint comparators and one
watchpoint comparator.
Debug facilitates:
• core halt
• core stepping
• core register access while halted
• read/write to:
— TCMs
— AHB address space
— internal Private Peripheral Bus (PPB)
• breakpoints
• watchpoints.
All the debug components exist on the internal PPB, 0xE000ED30 - 0xE000EEFF. Access to
the debug components is only possible when the debug extension is present.
Even when debug is present, you can only access the debug components from the debug
port. Accesses from software are reserved.
Debug control and data access occurs through the Advanced High-performance
Bus-Access Port (AHB-AP). This interface is driven by an external DP component. See
Chapter 9 Debug Access Port for information on the AHB-AP and implementation
options for the external DP component, typically a configurable SWJ-DP. Access
includes:
• The AHB-PPB. Through this bus, the debugger can access debug, including:
— debug control
— DW unit
8-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
— BPU unit
— the ROM Table
— TCMs if configured.
• The AHB address space. The AHB slaves in the debug system always expect
32-bit AHB transfers. If a byte or halfword access is created from the DAP, the
transfer is extended to a 32-bit access and all 32 bits in the register are accessed.
Figure 1-1 on page 1-4 shows the structure of the debug system, indicating how the
AHB-AP can access each of the system components and external buses.
DFSR 0x0 R/W 0xE000ED30 See Debug Fault Status Register on page 8-5
DHCSR 0x0 R/W 0xE000EDF0 See Debug Halting Control and Status Register on page 8-7
DCRSR 0x0 WO 0xE000EDF4 See Debug Core Register Selector Register on page 8-10
DCRDR 0x0 R/W 0xE000EDF8 See Debug Core Register Data Register on page 8-11
DEMCR 0x0 R/W 0xE000EDFC See Debug Exception and Monitor Control Register on page 8-11
BPU_CTRL 0x0 R/W 0xE0002000 See Breakpoint Control Register on page 8-16
BPU_COMP0 0x0 R/W 0xE0002008 See Breakpoint Comparator Registers on page 8-17
BPU_COMP1 0x0 R/W 0xE000200C See Breakpoint Comparator Registers on page 8-17
BPU_COMP2 0x0 R/W 0xE0002010 See Breakpoint Comparator Registers on page 8-17
BPU_COMP3 0x0 R/W 0xE0002014 See Breakpoint Comparator Registers on page 8-17
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-3
Debug
8-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
Note
The processor cannot access the debug control register on the PPB. Accesses are
Reserved if the processor attempts to access debug control. Debug control is accessed
through the DAP.
Multiple flags in the Debug Fault Status Register can be set when multiple debug
conditions occur. The register is sticky read/write clear. This means that it can be read
normally. Writing a 1 to a bit clears that bit.
C_DEBUGEN must be set before any bits in the DFSR are updated.
Figure 8-1 on page 8-6 shows the bit assignments of the Debug Fault Status Register.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-5
Debug
31 5 4 3 2 1 0
Reserved
EXTERNAL
VCATCH
DWTTRAP
BKPT
HALTED
Table 8-4 lists the bit assignments of the Debug Fault Status Register.
[31:5] - Reserved.
8-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
EXTERNAL, VCATCH, DWTRAP, BKPT, and HALTED are not set unless the event
is caught. If C_DEBUGEN is enabled, these events halt the processor and cause it to
enter Debug state.
The purpose of the Debug Halting Control and Status Register (DHCSR) is to:
• provide status information about the state of the processor
• enable core debug
• halt and step the processor.
Figure 8-2 on page 8-8 shows the bit assignments of the Debug Halting Control and
Status Register.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-7
Debug
31 26 25 24 23 18 17 16 15 4 3 2 1 0
S_REGRDY C_MASKINTS
S_HALT C_STEP
S_RETIRE_ST C_HALT
S_RESET_ST C_DEBUGEN
Figure 8-2 Debug Halting Control and Status Register bit assignments
[31:16] WO DBGKEYb Debug Key. 0xA05F must be written whenever this register is written. Reads back as
status bits [25:16]. If not written as Key, the write operation is ignored and no bits
are written into the register.
[31:26] - - Reserved.
[25] RO S_RESET_ST Indicates that the core has been reset, or is now being reset, since the last time this
bit was read. This a sticky bit that clears on read. So, reading twice and getting 1
then 0 means it was reset in the past. Reading twice and getting 1 both times means
that it is currently reset and held in reset.
[24] RO S_RETIRE_ST Indicates that an instruction has completed since last read. This is a sticky bit that
clears on read. You can use this to determine if the core is stalled on a load/store or
fetch.
[23:18] - - Reserved.
[17] RO S_HALT The core is halted in debug state when S_HALT is set.
[16] RO S_REGRDY Register Read/Write to the Debug Core Register Selector Register is available. Set
when the core is halted and there is no core register access in progress.
[15:4] - - Reserved.
[3] R/W C_MASKINTS When this bit is set and debug is enabled, external interrupts, SysTick, and PendSV
are masked. This bit does not affect NMI, Hard Fault or SVCall. When
C_DEBUGEN = 0, this bit has no effect.
8-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
[2] R/W C_STEP Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect.
[1] R/W C_HALT Halts the core. This bit is set automatically when the core halts, for example, on a
breakpoint. This bit clears on core reset. When C_DEBUGEN = 0, this bit has no
effect.
a. Bits [3], [2], [0] are reset by DBGRESETn. Bits [25], [24], [17], [16], [1] are reset by SYSRESETn.
b. Writes to this register with the wrong value in DBGKEY are ignored.
Note
• Only word accesses to the DHCSR are permitted.
• Non-word accesses are treated as if they were word accesses. If a byte or halfword
access is created from the DAP, the transfer is extended to a 32-bit access and all
32 bits in the register are accessed.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-9
Debug
The purpose of the Debug Core Register Selector Register (DCRSR) is to select the
processor register to transfer data to or from.
The register is 17 bits wide. The address and access type are:
Address 0xE000EDF4
Access Write-only
Figure 8-3 shows the bit assignments of the Debug Core Register Selector Register.
31 17 16 15 5 4 0
REGWnR
Table 8-6 lists the bit assignments of the Debug Core Selector Register.
[31:17] - - Reserved
[15:5] - - Reserved
8-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
a. This is the address of the next instruction to be executed. Bit [0] of DebugReturnAddress() is Reserved.
Bit [0] does not affect the EPSR T-bit, which is accessed independently through the xPSR register
selection. Modifying the T-bit in the EPSR has no effect on bit [0] of the DebugReturnAddress() so that
the T-bit and DebugReturnAddress() might be modified in either order when changing between Thumb
and ARM state while halted.
This write-only register generates a request to the core to transfer data to or from Debug
Core Register Data Register and the selected register. Until this core transaction is
complete, bit [16], S_REGRDY, of the DHCSR is 0. You must ensure that S_REGRDY
is HIGH before writing to the DCRSR.
Note
• Writes to this register when C_DEBUGEN=0 are ignored.
• Writes other than word accesses are not permitted.
• Writes with REGSEL other than as indicated are not permitted.
• Reads from this register are not permitted.
• Writes to the IPSR are ignored.
• Bit[1] of the CONTROL register can only be set if the OS extension is present and
the processor is in Thread mode.
The purpose of the Debug Core Register Data Register (DCRDR) is to hold data read
from or written to core registers.
This is the data value written to the register selected by the Debug Register Selector
Register.
The purpose of the Debug Exception and Monitor Control Register (DEMCR) is:
• Global enable for the DW unit.
• Vector catching. That is, causes debug entry on execution of a specified vector.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-11
Debug
Figure 8-4 shows the bit assignments of the Debug Exception and Monitor Control
Register.
31 25 24 23 11 10 9 1 0
Figure 8-4 Debug Exception and Monitor Control Register bit assignments
Table 8-7 lists the bit assignments of the Debug Exception and Monitor Control
Register.
[31:25] - Reserved.
[23:11] - Reserved.
[9:1] - Reserved.
[0] VC_CORERESET Reset Vector Catch. Halt running system if SYSRESETn is asserted.
Debug entry caused by a vector catch is only guaranteed to occur before the execution
of the first instruction of the trapped exception handler. However, another higher
priority exception can be taken. For example, if the VC_HARDERR bit is set, the
processor is able to:
1. Take a Hard Fault exception.
2. Take an NMI exception before the first instruction in the Hard Fault handler.
3. Enter debug state on the first instruction in the NMI handler.
8-12 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
0xE00FF000 0xFFF0F003 SCS [31:0] Points to the System Control Space (SCS) at 0xE000E000. This
includes core debug control registers.
0xE00FF00C 0x00000000 end [31:0] Marks of end of table. Because adding more debug components
is not permitted, this value is fixed.
0xE00FFFCC 0x00000001 MEMTYPE [7:0] System memory map is always accessible from the DAP.
Always set to 0x1.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-13
Debug
[7:0] Preamblea.
[3:0] Preamblea.
[7:0] Preamblea.
[7:0] Preamblea.
Note
The complete:
• JEP106 continuation code is 0x4
• JEP106 ID code for ARM is 0x3B
8-14 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-15
Debug
8.4 BPU
The BPU implements:
• four instruction comparators in the full debug configuration
• two instruction comparators in the reduced debug configuration.
A BP comparator register matching the address of the second half word of a 32-bit
instruction generates the breakpoint.
Figure 8-5 shows the bit assignments of the Breakpoint Control Register.
31 8 7 4 3 2 1 0
Reserved NUM_CODE1
Reserved
KEY
ENABLE
8-16 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
Table 8-9 lists the bit assignments of the Breakpoint Control Register.
[31:8] - RO Reserved.
[7:4] NUM_CODE1 RO Number of comparators. This read-only field and contains either:
b0100 = four instruction comparators in use
b0010 = two instruction comparators in use.
[3:2] - RO Reserved.
[1] KEY WO Key field. To write to the Breakpoint Control Register, you must write a 1 to this
write-only bit. This bit is reads as zero.
Use the Breakpoint Comparator Registers to store the values to compare with the
instruction address.
In the full debug configuration the register address, access type, and reset value are:
Address 0xE0002008, 0xE000200C, 0xE0002010, and 0xE0002014
Access Read/write
Reset value Bit [0] (ENABLE) is reset to b0.
In the reduced debug configuration the register address, access type, and reset value are:
Address 0xE0002008, 0xE000200C
Access Read/write
Reset value Bit [0] (ENABLE) is reset to b0.
Figure 8-6 on page 8-18 shows the bit assignments of the Breakpoint Comparator
Registers.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-17
Debug
31 30 29 28 2 1 0
COMP
Reserved Reserved
BP_MATCH ENABLE
Table 8-10 lists the bit assignments of the Breakpoint Comparator Registers.
[31:30] BP_MATCH This field selects what happens when the COMP address is matched.It is interpreted as:
b00 = no breakpoint matching
b01 = set breakpoint on lower halfword, upper is unaffected
b10 = set breakpoint on upper halfword, lower is unaffected
b11 = set breakpoint on both lower and upper halfwords.
[29] - Reserved.
[28:2] COMP Comparison address. Although it is architecturally Unpredictable whether breakpoint matches
on the address of the second halfword of a 32-bit instruction to generate a debug event, in this
processor it is predictable and a debug event is generated.
[1] - Reserved.
8-18 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
8.5 DW unit
The DW unit implements:
• two comparators in the full debug configuration
• one comparator in the reduced debug configuration.
Note
The information in this section is for both the full and reduced debug configuration
unless otherwise stated.
Use the DW Control Register to check how many comparators are available.
31 28 27 0
NUMCOMP Reserved
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-19
Debug
[27:0] - Reserved.
If the core is not in debug state, the value returned is the instruction address of a recently
executed instruction.
Note
When polling this register the timing of what is running on the core might differ when
compared to not polling if the core makes accesses to the PPB. This is because the core
and the DAP share access to the PPB, where the DAP has higher priority.
[31:0] EIASAMPLE Execution instruction address sample, or 0xFFFFFFFF if the core is halted or DWTENA is LOW
Use the DW Comparator Registers to write the values that trigger watchpoint events.
8-20 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
In the full debug configuration the register address, access type, and reset value are:
Address 0xE0001020, 0xE0001030
Access Read/write
Reset value 0x00000000
In the reduced debug configuration the register address, access type, and reset value are:
Address 0xE0001020
Access Read/write
Reset value 0x00000000
[31:0] COMP DW_COMP to compare against PC or the data address as given by DW_FUNCTION Register.
DW_COMP is always masked using the DW Mask Register value before a compare is done.
Use the DW Mask Registers to apply a mask to data addresses when matching against
COMP.
In the full debug configuration the register address, access type, and reset value are:
Address 0xE0001024, 0xE0001034
Access Read/write
Reset value 0x00000000
In the reduced debug configuration the register address, access type, and reset value are:
Address 0xE0001024
Access Read/write
Reset value 0x00000000
31 4 3 0
Reserved MASK
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-21
Debug
[31:5] - Reserved.
[4:0] MASK Mask on data address when matching against COMP. This is the size of the ignore mask.
So, ~0<<MASK forms the mask against the address to use. That is, DW matching is performed as:
(ADDR & (~0 << MASK)) == (COMP & (~0 << MASK))
For word accesses the two least significant bits are not compared.
For halfword accesses the least significant bit is not compared.
For PC matches the least significant bit is not compared.
Use the DW Function Registers to control the operation of the comparator. Each
comparator can match against either the PC or the data address and halt the core. This
function is in conjunction with DW_COMP.
In the full debug configuration the register address, access type, and reset value are:
Address 0xE0001028, 0xE0001038
Access Read/write
Address 0x00000000
In the reduced debug configuration the register the register address, access type, and
reset value are:
Address 0xE0001028
Access Read/write
Address 0x00000000
31 25 24 23 4 3 2 1 0
MATCHED
8-22 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
[31:25] - Reserved.
[24] MATCHED This bit is set when the comparator matches this bit is cleared on read.
[23:4] - Reserved.
You can use the mask and compare address to specify a watchpoint.
Value Function
b0000 Disabled
b0001-b0011 Reserved
b1000-b1111 Reserved
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-23
Debug
Note
Unless the core is halted or held in reset by SYSRESETn, any debug access to the TCM
memory might conflict with core operation.
8-24 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
This is an example of a debug halt. If you want to halt the processor, perform the
following:
1. Write 0xA05F0003 to the Debug Halting Control and Status Register. This enables
debug and halts the core.
2. Wait for the S_HALT bit of the DHCSR to be set. This indicates that the core is
halted.
This is an example of a debug read register access. If you want to halt the processor and
read a value from one of the core registers, perform the following:
1. Write 0xA05F0003 to the Debug Halting Control and Status Register. This enables
debug and halts the core.
2. Wait for the S_HALT bit of the Debug Halting Control and Status Register to be
set. This indicates that the core is halted.
3. Write the register number that you want to read into the Debug Core Register
Selector Register and set bit [16] to 0 simultaneously.
4. Wait for the S_REGRDY bit in the DHCSR to set. This indicates the core has
completed the read master.
This is an example of a debug register access. If you want to halt the processor and write
a value into one of the registers, perform the following:
1. Write 0xA05F0003 to the Debug Halting Control and Status register. This enables
debug and halts the core.
2. Wait for the S_HALT bit of the Debug Halting Control and Status Register to be
set. This indicates that the core is halted.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-25
Debug
4. Write the register number that you want to write to into the Debug Core Register
Selector Register and set bit [16] to 0 simultaneously.
5. Wait for the S_REGRDY bit in the DCRSR to be set. This indicates the core has
completed the write transfer.
This is an example of a debug step. If you want to step the processor, perform the
following:
1. Write 0xA05F0003 to the Debug Halting Control and Status Register. This enables
debug and halts the core.
2. Wait for S_HALT to be set one in the DHCSR to indicate that the core is halted.
3. Write 0xA05F0005 to the Debug Halting Control and Status Register. This clears
C_HALT and sets C_STEP to one.
4. The core exits debug state, executes one instruction and returns to halted debug
state.
Note
When entering debug halt step, you can set C_DEBUGEN, C_HALT and C_STEP in
one write instruction.
This is an example of a hardware PC breakpoint using the BPU. If you want to halt the
processor with a breakpoint, perform the following:
2. Set the value in BU_COMP0 register to the address of the instruction that you
want to set as a breakpoint to break the execution flow.
8-26 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
• clearing the C_DEBUGEN and C_HALT bits in the Debug Halting Control and
Status Register.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-27
Debug
8-28 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug
Note
The instruction executed can include an exception return sequence or any number of
exception entry sequences.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 8-29
Debug
8-30 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Chapter 9
Debug Access Port
This chapter describes the processor Debug Access Port (DAP). It contains:
• About the DAP on page 9-2
• Debug access on page 9-3
• AHB-AP on page 9-5.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 9-1
Debug Access Port
• Serial Wire JTAG Debug Port (SWJ-DP). This is a standard CoreSight debug port
that combines JTAG-DP and the Serial Wire Debug Port (SW-DP) and allows
switching between Serial Wire and JTAG.
The DP and AP together are referred to as the Debug Access Port (DAP).
DAP
Cortex-M1
SWJ-DP
JTAG-DP
Debug port DAP internal
AHB-AP AHB-AP interface
interface interface
SW-DP
For additional information about the DP components, see the CoreSight Components
Technical Reference Manual.
Note
If your implementation of the DAP does not include both JTAG-DP and SW-DP, you
cannot switch between them.
9-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug Access Port
To enable access to the debug modules at all times, all processor debug logic is reset by
the DBGRESETn signal instead of the SYSRESETn signal. The debug interface and
debug access logic are accessible when SYSRESETn is asserted.
• debug reads from non-debug components, including the core registers, return
unpredictable data.
• accesses from the DAP to the system AHB bus through the AHB Matrix
complete, but the returned read data is unpredictable.
Arbitration between the core and debug is so that DAP accesses always have priority.
This means that polling for an event using the DAP is always possible, but might change
the precise cycle timing of core accesses.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 9-3
Debug Access Port
Caution
• Only use a debugger to write to TCMs when the core is halted.
• Although a debugger can perform debug accesses to TCM when the core is
running, some FPGA RAM implementations might have unpredictable results
when a read and write occur simultaneously to the same location. If this is the
case, you must ensure logic is included to prevent accesses occurring
simultaneously.
The core of the processor has a single address for each TCM for both reads and writes
to enable a non-debug processor to use single-ported RAMs. You can use dual-port
RAMs for TCMs to enable programming before the core of the processor is removed
from reset and to facilitate debug removal.
9-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug Access Port
9.3 AHB-AP
This section describes the AHB Access Port (AHB-AP), for access to a system AHB bus
through an AHB-Lite master. It acts as a slave to the DAP internal bus, driven by only
a single debug port, typically an external SWJ-DP, at any one time. Figure 9-2 shows
the internal structure of the AHB-AP.
DAPCLK HCLK
The AHB-Lite master port supports AHB in AMBA v2.0. The AHB-Lite master port
does not support:
• BURST and SEQ
• Exclusive accesses
• Unaligned transfers.
nCSOCPWRDN Inputb Indicates that the system AHB interface is powered down
a. Tied LOW.
b. Tied HIGH.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 9-5
Debug Access Port
9-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug Access Port
This is the control word used to configure and control transfers through the AHB
interface.
31 28 27 24 23 22 12 11 8 7 6 5 4 3 2 0
TrInProg
DbgStatus
Reserved SPIStatus AddrInc
Reserved
[27:24] R/W Prot Specifies the protection signal encoding to be output on HPROT[3:0].
Reset value is noncacheable, non-bufferable, data access, privileged = b0011.
[23] RO SPIStatus Indicates the status of the SPIDEN port. Always reads as b1.
[7] RO TrInProg Transfer in progress. This field indicates if a transfer is currently in progress on the
AHB master port.
[6] RO DbgStatus Indicates the status of the DBGEN port. Always reads as b1 = AHB transfers permitted.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 9-7
Debug Access Port
[5:4] R/W AddrInc Auto address increment and packing mode on Read or Write data access. Only
increments if the current transaction completes without an Error Response. Does not
increment if the transaction completes with an Error Response or the transaction is
aborted.
Auto address incrementing and packed transfers are not performed on access to Banked
Data registers 0x10-0x1C. The status of these bits is ignored in these cases.
Increments and wraps within a 1KB address boundary, for example, for word
incrementing from 0x1400-0x17FC. If the start is at 0x14A0, then the counter increments
to 0x17FC, wraps to 0x1400, then continues incrementing to 0x149C.
b00 = auto increment off
b01 = increment, single.
Single transfer from corresponding byte lane.
b10 = increment, packed
Word = same effect as single increment.
Byte/Halfword. Packs four 8-bit transfers or two 16-bit transfers into a 32-bit DAP
transfer. Multiple transactions are carried out on the AHB interface.
b11 = Reserved SBZ, no transfer.
Size of address increment is defined by the Size field, bits [2:0].
Reset value = b00.
Table 9-4 shows the AHB-AP Transfer Address Register bit assignments.
[31:0] R/W Address Address of the current transfer. Unaligned address values with respect to the Size field
of the Control/Status Word Register are unsupported.
Reset value is 0x00000000.
9-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug Access Port
Table 9-5 shows the AHB-AP Data Read/Write Register bit assignments.
BD0-BD3 provide a mechanism for directly mapping through DAP accesses to AHB
transfers without having to rewrite the Transfer Address Register (TAR) within a
four-location boundary. BD0 reads/writes from TA. BD1 reads/writes from TA+4.
Table 9-6 shows the AHB-AP Banked Data Register bit assignments.
[31:0] R/W Data If DAPADDR[7:4] = 0x0001, so accessing AHB-AP registers in the range 0x10-0x1C, the
derived HADDR[31:0] is:
• Write mode:
Data value to write for the current transfer to external address TAR[31:4] +
DAPADDR[3:2] + 2'b00.
• Read mode:
Data value read from the current transfer from external address TAR[31:4] +
DAPADDR[3:2] + 2'b00.
Auto address incrementing is not performed on DAP accesses to BD0-BD3.
Banked transfers are only supported for word transfers. Non-word banked transfers are
reserved and Unpredictable. Transfer size is currently ignored for banked transfers.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 9-9
Debug Access Port
[31:0] RO Debug AHB ROM Address Base address of a ROM table. The ROM provides a look-up table for
system components. Set to 0xE00FF000 in the AHB-AP in the initial
release.
31 28 27 24 23 17 16 15 8 7 0
JEDEC
Revision JEDEC code Reserved Identity value
bank
AP
a. Using JEDEC bank 0x0 with a JEDEC code of 0x00 is reserved for
use by ARM.
9-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug Access Port
DAPCLK Drives the DAP bus interface and access control for register read and
writes. DAPCLK must be driven by a constant clock. When started, it
must not be stopped or altered while the DAP is in use.
DAPCLK can be connected to HCLK or can be asynchronous to
HCLK, if there are other APs in the SoC that cannot operate at full
HCLK.
DAPRESETn
Initializes the state of all registers in the AHB-AP.
HPROT encodings
HPROT[3:0] is provided as an external port and is programmed from the Prot field in
the CSW register with the following conditions:
See AHB-AP Control/Status Word Register, CSW, 0x00 on page 9-7 for values of the
Prot field.
HRESP
• AHB-Lite devices do not support SPLIT and RETRY and so HRESP[1] is not
required.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 9-11
Debug Access Port
The AHB-AP cannot initiate a new AHB transfer every clock cycle (unpacked) because
of the additional cycles required to serial scan in the new address or data value through
a debug port. The AHB-AP supports two HTRANS transfer types, IDLE and
NONSEQ.
• When no transfer is in progress and the AHB-AP is still granted the bus then the
transfer is of type IDLE.
The only unpacked HBURST encoding supported is SINGLE. Packed 8-bit transfers or
16-bit transfers are treated as individual NONSEQ, SINGLE transfers at the AHB-Lite
interface. This ensures that there are no issues with boundary wrapping, to avoid
additional AHB-AP complexity.
The DAP internal interface is a 32-bit data bus. 8-bit or 16-bit transfers can be formed
on AHB according to the Size field in the Control/Status Word Register at 0x00. The
AddrInc field in the Control/Status Word Register enables optimized use of the DAP
internal bus to reduce the number of accesses from the tools to the DAP. It indicates if
the entire data word is to be used to pack more than one transfer. Address incrementing
is automatically enabled if packet transfers are initiated so that multiple transfers are
carried out at the sequential addresses. The size of the address increment is based on the
size of the transfer.
See AHB-AP Control/Status Word Register, CSW, 0x00 on page 9-7 for values of the
AddrInc field and AHB-AP Data Read/Write Register, DRW, 0x0C on page 9-9 for Data
Read/Write Register bit values.
9-12 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Debug Access Port
If the current transfer is aborted or the current transfer receives an ERROR response, the
AHB-AP does not complete the following packed transfers.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 9-13
Debug Access Port
9-14 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Chapter 10
External and Memory Interfaces
This chapter describes the processor external and memory interfaces. It contains the
following sections:
• About bus interfaces on page 10-2
• External interface on page 10-3
• Write buffer on page 10-4
• Memory attributes on page 10-5
• Memory interfaces on page 10-6.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 10-1
External and Memory Interfaces
Note
The processor contains an internal PPB for accesses to the Nested Vectored Interrupt
Controller (NVIC), Data Watchpoint (DW) unit, and BreakPoint Unit (BPU).
10-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
External and Memory Interfaces
Processor accesses and debug accesses to external AHB peripherals are implemented
over this bus. Because processor AHB access to zero wait state slaves typically take two
cycles longer than TCM accesses, instructions and data must be contained in TCM
where possible. If on-chip FPGA memory is used for the processor, highest
performance is possible if this is TCM memory, rather than SRAM mapped onto the
AHB interface.
Processor accesses and debug accesses share the external interface. Debug accesses take
priority over processor accesses.
If an external AHB peripheral incorrectly deadlocks the AHB bus, the debugger might
not be able to halt or access the core registers. Contact your implementation team for
FPGA probing tools to debug the system external to the core.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 10-3
External and Memory Interfaces
DMB and DSB instructions wait for the write buffer to drain before completing.
10-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
External and Memory Interfaces
0 0 0 0 Invalid
0 0 0 1 Invalid
0 0 1 0 Instruction fetch
0 0 1 1 Data fetch
0 1 X X Invalid
1 X X X Invalid
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 10-5
External and Memory Interfaces
See Memory interfaces on page A-6 for descriptions of the ITCM and DTCM interface
signals.
The processor does not support wait states for the memory interfaces.
Note
This section describes the ITCM interface. This description also applies to the DTCM
interface.
Table 10-2 shows the ITCMBYTEWR value for different sizes of write accesses.
4'b1111 Word
Figure 10-1 shows the write signal timings for the ITCM interface.
CLK
ITCMADDR
Write address
ITCMWDATA
Write data
ITCMBYTEWR
Write enable
ITCMRD
ITCMWR
ITCMRDATA
10-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
External and Memory Interfaces
For writes, the write address, write data, and control signals are driven on the same
cycle. The write enable signals ensure individual bytes within a word are written
without corrupting the other bytes in the same word. For example, if
ITCMBYTEWR[1] is asserted, bits ITCMBYTEWR[15:8] are written in to byte 1 of
the word at address ITCMADRR.
Figure 10-1 on page 10-6 shows the read signal timings for the ITCM interface.
CLK
ITCMADDR
Read address
ITCMWDATA
ITCMBYTEWR 0
ITCMRD
ITCMWR
ITCMRDATA
Read data
Table 10-3 shows the TCM sizes that are defined through input pins. These sizes are
factored into both the core and debug address decoders.
CFGITCMSZE or
TCM size
CFGDTCMSZE
4'h0 0KB
4'h1 1KB
4'h2 2KB
4'h3 4KB
4'h4 8KB
4'h5 16KB
4'h6 32KB
4'h7 64KB
4'h8 128KB
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. 10-7
External and Memory Interfaces
CFGITCMSZE or
TCM size
CFGDTCMSZE
4'h9 256KB
4'hA 512KB
4'hB 1MB
If you use other values than those that Table 10-3 on page 10-7 shows, the effects are
Unpredictable.
10-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Appendix A
Signal Descriptions
This appendix lists the processor interfaces and the interface signals. Full description of
an interface or signal is given where the interfaces or signals differ from those described
in the appropriate interface specification. It contains the following sections:
• Clocks and Resets on page A-2
• Miscellaneous on page A-3
• Interrupt interface on page A-4
• External AHB-Lite interface on page A-5
• Memory interfaces on page A-6
• AHB-AP interface on page A-9.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. A-1
Signal Descriptions
DAPCLKa Input AHB-AP clock. Can be connected to HCLK or can be asynchronous to HCLK if there
are other APs in the SoC that cannot operate at full HCLK.
SYSRESETn Input System reset. Resets processor and non-debug portion of NVIC. Debug components are
not reset by SYSRESETn.
A-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Signal Descriptions
A.2 Miscellaneous
Table A-2 lists the miscellaneous signals.
HALTEDa Output Indicates halting debug mode. HALTED remains asserted while the core is in debug.
SYSRESETREQ Output Requests that the system reset controller resets the core. It is cleared on reset. Do not
connect this line directly to the reset input, use a flop to hold the reset LOW for a cycle.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. A-3
Signal Descriptions
A-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Signal Descriptions
HADDR[31:0] Output For more information, see the AMBA 3 AHB-Lite Protocol Specification
HBURST[2:0] Output
HPROT[3:0] Output
HRDATA[31:0] Input
HREADY Input
HRESP Input
HSIZE[2:0] Output
HTRANS[1:0] Output
HWDATA[31:0] Output
HWRITE Output
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. A-5
Signal Descriptions
ITCMWR Output Write Enable, set if and only if ITCMBYTEWR is non zero, and only if
ITCMEN is set.
ITCMBYTEWR[3:0] Output Write Enables for each byte, if any of these are set, ITCMWR is also set.
ITCMWDATA[31:0] Output Data to be written to ITCM. Only bytes that ITCMBYTEWR is set for are valid.
ITCMRDATA[31:0] Input Data read from the ITCMADDR. All reads are 32 bit.
CFGITCMSZ[3:0] Input Size encoded onto 4 bits. Tie off at synthesis time to optimize logic for speed, or
wire to a static value at run time to permit more flexibility.
CFGITCMEN[1:0] Input ITCM Alias Enables. Sets the value written into the Upper and Lower ITCM
Alias Enable bits in the Auxiliary Control Register on reset.
CFGITCMEN[1] sets the Upper Alias Enable bit and CFGITCMEN[0] sets the
Lower Alias Enable bit.
The value on these pins must be held constant for at least 2 cycles before
SYSRESETn is deasserted.
DTCMWR Output Write Enable, set if and only if DTCMBYTEWR is non zero, and only if
DTCMEN is set.
DTCMBYTEWR[3:0] Output Write Enables for each byte. If any of these are set, DTCMWR is also set.
A-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Signal Descriptions
DTCMWDATA[31:0] Output Data to be written to DTCM. Only bytes that DTCMBYTEWR is set for are
valid.
DTCMRDATA[31:0] Input Data read from the DTCMADDR. All reads are 32-bit.
CFGDTCMSZ[3:0] Input Size encoded onto 4 bits. Tie off at synthesis time to optimize logic for speed, or
wire to a static value at run time to permit more flexibility.
DBGITCMWR Output Write Enable, set if and only if DBGITCMBYTEWR is non zero, and only
if DBGITCMEN is set.
DBGITCMBYTEWR[3:0] Output Write Enables for each byte, if any of these are set, DBGITCMWR is also
set.
DBGITCMWDATA[31:0] Output Data to be written to ITCM. Only bytes that DBGITCMBYTEWR is set
for are valid.
DBGITCMRDATA[31:0] Input Data read from the DBGITCMADDR. All reads are 32 bit.
DBGDTCMWR Output Write Enable, set if and only if DBGDTCMBYTEWR is non zero, and
only if DBGDTCMEN is set.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. A-7
Signal Descriptions
DBGDTCMBYTEWR[3:0] Output Write Enables for each byte. If any of these are set, DBGDTCMWR is
also set.
DBGDTCMWDATA[31:0] Output Data to be written to DTCM. Only bytes that DBGDTCMBYTEWR is set
for are valid.
DBGDTCMRDATA[31:0] Input Data read from the DBGDTCMADDR. All reads are 32-bit.
A-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Signal Descriptions
DAPRDATA[31:0] Output The read bus is driven by the selected AHB-AP during read cycles when
DAPWRITE is LOW.
DAPREADY Output The AHB-AP uses this signal to extend a DAP transfer.
DAPSEL Input Select signal generated from the DAP decoder to each AP. This signal indicates that
the slave device is selected, and a data transfer is required. There is a DAPSEL
signal for each slave. The signal is not generated by the driving DP. The decoder
monitors the address bus and asserts the relevant DAPSEL.
DAPENABLE Input This signal indicates the second and subsequent cycles of a DAP transfer from DP
to AHB-AP.
DAPWRITE Input When HIGH indicates a DAP write access from DP to AHB-AP. When LOW
indicates a read access.
DAPWDATA[31:0] Input The write bus is driven by the DP block during write cycles when DAPWRITE is
HIGH.
DAPABORT Input Aborts the current transfer. The AHB-AP returns DAPREADY HIGH without
affecting the state of the transfer in progress in the AHB Master Port.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. A-9
Signal Descriptions
A-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Glossary
This glossary describes some of the terms used in technical documents from ARM
Limited.
Abort A mechanism that indicates to a core that the attempted memory access is invalid or not
allowed or that the data returned by the memory access is invalid. An abort can be
caused by the external or internal memory system as a result of attempting to access
invalid or protected instruction or data memory.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. Glossary-1
Glossary
Glossary-2 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Glossary
Base register A register specified by a load or store instruction that is used to hold the base value for
the instruction’s address calculation. Depending on the instruction and its addressing
mode, an offset can be added to or subtracted from the base register value to form the
address that is sent to memory.
Base register write-back
Updating the contents of the base register used in an instruction target address
calculation so that the modified address is changed to the next higher or lower
sequential address in memory. This means that it is not necessary to fetch the target
address for successive instruction transfers and enables faster burst accesses to
sequential memory.
Beat Alternative word for an individual data transfer within a burst. For example, an INCR4
burst comprises four beats.
BE-8 Big-endian view of memory in a byte-invariant system.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. Glossary-3
Glossary
Burst A group of transfers to consecutive addresses. Because the addresses are consecutive,
there is no requirement to supply an address for any of the transfers after the first one.
This increases the speed at which the group of transfers can occur. Bursts over AMBA
are controlled using signals to indicate the length of the burst and how the addresses are
incremented.
Glossary-4 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Glossary
Endianness Byte ordering. The scheme that determines the order that successive bytes of a data
word are stored in memory. An aspect of the system’s memory mapping.
Interrupt vector One of a number of fixed addresses in low memory that contains the first instruction of
the corresponding interrupt service routine.
Joint Test Action Group (JTAG)
The name of the organization that developed standard IEEE 1149.1. This standard
defines a boundary-scan architecture used for in-circuit testing of integrated circuit
devices. It is commonly known by the initials JTAG.
JTAG See Joint Test Action Group.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. Glossary-5
Glossary
Glossary-6 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Glossary
Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the
pipeline before the preceding instructions have finished executing. Prefetching an
instruction does not mean that the instruction has to be executed.
Prefetch Abort An indication from a memory system to the core that an instruction has been fetched
from an illegal memory location. An exception must be taken if the processor attempts
to execute the instruction. A Prefetch Abort can be caused by the external or internal
memory system as a result of attempting to access invalid instruction memory.
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. Glossary-7
Glossary
Glossary-8 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D
Glossary
ARM DDI0413D Copyright © 2006-2008 ARM Limited. All rights reserved. Glossary-9
Glossary
Glossary-10 Copyright © 2006-2008 ARM Limited. All rights reserved. ARM DDI0413D