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FPGA-Based PID Controller Implementation

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 FPGA-Based PID Controller Implementation

Mohamed Abdelati
The Islamic University of Gaza
Gaza, Palestine

:!‫ﻠﺨ‬$
!‫ﻴ‬#$!‫ﻫﺎ‬ .
.
.
FPGAs
.
.

Abstract: Proportional-Integral-Derivative (PID) controllers are widely used in au-

tomation systems. They are usually implemented either in hardware using analog
components or in software using computer-based systems. They may also be imple-
mented using Application Specific Integrated Circuits (ASICs). This paper outlines
several modules necessary for building PID controllers on Field Programmable Gate
Arrays (FPGAs) which improve speed, accuracy, power, compactness, and cost ef-
fectiveness. Two PID controllers for speed and position utilizing these modules are
implemented and used as experimental platforms to illustrate and test the designed
modules.

1 Introduction

There are two approaches for implementing control systems using digital technol-
ogy. The first approach is based on software which implies a memory-processor
interaction. The memory holds the application program while the processor fetches,
decodes, and executes the program instructions. Programmable Logic Controllers
(PLCs), microcontrollers, microprocessors, Digital Signal Processors (DSPs), and
general purpose computers are tools for software implementation.


This research was supported by the Ministry of Higher Education in Palestine.

1
On the other hand, the second approach is based on hardware. Early hardware
implementation is achieved by magnetic relays extensively used in old industry au-
tomation systems. It then became achievable by means of digital logic gates and
Medium Scale Integration (MSI) components. When the system size and complex-
ity increases, Application Specific Integrated Circuits (ASICs) are utilized. The
ASIC must be fabricated on a manufacturing line, a process that takes several
months, before it can be used or even tested [1]. FPGAs are configurable ICs and
used to implement logic functions. Early generations of FPGAs were most often
used as glue logic which is the logic needed to connect the major components of
a system. They were often used in prototypes because they could be programmed
and inserted into a board in a few minutes, but they did not always make it into the
final product. Today’s high-end FPGAs can hold several millions gates and have
some significant advantages over ASICs. They ensure ease of design, lower de-
velopment costs, more product revenue, and the opportunity to speed products to
market. At the same time they are superior to software-based controllers as they are
more compact, power-efficient, while adding high speed capabilities [2].

The target FPGA device used in this research is Spartan-3 manufactured recently
by Xilinx [3]. Design development and debugging is carried on a low-cost, full
featured kit provided by Digilent [4]. This board, which costs less than a 100$,
provides all the tools required to quickly begin designing and verifying Spartan-3
platform designs. While the implemented modules are also suited to other high den-
sity FPGAs, designs are based on 50 MHz clock and should be updated if different
frequency is used.

In control systems, the majority of actuating signals and sensor returns are analog
signals. Therefore, analog to digital and digital to analog conversion plays an im-
portant role in digital controllers. These converters are located at the boundary of
the digital controller. Usually there are some modules within the digital system
that facilitate communication with these converters. In addition, digital controllers
usually encompass input/output (I/O) modules to communicate with users. Push-
buttons and seven segment displays are well suited to small size and compact con-
trollers. Along with these four mentioned building blocks a pulse width modulation
(PWM) device and an optical encoder interface adapter will be designed. They are
used as building blocks in many control applications such as speed and position
control. One more building block for digital filters will be addressed in this work.
It is essential to implement transfer functions in PID controllers.

2
The rest of this paper is organized as follows. In Section 2 relevant work is ad-
dressed. In Section 3, the building blocks are constructed. In Section 4, experimen-
tal work is described. Finally in Section 5, conclusions and suggestions for future
work are outlined.

2 Relevant work

Modern FPGAs and their distinguishable capabilities have been advertised exten-
sively by FPGA vendors. Moreover, some refereed articles addressed the advan-
tages of utilizing these powerful chips [2][5]. In the past two years, Spartan II
and III FPGA families from Xilinx have been successfully utilized in a variety of
applications which include inverters [6][7], communications [8][9], imbedded pro-
cessors [10], and image processing [11].

The implementation of PID controllers using microprocessors and DSP chips is old
and well known [12][13], whereas very little work can be found in the literature on
how to implement PID controllers using FPGAs. The scheme proposed in [14] is
based on a distributed arithmetic algorithm where a Look-Up-table (LUT) mecha-
nism inside the FPGA is utilized. The contribution focused on power and area issues
while FPGA interfacing is totally unaddressed. In our work we introduce a simple
method for implementing PID controllers together with many related constructing
modules. Some other contributions focused on proposing algorithms for tuning the
coefficients of PID controllers using FPGAs while the controller itself is still im-
plemented in software. These contributions are considered complementary to our
work as they provide tools for building adaptive PID applications. In [15] [16] two
different algorithms for fuzzy PID gain conditioner algorithm are proposed. Both
are based on fuzzy control that tunes the PID controller on-line.

A PWM generator is introduced in [17]. However, only simulation results are

presented and the proposed algorithm results in greater consumption of FPGA re-
sources compared to our algorithm which is tested experimentally. However, de-
spite its complexity, the algorithm in [17] is superior in terms of harmonic content
and is more suited to inverter applications.

In [18] the authors describe the architecture of a data acquisition system for a
gamma-ray imaging camera. The system has been designed by using Xilinx Spar-
tan II devices and 12-bit parallel A/D converters. In our work, data acquisition for

3
 CLK50

Sample

CONVST

ADIA SCLK

int 1 2 3 4 5 6 7 8
Sin

ISR 1 2 3 4 5 6 7 8

OSR=DB unvalid valid

int
1ms 4ms The Data is latched from the
internal Input Sift Register
(ISR) to the Output Shift
(a) (b) Register (OSR)

Figure 1. A/D converter interface and timing diagram.

the PID controller, which is implemented using Xilinx Spartan III, is based on 8-bit
serial A/D converters. Similar converters are utilized in [19] to implement an adapt-
able strain gage conditioner using FPGAs. While being a smart data acquisition
approach, it is costly as it is based on a soft intellectual property (IP) processor.

3 PID building blocks

In this section, implementation of analog input interface, analog output interface,

pulse width modulation, optical encoder interface, user interface, and digital filters
are introduced. These building blocks are the major blocks that are essential for
implementing most PID controllers on FPGAs.

3.1 Analog input interface

FPGAs are well suited for serial Analog to Digital (A/D) converters. This is mainly
because serial interface consumes less communication lines while the FPGA is fast
enough to accommodate the high speed serial data. The AD7823 is a high speed,
low power, 8-bit A/D converter [20]. The part contains a 4  s typical successive
approximation A/D converter and a high speed serial interface that interfaces easily
to FPGAs as illustrated in Figure 1a.

The A/D interface adapter (ADIA) is implemented within the FPGA. Inside the
FPGA, this adapter facilitates parallel data acquisition. Sampling is initiated at the

4
 CLK50
AD 7303
SYNC
SYNC SCLK
VA
DAIA
VB
Sout SYNC
OSR Din

Sout 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
CB DB
The Data is latched from
the control and data
buses to the Output Sift
(a) Register (OSR) (b)

Figure 2. D/A converter interface and timing diagram.

rising edge of a clock applied at the line sample. Once conversion and transmission
is completed, a pulse is generated at the interrupt line (int ) and the parallel data
will be available at the Data Bus (DB ). The timing diagram of the communication
protocol is illustrated in Figure 1b. The whole conversion and acquisition period is
5.4  s allowing sampling up to a rate of 185 Kilo Sample per second. This rate is
more than sufficient for most PID control applications.

3.2 Analog output interface

The AD7303 is a dual, 8-bit voltage out Digital to Analog (D/A) converter [21].
This devive uses a verstile 3-wire serial interface that operates at a clock up to 30
MHz. The serial input register is 16 bits wide; 8 bits act as data bits for the D/A
converter, and the remaining 8 bits make up a control register. It is interfaced to an
FPGA as illustrated in Figure 2a.

The D/A interface adapter (DAIA), which is implemented within the FPGA, facil-
itates parallel data input for the dual D/A converters. A logic zero on the synchro-
nization signal (SYNC ) enables the shift register at the D/A chip to receive data
from the DAIA’s serial data output (Sout ). Its serial clock (SCLK ) frequency is 25
MHz which is half of the master clock (CLK50 ) frequency. Data is clocked into
the shift register on the rising edge of the serial clock and it is sent most significant
bit (MSB) first. Each transfer must consist of a 16-bit packet which is described
in Table 1 while the timing diagram of the communication protocol is illustrated in
Figure 2b. The transmission period of a sample is 680 ns allowing D/A conversion
at an excellent rate of 1.47 MHz.

5
 Table 1. Description of the D/A data packet.

Location Mnemonic Description

15  /EXT Select between internal and external reference.
14 X Uncommitted bit.
13 LDAC Load DAC bit for synchronous update of DAC outputs.
12 PDB Power-down converter B.
11 PDA Power-down converter A.
10  /B Address bit to select either converter A or converter B.
9 CR1 Control Bit 1 used to implement the various data loading functions.
8 CR0 Control Bit 0 used to implement the various data loading functions.
7-0 DATA 8-bit data word where DB7 is the MSB.

Analog
Signal

Sampling Period
Vcc

PWM
Signal
t
M DC Motor

t
a

Variable Pulse Widths

PWMD PWMout BUK555-60A
DB
220W

Constant Pulse Periods

(a) (b)

Figure 3. Pulse width modulation waveforms and hardware.

3.3 Pulse width modulation

Switching power converters are used in most DC motor drives to deliver the required
energy to the motor. The energy that a switching power converter delivers to a
DC motor is controlled by Pulse Width Modulated (PWM) signal applied to the
gate of a power transistor. PWM signals are pulse trains with fixed frequency and
magnitude and variable pulse width. There is one pulse of fixed magnitude in every
Pulse Width Modulation (PWM) period. However, the width of the pulses (duty
cycle) changes from pulse to pulse according to a modulating signal as illustrated
in Figure 3a.

A pulse width modulation device (PWMD) implemented within an FPGA and used
to control a DC motor through a Mosfet transistor driver is illustrated in Figure 3b.
The modulating signal is supplied in 8-bit digital format. With 50 MHz synchro-
nization clock, a minimum pulse width of 20 ns for the synchronization clock period
is obtained. Therefore, 
  
ns period is necessary to represent the 256
levels of the modulating signal. This allows a maximum PWM frequency of about
195 KHz. However, such a high frequency is unnecessary and may cause undesir-

6
 1 cycle clockwise
o
90

Channel A
l Enc
A Channel A ca

od
Opti
OEIA B Channel B

er
Channel B I Index
DB

Index

(a) (b)

Figure 4. Optical encoder output waveforms and FPGA interface.

able effects. It contains more high frequency harmonics and its very short pulse
widths may be unable to trigger the transistor driver. In most control applications,
the maximum frequency content of the modulating signal is very low and a PWM
frequency of about 50 Hz is suitable. A 20-bit counter runs at 50MHz completes
cycles at a rate 50M  ! Hz. In this case, each level in an 8-bit modulating
signal corresponds to   "# %$  clock pulses. Therefore, in order to gener-
ate a PWM signal at a frequency of about 47 Hz for an 8-bit modulating signal,
the modulating signal is multiplied by $  and a 20-bit counter with 50 MHz clock
is fired. Then, this counter is compared with the scaled modulating signal. If the
scaled modulating signal is larger, the PWM output is set to one, otherwise, it is set
to zero.

3.4 Optical encoder interface

An incremental optical encoder is basically an instrumented mechanical light chop-

per. It produces a certain number of square pulses for each shaft revolution. Sin-
gle channel type encoder has one output only while phase-quadrature type has two
channels whose pulse trains are &
' out of phase as illustrated in Figure 4a. Un-
like single-channel encoders, the phase-quadrature encoders are able to detect the
direction of rotation. An external electronic circuit determines which channel is
leading the other and hence ascertain the direction of rotation. In order to provide a
reference for the angular position information, most encoders incorporate an index
output that goes high once for each complete revolution of the shaft [22].

Figure 4b illustrates interfacing an optical encoder to an FPGA. The optical encoder

interface adapter (OEIA) helps decoding the encoder signals and provides an abso-
lute value for the angular displacement. At the rising edge of Channel A signal, the
value of Channel B is monitored. If it is found logic low, then clockwise rotation

7
 DOUN
PB(0)
DB
VCC1 UP
PB(1)
PBIA
CLK50
4.7KW
BCD

7
6
5
4

Row
3
2
SSIA
1
0 Column
3 2 1 0

4.7KW VCC2

T2A42
100W
6

1 5
0

2 4

3 7
Common anode

Figure 5. Push-buttons and multiplexed 7-segment displays interfacing.

is concluded and the value of DB is incremented by one. On the other hand, if

Channel B is found logic high, counterclockwise rotation is inferred, and hence, the
value of DB is decremented by one. The Index signal is asynchronous as it is eval-
uated before Channel A rising edge action. Once this signal is detected, the value
of DB is reset. This helps initial condition setup and also run-time correction for
any possible drift caused by noise.

3.5 User interface

An input module that implements a simple technique widely used in digital equip-
ments is implemented. This module utilizes two push-buttons to input an 8-bit
value. Pressing on the UP push-button increments the input register while pressing
on the DOWN push-button decrements it. The module handles the bounce effect
of the push-buttons and adjusts scanning cycle of the push-buttons according to the
period of time a push-button is pressed. On the other hand, a module that facilitates
displaying Binary Coded Decimal (BCD) digits on 4 multiplexed 7-segment display
units is designed. This general purpose module is utilized here to display the value
of the input register of the input module.

Figure 5 illustrates interfacing the input push-buttons and the multiplexed 7-segment
display units. The push-buttons interface adapter (PBIA) overcomes the bounce ef-
fect, calculates the input value, supplies it to the data bus (DB ), and generates its
BCD code for possible display on 7-segment display units. The seven segments

8
interface adapter (SSIA) accepts a 16-bit BCD number and generates the scan pat-
terns necessary to display the coded decimal number on the 7-segment display units
which are multiplexed at a rate of 1KHz.

The bounce effect is eliminated by scanning the push-buttons at a rate with time
period larger than the bounce time of the push-buttons. A bounce might last for
few tens of milliseconds. Therefore, the default scanning period used in the PBIA,
which is about 167.77 ms, cancels the bounce effect and yet allows fast sensitivity
for the input. This scan period is made adaptive according to the last 5 input samples
of the push-buttons. This history information about the input samples is used to
adjust the scan rate.

3.6 Digital filters

While integer addition, subtraction, and multiplication operators are inferred by the
synthesis tool, division as well as floating point arithmetic are not supported. When
the divisor is an order of 2, division may be carried easily by shift operation. How-
ever, when the divisor is an arbitrary number, division is not straight forward and
considered to be a difficult and time consuming operation. Little is available in the
literature for VHDL source code of floating point arithmetic modules. Although
there are some limited contributions available on the Internet [23], they are not of-
ficially refereed and tested by experts. The majority of contributions are not open
source and sold commercially as Intellectual Property (IP) cores [24]. While they
are not free, IP cores consume a substantial amount of the FPGA resources. One
may avoid division in filter implementation by some normalization tricks. To illus-
trate these methods and compare their performance, consider the transfer function
of a first order filter given by

. ),+%- 0 0 +!3
(*),+%- $
 / ),+%-  21 $+ 3 (1)
 $
154 $

The time domain relationship between the input 6 and the output 7 at time 8 is given
by

) - 0 ) - 0 ) - ) -
7 8  6 8 6 8:9; 9 7 8:9; (2)
 1 $ 4 $

In order to avoid floating point computation, the designer should restrict all data

9
representation to be integers. The communication with all interface devices is al-
ready specified to have 8-bit data width. Therefore, in order to calculate the right
hand side of Equation 2 using 2’s complement arithmetic, the coefficients must be
rounded to integers. Unfortunately, this will not work as most of these coefficients
are usually less than one or they spread a very small part of the available data do-
main. This can best be illustrated by examining the coefficients of the following
filter which is used in the position controller example that is given in next section.

) - ) - ) - ) -
7 8 <&>= ?&6 8 9@&>=AB%?6 89;
>= C%B7 89; (3)
1

One way to overcome this trouble is to scale the equation by a suitable large number
( D ) which is an order of 2 so that the scaled coefficients in the right side are fairly
spread and rounded. Then the number of bits required to represent these scaled
coefficients are determined. Denoting the integer rounding operator by EGF , then
Equation 3 is approximated by

0 ) - 0 ) - ) -
) - EID F6 8 EID F6 8:9; E9JD F7 8:9;
7 8 HE  1 $ 1 4 $ F (4)
D

Since D is chosen to be a power of 2, division is simply handled by shifting opera-

tion. This approach while being easy will not provide satisfactory results whatever
the value of D . This is because D helps only to increase the resolution of the filter
coefficients. But there is another source of error which is rounding the value of 7
each time, the fact that it influences the upcoming values in this recursive formula.
This crude approximation method is used in the filter example specified in Equa-
tion 3 with DKLM . The resulting unit step response is shown in Figure 6 and
labeled “Crude approximation.”

In order to achieve fine approximation, the amount of information lost after each
recursive iteration should be reduced. This can be done by keeping the quantity
) - ) -
DNO7 8 instead of 7 8 and utilizing it in the upcoming iteration. This approach
leads to

) -
) - 0 ) - 0 ) - DNR7 8S9T
D  7 8 PEID  F6 8 EID  F6 8:9; 9QEID FG@E F (5)
 1 $ 4 $ D

The block diagram implementation is illustrated in Figure 7. Using this method

with DUVM for the example filter used above, the filter’s unit step response will

10
 10

Filter output
Crude approximation

Fine approximation
2
Exact

k
5 10 15 20 25 30

Figure 6. Unit step response of the filter.

Input 8-bits
8-bit 8-bit 12-bit
u(k) u(k-1) Ny(k-1)

b0 N
2
x b1 N
2
x -a1 N x
13-bit 13-bit 5-bit

S
21-bit
N2 y(k)

N = 16 bit[15:8] bit[7] bit[15:4] bit[3]

a1 = - 0.865
S S
b0 = 9.639
b1 = - 9.543
Output 8-bits

Figure 7. Implementing Equation 5.

be as shown in Figure 6. It is labeled “Fine approximation” in the figure.

4 Experimental work

This section aims to integrate the modules designed earlier in some practical exam-
ples so that they are tested and illustrated. The first example is a standard DC-motor
speed control while the other one addresses demonstration of position control of an
unmanned electrical dual rotor helicopter.

4.1 DC-motor speed controller

Figure 8 represents a block diagrams of a feedback motor speed control system.

The formula for this basic proportional closed-loop system is

11
 w

DC Motor
B
A

+ + + 1 DC to PWM + + A
r K y
-S S
A (unity gain)
S
(t1 s+1)(t2 s+1)

Tachometer
(unity gain)

Figure 8. Proportional feedback control of a DC-Motor.

12V
mechanical
coupling
Speed_Controller + +
M G
yr PsiRef CLK50 y
+ + Ybuf Y
PBIA S K
+ S PWMD
BUK555-60A
- 220W
Rp=10KW
SSIA ADIA AD7823
Psi
100nF Rx

Figure 9. DC-motor speed control using FPGA.

Y ^
W )IX-  WJ] )IX- )IX-
 )[Z X -\)[Z 1 X - Y )[Z X -\)[Z X - YQ_ (6)
  1  
$ 1  1 1 $ 1  1 1

Y Z Z
where is the gain of the proportional controller, and , as well as the con-
^ $ 
stants and ` (appears in the figure) are expressed in terms of the DC motor
Wa] )IX- )IX-
variables [25]. and _ are the Laplace transforms of the reference speed
)cb ] )[de-e- )[de-
and the load torque ( f ) respectively. If these quantities are constants,
b ] )[de- b ] )[de-
that is  and f Qf , then the steady-state speed is given by

^
b2gIg b ]
 ) Y - f (7)
1 
1

The DC motor used in this experimental example has a rated voltage 12V, a rated
speed 2500 rpm, and equipped with a tachometer which generates 18V at rated
speed. A value of K=64 is found suitable for a good dynamic response of the
system. Using FPGA technology, the system may be implemented as illustrated
in Figure 9. The input module (PBIA) is supposed to handle entering the reference
speed which will be any value from 0 to 2500 or as a percentage from 0% to 100%.

12
However, as 8-bit A/D converter will be used to read the actual speed, it makes no
sense to have very fine reference speed specification. As the actual speed will be
quantized to a maximum of 256 levels, the reference speed is better specified in 256
or less levels. Taking the speed step to be 10, a total of 250 steps will be used to
cover the whole speed range.

The feedback signal is a low pass signal. Thus, the voltage divider and the capacitor
at the entrance of the A/D converter are implemented to act as a low pass filter that
suppresses any potential high frequency noise. Moreover, the voltage divider acts
as a signal conditioner device that maps the sensor signal to the convertible input
range of the A/D converter. In this experiment a 3.3V reference voltage is used for
the converter which implies that in order to utilize the whole range of the converter
the range of the feedback signal should be treated to be from 0 to 3.3V. As the rated
speed will be represented by the number 250, its corresponding input voltage will
be ?>= ?h i j?>=A ?%?%k . Therefore, the voltage divider ratio is
ii
lnm
?>=A ?%?
lpoq j
>=r&%
MC

A M
sut sensitive potentiometer is used to implement this voltage divider. It should
be noted that these precise calculations are just to clarify design steps and method-
ology. However, realization is easier; once the system is built, a certain reference
speed is set and the actual speed is measured using a tachometer. Then the poten-
tiometer is adjusted so that the measured speed is matched to the input reference
speed.

The top-level module of the motor controller will utilize the PBIA, SSIA, ADIA,
and PWMD modules developed earlier. Therefore, these components are declared
and instanced properly. The module basically consists of 3 processes: The first one
generates the sampling clock from CLK50. The maximum permissible sampling
clock frequency is 185 KHz which is determined by the A/D converter as mentioned
in Section 3.1. For this simple application, sampling clock frequency in the order
of few hundreds is sufficient. This clock is connected to the “Sample ” port of
ADIA. Consequently, this adapter generates interrupt pulses at its port “int ” after
each sample acquisition as illustrated earlier in Figure 1. These pulses are used to
synchronize the other two processes. One process works at the rising edge of the
“int ” signal to calculate the unsaturated output while the other process works at
the falling edge of the “int ” signal to register this output after handling saturation
conditions.

13
 Figure 10. The FPGA-based DC-motor speed controller implementation.

potentiometer

counter moment of inertia =J

wight
l
optical encoder
l
mg
h

y
x

Figure 11. An unmanned helicopter model and its free-body diagram.

The pinouts of the target FPGA are specified and the standard design procedure is
followed to generate and download the configuration file. The implemented system
is shown in Figure 10. It worked properly as expected.

4.2 Position controller

The second experiment demonstrates position control of an unmanned electric dual

rotor helicopter using the model shown in Figure 11. Each rotor in this model is
powered by a 12V rated DC motor. While generating force in a direction perpen-
dicular to the body, rotors rotate in opposite directions so that they almost cancel the
moment in that direction. The control variables of the system are the elevation ( v )
and the slope angle ( w ). These two physical quantities are measured in our model
by means of a potentiometer and an optical encoder respectively.
)[de-
The force ( x ) generated by each rotor is adjusted by changing its speed. There-
fore, this force, which is proportional to the speed of a DC motor, is related to its
)[de-
voltage ( y ) in the Laplace domain as follows [25]:

14
 )IX-
z )IX- ` k
 )[Z X { $ $\
- )[Z $ X - (8)
$  
$$ 1 $  1

)IX-
z )IX- ` k
 )[Z X {  \
- )[Z  X - (9)
  
 $ 1  1
Z Z Z Z
where , ` , , , , ` , , and are constants. The angular acceleration
{ $ $ $$ $  {    $ 
along the x-axis equals the net torque in this direction divided by the model’s mo-
ment of inertia ( | ) at the axis of rotation. Therefore, the angular displacement ( w )
is given by

}h)IX- ) z )IX- z )IX-e-~

 9 X (10)
$  | 

where ~ is the force-arm length. The net vertical force is the summation of the two
forces multiplied by cos( w ) minus the effective weight of the model1 . However,
since w is small, the cosine factor may be safely dropped. The resultant vertical
acceleration equals the net vertical force divided by the model’s effective mass (€ ).
Therefore, the vertical displacement ( v ) is given by

 )IX- ) z )IX- z )IX- - 

 9"€‚ X (11)
$ 1  € 

where ‚ is the acceleration of gravity. This described feedback control system may
] ]
be modeled as shown in Figure 12. In this system, v and w represent the reference
points of the elevation and slope respectively while v and w are the actual measured
values. The error signal in v influences both forces in the same direction whereas
the error signal in w influences them in opposite directions. The elevation and slope
controllers are decoupled to simplify design and implementation.

This model is digitized and Matlab is used for simulation and estimation of the PID
filters’ parameters. It is found that
+!3
(*),+%- &>= ?&a9@&>=AB%? $
 + 3 (12)
ƒ9@
>= C% $
1
Similar to elevators, a counter weight is used to minimize the force necessary to move the body.
Therefore, the effective mass („ ) equals the mass of the main body minus the mass used in the
counter weight. Equivalently, the effective weight equals the weight of the main body minus the
counter weight.

15
 mg
-
hr
+ S D(s)
+ S
V1 q1 A 1 F1 + S
1
h
(t11 s+1)(t12 s+1) ms2
+

+ + S+ q2 A 2 + l
qr S G(s) S q
V2 (t21s+1)(t22 s+1) F2 Js2
-

Figure 12. Block diagram of the position control system.

Position_Controller

Column(3:0) CONVST
SSIA ADIA SCLK1
Row(7:0) Sin

PB(0) -
PBIA1
+ S D(s)
+ S PWMD1 PWMout1
PB(1) +
CLK50

PB(2) +
PBIA2 S G(s)
+ S PWMD2 PWMout2
PB(3)
-
SYNC Channel A
SCLK2 DAIA EIA Channel B
Sout 00000100 Index

Figure 13. The top-level module of the position controller.

and

+!3
… ),+%- >= %C% J9@>= ?& $
 + 3 (13)
ƒ9"
>= &>M? $

insures good dynamic response behavior. The top-level module of the position con-
troller is illustrated in Figure 13. Push-buttons PB(0) and PB(1) are used to enter
the elevation set point which is echoed on seven segment displays. On the other
hand, push-buttons PB(2) and PB(3) are used to enter the slope set point which is
displayed on an analog voltmeter. The rest of work is similar to what is done in the
first experiment. Upon running the system, it is noticed that the angle control works
perfectly while the elevation control has some lazy behavior. This unexpected be-
havior is reasoned by considerable friction encountered in the vertical mounting
beam. However, as an overall performance, results are good and fulfil the aim of
the experiment.

16
5 Conclusions

Today’s high-speed and high-density FPGAs provide viable design alternatives to

ASIC and microprocessor-based implementations. Several building modules for
implementing PID controllers on these FPGAs are constructed in this work. These
modules are tested successfully through two experimental platforms.

Algorithms and implementations are described in sufficient details from a practical

point of view for readers to digest the addressed subject and replicate the work. The
VHDL code of all presented modules and examples may be obtained directly from
the author.

Implementing PID controllers on FPGAs features speed, accuracy, power, com-

pactness, and cost improvement over other digital implementation techniques. In a
future fork we plan to investigate implementation of fuzzy logic controllers on FP-
GAs. Also we plan to explore embedded soft processors, such as MicroBlaze, and
study some applications in which design partitioning between software and hard-
ware provides better implementations.

Acknowledgment: The author is grateful to his Fulbright host at Texas A&M uni-
versity, Dr. Reza Langari, for his kind company and helpful research environment.

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