ALC268-GR

ALC268Q-GR

2+2 CHANNEL HIGH DEFINITION AUDIO CODEC

DATASHEET

Rev. 1.0
04 September 2006
Track ID: JATR-1076-21

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw

ALC268 Series
Datasheet
COPYRIGHT
2006 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER
Realtek provides this document as is, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.

TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document is intended for the hardware and software engineers general information on the Realtek
ALC268 Series Audio Codecs.
Though every effort has been made to assure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.

REVISION HISTORY
Revision
1.0

Release Date
2006/09/04

Summary
First release.

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Table of Contents
1.

General Description .................................................................................................... 1

2.

Features ........................................................................................................................ 2
2.1.
2.2.

HARDWARE FEATURES .....................................................................................................................2

SOFTWARE FEATURES ......................................................................................................................3

3.

System Applications .................................................................................................... 3

4.

Block Diagram ............................................................................................................. 4

4.1.

5.

Pin Assignments........................................................................................................... 5
5.1.
5.2.
5.3.

6.

ALC268-GR (LQFP-48)..................................................................................................................5
ALC268Q-GR (QFN-48) ................................................................................................................6
GREEN PACKAGE AND VERSION IDENTIFICATION ............................................................................6

Pin Descriptions........................................................................................................... 7
6.1.
6.2.
6.3.
6.4.

7.

ANALOG INPUT/OUTPUT UNIT .........................................................................................................4

DIGITAL I/O PINS .............................................................................................................................7

ANALOG I/O PINS .............................................................................................................................8
FILTER/REFERENCE/NOT CONNECTED .............................................................................................9
POWER/GROUND ..............................................................................................................................9

High Definition Audio Link Protocol ...................................................................... 10

7.1.
7.1.1.
7.1.2.

7.2.
7.2.1.
7.2.2.
7.2.3.
7.2.4.
7.2.5.

7.3.
7.3.1.
7.3.2.
7.3.3.

7.4.
7.4.1.
7.4.2.

7.5.

LINK SIGNALS ................................................................................................................................10

Signal Definitions ................................................................................................................................................. 11
Signaling Topology ...............................................................................................................................................12

FRAME COMPOSITION.....................................................................................................................13
Outbound Frame Single SDO............................................................................................................................13
Outbound Frame Multiple SDO ........................................................................................................................14
Inbound Frame Single SDI ................................................................................................................................15
Inbound Frame Multiple SDI ............................................................................................................................16
Variable Sample Rates..........................................................................................................................................16

RESET AND INITIALIZATION............................................................................................................19

Link Reset .............................................................................................................................................................19
Codec Reset ..........................................................................................................................................................20
Codec Initialization Sequence ..............................................................................................................................21

VERB AND RESPONSE FORMAT .......................................................................................................22

Command Verb Format ........................................................................................................................................22
Response Format..................................................................................................................................................22

POWER MANAGEMENT ...................................................................................................................23

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8.

Supported Verbs and Parameters............................................................................ 24

8.1.

VERB GET PARAMETERS (VERB ID=F00H) .................................................................................24

8.1.1.
8.1.2.
8.1.3.
8.1.4.
8.1.5.
8.1.6.
8.1.7.
8.1.8.
8.1.9.
8.1.10.
8.1.11.
8.1.12.
8.1.13.
8.1.14.
8.1.15.
8.1.16.

8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
8.11.
8.12.
8.13.
8.14.
8.15.
8.16.
8.17.
8.18.
8.19.
8.20.
8.21.
8.22.
8.23.
8.24.
8.25.
8.26.
8.27.
8.28.
8.29.
8.30.

Parameter Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................24

Parameter Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................24
Parameter Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................25
Parameter Function Group Type (Verb ID=F00h, Parameter ID=05h) ...........................................................26
Parameter Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................26
Parameter Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................27
Parameter Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................28
Parameter Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................29
Parameter Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................30
Parameter Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)................................31
Parameter Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)..............................31
Parameter Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ............................................................32
Parameter Supported Power States (Verb ID=F00h, Parameter ID=0Fh).......................................................32
Parameter Processing Capabilities (Verb ID=F00h, Parameter ID=10h) .......................................................32
Parameter GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ...............................................................33
Parameter Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) ...................................................33

VERB GET CONNECTION SELECT CONTROL (VERB ID=F01H) ....................................................34

VERB SET CONNECTION SELECT (VERB ID=701H) .....................................................................34
VERB GET CONNECTION LIST ENTRY (VERB ID=F02H)..............................................................35
VERB GET PROCESSING STATE (VERB ID=F03H)........................................................................38
VERB SET PROCESSING STATE (VERB ID=703H) ........................................................................38
VERB GET COEFFICIENT INDEX (VERB ID=DH) ..........................................................................39
VERB SET COEFFICIENT INDEX (VERB ID=5H)............................................................................39
VERB GET PROCESSING COEFFICIENT (VERB ID=CH).................................................................40
VERB SET PROCESSING COEFFICIENT (VERB ID=4H) ..................................................................40
VERB GET AMPLIFIER GAIN (VERB ID=BH) ...............................................................................41
VERB SET AMPLIFIER GAIN (VERB ID=3H).................................................................................45
VERB GET CONVERTER FORMAT (VERB ID=AH)........................................................................46
VERB SET CONVERTER FORMAT (VERB ID=2H) .........................................................................47
VERB GET POWER STATE (VERB ID=F05H)................................................................................48
VERB SET POWER STATE (VERB ID=705H).................................................................................48
VERB GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...................................................49
VERB SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ....................................................49
VERB GET PIN WIDGET CONTROL (VERB ID=F07H)...................................................................50
VERB SET PIN WIDGET CONTROL (VERB ID=707H) ...................................................................51
VERB GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...............................................52
VERB SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ................................................52
VERB GET PIN SENSE (VERB ID=F09H) ......................................................................................53
VERB EXECUTE PIN SENSE (VERB ID=709H) ..............................................................................53
VERB GET CONFIGURATION DEFAULT (VERB ID=F1CH) ...........................................................54
VERB SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR
BYTES 0, 1, 2, 3).............................................................................................................................54
VERB GET BEEP GENERATOR (VERB ID=F0AH) .......................................................................55
VERB SET BEEP GENERATOR (VERB ID=70AH) ........................................................................55
VERB GET GPIO DATA (VERB ID=F15H) ...................................................................................56
VERB SET GPIO DATA (VERB ID=715H)....................................................................................56

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8.31.
8.32.
8.33.
8.34.
8.35.
8.36.
8.37.
8.38.
8.39.
8.40.
8.41.

9.

VERB GET GPIO ENABLE MASK (VERB ID=F16H).....................................................................57

VERB SET GPIO ENABLE MASK (VERB ID=716H)......................................................................57
VERB GET GPIO DIRECTION (VERB ID=F17H)...........................................................................58
VERB SET GPIO DIRECTION (VERB ID=717H)............................................................................58
VERB GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) .............................59
VERB SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H).............................59
VERB FUNCTION RESET (VERB ID=7FFH) ..................................................................................60
VERB GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=F0DH, F0EH)..............61
VERB SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ................62
GET/SET VOLUME KNOB WIDGET (VERB ID=F0FH/70FH)............................................................63
GET/SET SUBSYSTEM ID [31:0] (VERB ID=F20H / 723H~720H TO SET BIT[31:0]) ......................63

Electrical Characteristics ......................................................................................... 64

9.1.
9.1.1.
9.1.2.
9.1.3.
9.1.4.

9.2.
9.2.1.
9.2.2.
9.2.3.
9.2.4.

9.3.

DC CHARACTERISTICS ...................................................................................................................64
Absolute Maximum Ratings ..................................................................................................................................64
Threshold Voltage .................................................................................................................................................64
Digital Filter Characteristics ...............................................................................................................................65
S/PDIF Output Characteristics ............................................................................................................................65

AC CHARACTERISTICS ...................................................................................................................66
Link Reset and Initialization Timing.....................................................................................................................66
Link Timing Parameters at the Codec ..................................................................................................................67
S/PDIF Output Timing..........................................................................................................................................68
Test Mode..............................................................................................................................................................68

ANALOG PERFORMANCE ................................................................................................................69

10. Application Notes ...................................................................................................... 70

10.1. APPLICATION CIRCUITS ..................................................................................................................70
10.2. DIGITAL MICROPHONE IMPLEMENTATION ......................................................................................73

11. Mechanical Dimensions ............................................................................................ 74

11.1. LQFP-48 MECHANICAL DIMENSIONS ............................................................................................74
11.2. LQFP-48 MECHANICAL DIMENSIONS NOTES .................................................................................75
11.3. QFN-48 MECHANICAL DIMENSIONS ..............................................................................................76

12. Ordering Information ............................................................................................... 77

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List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.

Digital I/O Pins ...........................................................................................................................7

Analog I/O Pins...........................................................................................................................8
Filter/Reference...........................................................................................................................9
Power/Ground .............................................................................................................................9
Link Signal Definitions.............................................................................................................11
HDA Signal Definitions............................................................................................................11
Defined Sample Rate and Transmission Rate...........................................................................17
48kHz Variable Rate of Delivery Timing .................................................................................17
44.1kHz Variable Rate of Delivery Timing ..............................................................................18
40-Bit Commands in 4-Bit Verb Format...................................................................................22
40-Bit Commands in 12-Bit Verb Format.................................................................................22
Solicited Response Format .......................................................................................................22
Unsolicited Response Format ...................................................................................................22
System Power State Definitions ...............................................................................................23
Power Controls in NID=01h .....................................................................................................23
Powered Down Conditions .......................................................................................................23
Verb Get Parameters (Verb ID=F00h) ...................................................................................24
Parameter Vendor ID (Verb ID=F00h, Parameter ID=00h) ...................................................24
Parameter Revision ID (Verb ID=F00h, Parameter ID=02h) ................................................24
Parameter Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)............................25
Parameter Function Group Type (Verb ID=F00h, Parameter ID=05h) .................................26
Parameter Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h).......................26
Parameter Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) .........................27
Parameter Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ......................28
Parameter Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) ........................29
Parameter Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..........................................30
Parameter Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) .....31
Parameter Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ...31
Parameter Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ..................................32
Parameter Supported Power States (Verb ID=F00h, Parameter ID=0Fh) .............................32
Parameter Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..............................32
Parameter GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ......................................33
Parameter Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) .........................33
Verb Get Connection Select Control (Verb ID=F01h)...........................................................34
Verb Set Connection Select (Verb ID=701h) .........................................................................34
Verb Get Connection List Entry (Verb ID=F02h)..................................................................35
Verb Get Processing State (Verb ID=F03h) ...........................................................................38
Verb Set Processing State (Verb ID=703h)............................................................................38
Verb Get Coefficient Index (Verb ID=Dh).............................................................................39
Verb Set Coefficient Index (Verb ID=5h) ..............................................................................39
Verb Get Processing Coefficient (Verb ID=Ch).....................................................................40
Verb Set Processing Coefficient (Verb ID=4h)......................................................................40
Verb Get Amplifier Gain (Verb ID=Bh) ................................................................................41
Verb Set Amplifier Gain (Verb ID=3h)..................................................................................45

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Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.

Verb Get Converter Format (Verb ID=Ah) ............................................................................46

Verb Set Converter Format (Verb ID=2h)..............................................................................47
Verb Get Power State (Verb ID=F05h) ..................................................................................48
Verb Set Power State (Verb ID=705h) ...................................................................................48
Verb Set Converter Stream, Channel (Verb ID=706h)...........................................................49
Verb Get Pin Widget Control (Verb ID=F07h) ......................................................................50
Verb Set Pin Widget Control (Verb ID=707h) .......................................................................51
Verb Get Unsolicited Response Control (Verb ID=F08h) .....................................................52
Verb Set Unsolicited Response Control (Verb ID=708h) ......................................................52
Verb Get Pin Sense (Verb ID=F09h)......................................................................................53
Verb Execute Pin Sense (Verb ID=709h)...............................................................................53
Verb Get Configuration Default (Verb ID=F1Ch) .................................................................54
Verb Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3) ............................................................54
Verb Get BEEP Generator (Verb ID=F0Ah)..........................................................................55
Verb Set BEEP Generator (Verb ID=70Ah)...........................................................................55
Verb Get GPIO Data (Verb ID=F15h) ...................................................................................56
Verb Set GPIO Data (Verb ID=715h) ....................................................................................56
Verb Get GPIO Enable Mask (Verb ID=F16h) ......................................................................57
Verb Set GPIO Enable Mask (Verb ID=716h).......................................................................57
Verb Get GPIO Direction (Verb ID=F17h)............................................................................58
Verb Set GPIO Direction (Verb ID=717h).............................................................................58
Verb Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) ..................................59
Verb Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) ...................................59
Verb Function Reset (Verb ID=7FFh)....................................................................................60
Verb Get Digital Converter Control 1 & Control 2 (Verb ID=F0Dh, F0Eh) .........................61
Verb Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) ..........................62
Get/Set Volume Knob Widget (Verb ID=F0Fh/70Fh) ..............................................................63
Get/Set Subsystem ID [31:0] (Verb ID=F20h / 723h~720h to Set Bit[31:0]) ..........................63
Absolute Maximum Ratings .....................................................................................................64
Threshold Voltage .....................................................................................................................64
Digital Filter Characteristics .....................................................................................................65
S/PDIF Input/Output Characteristics ........................................................................................65
Link Reset and Initialization Timing ........................................................................................66
Link Timing Parameters at the Codec.......................................................................................67
S/PDIF Output Timing..............................................................................................................68
Analog Performance .................................................................................................................69
Ordering Information ................................................................................................................77

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List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.

Block Diagram ..........................................................................................................................4

Analog Input/Output Unit .........................................................................................................4
Pin Assignments ALC268-GR (LQFP-48)................................................................................5
Pin Assignments ALC268Q-GR (QFN-48)...............................................................................6
HDA Link Protocol .................................................................................................................10
Bit Timing ...............................................................................................................................11
Signaling Topology .................................................................................................................12
SDO Outbound Frame.............................................................................................................13
SDO Stream Tag is Indicated in SYNC ..................................................................................13
Stripped Stream on Multiple SDOs.........................................................................................14
SDI Inbound Stream ................................................................................................................15
SDI Stream Tag and Data ........................................................................................................15
Codec Transmits Data Over Multiple SDIs.............................................................................16
Link Reset Timing...................................................................................................................20
Codec Initialization Sequence.................................................................................................21
Link Reset and Initialization Timing.......................................................................................66
Link Signals Timing ................................................................................................................67
Output Timing .........................................................................................................................68
Filter Connection.....................................................................................................................70
Power and Rear Panel Jack Connection..................................................................................71
Front Panel Header and Front Panel I/O Cable.......................................................................72
S/PDIF-OUT Connection ........................................................................................................72
Digital Microphone Implementation-1....................................................................................73
Digital Microphone Implementation-2....................................................................................73

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1.

General Description

The ALC268 series are 4-Channel High Definition Audio Codecs with UAA (Universal Audio
Architecture), featuring two stereo DACs and two stereo ADCs. The 4 channels of DAC support stereo
sound playback on the rear panel and independent stereo sound output on the front panel simultaneously
(multiple streaming). The two stereo ADCs integrate two stereo and independent analog sound inputs.
The ALC268 series incorporates Realtek proprietary converter technology to achieve 95dB dynamic
range playback quality and 90dB dynamic range recording quality. They are designed for Windows Vista
premium desktop and laptop systems.
The ALC268 series also supports up to 4 digital microphone channels (microphone array) with Acoustic
Echo Cancellation (AEC), Beam Forming (BF), and Noise Suppression (NS) technology simultaneously,
significantly improving sound quality for PC VoIP applications.
The S/PDIF output offers easy connection of PCs to high quality consumer electronic products such as
digital decoders and speakers.
The ALC268 supports host/soft audio from the Intel ICH chipset, and also from any other HDA
compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and excellent
software utilities like Karaoke mode, environment emulation, and software equalizer audio technology to
provide an excellent entertainment package and game experience for PC users.

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2.

Features

2.1.

Hardware Features

95dB SNR DACs meet Windows Vista Premium requirement

90dB SNR ADCs meet Windows Vista Premium requirement
Two stereo DACs support 16/20/24-bit PCM format for stereo audio playback
Two stereo ADCs support 16/20-bit PCM format for two stereo independent sound inputs
All DACs supports 44.1k/48K/96k/192kHz sample rate
All ADCs support 44.1k/48k/96kHz sample rate
16/20/24-bit S/PDIF-OUT supports 44.1k/48k/88.2k/96k/192kHz sample rate
Up to four channels of digital microphone input are supported
Supports MONO line output with independent volume control
High-quality analog differential CD input
Supports external PCBEEP input and built-in digital BEEP generator
Software selectable 2.5V/3.75V/4.2V VREFOUT
Two jack detection pins each designed to detect up to 4 jacks
1dB resolution of analog output volume control
Programmable 20dB and 40dB boost for analog microphone input
Supports hardware digital volume control for digital microphone input
Built-in headphone amplifiers for port-A and port-D
4 GPIOs (GPIO0/GPIO3 are digital GPIO shared with digital MIC interface, GPIO1/GPIO2 are
analog) for customized applications
EAPD (External Amplifier Power Down) is supported
Supports Anti-pop mode when analog power AVDD is on and digital power is off.
Power support: 3.3V digital core power; 1.5V~3.3V digital IO power for HDA link; 3.3V~5.0V
analog power
Power management features
48-pin LQFP Green package
48-pin QFN Green package

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2.2.

3.

Software Features

Meets Microsoft WLP 3.0x audio requirements

EAX 1.0 & 2.0 compatible
Direct Sound 3D compatible
A3D compatible
I3DL2 compatible
HRTF 3D Positional Audio
Emulation of 26 sound environments to enhance gaming experience
10 Software Equalizer Bands
Voice Cancellation and Key Shifting in Karaoke mode
Realtek Media Player
Enhanced Configuration Panels (2 feet UI and 10 feet UI for Media Center)
Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)
technology for voice applications

System Applications
Windows Vista premium desktop and laptop PCs
Information appliances (IA) with High Definition Audio Controller

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4.

Block Diagram

Figure 1.

4.1.

Block Diagram

Analog Input/Output Unit

Pin widgets NID=14h, 15h, 18h and 1Ah are re-tasking IO support input unit, NID=14h and 15h support
amplifier unit.
R

Output_Signal_Left

A
EN_OBUF

Output_Signal_Right

EN_AMP

Left
Right

EN_OBUF

Input_Signal_Left
Input_Signal_Right

Figure 2.
2+2 Channel High Definition Audio Codec

EN_IBUF

Analog Input/Output Unit

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5.
5.1.

Pin Assignments
ALC268-GR (LQFP-48)

Figure 3.

2+2 Channel High Definition Audio Codec

Pin Assignments ALC268-GR (LQFP-48)

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5.2.

ALC268Q-GR (QFN-48)

Figure 4.

5.3.

Pin Assignments ALC268Q-GR (QFN-48)

Green Package and Version Identification

The ALC268 series includes the parts listed in section 12 Ordering Information, page 77.
Green package is indicated by a G in the location marked T in Figure 4. The version number is shown
in the location marked VV.

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Datasheet

6.
6.1.

Pin Descriptions
Digital I/O Pins

Table 1. Digital I/O Pins

Type ALC268-GR ALC268Q-GR Description
(LQFP-48)
(QFN-48)
Pin No.
Pin No.
RESET#
I
11
11
H/W reset control
SYNC
I
10
10
Sample Sync (48kHz)
BCLK
I
6
6
24MHz Bit clock input
SDATA-OUT I
5
5
Serial TDM data input
SDATA-IN
O
8
8
Serial TDM data
output
EAPD
O
47
47
Signal to power down
ext. amp
SPDIFO
O
48
48
S/PDIF output
GPIO0 /
I/O
2
2
General Purpose
Input/Output 0
DMIC-12
Data input from digital
MIC 1&2
GPIO3 /
I/O
3
4
General Purpose
Input/Output 3
DMIC-34
Data input from digital
MIC 3&4
DMIC-CLK
O
46
46
Clock output for
digital MIC
Total
10 pins
10 pins
Name

2+2 Channel High Definition Audio Codec

Characteristic Definition

Vt=0.5*DVDD
Vt=0.5*DVDD
Vt=0.5*DVDD
Vt=0.5*DVDD
VOH=0.9*DVDD, VOL=0.1*DVDD
Output VOH=DVDD, VOL=DVSS
Output has 12mA@75 driving capability.
Input Vt=(2/3)*DVDD, output VOH=DVDD,
VOL=DVSS, internal pulled up by 50K

Input Vt=(2/3)*DVDD, output VOH=DVDD,

VOL=DVSS, internal pulled up by 50K

Default 2.048MHz clock output

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ALC268 Series
Datasheet

6.2.

Analog I/O Pins

Table 2. Analog I/O Pins

Type ALC268-GR ALC268Q-GR Description
(LQFP-48)
(QFN-48)
Pin No.
Pin No.
MIC2-L
I/O
16
16
2nd stereo microphone
input left channel
MIC2-R
I/O
17
17
2nd stereo microphone
input right channel
CD-L
I
18
18
CD input left channel
CD-G
I
19
19
CD input reference
ground
CD-R
I
20
20
CD input right channel
MIC1-L
I/O
21
21
1st stereo microphone
input left channel
MIC1-R
I/O
22
22
1st stereo microphone
input right channel
LINE1-L
I/O
23
23
1st line input left
channel
LINE1-R
I/O
24
24
1st line input right
channel
PCBEEP
I
12 pin
12 pin
External PCBEEP input
LINE-OUT-L I/O
35
35
Line output left channel
LINE-OUT-R I/O
36
36
Line output right
channel
HP-OUT-L
I/O
39
39
Headphone out left
channel
HP-OUT-R
I/O
41
41
Headphone out right
channel
MONO-OUT O
37
32
MONO output

Name

Sense A

13

13

Jack Detect pin l

Sense B

34

34

Jack Detect pin 2

GPIO1

I/O

31

31

GPIO2

I/O

30

General Purpose
Input/Output 1
General Purpose
Input/Output 2

18 pins

19 pins

Total

2+2 Channel High Definition Audio Codec

Characteristic Definition

Analog input/output, default is input

(PORT F)
Analog input/output, default is input
(PORT F)
Analog input, 1.6Vrms of full scale input
Analog input, 1.6Vrms of full scale input
Analog input, 1.6Vrms of full scale input
Analog input/output, default is input
(PORT B)
Analog input/output, default is input
(PORT B)
Analog input/output, default is input
(PORT C)
Analog input/output, default is input
(PORT C)
Analog input, 1.6Vrms of full scale input
Analog output (PORT D)
Analog output (PORT D)
Analog output (PORT A)
Analog output (PORT A)
Analog mono output is summation of
(L+R)/2
Resistor {5.1K, 10K, 20K, 39.2K} w/ 1%
accuracy
Resistor {5.1K, 10K, 20K, 39.2K} w/ 1%
accuracy

Input Vt=(2/3)*AVDD, output VOH=AVDD,

VOL=AVSS, internal pulled up by 50K
Input Vt=(2/3)*AVDD, output VOH=AVDD,
VOL=AVSS, internal pulled up by 50K

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ALC268 Series
Datasheet

6.3.

Filter/Reference/Not Connected

Name

Type

VREF
MIC1-VREFO-L
LINE1-VREFO

O
O

MIC2-VREFO
MIC1-VREFO-R
JDREF
NC
NC
NC
NC
NC
NC
NC
Total

O
O
-

6.4.

ALC268-GR
(LQFP-48)
Pin No.
27
28
29
30
32
40
14
15
33
43
44
45
12 pins

Table 3. Filter/Reference
ALC268Q-GR Description
(QFN-48)
Pin No.
27
2.5V Reference voltage
28
Bias voltage for MIC1 jack
29
Bias voltage for LINE1
jack
Bias voltage for MIC2 jack
Bias voltage for MIC1 jack
33
Ref. resistor for Jack Detect
14
Not Connected
15
Not Connected
37
Not Connected
43
Not Connected
44
Not Connected
45
Not Connected
40
Not Connected
11 pins

Characteristic Definition

1uf capacitor to analog ground

2.5V/3.2/4.2Vreference voltage
2.5V/3.2/4.2Vreference voltage
2.5V/3.2/4.2Vreference voltage
2.5V/3.2/4.2Vreference voltage
20K, 1% resistor to analog ground

Power/Ground

Table 4. Power/Ground
Name
Type ALC268-GR ALC268Q-GR Description
(LQFP-48)
(QFN-48)
Pin No
Pin No.
AVDD1
I
25
25
Analog VDD (5V or 3.3V)
AVSS1
I
26
26
Analog GND
AVDD2
I
38
38
Analog VDD (5V or 3.3V)
AVSS2
I
42
42
Analog GND
DVDD
I
1
1
Digital VDD (3.3V)
DVSS
I
4
Digital GND
DVDD-IO I
9
3
Digital VDD (1.5V~3.3V)
DVSS
I
7
7
Digital GND
DVDD
I
9
Digital VDD (3.3V)
Total
8 pins
8 pins

2+2 Channel High Definition Audio Codec

Characteristic Definition

Analog power for mixer and amplifier

Analog ground for mixer and amplifier
Analog power for DACs and ADCs
Analog ground for DACs and ADCs
Digital power
Digital ground
Scalable digital power for HDA link.
Digital ground
Digital power

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ALC268 Series
Datasheet

7.
7.1.

High Definition Audio Link Protocol

Link Signals

The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the
HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent
by the HDA controller. The input and output streams, including command and PCM data, are isochronous
with a 48kHz frame rate. Figure 5 shows the basic concept of the HDA link protocol.

Tframe_sync = 20.833 s (48KHz)

Previous Frame

Next Frame

BCLK
Stream 'A' Tag
(Here 'A' = 5)

Stream 'B' Tag

(Here 'B' = 6)

Stream 'A' Data

Stream 'B' Data

Frame SYNC= 8 BCLK

SYNC

SDO

Command Stream
(40-bit data)

SDI

Response Stream

Stream
'C' Tag

Stream 'C' Data

(n bytes + 10-bit data)

(36-bit data)
RST#

Figure 5.

2+2 Channel High Definition Audio Codec

HDA Link Protocol

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Datasheet

7.1.1.
Item
BCLK
SYNC
SDO

SDI

RST#

Signal Definitions
Table 5. Link Signal Definitions
Description
24.0MHz of bit clock sourced from the HDA controller and connecting to all codecs.
48kHz of signal is used to synchronize input and output streams on the link. It is sourced from the HDA
controller and connects to all codecs.
Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are carried
on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec samples data
present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To
extend outbound bandwidth, multiple SDOs may be supported.
Serial data input signal driven by the codec. It is point-to-point serial data from the codec to the HDA
controller. The controller must support at least one SDI, and up to a maximum of 15 SDIs can be supported.
SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of
BCLK. SDI can be driven by the controller to initialize the codecs ID.
Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the
HDA controller and connects to all codecs.

Table 6. HDA Signal Definitions

Signal Name
Source
Type for Controller Description
BCLK
Controller
Output
Global 24.0MHz bit clock.
SYNC
Controller
Output
Global 48kHz Frame Sync and outbound tag signal.
SDO
Controller
Output
Serial data output from controller.
SDI
Codec/Controller
Input/Output
Serial data input from codec. Weakly pulled down by the
controller.
RST#
Controller
Output
Global active low reset signal.

BCLK
SYNC

8-Bit Frame SYNC

Start of Frame

SDO

SDI

0 999 998 997 996 995 994 993 992 991 990

499

498

497

496

495

494

Codec samples SDO at both rising and falling edge of BCLK

Controller samples SDI at rising edge of BCLK

Figure 6.

2+2 Channel High Definition Audio Codec

Bit Timing

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ALC268 Series
Datasheet

7.1.2.

Signaling Topology

The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream.
RST#, BCLK, SYNC, SDO0 and SDO1 are driven by controller to codecs. Each codec drives its own
point-to-point SDI signal(s) to the controller.
Figure 7 shows the possible connections between the HDA controller and codecs:
Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission
Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate
Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate
Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and
codecs. Section 7.2 Frame Composition, page 13 describes the detailed outbound and inbound stream
compositions for single and multiple SDOs/SDIs.
The connections shown in Figure 7 can be implemented concurrently in an HDA system. The ALC268 is
designed to receive a single SDO stream.

SDI14
.
.
.

.
.
.

SDI13
SDI2
HDA
SDI1
Controller SDI0
SDO1
SDO0
SYNC
BCLK
RST#

SDI2
SDI1
SDI0
SDO1
SDO0
SYNC
BCLK
RST#

SDI1
SDI0

SDO0
SYNC
BCLK
RST#

S DI0
SDO1
SDO0
SYNC
BCLK
RST#

SDI0

SDO0
SYNC
BCLK
RST#

...

Codec 0

Codec 1

Codec 2

Single SDO

Two SDOs

Single SDO

Two SDOs

Single SDI

Single SDI

Two SDIs

Multiple SDIs

Figure 7.

2+2 Channel High Definition Audio Codec

Codec N

Signaling Topology

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Datasheet

7.2.
7.2.1.

Frame Composition
Outbound Frame Single SDO

An outbound frame is composed of one 32-Bit command stream and multiple data streams. There are one
or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA
controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the
sample rate is a multiple of 48kHz. This means there should be 2 blocks in the same stream to carry
96kHz samples (Figure 8).
For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started
at the end of the stream tag. The stream tag includes a 4-Bit preamble and 4-Bit stream ID (Figure 9).
To keep the cadence of converters bound to the same stream, samples for these converters must be placed
in the same block.
A 48kHz Frame is composed of Command stream and multiple Data streams

Previous Frame

Frame SYNC

Stream 'A' Tag

Stream 'X' Tag

(Here 'A' = 5)

(Here 'X' = 6)

SYNC

SDO

Command Stream

Stream 'A' Data

One or multiple blocks in a stream

Sample Block(s)
Block 1

Block 2

..
.

Sample 1

Sample 2

..
.

msb

...

lsb

Stream 'X' Data

Block Y

Null Field

Next Frame

0s

Padded at the
end of Frame

For 48kHz rate, only Block1 is included

For 96kHz rate, Block1 includes (N)th time of samples, Block2
includes (N+1)th time of samples

Sample Z Z channels of PCM Sample

msb first in a sample

Figure 8.

SDO Outbound Frame

BCLK
Stream Tag

msb

lsb

1010
Preamble
(4-Bit)

Stream=10
(4-Bit)

7 6 5 4 3 2 1 0

SDO

Data of Stream 10

ms b

SYNC

Previous Stream

Figure 9.
2+2 Channel High Definition Audio Codec

SDO Stream Tag is Indicated in SYNC

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ALC268 Series
Datasheet

7.2.2.

Outbound Frame Multiple SDO

The HDA controller allows two SDO signals to be used to strip outbound data, completing transmission
in less time to get more bandwidth. If software determines the target codec supports multiple SDO
capability, it enables the Strip Control bit in the controllers Output Stream Control Register to initiate a
specific stream (Stream A in Figure 10) to be transmitted on multiple SDOs. In this case, the MSB of
stream data is always carried on SDO0, the second bit on SDO1 and so forth.
SDO1 is for transmitting a stripped stream. The codec does not support multiple SDOs connected to
SDO0.
To guarantee all codecs can determine their corresponding stream, the command stream is not stripped. It
is always transmitted on SDO0, and copied on SDO1.
Stream 'A' Tag

Stream 'X' Tag

Stream 'Y' Tag

SYNC
Frame SYNC
SDO0

Stream 'A' to Codec A

...

Command Stream

Stream 'X' to Codec X

Stream 'Y' to Codec Y

Dn Dn-2
SDO1

...

Command Stream

0s

0s

D Dn-3 . . .
n-1

Stream A is "bit-stripped" on SDO0 and SDO1

Command Stream is unchanged, not stripped

Figure 10. Stripped Stream on Multiple SDOs

2+2 Channel High Definition Audio Codec

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ALC268 Series
Datasheet

7.2.3.

Inbound Frame Single SDI

An Inbound Frame Single SDI is composed of one 36-Bit response stream and multiple data streams.
Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each
rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 11).
The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream
includes one 4-Bit stream tag, one 6-Bit data length, and n-Bit sample blocks. Zeros will be padded if the
total length of the contiguous sample blocks within a given stream is not of integral byte
length (Figure 12).
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams

Previous Frame

Next Frame

Frame SYNC
SYNC

SDI

0s

Stream 'X'

Stream 'A'

Response Stream

Null Field
Stream Tag
Block 1

...

Block 2

Sample 1 Sample 2
msb

...

Padded at the end of Frame

Sample Block(s)
Block Y

For 48kHz rate, only Block1 is included

For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples

Sample Z Z channels of PCM Sample

...
lsb

Null Pad

msb first in a sample

Figure 11. SDI Inbound Stream

BCLK
Stream Tag

SDI

B9

B8

B7

B6

B5

B4

B3

B2

B1

Null Pad

n-Bit Sample Block

Data Length in Bytes

B0 Dn-1 Dn-2

D0

Next Stream
0

(Data Length in Bytes *8)-Bit

A Complete Stream

Figure 12. SDI Stream Tag and Data

2+2 Channel High Definition Audio Codec

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ALC268 Series
Datasheet

7.2.4.

Inbound Frame Multiple SDI

A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound
stream exceeds the data transfer limits of a single SDI, the codec can divide the data onto separate SDI
signals, each of which operate independently, with different stream numbers at the same frame time. This
is similar to having multiple codecs connected to the controller. The controller samples the divided stream
into separate memory with multiple DMA descriptors, then software re-combines the divided data into a
meaningful stream.
SYNC
Frame SYNC
SDI 0

Stream 'A'

Response Stream

Tag A

Data A

Stream 'Y'

Stream 'X'

Stream 'B'
SDI 1

Response Stream

Codec drives SDI0 and SDI1

Tag B

Data B

0s

0s

Stream A, B, X, and Y are independent and have separate IDs

Figure 13. Codec Transmits Data Over Multiple SDIs

7.2.5.

Variable Sample Rates

The HDA link is designed for sample rates of 48kHz. Variable rates of sample are delivered in multiple or
sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample
block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate
of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own
sample rate, independent of any other stream.
The HDA controller supports 48kHz and 44.1kHz base rates. Table 7, page 17, shows the recommended
sample rates based on multiples or sub-multiples of one of the two base rates.
Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in
multiples (n) of 48kHz contain n sample blocks in a frame. Table 8, page 17, shows the delivery cadence
of variable rates based on 48kHz.

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Datasheet
The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple
rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid
frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample
blocks are transmitted every 160 frames. The cadence
12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
interleaves 13 frames containing no sample blocks in every 160 frames. It provides a low long-term
frequency drift for 44.1kHz of delivery rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this
cadence AND interleave n empty frames. Rates in multiples (n) of 44.1kHz applying this cadence contain
n sample blocks in the non-empty frame AND interleave an empty frame between non-empty
frames (Table 9, page 18).
(Sub) Multiple
1/6
1/4
1/3
1/2
2/3
1
2
4

Table 7. Defined Sample Rate and Transmission Rate

48kHz Base
44.1kHz Base
8kHz (1 sample block every 6 frames)
12kHz (1 sample block every 4 frames)
11.025kHz (1 sample block every 4 frames)
16kHz (1 sample block every 3 frames)
22.05kHz (1 sample block every 2 frames)
32kHz (2 sample blocks every 3 frames)
48kHz (1 sample block per frame)
44.1kHz (1 sample block per frame)
96kHz (2 sample blocks per frame)
88.2kHz (2 sample blocks per frame)
192kHz (4 sample blocks per frame)
176.4kHz (4 sample blocks per frame)

Table 8.
Rate
Delivery Cadence
8kHz
YNNNNN (repeat)
12kHz
YNNN (repeat)
16kHz
YNN (repeat)
32kHz
Y2NN (repeat)
48kHz
Y (repeat)
96kHz
Y2 (repeat)
192kHz
Y4 (repeat)
N: No sample block in a frame
Y: One sample block in a frame
Yx: X sample blocks in a frame

2+2 Channel High Definition Audio Codec

48kHz Variable Rate of Delivery Timing

Description
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 4 frames
One sample block is transmitted in every 3 frames
One sample block is transmitted in every 6 frames
One sample block is transmitted in every 6 frames
Two sample blocks are transmitted in each frame
Four sample blocks are transmitted in each frame

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Datasheet
Table 9. 44.1kHz Variable Rate of Delivery Timing
Rate
Delivery Cadence
11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-}
(repeat)
44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)
88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat)
174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)

11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN
{ - } =NNNN
22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN
{11}=YNYNYNYNYNYNYNYNYNYNYN
{ - }=NN
44.1kHz

12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with
no sample block.

88.2kHz

122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with
no sample block.

176.4kHz

124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with
no sample block.

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Datasheet

7.3.

Reset and Initialization

There are two types of reset within an HDA link:

Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state

Codec Reset. Generated by software directing a command to reset a specific codec back to its default
state

An initialization sequence is requested after any of the following three events:

1.

Link Reset

2.

Codec Reset

3.

Codec changes its power state (For example, hot docking a codec to an HDA system)

7.3.1.

Link Reset

A link reset may be caused by 3 events:

1.

The HDA controller asserts RST# for any reason (power up, or PCI reset)

2.

Software initiates a link reset via the CRST bit in the Global Control Register (GCR) of the HDA
controller

3.

Software initiates power management sequences. Figure 14, page 20, shows the Link Reset timing
including the Enter sequence (n~r) and Exit sequence (s~v)

Enter Link Reset:

n Software writes a 0 to the CRST bit in the Global Control Register of the HDA controller to initiate a
link reset
o As the controller completes the current frame, it does not signal the normal 8-Bit frame SYNC at the
end of the frame
p The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low
q The controller asserts the RST# signal to low, and enters the Link Reset state
r All link signals driven by controller and codecs should be tri-state by internal pull low resistors

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Exit from Link Reset:
s If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
t Software is responsible for de-asserting RST# after a minimum of 100sec BCLK running time (the
100sec provides time for the codec PLL to stabilize)
u Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
v When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at
the last bit of frame SYNC, it means the codec requests an initialization sequence)
4 BCLK

Previous Frame

Link in Reset

4 BCLK

>=100 usec

>= 4 BCLK

Initialization Sequence

BCLK
Normal Frame
SYNC is absent

SYNC

Driven Low

Normal Frame
SYNC

Pulled Low

SDOs

Driven Low

Pulled Low

SDIs

Driven Low

Pulled Low

Wake Event
9

RST#

Pulled Low
1

Figure 14. Link Reset Timing

7.3.2.

Codec Reset

A Codec Reset is initiated via the Codec RESET command verb. It results in the target codec being
reset to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.

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7.3.3.

Codec Initialization Sequence

n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller.
o The codec will stop driving the SDI during this turnaround period.
pqrs The controller drives SDI to assign a CAD to the codec.
t The controller releases the SDI after the CAD has been assigned.
u Normal operation state.
Exit from Reset

Turnaround Frame
(Non-48kHz Frame)

Connection Frame

Address Frame
(Non-48kHz Frame)

Normal Operation

BCLK
SYNC

Frame SYNC

Frame SYNC

Frame SYNC
4

SDIx

SD0 SD1

RST#

Codec
Drives SDIx

Response

SD14

Codec
Turnaround
(477 BCLK
Max.)

Controller Drives SDIx

Controller
Turnaround
(477 BCLK
Max.)

Codec Drives SDIx

Figure 15. Codec Initialization Sequence

2+2 Channel High Definition Audio Codec

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Datasheet

7.4.
7.4.1.

Verb and Response Format

Command Verb Format

There are two types of verbs: one with 4-Bit identifiers (4-Bit verbs) and 16-Bits of data, the other with
12-Bit identifiers (12-Bit verbs) and 8-Bits of data. Table 10 shows the 4-Bit verb structure of a command
stream sent from the controller to operate the codec. Table 11 is the 12-Bit verb structure that gets and
controls parameters in the codec.

7.4.2.

Bit [39:32]
Reserved

Table 10. 40-Bit Commands in 4-Bit Verb Format

Bit [31:28]
Bit [27:20]
Bit [19:16]
Codec Address
Node ID
Verb ID

Bit [15:0]
Payload

Bit [39:32]
Reserved

Table 11. 40-Bit Commands in 12-Bit Verb Format

Bit [31:28]
Bit [27:20]
Bit [19:8]
Codec Address
Node ID
Verb ID

Bit [7:0]
Payload

Response Format

There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-Bit Response is interpreted by
software, opaque to the controller.
Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The Tag in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Bit [35]
Valid

Bit [35]
Valid

Note:

Table 12. Solicited Response Format

Bit [34]
Bit [33:32]
Unsol=0
Reserved

Bit [31:0]
Response

Table 13. Unsolicited Response Format

Bit [34]
Bit [33:32]
Bit [31:28]
Unsol=1
Reserved
Tag

Bit [27:0]
Response

The response stream in the link protocol is 36-Bits wide. The response is placed in the lower
32-bit field. Bit-35 is a Valid bit to indicate the response is Ready. Bit-34 is set to indicate that
an unsolicited response was sent.

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7.5.

Power Management

The ALC268 does not support Wake-Up events when in low power mode. All power management state
changes in widgets are driven by software. Table 14 shows the System Power State Definitions.
In the ALC268, all the widgets include output/input converters support power control. Software may have
various power states depending on system configuration.
Table 15 indicates those nodes that support power management. To simplify power control, software can
configure whole codec power states through the audio function (NID=01h). Output converters (DACs)
and input converters (ADCs) have no individual power control to supply fine-grained power control.
Power States
D0
D1
D2
D3 (Hot)
D3 (Cold)

Table 14. System Power State Definitions

Definitions
All power on. Individual DACs and ADCs can be powered up or down as required.
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog reference
stays up.
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog
reference off (D1 + analog reference off).
Power still supplied. The codec stops the internal clock. State is maintained.
All power removed. State lost.

Description
Audio Function
LINK
Response
(NID=01h)
DACs
ADCs
All Headphone
Drivers
All Mixers
All Reference
Note: PD=Powered Down

Condition
LINK Response powered down

DAC powered down

ADC powered down
Headphone Driver powered down
Mixers powered down
Reference power down

Table 15. Power Controls in NID=01h

D0
D1
D2
Normal
Normal
Normal

D3 (Hot/Cold)
PD

Link Reset
PD

Normal
Normal
Normal

PD
PD
Normal

PD
PD
PD

PD
PD
PD

PD
PD
Normal

Normal
Normal

Normal
Normal

PD
PD

PD
PD

Normal
Normal

Table 16. Powered Down Conditions

Description
Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with
pulled low 47K resistors internally. Detection of Link Reset Entry and
Link Reset Exit sequences are supported. All states are maintained if
DVDD is supplied.
Analog block and digital filter are powered down.
Analog block and digital filter are powered down. The data on SDATA-IN
is quiet.
All headphone drivers are powered down.
All internal mixer widgets are powered down. The DC reference and
VREFOUTx at individual pin complex are still alive.
All internal references, DC reference, and VREFOUTx at individual pin
complexes are off.

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8.

Supported Verbs and Parameters

This chapter describes the Verbs and Parameters supported by various widgets in the ALC268. If a verb is
not supported by the addressed widget, it will respond with 32 bits of 0.

8.1.

Verb Get Parameters (Verb ID=F00h)

The Get Parameters verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. Refer to section 7.4.1 Command Verb Format, page 22, to get
detailed information about supported parameters.
Table 17. Verb Get Parameters (Verb ID=F00h)
Get Parameter Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=00h Verb ID=F00h
Parameter ID[7:0]
32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of 0.

8.1.1.

Parameter Vendor ID (Verb ID=F00h, Parameter ID=00h)

Table 18. Parameter Vendor ID (Verb ID=F00h, Parameter ID=00h)

Codec Response Format
Bit
Description
31:16
Vendor ID=10Ech (Realteks PCI vendor ID).
15:0
Device ID=0268h.
Note: The Root Node (NID=00h) supports this parameter.

8.1.2.

Parameter Revision ID (Verb ID=F00h, Parameter ID=02h)

Table 19. Parameter Revision ID (Verb ID=F00h, Parameter ID=02h)

Codec Response Format
Bit
Description
31:24
Reserved. Read as 0s.
23:20
MajRev. The major version number (in decimal) of the HDA Spec to which the ALC268 is fully
compliant.
19:16
MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC268 is fully
compliant.
15:8
Revision ID. The vendors revision number.
00h is for the first silicon version A, 01h is for the second version B, etc.
7:0
Stepping ID. The vendors stepping number within the given Revision ID.
Note: The Root Node (NID=00h in the ALC268) supports this parameter.
For example the Revision ID=00h and Stepping ID=01h stand for the silicon is A1 version.

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8.1.3.

Parameter Subordinate Node Count (Verb ID=F00h,

Parameter ID=04h)

For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node.
For function group nodes, it provides the total number of widgets associated with this function node.
Table 20. Parameter Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Codec Response Format
Bit
Description
31:24
Reserved. Read as 0s.
23:16
Starting Node Number.
The starting node number in the sequential widgets.
15:8
Reserved. Read as 0s.
7:0
Total Number of Nodes.
For a root node, the total number of function groups in the root node.
For a function group, the total number of widget nodes in the function group.

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8.1.4.

Parameter Function Group Type

(Verb ID=F00h, Parameter ID=05h)

Table 21. Parameter Function Group Type (Verb ID=F00h, Parameter ID=05h)
Codec Response Format
Bit
Description
31:9
Reserved. Read as 0s.
8
UnSol Capable
0: Unsolicited response is not supported by this function group
1: Unsolicited response is supported by this function group
7:0
Function Group Type.
00h: Reserved
01h: Audio Function
02h: Modem Function
03h~7Fh: Reserved
80h~FFh: Vendor Defined Function.
Note: The Audio Function Group (NID=01h) supports this parameter.

8.1.5.

Parameter Audio Function Capabilities

(Verb ID=F00h, Parameter ID=08h)

Table 22. Parameter Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Codec Response Format
Bit
Description
31:17
Reserved. Read as 0s.
16
Beep Generator
A 1 indicates the presence of an integrated Beep generator within the Audio Function Group.
15:12
Reserved. Read as 0s.
11:8
Input Delay.
7:4
Reserved. Read as 0s.
3:0
Output Delay.
Note: The Audio Function Group (NID=01h) supports this parameter.

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8.1.6.

Parameter Audio Widget Capabilities

(Verb ID=F00h, Parameter ID=09h)

Table 23. Parameter Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Codec Response Format
Bit
Description
31:24
Reserved. Read as 0s.
23:20
Widget Type.
0h: Audio Output 1h: Audio Input 2h: Mixer 3h: Selector 4h: Pin Complex
5h: Power Widget 6h: Volume Knob Widget
7h~Eh: Reserved
Fh: Vendor defined audio widget
19:16
Delay. Samples delayed between the HDA link and widgets.
15:11
Reserved. Read as 0s.
10
Power Control.
0: Power state control is not supported on this widget
1: Power state is supported on this widget
9
Digital.
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (S/PDIF, I2S, etc.)
8
ConnList. Connection List.
0: Connected to HDA link. No Connection List Entry should be queried
1: Connection List Entry must be queried
7
UnsolCap. Unsolicited Capable.
0: Unsolicited response is not supported
1: Unsolicited response is supported
6
ProcWidget. Processing Widget.
0: No processing control
1: Processing control is supported
5
Reserved. Read as 0.
4
Format Override.
3
AmpParOvr, AMP Param Override.
2
OutAmpPre, Out AMP Present.
1
InAmpPre, In AMP Present.
0
Stereo.
0: Mono Widget
1: Stereo Widget

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8.1.7.

Parameter Supported PCM Size, Rates

(Verb ID=F00h, Parameter ID=0Ah)

Parameter in audio function provides default information about formats. Individual converters have their
own parameters to provide supported formats if their Format Override bit is set.
Table 24. Parameter Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Codec Response Format
Bit
Description
31:21
Reserved. Read as 0s.
20
B32, indicates the 32-Bit audio format is supported or not.
0: Not supported
1: Supported
19
B24, indicates the 24-Bit audio format is supported or not.
0: Not supported
1: Supported
18
B20, indicates the 20-Bit audio format is supported or not.
0: Not supported
1: Supported
17
B16, indicates the 16-Bit audio format is supported or not.
0: Not supported
1: Supported
16
B8, indicates the 8-Bit audio format is supported or not.
0: Not supported
1: Supported
15:12
Reserved. Read as 0s.
11
R12, indicates the 384kHz (=8*48kHz) rate is supported or not.
0: Not supported
1: Supported
10
R11, indicates the 192kHz (=4*48kHz) rate is supported or not.
0: Not supported
1: Supported
9
R10, indicates the 176.4kHz (=4*44.1kHz) rate is supported or not.
0: Not supported
1: Supported
8
R9, indicates the 96kHz (=2*48kHz) rate is supported or not.
0: Not supported
1: Supported
7
R8, indicates the 88.2kHz (=2*44.1kHz) rate is supported or not.
0: Not supported
1: Supported
6
R7, indicates the 48kHz rate is supported or not.
0: Not supported
1: Supported

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Codec Response Format
Bit
Description
5
R6, indicates the 44.1kHz rate is supported or not.
0: Not supported
1: Supported
4
R5, indicates the 32kHz (=2/3*48kHz) rate is supported or not.
0: Not supported
1: Supported
3
R4, indicates the 22.05kHz (=1/2*44.1kHz) rate is supported or not.
0: Not supported
1: Supported
2
R3, indicates the 16kHz (=1/3*48kHz) rate is supported or not.
0: Not supported
1: Supported
1
R2, indicates the 11.025kHz (=1/4*44.1kHz) rate is supported or not.
0: Not supported
1: Supported
0
R1, indicates the 8kHz (=1/6*48kHz) rate is supported or not.
0: Not supported
1: Supported

8.1.8.

Parameter Supported Stream Formats

(Verb ID=F00h, Parameter ID=0Bh)

Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the Format Override bit is set.
Table 25. Parameter Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Codec Response Format
Bit
Description
31:3
Reserved. Read as 0s.
2
AC3.
0: Not supported
1: Supported)
1
Float32.
0: Not supported
1: Supported
0
PCM.
0: Not supported
1: Supported
Note: Input converters and output converters support this parameter.

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8.1.9.

Parameter Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)

The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 26. Parameter Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
Codec Response Format
Bit
Description
31:16
Reserved. Read as 0s.
15:8
VREF Control Capability.
1 in corresponding bit field indicates signal levels of associated Vrefout are specified as a percentage of
AVDD.
7:6
5
4
3
2
1
0
Reserved
100%
80%
Reserved
Ground
50%
Hi-Z
7
L-R Swap. Indicates the capability of swapping the left and rights.
6
Balanced I/O Pin.
1 indicates this pin complex has balanced pins.
5
Input Capable.
1 indicates this pin complex supports input.
4
Output Capable.
1 indicates this pin complex supports output.
3
Headphone Drive Capable.
1 indicates this pin complex has an amplifier to drive a headphone.
2
Presence Detect Capable.
1 indicates this pin complex can detect whether there is anything plugged in.
1
Trigger Required.
1 indicates whether a software trigger is required for an impedance measurement.
0
Impedance Sense Capable.
1 indicates this pin complex can perform analog sense on the attached device to determine its type.
Note: Only Pin Complex widgets support this parameter.

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8.1.10. Parameter Amplifier Capabilities

(Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the AMP Param Override bit is set.
Table 27. Parameter Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Codec Response Format
Bit
Description
31
(Input) Mute Capable.
30:23
Reserved. Read as 0.
22:16
Step Size.
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
0 indicates a step of 0.25dB. 127 indicates a step of 32dB.
15
Reserved. Read as 0.
14:8
Number of Steps.
Indicates the number of steps in the gain range. 0 means the gain is fixed.
7
Reserved. Read as 0.
6:0
Offset.
Indicates which step is 0dB.

8.1.11. Parameter Amplifier Capabilities (Verb ID=F00h, Output

Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the AMP Param Override bit is set.
Table 28. Parameter Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Codec Response Format
Bit
Description
31
(Output) Mute Capable.
30:23
Reserved. Read as 0.
22:16
Step Size.
Indicates the size of each step in the gain range. Each step may be 0~32dB, specified in 0.25dB steps.
0 indicates a step of 0.25dB. 127 indicates a step of 32dB.
15
Reserved. Read as 0.
14:8
Number of Steps.
Indicates the number of steps in the gain range. 0 means the gain is fixed.
7
Reserved. Read as 0.
6:0
Offset.
Indicates which step is 0dB.

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8.1.12. Parameter Connect List Length (Verb ID=F00h,

Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 29. Parameter Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Codec Response Format
Bit
Description
31:8
Reserved. Read as 0.
7
Short Form.
0: Short Form
1: Long Form
6:0
Connect List Length.
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one
input, and there is no Connection Select Control (Not a MUX widget).

8.1.13. Parameter Supported Power States (Verb ID=F00h,

Parameter ID=0Fh)
Table 30. Parameter Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Codec Response Format
Bit
Description
31:4
Reserved. Read as 0s.
3
D3Sup.
1: Power state D3 is supported.
2
D2Sup.
1: Power state D2 is supported.
1
D1Sup.
1: Power state D1 is supported.
0
D0Sup
1: Power state D0 is supported.

8.1.14. Parameter Processing Capabilities (Verb ID=F00h,

Parameter ID=10h)
Table 31. Parameter Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Codec Response Format
Bit
Description
31:16
Reserved. Read as 0s.
15:8
NumCoeff. Number of Coefficient.
7:1
Reserved. Read as 0s.
0
Benign.
0: Processing unit is not linear and time invariant
1: Processing unit is linear and time invariant
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8.1.15. Parameter GPIO Capabilities (Verb ID=F00h,

Parameter ID=11h)
Table 32. Parameter GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Codec Response Format
Bit
Description
31
GPIWake=0.
The ALC268 does not support GPIO wake up function.
30
GPIUnsol=1.
The ALC268 supports GPIO unsolicited response.
29:24
Reserved. Read as 0s.
23:16
NumGPIs=00h.
No GPI pin is supported.
15:8
NumGPOs=00h.
No GPO pin is supported.
7:0
NumGPIOs=04h.
Two GPIO pins are supported.

8.1.16. Parameter Volume Knob Capabilities (Verb ID=F00h,

Parameter ID=13h)
Table 33. Parameter Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Codec Response Format for NID=21h (Volume Control Knob)
Bit
Description
31:8
Reserved. Read as 0s.
7
Delta.
0: Software cannot modify the Volume Control Knob volume
1: Software can write a base volume to the Volume Control Knob
6:0
NumSteps.
The number of steps in the range of the Volume Control Knob.
Note: The ALC268 does not support volume control knob.

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8.2.

Verb Get Connection Select Control (Verb ID=F01h)

Table 34. Verb Get Connection Select Control (Verb ID=F01h)

Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=F01h
0s
Bit[7:0] are Connection Index

Codec Response for Multiplexer Widget NID=23h

Bit
Description
31:8
0s.
7:0
Connection Index currently Set (Default value is 00h).
00h: Pin Widget NID=18h (port-B)
01h: Pin Widget NID=19h (port-F)
02h: Pin Widget NID=1Ah (port-C)
03h: Pin Widget NID=1Ch (Analog CD-IN)
04h: Pin Widget NID=14h (port-D)
05h: Pin Widget NID=15h (port-A)
06h: Pin Widget NID=12h (Digital MIC 1&2)
Other: Reserved

Codec Response for Multiplexer Widget NID=24h

Bit
Description
31:8
0s.
7:0
Connection Index currently Set (Default value is 00h).
00h: Pin Widget NID=18h (port-B)
01h: Pin Widget NID=19h (port-F)
02h: Pin Widget NID=1Ah (port-C)
03h: Pin Widget NID=1Ch (Analog CD-IN)
04h: Pin Widget NID=14h (port-D)
05h: Pin Widget NID=15h (port-A)
06h: Pin Widget NID=13h (Digital MIC 3&4)
Other: Reserved

Codec Response for other NID

Bit
Description
31:0
Not supported (returns 00000000h).

8.3.

Verb Set Connection Select (Verb ID=701h)

Table 35. Verb Set Connection Select (Verb ID=701h)

Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=701h
Select Index [7:0]
0s for all nodes
Note: Only MUX NID-23h and 24h support this verb.
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8.4.

Verb Get Connection List Entry (Verb ID=F02h)

Table 36. Verb Get Connection List Entry (Verb ID=F02h)

Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=F02h
Offset Index N[7:0]
32-bit Response
Codec Response for NID=07h ADC
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 24h (Sum Widget) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=08h ADC
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 23h (Sum Widget) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=0Eh)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
Connection List Entry (N+2).
Returns 00h.
15:8
Connection List Entry (N+1).
Returns 03h (LOUT2 DAC) for N=0~3.
Returns 00h for N>3.
7:0
Connection List Entry (N)
Returns 02h (LOUT1 DAC) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=0Fh)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
Connection List Entry (N+2).
Returns 00h.
15:8
Connection List Entry (N+1).
Returns 1Dh (PCBEEP) for N=0~3.
Returns 00h for N>3.
7:0
Connection List Entry (N).
Returns 02h (LOUT1 DAC) for N=0~3.
Returns 00h for N>3.

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Codec Response for NID=10h)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
Connection List Entry (N+2).
Returns 00h.
15:8
Connection List Entry (N+1).
Returns 1Dh (PCBEEP) for N=0~3.
Returns 00h for N>3.
7:0
Connection List Entry (N).
Returns 03h (LOUT2 DAC) for N=0~3.
Returns 00h for N>3.
Codec Response for NID =18h (MIC1, port-B), 1Ah (LINE1, port-C)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 00h.
23:16
Connection List Entry (N+2).
Returns 00h.
15:8
Connection List Entry (N+1).
Returns 00h.
7:0
Connection List Entry (N).
Returns 02h (LOUT1 DAC) for N=0~3.
Returns 00h for N>3.
Codec Response for NID =14h (LOUT, port-D)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 00h.
23:16
Connection List Entry (N+2).
Returns 00h.
15:8
Connection List Entry (N+1).
Returns 00h.
7:0
Connection List Entry (N).
Returns 0Fh (Mixer) for N=0~3.
Returns 00h for N>3.
Codec Response for NID =15h (HPOUT, port-A)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 00h.
23:16
Connection List Entry (N+2).
Returns 00h.
15:8
Connection List Entry (N+1).
Returns 00h.
7:0
Connection List Entry (N).
Returns 10h (Mixer) for N=0~3.
Returns 00h for N>3.

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Datasheet
Codec Response for NID=16h (Pin Widget: MONO-OUT)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 0Eh for N=0~3.
Returns 00h for N>3.
Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT)
Bit
Description
31:8
Connection List Entry (N+3), (N+2) and (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 06h (S/PDIF-OUT Converter) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=23h (MUX Widget)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 1Ch (Pin Complex CD) for N=0~3.
Returns 00h for N>3.
23:16
Connection List Entry (N+2).
Returns 1Ah (Pin Complex LINE1, port-C) for N=0~3.
Returns 12h (Pin Complex Digital MIC 1&2) for N=4~7
Returns 00h for N>7.
15:8
Connection List Entry (N+1).
Returns 19h (Pin Complex MIC2, port-F) for N=0~3.
Returns 15h (Pin Complex HPOUT, port-A) for N=4~7.
Returns 00h for N>7.
7:0
Connection List Entry (N).
Returns 18h (Pin Complex MIC1, port-B) for N=0~3.
Returns 14h (Pin Complex LOUT, port-D) for N=4~7.
Returns 00h for N>7.

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ALC268 Series
Datasheet
Codec Response for NID=24h (MUX Widget)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 1Ch (Pin Complex CD) for N=0~3.
Returns 00h for N>3.
23:16
Connection List Entry (N+2).
Returns 1Ah (Pin Complex LINE1, port-C) for N=0~3.
Returns 13h (Pin Complex Digital MIC 3&4) for N=4~7
Returns 00h for N>7.
15:8
Connection List Entry (N+1).
Returns 19h (Pin Complex MIC2, port-F) for N=0~3.
Returns 15h (Pin Complex HPOUT, port-A) for N=4~7.
Returns 00h for N>7.
7:0
Connection List Entry (N).
Returns 18h (Pin Complex MIC1, port-B) for N=0~3.
Returns 14h (Pin Complex LOUT, port-D) for N=4~7.
Returns 00h for N>7.

Codec Response for Other NID

Bit
Description
31:0
Not supported (returns 00000000h).

8.5.

Verb Get Processing State (Verb ID=F03h)

Get Command Format

Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Table 37. Verb Get Processing State (Verb ID=F03h)

Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID=F03h
0s
32-bit response

Codec Response for All NID

Bit
Description
31:0
Not supported (returns 00000000h).

8.6.

Verb Set Processing State (Verb ID=703h)

Set Command Format

Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Table 38. Verb Set Processing State (Verb ID=703h)

Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID=703h
Processing State [7:0]
0s for all nodes

Codec Response for All NID

Bit
Description
31:0
0s
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ALC268 Series
Datasheet

8.7.

Verb Get Coefficient Index (Verb ID=Dh)

Get Command Format

Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Table 39. Verb Get Coefficient Index (Verb ID=Dh)

Codec Response Format
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Verb ID=Dh
0s
Bit [15:0] are Coefficient Index

Codec Response for NID=20h (Realtek Vendor Registers)

Bit
Description
31:16
Reserved. Read as 0s.
15:0
Coefficient Index.

Codec Response for Other NID

Bit
Description
31:0
Not supported (returns 00000000h).

8.8.

Verb Set Coefficient Index (Verb ID=5h)

Set Command Format

Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Table 40. Verb Set Coefficient Index (Verb ID=5h)

Codec Response Format
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Verb ID=5h
Coefficient Index [15:0]
0s for all nodes

Codec Response for All NID

Bit
Description
31:0
0s

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ALC268 Series
Datasheet

8.9.

Verb Get Processing Coefficient (Verb ID=Ch)

Table 41. Verb Get Processing Coefficient (Verb ID=Ch)

Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=Ch
0s
Processing Coefficient [15:0]

Codec Response for NID=20h (Realtek Vendor Registers)

Bit
Description
31:16
Reserved. Read as 0s.
15:0
Processing Coefficient.

Codec Response for Other NID

Bit
Description
31:0
Not supported (returns 00000000h).

8.10. Verb Set Processing Coefficient (Verb ID=4h)

Table 42. Verb Set Processing Coefficient (Verb ID=4h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=4h
Coefficient [15:0]
0s for all nodes

Codec Response for All NID

Bit
Description
31:0
0s

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ALC268 Series
Datasheet

8.11. Verb Get Amplifier Gain (Verb ID=Bh)

This verb is used to get gain/attenuation settings from each widget.
Table 43. Verb Get Amplifier Gain (Verb ID=Bh)
Get Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Bit [19:16]
Verb ID=Bh

Payload Bit [15:0]

Get payload [15:0]

Codec Response Format

Response [31:0]
Bit[7:0] are responsible for Get

Get Payload in Command Bit[15:0]

Bit
Description
15
Get Input/Output.
0: Input amplifier gain is requested
1: Output amplifier gain is requested
14
Reserved. Read as 0.
13
Get Left/Right.
0: Right amplifier gain is requested
1: Left amplifier gain is requested
12:4
Reserved. Read as 0s.
3:0
Index[3:0] for Input Source.
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored.

Codec Response for NID=02h (LOUT1 DAC) and 03h (LOUT2 DAC)
Bit
Description
31:8
0s.
7
Payload[15] is 0 in Get Amplifier Gain: Read as 0 (No Output Amplifier Mute).
Payload[15] is 1 in Get Amplifier Gain: Read as 0 (No Output Amplifier Mute).
6:0
Payload[15] is 0 in Get Amplifier Gain: Read as 0s (No Input Amplifier Gain.)
Payload[15] is 1 in Get Amplifier Gain: 6-bit control specifying the volume from64dB~ 0dB in 1dB
step.
Node
Gain[6:0] (Default)
Gain Range
LOUT1 DAC(NID=02h)
1000000b=40h (0dB)
64dB~0dB in 1dB step
LOUT2 DAC (NID=03h)
1000000b=40h (0dB)
64dB~0dB in 1dB step

Codec Response for NID=0Eh (MONO Sum Widgets)

Bit
Description
31:8
0s.

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Datasheet
Codec Response for NID=0Eh (MONO Sum Widgets)
7
Payload[15] is 0 in Get Amplifier Gain: (Input Amplifier Mute, 0: Unmute 1: Mute)
Index[3:0]=0
Index[3:0]=Other
(from LOUT1)
Node
Default of Bit [7]
MONO Sum (NID=0Eh)
0 (Unmute)
0

6:0

Payload[15] is 1 in Get Amplifier Gain: Read as 0 (No Output Amplifier Mute).

Payload[15] is 0 in Get Amplifier Gain: Read as 0s. (No Input Amplifier Gain).
Payload[15] is 1 in Get Amplifier Gain: Read as 4 (No Output Amplifier Gain).

Codec Response for NID=0Fh (LINE-OUT Sum Widgets)

Bit
Description
31:8
0s.
7
Payload[15] is 0 in Get Amplifier Gain: (Input Amplifier Mute, 0: Unmute 1: Mute)
Index[3:0]=0
Index[3:0]=1
Index[3:0]=Other
(from LOUT1)
(from BEEP)
Node
Default of Bit [7]
Default of Bit [7]
LINE-OUT Sum
0 (Unmute)
1 (Mute)
0

6:0

Payload[15] is 1 in Get Amplifier Gain: Read as 0 (No Output Amplifier Mute).

Payload[15] is 0 in Get Amplifier Gain: Read as 0s (No Input Amplifier Gain).
Payload[15] is 1 in Get Amplifier Gain: Read as 0s (No Output Amplifier Gain).

Codec Response for NID=10h (HP-OUT Sum Widgets)

Bit
Description
31:8
0s.
7
Payload[15] is 0 in Get Amplifier Gain: (Input Amplifier Mute, 0: Unmute 1: Mute)
Index[3:0]=0
Index[3:0]=1
Index[3:0]=2
Index[3:0]=Other
(from LOUT2)
(from BEEP)
(from LOUT1)
Node
Default of Bit [7] Default of Bit [7] Default of Bit [7]
LINE-OUT Sum
1 (Mute)
1 (Mute)
1 (Mute)
0

6:0

Payload[15] is 1 in Get Amplifier Gain: Read as 0 (No Output Amplifier Mute).

Payload[15] is 0 in Get Amplifier Gain: Read as 0s (No Input Amplifier Gain).
Payload[15] is 1 in Get Amplifier Gain: Read as 0s (No Output Amplifier Gain).

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Datasheet
Codec Response for NID=18h (MIC1, port-B) and 1Ah (LINE1, port-C)
Bit
Description
31:8
0s.
7
Payload[15] is 0 in Get Amplifier Gain: Read as 0 (No Input Amplifier Mute).
Payload[15] is 1 in Get Amplifier Gain: Output Amplifier Mute, 0:Unmute 1:Mute (Default=1)
6:0
Payload[15] is 0 in Get Amplifier Gain: Input Amplifier Gain [6:0].
The volume 0dB/20dB/40dB in 20dB per step. (Default=0, 0dB)
Payload[15] is 1 in Get Amplifier Gain: Read as 0s (No Output Amplifier Gain).

Codec Response for NID=19h (MIC2, port-F)

Bit
Description
31:8
0s.
7
Payload[15] is 0 in Get Amplifier Gain: Read as 0 (No Input Amplifier Mute).
Payload[15] is 1 in Get Amplifier Gain: Read as 0 (No Output Amplifier Mute).
6:0
Payload[15] is 0 in Get Amplifier Gain: Input Amplifier Gain [6:0].
The volume 0dB/20dB/40dB in 20dB per step. (Default=0, 0dB)
Payload[15] is 1 in Get Amplifier Gain: Read as 0s (No Output Amplifier Gain).
Codec Response for NID=14h (LINE-OUT, port-D)
Bit
Description
31:8
0s.
7
Payload[15] is 0 in Get Amplifier Gain: Read as 0 (No Input Amplifier Mute).
Payload[15] is 1 in Get Amplifier Gain: Output Amplifier Mute, 0:Unmute 1:Mute (Default=1)
6:0
Payload[15] is 0 in Get Amplifier Gain: Read as 0s (No Input Amplifier Gain).
Payload[15] is 1 in Get Amplifier Gain: Read as 0s (No Output Amplifier Gain).

Codec Response for NID=15h (HP-OUT, port-A)

Bit
Description
31:8
0s.
7
Payload[15] is 0 in Get Amplifier Gain: Read as 0 (No Input Amplifier Mute).
Payload[15] is 1 in Get Amplifier Gain: Output Amplifier Mute, 0:Unmute 1:Mute (Default=1)
6:0
Payload[15] is 0 in Get Amplifier Gain: Read as 0s (No Input Amplifier Gain).
Payload[15] is 1 in Get Amplifier Gain: Read as 0s (No Output Amplifier Gain).

Codec Response for NID=1Dh (PCBEEP)

Bit
Description
31:8
0s.
7
Payload[15] is 0 in Get Amplifier Gain: Read as 0 (No Input Amplifier Mute).
Payload[15] is 1 in Get Amplifier Gain: Read as 0 (No Output Amplifier Mute).
6:0
Payload[15] is 0 in Get Amplifier Gain: Input Amplifier Gain [6:0] specifying the volume from 24dB
to 0dB in 3dB per step. (Default=0000001b, -21dB)
Payload[15] is 1 in Get Amplifier Gain: Read as 0s (No Output Amplifier Mute).

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Datasheet
Codec Response for NID=12h (Digital MIC DMIC-12) and 13h (Digital MIC DMIC-34)
Bit
Description
31:8
0s.
7
Payload[15] is 0 in Get Amplifier Gain: Read as 0 (No Input Amplifier Mute).
Payload[15] is 1 in Get Amplifier Gain: Read as 0 (No Output Amplifier Mute).
6:0
Payload[15] is 0 in Get Amplifier Gain: Read as 0s (No Input Amplifier Gain).
Payload[15] is 1 in Get Amplifier Gain: Read as 0s (No Output Amplifier Gain).

Codec Response for NID=16h (MONO-OUT)

Bit
Description
31:8
0s.
7
Payload[15] is 0 in Get Amplifier Gain: Read as 0 (No Input Amplifier Mute).
Payload[15] is 1 in Get Amplifier Gain: Output Amplifier Mute, 0:Unmute 1:Mute (Default=1)
6:0
Payload[15] is 0 in Get Amplifier Gain: Read as 0s (No Input Amplifier Gain).
Payload[15] is 1 in Get Amplifier Gain: Read as 0s (No Output Amplifier Gain).

Codec Response for NID=23h and 24h (Multiplexer widgets in front of ADCs)
Bit
Description
31:8
0s.
7
Payload[15] is 0 in Get Amplifier Gain: Read as 0 (No Input Amplifier Mute for all index.).
Payload[15] is 1 in Get Amplifier Gain: Output Amplifier Mute, 0:Unmute 1:Mute (Default=1)
6:0
Payload[15] is 0 in Get Amplifier Gain: Read as 0s (No Input Amplifier Gain for all index).
Payload[15] is 1 in Get Amplifier Gain: Output Amplifier Gain [6:0] specifying the volume
from 16.5dB to 30dB in 1.5dB per step. (Default=0000001b, -15dB)

Codec Response to Other NID

Bit
Description
31:0
Not supported (returns 00000000h).

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ALC268 Series
Datasheet

8.12. Verb Set Amplifier Gain (Verb ID=3h)

This verb is used to set amplifier gain/attenuation in each widget.
Table 44. Verb Set Amplifier Gain (Verb ID=3h)
Set Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Bit [19:8]
Verb ID=3h

Payload Bit [7:0]

Set payload [7:0]

Codec Response Format

Response [31:0]
0s for all nodes

Set Payload in Command Bit[15:0]

Bit
Description
15
Set Output Amp.
1 indicates output amplifier gain will be set.
14
Set Input Amp.
1 indicates input amplifier gain will be set.
13
Set Left Amp.
1 indicates left amplifier gain will be set.
12
Set Right Amp.
1 indicates right amplifier gain will be set.
11:8
Index Offset (for input amplifiers on Sum widgets and Selector Widgets).
5 bits index offset in connection list is used to select which input gain will be set on a mixer or a
multiplexer widget. The index is ignored if the node is not a mixer or a multiplexer widget, or the Set
Input Amp bit is not set.
7
Mute.
0: Unmute
1: Mute (- gain)
6:0

Gain[6:0].
A 7-bit step value specifying the amplifier gain.

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Datasheet

8.13. Verb Get Converter Format (Verb ID=Ah)

Get Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Table 45. Verb Get Converter Format (Verb ID=Ah)

Codec Response Format
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Verb ID=Ah
0s
Bit[15:0] are converter format

Codec Response for NID=02h, 03h, 06h (Output Converters: LOUT1 DAC, LOUT2 DAC, S/PDIF-OUT).
Codec Response for NID=07h, 08h (Input Converters: MIC ADC, LINE ADC)
Bit
Description
31:16
Reserved. Read as 0.
15
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
Sample Base Rate Multiple (MULT).
000b: *1 001b: *2
010b: *3 011b: *4
100b~111b: Reserved.
10:8
Sample Base Rate Divisor (DIV).
000b: /1 001b: /2
010b: /3
011b: /4 100b: /5
101b: /6 110b: /7 111b: /8
The ALC268 does not support Divisor. Always read as 000b.
7
Reserved. Read as 0.
6:4
Bits per Sample (BITS).
000b: 8 bits
001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved
3:0
Number of Channels.
0: 1 channel 1: 2 channels 2: 3 channels .. 15: 16 channels

NID=02h (LOUT1 DAC)

NID=03h (LOUT2 DAC)
NID=06h (S/PDIF-OUT)
NID=07h (MIC ADC)
NID=08h (LINE ADC)

BASE
0
1
0
1
0
1
0
1
0
1

MULT
000b, 001b, 011b
000b
000b, 001b, 011b
000b
000b, 001b, 011b
000b, 001b
000b, 001b
000b
000b, 001b
000b

DIV
000b
000b
000b
000b
000b
000b
000b
000b
000b
000b

BITS
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b, 100b
001b, 010b, 011b, 100b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b
001b, 010b, 011b

Sample rate
48K, 96K,192K
44.1K
48K, 96K,192K
44.1K
48K, 96K, 192K
44.1K, 88.2K
48K, 96K
44.1K
48K, 96K
44.1K

Codec Response for other NID

Bit
Description
31:0
Not supported (returns 00000000h).
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ALC268 Series
Datasheet

8.14. Verb Set Converter Format (Verb ID=2h)

Set Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Table 46. Verb Set Converter Format (Verb ID=2h)

Codec Response Format
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Verb ID=2h
Set format [15:0]
0s for all nodes

Set Payload in Command Bit[15:0]

Bit
Description
31:16
Reserved. Read as 0.
15
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
Sample Base Rate Multiple (MULT).
000b: *1 001b: *2
010b: *3 011b: *4
100b~111b: Reserved.
10:8
Sample Base Rate Divisor (DIV).
000b: /1 001b: /2
010b: /3
011b: /4 100b: /5
101b: /6 110b: /7 111b: /8
7
Reserved. Read as 0.
6:4
Bits per Sample (BITS).
000b: 8 bits
001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved
3:0
Number of Channels.
0: 1 channel 1: 2 channels 2: 3 channels .. 15: 16 channels

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Datasheet

8.15. Verb Get Power State (Verb ID=F05h)

Table 47. Verb Get Power State (Verb ID=F05h)
Get Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Bit [19:8]
Verb ID=Ah

Codec Response Format

Response [31:0]
Power State [7:0]

Payload Bit [7:0]

0s

Codec Response for NID=01h (Audio Function Group)

Bit
Description
31:6
Reserved. Read as 0s.
5:4
PS-Act. Actual Power State [1:0].
00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set.
3:2
Reserved. Read as 0s.
1:0
PS-Set, Set Power State [1:0].
00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3
PS-Set controls the current power setting of the referenced node.
Note: Specific blocks will be powered down in each power state. Refer to section 7.5 Power Management, page 23.

Codec Response for other NID

Bit
Description
31:0
Not supported (returns 00000000h).

8.16. Verb Set Power State (Verb ID=705h)

Table 48. Verb Set Power State (Verb ID=705h)
Set Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Bit [19:8]
Verb ID=705h

Payload Bit [7:0]

Power State [7:0]

Codec Response Format

Response [31:0]
0s for all nodes

Power State in Command Bit[7:0]

Bit
Description
7:6
Reserved. Read as 0s.
5:4
PS-Act. Actual Power State [1:0].
00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3
PS-Act indicates the actual power state of the referenced node.
3:2
Reserved. Read as 0s.
1:0
PS-Set. Set Power State [1:0].
00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3

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ALC268 Series
Datasheet

8.17. Verb Get Converter Stream, Channel (Verb ID=F06h)

Table 49. Verb Get Converter Stream, Channel (Verb ID=F06h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=F06h
0s
Stream & Channel [7:0]

Codec Response for NID=02h, 03h, 06h (Output Converters: LOUT1 DAC, LOUT2 DAC, S/PDIF-OUT).
Codec Response for NID=07h, 08h (Input Converters: MIC ADC, LINE ADC)
Bit
Description
31:8
Reserved. Read as 0s.
7:4
Stream[3:0].
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
3:0
Channel[3:0].
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1
for its left and right channel.

Codec Response for other NID

Bit
Description
31:0
Not supported (returns 00000000h).

8.18. Verb Set Converter Stream, Channel (Verb ID=706h)

Table 49. Verb Set Converter Stream, Channel (Verb ID=706h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=706h
Stream & Channel [7:0]
0s for all nodes
Stream and Channel in Command Bit[7:0]
Bit
Description
31:8
Reserved. Read as 0s.
7:4
Set Stream[3:0].
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
1:0
Set Channel[3:0].
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1
for its left and right channel.
Note: This verb assigns stream and channel for output converters (NID=02h, 03h, 06h) and input converters
(NID=07h,08h). Other widgets will ignore this verb.

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8.19. Verb Get Pin Widget Control (Verb ID=F07h)

Table 50. Verb Get Pin Widget Control (Verb ID=F07h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=F07h
0s
Pin Control [7:0]
Codec Response for pin widget NID=12h (DMIC-12), 13h (DMIC-34), 14h (LINE-OUT), 15h (HP-OUT), 16h (MONO),
18h (MIC1), 19h (MIC2), 1Ah (LINE1), 1Ch (CD-IN), 1Dh (PCBEEP) and 1Eh (S/PDIF-OUT)
Bit
Description
31:1
Reserved. Read as 0s.
7
H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit).
0: Disabled
1: Enabled
Note: Only HP-OUT (NID=15h) and LINE-OUT (NID=14h) support the headphone amplifier.
6
Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit).
0: Disabled
1: Enabled
Note: DMIC-12(NID=12h),DMIC-34(NID=13h), MIC2 (NID=19h), CD-IN(NID=1Ch), and
PCBEEP(NID=1Dh) do not support output.
5
In Enable (Input Buffer Enable, EN_IBUF for a I/O unit).
0: Disabled
1: Enabled
Note: MONO-OUT (NID-16h) does not support input.
4:3
Reserved.
2:0
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled)
001b: 50% of AVDD
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD
101b: 100% of AVDD
110b~111b: Reserved
Note: Only MIC1 (NID=18h), MIC2 (NID=19h) and LINE1 (NID=1Ah) support reference voltage
outputs.
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h).

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8.20. Verb Set Pin Widget Control (Verb ID=707h)

Set Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Table 51. Verb Set Pin Widget Control (Verb ID=707h)

Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID=707h
Pin Control [7:0]
0s for all nodes

Pin Control in command [7:0]: pin widget NID=12h (DMIC-12), 13h (DMIC-34), 14h (LINE-OUT), 15h (HP-OUT),
16h (MONO), 18h (MIC1), 19h (MIC2), 1Ah (LINE1), 1Ch (CD-IN), 1Dh (PCBEEP) and 1Eh (S/PDIF-OUT)
Bit
Description
31:1
Reserved. Read as 0s.
7
H-Phn Enable.
0: Disabled
1: Enabled
Note: Only HP-OUT (NID=15h) and LINE-OUT (NID=14h) support the headphone amplifier.
6
Out Enable.
0: Disabled
1: Enabled
Note; DMIC-12(NID=12h),DMIC-34(NID=13h), MIC2 (NID=19h), CD-IN(NID=1Ch), and
PCBEEP(NID=1Dh) do not support output.
5
In Enable (Input Buffer Enable, EN_IBUF for a I/O unit).
0: Disabled
1: Enabled
Note: MONO-OUT (NID-16h) does not support input.
4:
Reserved.
2:0
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled)
001b: 50% of AVDD
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD)
101b: 100% of AVDD
110b~111b: Reserved
Note: Only MIC1 (NID=18h), MIC2 (NID=19h) and LINE1 (NID=1Ah) support reference voltage
outputs.

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8.21. Verb Get Unsolicited Response Control (Verb ID=F08h)

Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real time event.
Table 52. Verb Get Unsolicited Response Control (Verb ID=F08h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=F08h
0s
32-bit Response
Codec Response for NID=01h (GPIO in Audio Function Group), 14h~16h (port jack detect), 18h~1Bh (port jack detect)
Bit
Description
31:8
Reserved. Read as 0s.
7
Unsolicited Response is Enabled.
0: Disabled
1: Enabled
6:4
Reserved. Read as 0s.
3:0
Assigned Tag for Unsolicited Response.
The tag[3:0] is assigned by software to determine which widget generates unsolicited responses.
Codec Response for other NID
Bit
Description
31:0
Not supported (returns 00000000h).

8.22. Verb Set Unsolicited Response Control (Verb ID=708h)

Enable a widget to generate an unsolicited response.
Table 53. Verb Set Unsolicited Response Control (Verb ID=708h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=708h
EnableUnsol [7:0]
0s for all nodes
EnableUnsol in Command Bit[7:0]
For NID=01h (GPIO in Audio Function Group), 14h~16h (port jack detect), 18h~1Bh (port jack detect)
Bit
Description
31:8
Reserved. Read as 0s.
7
Enable Unsolicited Response.
0: Disable
1: Enable
6:4
Reserved. Read as 0s.
3:0
Tag for Unsolicited Response.
Tag[3:0] is defined by software to assign a 4-bit tag for nodes that are enabled to generate unsolicited
responses.

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8.23. Verb Get Pin Sense (Verb ID=F09h)

Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 54. Verb Get Pin Sense (Verb ID=F09h)
Get Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Bit [19:8]
Verb ID=F09h

Codec Response Format

Response [31:0]
32-bit Response

Payload Bit [7:0]

0s

Codec Response: Pin widget 14h (LINE-OUT), 15h (HP-OUT), 18h (MIC1), 19h (MIC2), 1Ah (LINE1)
Bit
Description
31
Presence Detect Status.
0: No device is attached to the pin
1: Device is attached to the pin
30:0
Measured Impedance.
Note: The ALC268 does not support impedance sensing. Read as 0s.

Codec Response for other NID

Bit
Description
31:0
Not supported (returns 00000000h).

8.24. Verb Execute Pin Sense (Verb ID=709h)

Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Table 55. Verb Execute Pin Sense (Verb ID=709h)

Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID=709h
Right Channel[0]
0s for all nodes

Payload in Command Bit[7:0]

Bit
Description
7:1
Reserved. Read as 0s.
0
Right (Ring) Channel Select.
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)
Note: The ALC268 does not support Execute Pin Sense and will ignore this verb and respond with 0s.

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8.25. Verb Get Configuration Default (Verb ID=F1Ch)

Read the 32-bit sticky register for each Pin Widget configured by software.
Table 56. Verb Get Configuration Default (Verb ID=F1Ch)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh Verb ID=F1Ch
0s
32-bit Response

Codec Response for Pin Widget: NID=14h (LINE-OUT), 15h (HP-OUT), 16h (MONO-OUT), 18h (MIC1), 19h (MIC2),
1Ah (LINE1), 1Ch (CD-IN), 1Dh (PCBEEP), 1Eh (S/PDIF-OUT), 12h (DMIC-12) and 13h (DMIC-34)
Bit
Description
31:0
32-bit configuration information for each pin widget.
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).

8.26. Verb Set Configuration Default Bytes 0, 1, 2, 3

(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and
1Eh~1Fh such as placement and expected default device.
Table 57. Verb Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Label [7:0]
0s for all nodes
Verb ID=71Ch,
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=14h (LINE-OUT), 15h (HP-OUT), 16h (MONO-OUT), 18h (MIC1), 19h (MIC2),
1Ah (LINE1), 1Ch (CD-IN), 1Dh (PCBEEP), 1Eh (S/PDIF-OUT), 12h (DMIC-12) and 13h (DMIC-34). Other widgets
will ignore this verb.

Codec Response for All NID

Bit
Description
31:0
0s.

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8.27. Verb Get BEEP Generator (Verb ID=F0Ah)

Get Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Table 58. Verb Get BEEP Generator (Verb ID=F0Ah)

Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID=F1Bh
0s
Divider [7:0]

Response for NID=01h (Audio Function Group)

Bit
Description
31:8
Reserved.
7:0
Frequency Divider, F[7:0].
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0].
The lowest tone is 48kHz/(255*4)=47Hz.
The highest tone is 48kHz/(1*4)=12kHz.
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Codec Response for Other NID
Bit
Description
31:0
0s.

8.28. Verb Set BEEP Generator (Verb ID=70Ah)

Set Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=Xh

Table 59. Verb Set BEEP Generator (Verb ID=70Ah)

Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID=71Bh
Divider [7:0]
0s for all nodes

Divider in Set Command

Bit
Description
31:8
Reserved.
7:0
Frequency Divider, F[7:0].
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified
in F[7:0].
The lowest tone is 48kHz/(255*4)=47Hz.
The highest tone is 48kHz/(1*4)=12kHz.
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for All NID

Bit
Description
31:0
0s.

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8.29. Verb Get GPIO Data (Verb ID=F15h)

Table 60. Verb Get GPIO Data (Verb ID=F15h)
Get Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=01h

Bit [19:8]
Verb ID=F15h

Codec Response Format

Response [31:0]
32-bit Response

Payload Bit [7:0]

0s

Codec Response for NID=01h (Audio Function Group)

Bit
Description
31:8
Reserved.
7:4
GPIO[7:4] Data. Not supported in the ALC268.
3:0
GPIO[3:0] Data.
The value written (output) or sensed (input) on the corresponding pin if it is enabled.

Codec Response for Other NID

Bit
Description
31:0
0s.

8.30. Verb Set GPIO Data (Verb ID=715h)

Table 61. Verb Set GPIO Data (Verb ID=715h)
Set Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=01h

Bit [19:8]
Verb ID=715h

Payload Bit [7:0]

Data [7:0]

Codec Response Format

Response [31:0]
0s for all nodes

Data in Set command for NID=01h (Audio Function Group)

Bit
Description
31:8
Reserved.
7:4
GPIO[7:4] output Data. Not supported in the ALC268.
3:0
GPIO[3:0] Output Data.
The value written determines the value driven on a pin that is configured as an output pin.

Codec Response for All NID

Bit
Description
31:0
0s.

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8.31. Verb Get GPIO Enable Mask (Verb ID=F16h)

Table 62. Verb Get GPIO Enable Mask (Verb ID=F16h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=01h Verb ID=F16h
0s
EnableMask [7:0]

Codec Response for NID=01h (Audio Function Group)

Bit
Description
31:8
Reserved.
7:4
Reserved.
3:0
GPIO[3:0] Enable mask
0: The corresponding GPIO pin is disabled and is in Hi-Z state.
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control.
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for Other NID

Bit
Description
31:0
0s.

8.32. Verb Set GPIO Enable Mask (Verb ID=716h)

Set Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=01h

Table 63. Verb Set GPIO Enable Mask (Verb ID=716h)

Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID=716h
Enable Mask [7:0]
0s for all nodes

Codec Response for NID=01h (Audio Function Group)

Bit
Description
31:8
Reserved.
7:4
GPIO[7:4] Enable Mask, Not supported in the ALC268
3:0
GPIO[3:0] Enable Mask
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for All NID

Bit
Description
31:0
0s.

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8.33. Verb Get GPIO Direction (Verb ID=F17h)

Get Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=01h

Table 64. Verb Get GPIO Direction (Verb ID=F17h)

Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID=F17h
0s
Direction [7:0]

Codec Response for NID=01h (Audio Function Group)

Bit
Description
31:8
Reserved.
7:4
GPIO[7:4] Direction Control. Not supported in the ALC268.
3:0
GPIO[3:0] Direction Control.
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0s.

8.34. Verb Set GPIO Direction (Verb ID=717h)

Set Command Format
Bit [31:28]
Bit [27:20]
Cad=X
Node ID=01h

Table 65. Verb Set GPIO Direction (Verb ID=717h)

Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID=717h
Direction [7:0]
0s for all nodes

Codec Response for NID=01h (Audio Function Group)

Bit
Description
31:8
Reserved.
7:4
GPIO[7:4] Direction Control. Not supported in the ALC268.
3:0
GPIO[3:0] Direction Control.
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.

Codec Response for Other NID

Bit
Description
31:0
0s.

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8.35. Verb Get GPIO Unsolicited Response Enable Mask

(Verb ID=F19h)
Table 66. Verb Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=01h Verb ID=F19h
0s
UnsolEnable [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
Description
31:8
Reserved.
7:4
GPIO[7:4] Unsolicited Enable Mask. Not supported in the ALC268.
3:0
GPIO[3:0] Unsolicited Enable mask.
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0s.

8.36. Verb Set GPIO Unsolicited Response Enable Mask

(Verb ID=719h)
Table 67. Verb Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=01h Verb ID=719h
UnsolEnable [7:0]
0s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
Description
31:8
Reserved.
7:4
GPIO[7:4] Unsolicited Enable Mask. Not supported in the ALC268
3:0
GPIO[3:0] Unsolicited Enable Mask.
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Note 2: The unsolicited response of corresponding GPIO is enabled when its Enable Mask and Verb-Unsolicited
Response for NID=01h are enabled.
Codec Response for Other NID
Bit
Description
31:0
0s.
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8.37. Verb Function Reset (Verb ID=7FFh)

Table 68. Verb Function Reset (Verb ID=7FFh)
Command Format (NID=01H)
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=01h Verb ID=7FFh
0s
0s

Codec Response
Bit
Description
31:0
Reserved. Read as 0s.
Note: The Function Reset command causes all widgets in the ALC268 to return to their power-on default state.

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8.38. Verb Get Digital Converter Control 1 & Control 2

(Verb ID=F0Dh, F0Eh)
Table 69. Verb Get Digital Converter Control 1 & Control 2 (Verb ID=F0Dh, F0Eh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh Verb ID=F0Dh/
0s
Bit[31:16]=0s, Bit[15:0] are SIC bit
F0Eh

NID=06h (S/PDIF-OUT) Response to Get verb F0Dh (Control 1 for SIC bit[15:0]).
NID=06h (S/PDIF-OUT) Response to Get verb F0Eh (Control 2 for SIC bit[15:0])
Bit
Description SIC (S/PDIF IEC Control) Bit[7:0]
31:16
Read as 0s.
15
Reserved. Read as 0s.
14:8
CC[6:0] (Category Code).
7
LEVEL (Generation Level).
6
PRO (Professional or Consumer format).
0: Consumer format
1: Professional format
5
/AUDIO (Non-Audio Data type).
0: PCM data
1: AC3 or other digital non-audio data
4
COPY (Copyright).
0: Asserted
1: Not asserted
3
PRE (Pre-emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
VCFG for Validity Control (control V bit and data in Sub-Frame).
1
V for Validity Control (control V bit and data in Sub-Frame).
0
Digital Enable. DigEn.
0: OFF
1: ON
Codec Response for Other NID
Bit
Description
31:0
0s.

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8.39. Verb Set Digital Converter Control 1 & Control 2

(Verb ID=70Dh, 70Eh)
Table 70. Verb Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Set Command Format (Verb ID=70Dh, Set Control 1)
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh Verb ID=70Dh
SIC [7:0]
0s

Set Command Format (Verb ID=70Eh, Set Control 2)

Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Cad=X
Node ID=Xh
Verb ID=70Eh
SIC [15:8]

Codec Response Format

Response [31:0]
0s

Payload in Set Control 1 for NID=06h (S/PDIF-OUT)

Bit
Description SIC (S/PDIF IEC Control) Bit[7:0]
7
LEVEL (Generation Level).
6
PRO (Professional or Consumer format).
0: Consumer format
1: Professional format
5
/AUDIO (Non-Audio Data type).
0: PCM data
1: AC3 or other digital non-audio data
4
COPY (Copyright).
0: Asserted
1: Not asserted
3
PRE (Pre-emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
VCFG for Validity Control (control V bit and data in Sub-Frame).
1
V for Validity Control (control V bit and data in Sub-Frame).
0
Digital Enable. DigEn.
0: OFF
1: ON

Payload in Set Control 2 for NID=06h (S/PDIF-OUT)

Bit
Description SIC (S/PDIF IEC Control) Bit[7:0]
7
Reserved. Read as 0s.
6:0
CC[6:0] (Category Code).

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8.40. Get/Set Volume Knob Widget (Verb ID=F0Fh/70Fh)

Table 71. Get/Set Volume Knob Widget (Verb ID=F0Fh/70Fh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=F0Fh
0s
Bit[31:8]=0s, Bit[7:0] is volume
Codec Response for Volume Knob Widget
Bit
Description
31:8
Reserved.
7
Direct.
0: The volume generated by an external HW volume control will be sent by unsolicited response.
Software is responsible for programming the amplifier appropriately
1: The volume generated by an external HW volume control will directly affect amplifier volume
6:0
Volume in steps.
Note: The ALC268 does not support volume knob widget will ignore this verb and respond with 0s.
Set Command Format (Verb ID=70Fh)
Bit [31:28]
Bit [27:20]
Bit [19:8]
Cad=X
Node ID=Xh
Verb ID=70Fh

Payload Bit [7:0]

Bit[7] is Direct control

Codec Response Format

Response [31:0]
0s

Payload in Set Command for Volume Knob Widget

Bit
Description
31:8
Reserved.
7
Direct.
0: The volume generated by an external HW volume control will be sent by unsolicited response.
Software is responsible for programming the amplifier appropriately
1: The volume generated by an external HW volume control will directly affect amplifier volume
6:0
Reserved.
Note: The ALC268 does not support volume knob widget will ignore this verb and respond with 0s.

8.41. Get/Set Subsystem ID [31:0]

(Verb ID=F20h / 723h~720h to Set Bit[31:0])
Table 72. Get/Set Subsystem ID [31:0] (Verb ID=F20h / 723h~720h to Set Bit[31:0])
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Cad=X
Node ID=Xh
Verb ID=F20h
0s
32 bits response
Codec Response for NID=01h (Audio Function Group)
Bit
Description
31:16
Subsystem ID[23:8]. (Default=10Ech)
15:8
Subsystem ID[7:0]. (Default=02h).
7:0
Assembly ID[7:0]. (Default=68h).
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ALC268 Series
Datasheet

9.
9.1.
9.1.1.

Electrical Characteristics
DC Characteristics
Absolute Maximum Ratings

Parameter
Power Supplies:
Digital power for core
Digital Power for link
Analog power
Ambient Operating
Temperature
Storage Temperature

Table 73. Absolute Maximum Ratings

Symbol
Minimum
Typical
DVDD
DVDD-IO
AVDD1, AVDD2
Ta

3.0
1.5
3.0
0

3.3
3.3
3.3
-

Ts

Maximum

Units

3.6
3.6
5.5
+70

V
V
V
o
C
o

+125

ESD (Electrostatic Discharge)

Susceptibility Voltage
4000V
Note: DVDD-IO must be lower than DVDD.
If customers have lower AVDD(=3.0V) request, please contact Realtek sales representatives or agents

9.1.2.

Threshold Voltage

DVDD-IO=3.3V5%, Tambient=25C, with 50pF external load.

Parameter
Input Voltage Range
Low Level Input Voltage
(BCLK, RST#, SDO, SYNC, SDI)
High Level Input Voltage
(BCLK, RST#, SDO, SYNC, SDI)
Low Level Input Voltage
(S/PDIF-OUT, GPIOs)
High Level Input Voltage
(S/PDIF-OUT, GPIOs)
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current (Hi-Z)
Output Buffer Drive Current
Internal Pull Up Resistance

2+2 Channel High Definition Audio Codec

Table 74. Threshold Voltage

Symbol
Minimum
Typical
Vin
-0.30
VIL
-

Maximum
DVDD +0.30
0.30*DVDDIO

Units
V
V

VIH

0.65* DVDDIO

VIL

0.44*DVDD

VIH

0.56* DVDD

VOH
VOL
-

0.9*DVDD
-10
-10
-

5
50k

0.1*DVDD
10
10
-

V
V
A
A
mA

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Datasheet

9.1.3.

Digital Filter Characteristics

Filter
ADC Lowpass Filter

DAC Lowpass Filter

9.1.4.

Table 75. Digital Filter Characteristics

Symbol
Minimum
Typical
Passband
0
Stopband
28.8
Stopband Rejection
-76.0
Passband Ripple
0.02
Passband
0
Stopband
28.8
Stopband Rejection
-78.5
Passband Ripple
0.02

Maximum
0.454*Fs (-1dB)

0.454*Fs (-1dB)

Units
kHz
kHz
dB
dB
kHz
kHz
dB
dB

S/PDIF Output Characteristics

DVDD=3.3V, Tambient=25C, with 75 external load.

Parameter
S/PDIF-OUT High Level Output
S/PDIF-OUT Low Level Output

Table 76. S/PDIF Input/Output Characteristics

Symbol
Minimum
Typical
Maximum
VOH
3.0
3.3
VOL
0
0.3

2+2 Channel High Definition Audio Codec

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Units
V
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ALC268 Series
Datasheet

9.2.

AC Characteristics

9.2.1.

Link Reset and Initialization Timing

Table 77. Link Reset and Initialization Timing

Parameter
Symbol
Minimum
Typical
RESET# Active Low Pulse Width
TRST
1.0
RESET# Inactive to BCLK
TPLL
20
Startup delay for PLL ready time
SDI Initialization Request
TFRAME
-

4 BCLK

Maximum
-

Units
s
s

Frame Time

Initialization
Sequence

>= 4 BCLK

4 BCLK

BCLK
Normal Frame
SYNC

SYNC
SDO

Initialization
Request

SDI

RESET#
TRST

TPLL

T FRAME

Figure 16. Link Reset and Initialization Timing

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Datasheet

9.2.2.

Link Timing Parameters at the Codec

Table 78. Link Timing Parameters at the Codec

Symbol
Minimum
Typical
Maximum
24.0
Tcycle
41.67
Tjitter
2.0
Thigh
18.75
22.91
(45%)
(55%)
BCLK Low Pulse Width
Tlow
18.75
22.91
(45%)
(55%)
Tsetup
2.1
SDO Setup Time at Both Rising
and Falling Edge of BCLK
Thold
2.1
SDO Hold Time at Both Rising and
Falling Edge of BCLK
Ttco
7.5
8.0
SDI Valid Time After Rising Edge
of BCLK (1: 50pF external load)
SDI Flight Time
Tflight
2.0
Parameter
BCLK Frequency
BCLK Period
BCLK Jitter
BCLK High Pulse Width

Units
MHz
ns
ns
ns
(%)
ns
(%)
ns
ns
ns
ns

T_cycle
T_high

BCLK

V IH
VT
V IL
T_setup

T_hold

T_low

SDO

T_tco
VOH

SDI
VOL
T_flight

Figure 17. Link Signals Timing

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ALC268 Series
Datasheet

9.2.3.

S/PDIF Output Timing

Table 79. S/PDIF Output Timing

Parameter
Symbol
Minimum
Typical
S/PDIF-OUT Frequency *1
3.072
*1
S/PDIF-OUT Period
Tcycle
325.6
S/PDIF-OUT Jitter
Tjitter
*1
S/PDIF-OUT High Level Width
THigh
156.2 (48%)
162.8 (50%)
S/PDIF-OUT Low Level Width*1
TLow
156.2 (48%)
162.8 (50%)
S/PDIF-OUT Rising Time
Trise
2.0
S/PDIF-OUT Falling Time
Tfall
2.0
*1: Bit parameters for 48kHz sample rate of S/PDIF-OUT

Maximum
4
169.2 (52%)
169.2 (52%)
-

Units
MHz
ns
ns
ns (%)
ns (%)
ns
ns

Tcycle
Thigh

Tlow

VOH

VIH

Vt

VIL

V OL
Trise

T fall

Figure 18. Output Timing

9.2.4.

Test Mode

The ALC268 does not support codec test mode or Automatic Test Equipment (ATE) mode.

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ALC268 Series
Datasheet

9.3.

Analog Performance

Standard Test Conditions

Tambient=25 oC, DVDD-CORE=3.3V 5%, AVDD=5.0V5%

1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms

10K/50pF load; Test bench Characterization BW:10Hz~22kHz

Table 80. Analog Performance

Parameter
Min
Typ
Full Scale Input Voltage
All ADC (gain=0dB)
1.1
Full Scale Output Voltage
All DAC (gain=0dB)
1.4
Dynamic Range with 1kHz tone, DR (A Weighted)
ADC
90
DAC
95
Total Harmonic Distortion plus Noise, THD+N
ADC
-85
DAC
-92
-80
Headphone Out @32 Load
Frequency Response
ADC (-3dB lower edge, -1dB higher edge)
10
DAC (-3dB lower edge, -1dB higher edge)
10
Power Supply Rejection Ratio
-40
Total Out-of-Band Noise (28.8kHz~100kHz)
-60
Amplifier Gain Step
ADC
1.5
DAC
1.0
Crosstalk Between Input Channels
-80
Input Impedance (gain=0dB)
47
Output Impedance
Amplified Output
1
Non-amplified Output
200
Digital Power Supply Current (normal operation)
DVDD=3.3V, DVDD-IO=3.3V
Digital Power Supply Current (power down mode)
DVDD=3.3V, DVDD-IO=3.3V
Analog Power Supply Current (normal operation)
AVDD1, AVDD2=5.0V
AVDD1, AVDD2=3.3V
Analog Power Supply Current (power down mode)
AVDD1, AVDD2=5.0V
VREFOUTx Output Voltage
VREFOUTx Output Current
Note: FSA=Full Scale with A-weighting filter
FS=Full Scale
2+2 Channel High Definition Audio Codec

69

Max

Units

Vrms

Vrms

dB FSA*
dB FSA

dB FS*
dB FS
dB FS

0.454*Fs
0.454*Fs
-

Hz
Hz
dB
dB

dB
dB
dB
K

25

mA

400

35
19

mA
mA

2.50
5

700
4.20

A
V
mA

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ALC268 Series
Datasheet

10.

Application Notes

10.1. Application Circuits

Please contact Realtek for the latest application circuits. To get the best compatibility in hardware design
and software driver, any modification should be confirmed by Realtek. Realtek may upload the latest
application circuits onto our web site (www.realtek.com.tw) without modifying this datasheet.
MIC1-VREFO-R
GPIO1 (Power by AVDD)
MIC2-VREFO
MIC1-VREFO-L
R1

MIC2-JD

20K, 1%
C5
10u

LOUT-L

+5VA

LOUT-R
25
AVDD1

26
AVSS1

28

29

27
VREF

MIC1-VREFO-L

MIC2-VREFO

LINE1-VREFO

31

30

GPIO1

32

33
NC

MIC1-VREFO-R

Sense B

35

34

DMIC-CLK

C23
+

C16

1u

19

C17

1u

18

C19

1u

MIC2-L

13

PCBEEP

C24
10
C26
R13

DMIC-12 or GPIO0

C28

DMIC-34 or GPIO3

10p

CD-IN

14

NC

R11

CN1

15

Sense A

0.1u

4
3
2
1

MIC2-R

16

C25

10u

MIC1-L

20

17

NC

RESET#

DVDD

SPDIFO

MIC1-R

12

EAPD

1
+3.3VD

LINE-OUT-L

MIC2-L

11

48

MIC2-R

NC

SYNC

47

EAPD
S/PDIF-OUT

NC

10

46

DMIC-CLK

CD-L

DVDD-IO

45

ALC268

NC

LINE1-L

21

CD-GND

44

SDATA-IN

43

AVSS2

LINE1-R

22

CD-R

DVSS-IO

42

20K, 1%

HP-OUT-R

41

BIT-CLK

HP-OUT-R

R5

MIC1-L

10u

23

LINE1-L

JDREF

C7

24

LINE1-R

MIC1-R

40

0.1u

HP-OUT-L

SDATA-OUT

39

0.1u

HP-OUT-L

DVSS

10u

C15

GPIO3/DMIC-34

AVDD2

C14

MONO

GPIO0/DMIC-12

38

37

MONO-OUT
+5VA

LINE-OUT-R

36

C8
U1

NC

10

SY NC

C30

C29
+

0.1u

10u

5.1K, 1%

R7

10K, 1%

R8

20K, 1%

R9

39.2K,1%
R10

1u
RESET#

R6

47K

LOUT-JD
LINE1-JD
MIC1-JD
HP-JD
CN2
1
2

C27
100P

R12

BEEP_IN

10K

+3.3VD

SDIN

DGND

AGND

Tied at one point only under the

codec or near the codec

R16

10

R17

10

BCLK

C34
10p

SDOUT

C36
10p

Figure 19. Filter Connection

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ALC268 Series
Datasheet
PH1

Standby +5V

+12V

LOUT-L

C1
C2

LOUT-R

100u

LOUT-JD

100u

For Standby mode De-pop purpose

LINE-OUT-OUT (Jack-D)

Rear Panel

IN

FERB

MIC1-R
MIC1-L

R2

10

PH2
MIC1-JD

GND

OUT

+10u

100P

1N4148

LM7805CT/200mA
3

C4

100P
D2

B130LAW/1N5817

+5VA

C3

CN
CS
1
3
4
5

C6

1u

C9

1u

R3

2.2K

R4

2.2K

MIC1-VREFO-R

+100u

MIC1-VREFO-L

For improving the background

noise of MIC boosting.

CN
CS
1
3
4
5

C10

C11

MIC1(Jack-B)

100P

100P

Rear Panel

PH3
LINE1-JD
LINE1-R
LINE1-L

C18

1u

C20

1u

Configuation: (Standard Case)

Rear Panel: 3 dedicated audio jacks

Front Panel: 2 dedicated audio jacks
Pin/Port Assignment

Location

Functions

FRONT(pin-35,36)/Port-D

Rear Panel

LINE-OUT w/ amplfier

MIC1 (pin-21,22)/Port-B

Rear Panel

Mic-In

LINE1 (pin-23,24)/Port-C

Rear Panel

Line-In

HP-OUT (pin-39,41)/Port-A

Front Panel

HP-OOUT w/ amplifier

MIC2 (pin-16,17)/Port-F

Front Panel

Mic-In

CN
CS
1
3
4
5

C21

C22

LINE1(Jack-C)

100P

100P

Rear Panel

Figure 20. Power and Rear Panel Jack Connection

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ALC268 Series
Datasheet
HD Audio Front Panel I/O Cable

D3

MIC2-VREFO

D4

J2

FIO-MICIN-L
FIO-MICIN-R
FIO-HPOUT-R
FIO-JD
FIO-HPOUT-L

1N4148
1N4148

1
3
5
7
9

2
4
6
8
10

FMIC-JD-RETURN

KEY

FHP-JD-RETURN

CON10A

MIC2-L
MIC2-R
HP-OUT-L
HP-OUT-L

C31

1u

C32

1u

C33

100u

C35

100u

R14

R15

2.2K

2.2K

FIO-JD

J1
1
3
5
7
9

For re-tasking purpose,

Non-Polarity Caps are
recommended

2
4
6
8
10

FIO-MICIN-R

L2

FERB

FIO-MICIN-L

L3

FERB

MIC2-JD

Key

HP-JD

JACK 1
4
3
5

FMIC-JD-RETURN

C37

C38

100P

100P

2
1
FIO-MICIN

CON10A

Front panel header

FIO-JD

JACK 2
FHP-JD-RETURN

FIO-HPOUT-R

L4

FERB

FIO-HPOUT-L

L5

FERB
C40

C41

100P

100P

4
3
5
2
1
FIO-HPOUT

Figure 21. Front Panel Header and Front Panel I/O Cable

As the ALC268 does not support LINE2 (port-E), the HP-OUT (port-A) may be connected to the front
panel header as the headphone output. To accommodate the ALC268 and ALC262 on the same front
panel I/O cable, the connection of the front panel header in Figure 21 is modified. Please contact Realtek
to confirm your design can accommodate all ALC series HD Audio Codecs
S/PDIF module option 1: Optical
U3

Optical Transmitter

TOTX178

VCC
2

IN

N.C

N.C
GND

R21

C39
0.1u

10

S/PDIF-OUT

+5VD

S/PDIF module option 2: Coaxial

S/PDIF OUTPUT
J3

C42

R23

200
S/PDIF-OUT

C43

0.01u

100P

R24

100

Figure 22. S/PDIF-OUT Connection

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ALC268 Series
Datasheet

10.2. Digital Microphone Implementation

This section describes the ALC268 digital microphone implementation. There is one Clock output pin
and 1 Data input pin in the ALC268. The ALC268 provides the clock signal to the digital microphone.
When the digital microphone receives the external sound input, it converts the analog signals to digital in
a 1-bit format. The 1-bit data is delivered to the codec though the data input pin. The Digital Filter in the
audio codec converts the 1-bit data stream into Pulse Code Modulation (PCM) data. The PCM data is sent
to the HDA controller through the HDA link.

Figure 23. Digital Microphone Implementation-1

The ALC268 supports 2-wire and 3-wire interfaces for the digital microphone and operates in single
channel (mono type) or stereo channels (stereo) digital microphone mode. One pin is clock output to the
digital microphone, and the other two are serial pins. The default clock output is 2.048MHz.
In Type 1 (Figure 24), the ALC268 uses one data pin to support mono input from digital microphones
with an LMV1024 (L), SPD0205ND (L), or AKU2000 (L).
In Type 2 (Figure 24), the ALC268 uses one data pin to support stereo inputs from digital microphones
with an LMV1024/1026 (L/R), SPD0205ND (L & R), or AKU2000 (L & R).

Figure 24. Digital Microphone Implementation-2

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ALC268 Series
Datasheet

11. Mechanical Dimensions

11.1. LQFP-48 Mechanical Dimensions

L
L1
See the Mechanical Dimensions notes on the next page.

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ALC268 Series
Datasheet

11.2. LQFP-48 Mechanical Dimensions Notes

SYMBOL

A
A1
A2
c
D
D1
D2
E
E1
E2
b
e
TH
L
L1

MIN.

MILLIMETER
TYP
MAX.

0.05
1.35
0.09

1.60
0.15
1.45
0.20

1.40

9.00 BSC
7.00 BSC
5.50
9.00 BSC
7.00BSC
5.50
0.17
0.20
0.27
0.50 BSC
0o
3.5o
7o
0.45
0.60
0.75
1.00

MIN.

0.002
0.053
0.004

INCH
TYP

0.055

MAX

0.063
0.006
0.057
0.008

0.354 BSC
0.276 BSC
0.217
0.354 BSC
0.276 BSC
0.217
0.007 0.008
0.011
0.0196 BSC
0o
3.5o
7o
0.018 0.0236 0.030
0.0393

TITLE: LQFP-48 (7.0x7.0x1.6mm)

PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm
LEADFRAME MATERIAL
APPROVE
DOC. NO.
VERSION
02
CHECK
DWG NO.
PKGC-065
DATE
REALTEK SEMICONDUCTOR CORP.

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ALC268 Series
Datasheet

11.3. QFN-48 Mechanical Dimensions

MILLIMETER
MIN. TYPICAL MAX.
A
0.80
0.85
1.00
A1
0.00
0.02
0.05
A2
--0.65
1.00
A3
--0.20
---0
b
0.18
0.23
0.30
D
7.00 BSC
D1
6.75 BSC
D2
2.25
4.70
5.25
E
7.00 BSC
E1
6.75 BSC
E2
2.25
4.70
5.25
e
0.50 BSC
L
0.30
0.40
0.50
TH
0o
--12o
aaa
----0.25
bbb
----0.10
chamfer ----0.60

SYMBOL

INCH
MIN. TYPICAL MAX
0.031 0.033 0.039
0.000 0.001 0.002
--0.026 0.039
--0.008
--0.007 0.009 0.012
0.276 BSC
0.266 BSC
0.089 0.185 0.207
0.276 BSC
0.266 BSC
0.089 0.185 0.207
0.020 BSC
0.012 0.016 0.020
0o
--12o
----0.010
----0.004
----0.024

2+2 Channel High Definition Audio Codec

TITLE: QFN-48 (7.0x7.0x1.0mm)

PACKAGE OUTLINE DRAWING
LEADFRAME MATERIAL
APPROVE
DOC. NO.
VERSION
CHECK
DWG NO.
DATE
REALTEK SEMICONDUCTOR CORP.

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ALC268 Series
Datasheet

12. Ordering Information

Table 81. Ordering Information
Part Number
Package
Status
ALC268-GR
LQFP-48 & Green package
Sample
ALC268Q-GR
QFN-48 & Green package
Sample
Note 1: Above parts are tested under AVDD =5.0V. If customers have lower AVDD request, please contact Realtek
sales representatives or agents.

Realtek Semiconductor Corp.

Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
2+2 Channel High Definition Audio Codec

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