AT91RM9200 Architecture (Q&A) - Saeri 23

AR91RM9200 ARCHITECTURE
1. Explain briefly the AR91RM9200 architecture.

Answer: AT91RM9200 is a complete system-on-chip built around the ARM920T ARM Thumb
processor. It incorporates a rich set of system and application peripherals and standard interfaces
in order to provide a single-chip solution for a wide range of compute-intensive applications that
require maximum functionality at minimum power consumption at lowest cost.
The AT91RM9200 incorporates a high-speed on-chip SRAM workspace, and a low-latency
External Bus Interface (EBI) for seamless connection to whatever configuration of off-chip
memories and memory-mapped peripherals is required by the application. The EBI incorporates
controllers for synchronous DRAM (SDRAM), Burst Flash and Static memories and features
specific circuitry facilitating the interface for NAND Flash/Smart Media and CompactFlash.
The Advanced Interrupt Controller (AIC) enhances the interrupt handling performance of the
ARM920T processor by providing multiple vectored, prioritized interrupt sources and reducing
the time taken to transfer to an interrupt handler.
The Peripheral DMA Controller (PDC) provides DMA channels for all the serial peripherals,
enabling them to transfer data to or from on- and off-chip memories without processor
intervention. This reduces the processor overhead when dealing with transfers of continuous data
streams. The AT91RM9200 benefits from a generation of PDC which includes dual pointers that
significantly simplify buffer chaining.
The set of Parallel I/O (PIO) controllers multiplex the peripheral input/output lines with general-
purpose data I/Os for maximum flexibility in device configuration. An input change interrupt,
open drain capability and programmable pull-up resistor is included on each line.
The Power Management Controller (PMC) keeps system power consumption to a minimum by
selectively enabling/disabling the processor and various peripherals under software control. It
uses an enhanced clock generator to provide a selection of clock signals including a slow clock
(32 kHz) to optimize power consumption and performance at all times.
The AT91RM9200 integrates a wide range of standard interfaces including USB 2.0 Full Speed
Host and Device and Ethernet 10/100 Base-T Media Access Controller (MAC), which provides
connection to an extensive range of external peripheral devices and a widely used networking
layer. In addition, it provides a rich set of peripherals that operate in accordance with several
industry standards, such as those used in audio, telecommunication, Flash Card, infrared and
Smart Card applications.
2. Explain briefly about the memory mapping of AT91RM9200 architecture.

Answer: Memory mapping is divided into 3 memory mapping techniques. They are,
i. External memory mapping
ii. Internal memory mapping
iii. Peripheral mapping
 System peripheral mapping
 User peripheral mapping
External memory mapping:
A first level of address decoding is performed by the Memory Controller, i.e., by the
implementation of the Advanced System Bus (ASB) with additional features. Decoding splits the
4G bytes of address space into 16 areas of 256M bytes. The areas 1 to 8 are directed to the EBI
that associates these areas to the external chip selects NC0 to NCS7. The area 0 is reserved for
the addressing of the internal memories, and a second level of decoding provides 1M bytes of
internal memory area. The area 15 is reserved for the peripherals and provides access to the
Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them
provides an abort to the master requesting such an access.
Internal memory mapping:
 Internal RAM – The AT91RM9200 integrates a high-speed, 16-Kbyte internal SRAM. After
reset and until the Remap Command is performed, the SRAM is only accessible at address
0x20 0000. After Remap, the SRAM is also available at address 0x0.
 Internal ROM – The AT91RM9200 integrates a 128-Kbyte Internal ROM. At any time, the
ROM is mapped at address 0x10 0000. It is also accessible at address 0x0 after reset and
before the Remap Command if the BMS is tied high during reset.
 USB Host Port – The AT91RM9200 integrates a USB Host Port Open Host Controller
Interface (OHCI). The registers of this interface are directly accessible on the ASB Bus and
are mapped like a standard internal memory at address 0x30 0000.
Peripheral memory mapping:
i. System peripheral mapping: The System Peripherals are mapped to the top 4K bytes of
the address space, between the addresses 0xFFFF F000 and 0xFFFF FFFF. Each
peripheral has 256 or 512 bytes.
ii. User peripheral mapping: The User Peripherals are mapped in the upper 256M bytes of
the address space, between the addresses 0xFFFA 0000and 0xFFFE 3FFF. Each
peripheral has a 16-Kbyte address space.

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AR91RM9200 ARCHITECTURE

1. Explain briefly the AR91RM9200 architecture.

2. Explain briefly about the memory mapping of AT91RM9200 architecture.

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