‫‪2016\2017‬‬ ‫أ‪.‬م‪.‬د‪.

‬ﻣﯾﺳﺎء ﻋﺑد ﻋﻠﻲ ﺧﺿراﻟدﺑﺎس‬ ‫اﻟﺟﺎﻣﻌﺔ اﻟﺗﻛﻧوﻟوﺟﯾﺔ‪/‬ﻗﺳم ﻋﻠوم اﻟﺣﺎﺳوب‬

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‫‪3rd class‬‬
‫‪Computer Architecture / Course 2‬‬

‫اﺳﺗﺎذة اﻟﻣﺎدة‪:‬أ‪.‬م‪.‬د‪ .‬ﻣﯾﺳﺎء ﻋﺑد ﻋﻠﻲ ﺧﺿر‬

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Lecture One
Protected Mode Software Architecture of the 80386DX
1- Introduction:
It can be dealing with large size in protected mode is 230 equal 1 Gag byte and 4
Gag byte equal 32 line addressing.
In real mode can be dealing with large size is 220 equal 1 mega byte. In virtual
address can be dealing with large size is 64Tira byte equal 264.
• Paging address = offset + Selector ==== protected mode.
• Physical address = offset + base ==== real mode.
2- Registers in protected Mode 80386DX:
In protected mode find five new registers addition to register in real mode.
a- Global Descriptor Table Register (GDTR).
b- Interrupt Descriptor Table Register (IDTR).
c- Local Descriptor Table Register (LDTR).
d- Control Register (CR).
e- Task Register (TR).
• Furthermore, the functions of a few registers have been extended. For example,
the instruction pointer, which is now called EIP; more bits of the flag register
(EFLAGS) are active; and all four control register, CR0 through CR3 are
functional, as shown in Figure (31).

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‫‪Figure 31. The protected mode register model.‬‬

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a- Global Descriptor Table Register (GDTR): the contents of the global descriptor
table register defines a table in the 80386DX physical address space called the
global descriptor table (GDT). This global descriptor table is one important
element of the 80386DX memory management system.
GDTR is a 48-bit register that is located inside the 80386DX . the lower 2 bytes
of this register, which are identified as LIMIT specify the size in bytes of the
GDT. The value of LIMIT is 1 less than the actual size of the table. If LIMIT
equal 00FFH the table is 256 bytes in the length.
The upper 4 bytes of the GDTR, which are labeled BASE in locate the beginning
of GDT in physical memory. This 32-bit base address allows the table to be
position anywhere in the 80386 DX linear address space. And each descriptor is
8bytes long. If global descriptor table is increased to its maximum size 65.536
bytes, it can hold up to 8192 descriptors.
For example 1:
If the limit and base in the global descriptor table register are 0FFFH and
00100000H respectively, what is the beginning address of the descriptor table, size
of the table in bytes and the ending address of the table?
Solution:
The starting address of the global descriptor table in physical memory is given
base. Therefore,
GDTSTART = 00100000H
The limit is the offset to the end of the table. This gives
GDTEND = 00100000H + 0FFFH = 00100FFFH
Finally, The table is equal to the decimal value of the LIMIT plus 1.
GDTSIZE = FFFH + 1H = 4096 bytes

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For example 2:
How many descriptor can be stored in the global descriptor table defined in
example 1?
Solution:
Each descriptor takes up 8 bytes: therefore, a 4096-byte table can hold
4096/8 = 512 descriptors
b- Interrupt Descriptor Table Register (IDTR): this register like global descriptor
table, the interrupt descriptor table register (IDTR) define a table in physical
memory. This table contains what are called interrupt descriptors, not segment
descriptors. For this reason, it is known as the interrupt descriptor table (IDT).
The IDTR is 48 bits in length. Again, the lower two bytes of the register
(LIMIT) define the table size. That is, the size of the table equals LIMIT + 1
bytes. The 2 bytes define the size, the IDT can be also be up to 256.536 bytes
exceptions. The upper 4 bytes of IDTR (BASE) identify the starting address of
IDT in physical memory, as shown in Figure(32).

Figure 32. The interrupt descriptor table mechanism.

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For Example 1:
What is the maximum value that should be assigned to LIMIT in the IDTR?
Solution:
The maximum number of interrupt descriptors that can be used in an 80386DX
microcomputer system is 256. Therefore, the maximum table size in byte is
IDTSIZE = 8 × 256 = 2048 bytes
For Example 2:
What is the address range of the last descriptor in the interrupt descriptor table
defined by base address 00011000H and limit 01FFH?
Solution:
From the values of the base and limit, it find the that table is located in the address
range define by
IDTSTART = 00011000H
And
IDTEND = IDTSTART + 01FF
IDTEND = 00011000H + 01FF
IDTEND = 000111FF
The last descriptor in this table takes up the 8 bytes of memory from address
000111F8H through 000111FFH.
c-Local Descriptor Table Register:
The local descriptor table register (LDTR) is also part of the 80386DX memory
management support mechanism. Each task can have access to its own private
descriptor table in addition to the global descriptor table. This private table is
called local descriptor table (LDT), and defines a local memory address space for
use by the task.
The LDT holds segments descriptor that provide access to code and data in
segments of memory that are reserved for the current task. The protected mode-
mode software system may contain many local descriptor tables. For reason we

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have identified LDT0 through LDTN. The contents of the LDT is 16- bits does
not directly define the local descriptor table. Instead, it holds a selector that points
to an LDT descriptor in the GDT, as shown in Figure (33).

Figure 33. The task with global and local descriptor tables.

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d-Control Register:
The protected model includes the four system-control registers, identified as CR0
through CR3, as shown in Figure (34).

Figure 34. The control registers.

These register in more detail, that the lower 5 bits of CR0 are system-control
flags. These bits make up what is known as the machine status word (MSW). The
most significant bit of CR0 and register CR2 and CR3 are used by the 80386DX
paging mechanism.
The machine status word bits of CR0 they contain information about 80386DX
protected mode configuration and status. The 4 bits labeled PE, MP, EM, and R
are control bits that define the protected mode system configuration. The fifth bit,
TS, is a status bit. These bit can be examined or modified through software.
PE = Protected-mode Enable.
PE = 0 is real mode by software.
PE = 1 is protected mode by software.
MP = Math Present.
MP = 1 is indicate that a numeric coprocessor is present in the microprocessor
system. The EM is 1
MP = 0 is indicate that a numeric coprocessor isn't present in the microprocessor
system. The EM is 0

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EM = Emulate Math.
EM= 1 is the software emulate to perform numeric operation. The MP is 1
EM = 0 is the software emulate not to perform numeric operation. The MP is 0
R= Extension Type.
R =1 is complement 80387 to 80386.
R= 0 is complement 80287 to 80286.
TS = Task Switch, automatically gets set (1) whenever the 80386DX switches
from on task to another it can be clear by software. In the other hand,
TS = 0 in the same task.
TS =1 transfer in the other task.
PG = Paging
PG = 0 is not paging the address is physical address in memory.
PG = 1 is paging the address is paging address in memory.
CR1 = Reserved.
CR2 = Page Fault Linear Address.
CR3 = Page Directory Base Register (PDBR).
e-Task Register:
The Task register is a key element in the protected mode task switching
mechanism of the 80386DX microprocessor. This register holds a 16-bit index value
called a selector the initial selector must be loaded into TR under software control.
This starts the initial task after this is done, the selector is changed automatically
whenever the 80386DX executes an instruction that perform a task switch.
3- Virtual Address and Virtual Address Space:
The protected mode memory management unit (MMU) employ memory pointer
that are 48 bits in length and consists of two parts, the selector and offset. This 48 bits
memory pointer is called virtual address is used by program to specify the memory
locations of instructions or data. As shown in Figure (35), the selector is 16 bits in length
and the offset is 32 bits in long.

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Virtual address
Selector Offset
47 32 31 0

Figure 35. The protected mode memory pointer.

The virtual address maximum is 64T bytes, the offset is held in one of 80386DX other
user-accessible register (code access) and the offset is EIP register. This part of the
pointer is the displacement of the memory location that is to be accessed within the
selected segment of memory.
For example:
It points the first byte of the double word of instruction code that is to be fetched for
execution. The offset is 32 bits in length, segment code size as large as 4G bytes. we say
as long as 4G bytes because segment size is actually variable and can be defined to be as
small as 1 byte to as large as 4G bytes, as shown in Figure (36).

Physical memory space Virtual memory space

.......... 4G 4G 4G
04G bytes bytes bytes
80386DX ………… ……….
Size memory ……. 4G
microprocessor bytes
space 4G ……….. 4G
bytes bytes
…… 4G …….. ………
bytes

Figure 36. The virtual memory space.

Each part in virtual memory space equal 4G bytes, this consider a max size.
For example:
What is the max size of segment in virtual memory space.
Solution:
The max size in virtual memory space in protected mode is 64T byte. And each part 4G
bytes. Where are T = 264 and 4G = 232
64T byte / 4G byte = 2 14 = 24×210 = 16×103 byte.

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4- Segment Partitioning of The Virtual Address Space:

The memory management unit of the 80386DX, both segment model and page
model of virtual memory. The segment model is 64T byte virtual address space is
partitioned into a 32T byte global memory address space and 32T byte local address
space, as shown in Figure (37). T1 bit of the selector is used to select between the
global or local descriptor tables that define the virtual address space.

Local Segment 8191

Local Segment 8190

.
.
. Local address space
.
. 32 Tira bytes
.

Local Segment 1

Local Segment 0
Virtual address space

64 Tira bytes
Global Segment 8191

Global Segment 8190

.
. Global address space
.
32 Tira bytes
.
.
.

Global Segment 1

Global Segment 0

Figure 37. The protected mode memory management and address space.

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5-
6- Segment Descriptor:
Each descriptor is consist of 8 byte task switching, called task state selector, as
shown in Figure (38).

Figure 38. Segment descriptor.

Limit = Limit 1619 + Segment Limit 015

Base = Segment base 015+Base 1623 + Base 2431
2 byte = GXO AVL called (Access Right)
Bit number :
P = present bit 7
PDL = descriptor Privilege bit 6 and 5 its take level 00,01,10,11
S =1 code or data or stack.
S = segment descriptor
S = 0 system segment descriptor or gate descriptor
Sequences Interrupt.
E = Executable bit 3 (This bit identify information data or code).
Data segment S = 1, E = 0  data segment
Code segment S = 0, E = 1 code segment

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Bit 1 and 2 when 1 bit E = 0 is data

1bit Write able
0 not be written into
W
1 may be written into
2 bit  Expansions Direction
0 upper expand up
ED
1 down expand down
1 and 2 bits (R)
0 code segment not be read
Read able
1code segment may be read
0 bit (A)
0 segment has not be access
Accessed
1 segment has been loaded into register
Q) what meaning protected mode?
1- Protected mode naming is the data protected during transmit to execute more task.
1- Protected mode naming is the access right and descriptor to existence want protected
data .

• Multi Tasking: Multi Tasking: is the more operation existence in the same time,
the process in 80386DX is divided the time to treatment many operation, as
shown in Figure (39).

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Figure 39. Multi tasking.

7- Hardware Organization of The Physical Address Space in Protected Mode:
The 4GB in protected mode in physical address space is divided in four banks 0,
1, 2, 3, as shown in Figure (40-a,b).

FFFFFFFFH
FFFFFFFFH
FFFFFFFFH

4GB

00000002 H
00000001 H
00000000 H

Figure 40-a. one of banks.

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In protected mode the 32-bit address bus the 80386DX results in a 4GB byte
physical memory address space. Each word is 32-bit or 4-byte.

Figure 40-b. The hardware organization of protected mode.

• The address of bank must be start of zero.
• Miss aline: address can be start in 2H , 3H, 4H, 5H must be 4-byte this address
take two cycle 2H, 3H in cycle one and 4H, 5H in cycle two, the type of address is
miss aline.
• a line: address can be start in 4H , 5H, 6H, 7H must be 4-byte this address take
one cycle, the type of address is aline.

8- Hardware Organization of The Physical Address Space in Real Mode:

The size of physical address is 1M equal 220 also divided in four banks each bank
the size is 256K and the byte enable is selector, as shown in Figure (41).

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Figure 41. The hardware organization of real mode.

• The byte enable is selector.
• 18 line address to calculated in 256k equal 28 ×210
For example 1: Is the word 0000123EH is aline or miss aline?
Solution:
0000123E, 0000123F in cycle one and 00001240, 00001241 in cycle two, this
address is miss aline.
For example 2: Is the word 0000123CH is aline or miss aline?
Solution:
0000123C, 0000123D and 0000123E, 0000123F in one cycle, this address is
aline.

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