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    Bahria University, Lahore Campus: Department of Computer Sciences

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    Abdul Basit
    The document describes a lab experiment on constructing comparator circuits using logic gates. The objectives are to design 1-bit and 2-bit comparators using Multisim and write their truth tables. For the 1-bit comparator, the student constructs the circuit on a breadboard and provides the truth table. For the 2-bit comparator, the student designs the circuit in Multisim and writes the corresponding 16-line truth table.

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    Bahria University, Lahore Campus: Department of Computer Sciences

    Uploaded by

    Abdul Basit
    80 views7 pages
    The document describes a lab experiment on constructing comparator circuits using logic gates. The objectives are to design 1-bit and 2-bit comparators using Multisim and write their truth tables. For the 1-bit comparator, the student constructs the circuit on a breadboard and provides the truth table. For the 2-bit comparator, the student designs the circuit in Multisim and writes the corresponding 16-line truth table.

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    DLD Lab 3

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    The document describes a lab experiment on constructing comparator circuits using logic gates. The objectives are to design 1-bit and 2-bit comparators using Multisim and write their truth tables. For the 1-bit comparator, the student constructs the circuit on a breadboard and provides the truth table. For the 2-bit comparator, the student designs the circuit in Multisim and writes the corresponding 16-line truth table.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    80 views7 pages

    Bahria University, Lahore Campus: Department of Computer Sciences

    Uploaded by

    Abdul Basit
    The document describes a lab experiment on constructing comparator circuits using logic gates. The objectives are to design 1-bit and 2-bit comparators using Multisim and write their truth tables. For the 1-bit comparator, the student constructs the circuit on a breadboard and provides the truth table. For the 2-bit comparator, the student designs the circuit in Multisim and writes the corresponding 16-line truth table.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 7

    Bahria University, Lahore Campus

    Department of Computer Sciences


    Lab Journal 09
    (Spring 2020)

    Course: Digital Logic Design Lab Date:


    Course Code: CEL-120 Max Marks: 40
    Faculty’s Name: Ms. Munazza Sher Lab Engineer: Mr. Shoaib Khan

    Name: _____________________________ Enroll No: _______________________

    Objective(s):

     To construct comparator circuit.

    Lab Tasks:

    Task 1: Design a simple 1-bit Comparator with basic logic gates using multisim. Also write its
    truth table.

    Task 2: Design a simple 2-bit Comparator with basic logic gates using multisim. Also write its
    truth table.

    NOTE: 2-bit comparator consists of four inputs and three outputs to generate less than, equal to
    and greater than between two binary numbers.

    Lab Grading Sheet :


    Max
    Obtained
    Task Mark Comments(if any)
    Marks
    s
    1. 10
    2. 10

    Total 20 Signature

    Note : Attempt all tasks and get them checked by your Lab Instructor
    Lab 09: Comparator Circuit

    Objective(s):

    “To construct comparator circuit”.

    Tool(s) used:

     KL-31001 DLD Trainer


     Module KL-33002
     Connector leads

    Overview:

    A comparator compares the equality and inequality between variables.

    Task 01+02: Time: 30 Minutes

    Comparator constructed with basic logic gates. Construct the circuit on breadboard.

    a) Theoretical

    Design
    Truth Table

    Input Output

    SW2 (B) SW1 (A) A>B A<B A=B

    0 0 0 0 1

    0 1 0 1 0

    1 0 1 0 0

    1 1 0 0 1
    Time: 30 Minutes

    Task 2: Design a simple 2-bit Comparator with basic logic gates using multisim. Also write its
    truth table.

    Design:
    Truth Table:

    Input Output

    A0 A1 B0 B1 A<B A=B A>B

    0 0 0 0 0 1 0

    0 0 0 1 1 0 0

    0 0 1 0 1 0 0

    0 0 1 1 1 0 0

    0 1 0 0 0 0 1

    0 1 0 1 0 1 0

    0 1 1 0 1 0 0

    0 1 1 1 1 0 0

    1 0 0 0 0 0 1

    1 0 0 1 0 0 1

    1 0 1 0 0 1 0

    1 0 1 1 1 0 0

    1 1 0 0 0 0 1

    1 1 0 1 0 0 1

    1 1 1 0 0 0 1

    1 1 1 1 0 1 0

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