CHAPTER 9

1. List the differences between the 8086 and the 8088 microprocessors.
The main differences are the data bus width (16 vs 8) and the IO/M signal.

2. Is the 8086/8088 TTL-compatible? Explain your answer.

TTL-compatible if the noise immunity figure is derated to 350 mV from the customary
400 mV.

3. What is the fan-out from the 8086/8088 to the following devices:

(a) 74XXX TTL
(b) 74ALSXXX TTL
(c) 74HCXXX CMOS
(a) 1 (b) 5 (c) 5

4. What information appears on the address/data bus of the 8088 while ALE is active?
Address bits

5. What are the purposes of status bits S3 and S4?

These bits indicate the segment being addressed by the current instruction.

6. What condition does a logic 0 on the 8086/8088 -RD pin indicate?

Read operation.

7. Explain the operation of the pin and the WAIT instruction.

The WAIT instruction waits for the TEST pin to become a logic zero.

8. Describe the signal that is applied to the CLK input pin of the 8086/8088 microprocessors.
Is generated by 8284 external clock.

9. What mode of operation is selected when MN/-MX is grounded?

Maximum mode

10. What does the strobe signal -WR from the 8086/8088 indicate about the operation of the
8086/8088?
Indicates a write operation.

11. When does ALE float to its high-impedance state?

Never.
12. When DT/-R is a logic 1, what condition does it indicate about the operation of the
8086/8088?
The data stream goes from 8086 to I/O. (data transmit)

13. What happens when the HOLD input to the 8086/8088 is placed at its logic 1 level?
The microprocessor stops executing software and places address, data, and control bus
at high-impedance

14. What three minimum mode 8086/8088 pins are decoded to discover whether the processor
is halted?
Depends on the mode:
- Maximum -S0..2
- Minimum IO/-M DT/-R -SS0

15. Explain the operation of -LOCK the pin.

The LOCK pin becomes a logic zero during instructions that pre prefixed with the LOCK:
prefix.

16. What conditions do the QS1 and QS0 pins indicate about the 8086/8088?
QS1 QS0 Function
0 0 Queue is idle
0 1 First byte of opcode
1 0 Queue is empty
1 1 Subsequent byte of opcode

17. What three housekeeping chores are provided by the 8284A clock generator?
The clock signal is provided, the RESET input is synchronized, and the READY input is
synchronized.

18. By what factor does the 8284A clock generator divide the crystal oscillator’s output
frequency?
Depends 3 for CLK and 6 for PCLK

19. If the F/-C pin is placed at a logic 1 level, the crystal oscillator is disabled. Where is the
timing input signal attached to the 8284A under this condition?
External frequency

20. The PCLK output of the 8284A is ____________ MHz if the crystal oscillator is operating at
14 MHz.
14/6
21. The -RES input to the 8284A is placed at a logic ____________ level in order to reset the
8086/8088.
0 - confirma cineva?? +1 de la dutu

22. Which bus connections on the 8086 microprocessor are typically demultiplexed?
Address/Data bus

23. Which bus connections on the 8088 microprocessor are typically demultiplexed?
Address/Data bus

24. Which TTL-integrated circuit is often used to demultiplex the buses on the 8086/8088?
Transparent latches ‘373 (8282)

25. What is the purpose of the demultiplexed signal on the 8086 microprocessor?
The BHE signal is shared with a status bit (S7) (asta e din pdf-ul cu solutii)

26. Why are buffers often required in an 8086/8088-based system?

Tri-state
They are present in the system, so the memory or I/O can receive data to be written, or
so the microprocessor can accept the data read from the memory or I/O for a read operation

27. What 8086/8088 signal is used to select the direction of the data flows through the 74LS245
bidirectional bus buffer?
DT/ -R (aici e vorba de three state-uri i guess)

28. A bus cycle is equal to clocking ____________ periods.

4 // daca luam si wait cycles in considerare vine 4-11 nu?

29. If the CLK input to the 8086/8088 is 4 MHz, how long is one bus cycle?
1.0 µs // un bus cycle normal are 4 cicli de ceas de unde iar un ciclu de ceas are 1/4MHz

30. What two 8086/8088 operations occur during a bus cycle?

Opcode fetch, Read/Write MEM/IO (din document pagina 6)

31. How many MIPS is the 8086/8088 capable of obtaining when operated with a 10 MHz
clock?
2.5 MIPS (din solutii)

32. Briefly describe the purpose of each T state listed: (a) T1 (b) T2 (c) T3 (d) T4 (e) Tw
T1 – send out an address – on address bus
T2 – send out a signal (read/ write) – on control bus
T3 – read/ write data on that location – on data bus
Tw - wait state pentru periferice lente
 T4 – release all buses

33. How much time is allowed for memory access when the 8086/8088 is operated with a 5 MHz
clock?
600 ns – 110 ns – 30 ns = 460 ns (din soultie era si in sumarul capitolului)

34. How wide is -DEN if the 8088 is operated with a 5 MHz clock?
// aici presupun ca vrea timpul semnalului -DEN

35. If the READY pin is grounded, it will introduce____________ states into the bus cycle of the
8086/8088.
Wait

36. What does the input to the 8284A accomplish?

Ajuta la generarea semnalelor de READY, RESET si CLK pentru 8086

37. What logic levels must be applied to and RDY1 to obtain a logic 1 at the READY pin?
(Assume that is at a logic 1 level.)
0

38. Contrast minimum and maximum mode 8086/8088 operation.

In modul minim microP isi genereaza singur semnalele
In cel maxim se foloseste un bus controller

39. What main function is provided by the 8288 bus controller when used with 8086/8088
maximum mode operation?
It generates system control signals

CHAPTER 10
1. What types of connections are common to all memory devices?
All memory devices have address, data, and control connections

2. List the number of words found in each memory device for the following numbers of address
connections: (a) 8 (b) 11 (c) 12 (d) 13 (e) 20
Aici e la modul iti da numarul de biti scoate numarul de cuvinte

3. List the number of data items stored in each of the following memory devices and the number
of bits in each datum: (a) 2K × 4 (b) 1K × l (c) 4K × 8 (d) 16K × 1 (e) 64K × 4
 (a) 2048 four bit numbers (b) 1024 one bit numbers (c) 4096 eight bit numbers (d)
16,384 one bit numbers (e) 65,536 four bit numbers.
4. What is the purpose of the -CS or -CE pin on a memory component?
Selecteaza componenta respectiva

5. What is the purpose of the -OE pin on a memory device?

Permite citirea din memoria respectiva

6. What is the purpose of the -WE pin on a SRAM?

Permite scrierea in memorie

7. How many bytes of storage do the following EPROM memory devices contain?
(a) 2708 -> 1K x 8 (cred)
(b) 2716 -> 2K x 8
(c) 2732 -> 4K x 8
(d) 2764 -> 8K x 8
(e) 27512 -> 16K x 8

Din raspunsurile lor: (a) 1K (b) 2K (c) 4K (d) 8K (e) 128K

8. Why won’t a 450 ns EPROM work directly with a 5 MHz 8088?

The basic speed of this EPROM is 450 ns. Recall that 8086 operated with a 5 MHz clock
allowed memory 460 ns to access data

9. What can be stated about the amount of time needed to erase and write a location in a flash
memory device?
Flash memory requires an extended amount of time to accomplish an erase and write.

10. SRAM is an acronym for what type of device?

Static Random Access Memory

11. The 4016 memory has a -G pin, an -S pin, and a -W pin. What are these pins used for in this
RAM?
The G input cause a read, the W input causes a write, and the S input selects the chip.

12. How much memory access time is required by the slowest 4016?
250 ns

13. DRAM is an acronym for what type of device?

Dynamic Random Access Memory

14. The 256M DIMM has 28 address inputs, yet it is a 256M DRAM. Explain how a 28-bit
memory address is forced into 14 address inputs.
15. What are the purposes of the CAS and RAS inputs of a DRAM?
These inputs strobe the column and row addresses into a DRAM.

16. How much time is required to refresh the typical DRAM?

15 us (ceva de ordinul microsecundelor este sigur zicea in curs din 2 in 2 ms se face
refresh) dap, 15 microsecunde

17. Why are memory address decoders important?

Selectarea bancului de memorie aferent

18. Modify the NAND gate decoder of Figure 10–13 to select the memory for address range
DF800H–DFFFFH.
19. Modify the NAND gate decoder in Figure 10–13 to select the memory for address range
40000H–407FFH.
20. When the G1 input is high and both and are low, what happens to the outputs of the
74HCT138 3-to-8 line decoder?
21. Modify the circuit of Figure 10–15 to address memory range 70000H–7FFFFH.
22. Modify the circuit of Figure 10–15 to address memory range 40000H–4FFFFH.
23. Describe the 74LS139 decoder.
24. What is VHDL?
25. What are the five major keywords in VHDL for the five major logic functions (AND, OR,
NAND, NOR, and invert)?
26. Equations are placed in what major block of a VHDL program?
27. Modify the circuit of Figure 10–19 by rewriting the PLD program to address memory at
locations A0000H–BFFFFH for the ROM.

28. The -RD and -WR minimum mode control signals are replaced by what two control signals in
the 8086 maximum mode?
MRDC si MWTC
IORC si IOWC

29. Modify the circuit of Figure 10–20 to select memory at location 60000H–77FFFH.
30. Modify the circuit of Figure 10–20 to select eight 27256 32K × 8 EPROMs at memory
locations 40000H–7FFFFH.
31. Add another decoder to the circuit of Figure 10–21 so that an additional eight 62256 SRAMs
are added at locations C0000H–FFFFFH.
32. The 74LS636 error-correction and detection circuit stores a check code with each byte of
data. How many bits are stored for the check code?
33. What is the purpose of the SEF pin on the 74LS636?
34. The 74LS636 will correct ________ bits that are in error.

35. Outline the major difference between the buses of the 8086 and 8088 microprocessors.
 8088 lucreaza doar pe 8 biti
36. What is the purpose of the BHE and A0 pins on the 8086 microprocessor?
-BHE - enables / disables the higher byte of the 16bit data bus (D8..15) (-BHE = 1 => bank 1 is
selected)
A0 = 0 => bank0 of memory is selected  

37. What is the -BLE pin and what other pin has it replaced?

38. What two methods are used to select the memory in the 8086 microprocessor?
Linear, Block si Absolut sunt 3 moduri (cu un bit + shadowing address, decoder,
respectiv print-o adresa unica)

39. If -BHE is a logic 0, then the ________ memory bank is selected.

lower

40. If A0 is a logic 0, then the ________ memory bank is selected.

higher

41. Why don’t separate bank read ( RD) strobes need to be developed when interfacing
memory to the 8086?
42. Modify the circuit of Figure 10–30 so that the RAM is located at memory range
30000H–4FFFFH.
43. Develop a 16-bit-wide memory interface that contains SRAM memory at locations
200000H–21FFFFH for the 80386SX microprocessor.
44. Develop a 32-bit-wide memory interface that contains EPROM memory at locations
FFFF0000H–FFFFFFFFH.
45. Develop a 64-bit-wide memory for the Pentium–Core2 that contains EPROM at locations
FFF00000H–FFFFFFFFH and SRAM at locations 00000000H–003FFFFFH.
46. On the Internet, search for the largest size EEPROM you can find. List its size and
manufacturer.

47. What is an -RAS-only cycle?

Un ciclu care reimprospateaza toate liniile de meomrie (cred)
A cycle that does not read data, it only refreshes a row of memory. (asta e bun din
solutii)

48. Can a DRAM refresh be done while other sections of the memory operate?
Cred ca da.
Nu cred. Pentru a lucra cu memoria, ai nevoie si de semnalul RAS, care in cazul asta e
folosit pentru refresh. Practic, cat se face refresh, nu poti sa folosesti memoria DRAM (asta e un
bottleneck care o face mai lenta decat SRAM)
49. If a 1M × 1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no more
than ________ of time must pass before another row is refreshed.
4ms / 256 = 0.015625 (15.625 µs)

50. How wide is the data bus in the Intel Itanium?

51. Scour the Internet to find the largest DRAM currently available.
52. Write a report on DDR memory. (Hint: Samsung makes them.)
53. Write a report that details RAMBUS RAM. Try to determine why this technology appears to
have fallen by the wayside.

CHAPTER 11
1. Explain which way the data flow for an IN and an OUT instruction.
The IN instruction inputs data from an external device into the accumulator and the OUT
instruction sends data out to an external device from the accumulator.

2. Where is the I/O port number stored for a fixed I/O instruction?
The I/O address is stored in the second byte of the instruction.

3. Where is the I/O port number stored for a variable I/O instruction?
DX

4. Where is the I/O port number stored for a string I/O instruction?
DX

5. To which register are data input by the 16-bit IN instruction?

AX

6. Describe the operation of the OUTSB instruction.

The OUTSB instruction transfers the data segment byte addressed by SI to the I/O port
addressed by DX, then SI is incremented by one.

7. Describe the operation of the INSW instruction.

The INSW inputs data from the I/O port addressed by DX, as a word, into the extra
segment memory location addressed by DI; it then increments DI by 2.

8. Contrast a memory-mapped I/O system with an isolated I/O system.

Memory mapped I/O uses any instruction that transfers data to or from the memory for
I/O, while isolated I/O requires the use of the IN or OUT instruction.
9. What is the basic input interface?
The basic input interface is a three-state buffer that is enabled for the IN instruction.
When the buffer is enabled data is gated onto the data bus and into the accumulator.

10. What is the basic output interface?

The basic output interface is a latch that captures output data and holds it for the output
device.

11. Explain the term handshaking as it applies to computer I/O systems.

Handshaking is the act of synchronizing two systems that operate asynchronously.

12. An even-number I/O port address is found in the __​Lower​_______ I/O bank in the 8086
Microprocessor.

13. In the Pentium 4, what bank contains I/O port number 000AH?
D8–D15

14. How many I/O banks are found in the Pentium 4 or Core2 microprocessor?
4

15. Show the circuitry that generates the upper and lower I/O write strobes.
16. What is the purpose of a contact bounce eliminator?
It removes mechanical bounces from a switch.

17. Develop an interface to correctly drive a relay. The relay is 12 V and requires a coil current
of 150 mA.
18. Develop a relay coil driver that can control a 5.0 V relay that requires 60 mA of coil current.

19. Develop an I/O port decoder, using a 74ALS138, that generates low-bank I/O strobes, for a
16-bit microprocessor, for the following 8-bit I/O port addresses: 10H, 12H, 14H, 16H, 18H,
1AH, 1CH, and 1EH.
20. Develop an I/O port decoder, using a 74ALS138, that generates high-bank I/O strobes, for a
16-bit microprocessor, for the following 8-bit I/O port addresses: 11H, 13H, 15H, 17H, 19H,
1BH, 1DH, and 1FH.

21. Develop an I/O port decoder, using a PLD, that generates 16-bit I/O strobes for the following
16-bit I/O port addresses: 1000H–1001H, 1002H–103H, 1004H–1005H, 1006H–1007H,
1008H–1009H, 100AH–100BH, 100CH–100DH, and 100EH–100FH.
22. Develop an I/O port decoder, using a PLD, that generates the following low-bank I/O
strobes: 00A8H, 00B6H, and 00EEH.

23. Develop an I/O port decoder, using a PLD, that generates the following high-bank I/O
strobes: 300DH, 300BH, 1005H, and 1007H.
24. Why are both and (A0) ignored in a 16-bit port address decoder?
If the port is 16 bits wide, there is no need to enable either the low or high half.

25. An 8-bit I/O device, located at I/O port address 0010H, is connected to which data bus
connections in a Pentium 4?
D0-D7
26. An 8-bit I/O device, located at I/O port address 100DH, is connected to which data bus
connections in a Core2 microprocessor?
D47–D40
BHE BLE
BASIC I/O INTERFACE 449
27. The 82C55 has how many programmable I/O pin connections?
24

28. List the pins that belong to group A and to group B in the 82C55.
Group A is port A and PC4–PC7, while group B is port B and PC3–PC0.

29. Which two 82C55 pins accomplish internal I/O port address selection?
A0 and A1

30. The connection on the 82C55 is attached to which 8086 system control bus connection?
RD

31. Using a PLD, interface an 82C55 to the 8086 microprocessor so that it functions at I/O
locations 0380H, 0382H, 0384H, and 0386H.
32. When the 82C55 is reset, its I/O ports are all initialized as __​Inputs​____.

33. What three modes of operation are available to the 82C55?

Modes 0, 1, and 2

34. What is the purpose of the signal in strobed input operation of the 82C55?
The strobe input latches the input data and sets the buffer full flag and interrupt request.

35. Develop a time delay procedure for the 2.0 GHz Pentium 4 that waits for 80 μs.
DELAY PROC NEAR
MOV ECX, 479904
.REPEAT
.UNTIL ECX == 0
RET
DELAY ENDP

36. Develop a time delay procedure for the 3.0 GHz Pentium 4 that waits for 12 ms.
DELAY PROC NEAR USES ECX
MOV ECX, 7272727
D1:
LOOPD D1
RET
DELAY ENDP
37. Explain the operation of a simple four-coil stepper motor.
The 4-coil stepper is moved by activating (passing current through) a single coil at a time
in round-robin fashion to move the armature a step at a time.

38. What sets the IBF pin in strobed input operation of the 82C55?
The strobe signal ( ST B )

39. Write the software required to place a logic 1 on the PC7 pin of the 82C55 during strobed
input operation.
IN AL,PORTC
OR AL,80H
OUT PORTA,AL

40. How is the interrupt request pin (INTR) enabled in the strobed input mode of operation of
the 82C55?
The INTR pin is enabled by setting the INTE bit in PC4 (port A) or PC2 (port B).

41. In strobed output operation of the 82C55, what is the purpose of the signal?
The ACK signal is used by the I/O device to inform the 8255 that the output data has
been processed by the output device.

42. What clears the signal in strobed output operation of the 82C55?
When data are output to the port becomes a 0 and when is sent to the port becomes a 1.

43. Write the software required to decide whether PC4 is a logic 1 when the 82C55 is operated
in the strobed output mode.
IN AL,PORTC
BT AL,4
JZ IF_ZERO

44. Which group of pins is used during bidirectional operation of the 82C55?
Group or port A contains the bidirectional data.

45. Which pins are general-purpose I/O pins during mode 2 operation of the 82C55?
PC0, PC1, and PC2

46. Describe how the display is cleared in the LCD display.

The 01H command is sent to the LCD display.

47. How is a display position selected in the LCD display?

A display position is select by sending a command that contains the 7-bit address with
the 8th and most significant bit set.
48. Write a short procedure that places an ASCII null string in display position 6 on the LCD
display.
;Displays the null terminated string addressed by DS:BX
;uses a macro called SEND to send data to the display
;
DISP PROC NEAR USES BX
SEND 86H, 2, 1 ;move cursor to position 6
.WHILE BYTE PTR [BX] != 0
SEND [BX], 0, 1
INC BX
.ENDW
RET
DISP ENDP

49. How is the busy flag tested in the LCD display?

A read command is issued and the leftmost bit of the data read from the LCD display is
the BUSY bit.

50. What changes must be made to Figure 11–25 so that it functions with a keyboard matrix that
contains three rows and five columns?
The only changes that need to be made are that instead of four rows there are three
rows and three pull-up resisters connected to port A and five columns to connect to port B. Of
course, the software also needs some minor changes.

51. What time is usually used to debounce a keyboard?

10–20 ms.

52. Develop the interface to a three- by four-key telephone-style keypad. You will need to use a
lookup table to convert to the proper key code.
53. The 8254 interval timer functions from DC to ____​10 MHz​____ Hz.

54. Each counter in the 8254 functions in how many different modes?
6

55. Interface an 8254 to function at I/O port addresses XX10H, XX12H, XX14H, and XX16H.
56. Write the software that programs counter 2 to generate an 80 KHz square wave if the CLK
input to counter 2 is 8 MHz.
57. What number is programmed in an 8254 counter to count 300 events?
300

58. If a 16-bit count is programmed into the 8254, which byte of the count is programmed first?
Least significant
59. Explain how the read-back control word functions in the 8254.
The counter is latched then the counter read-back control reads the counter at the time
of the latching.

60. Program counter 1 of the 8254 so that it generates a continuous series of pulses that have a
high time of 100 μs and a low time of 1 μs. Make sure to indicate the CLK frequency
required for this task.
61. Why does a 50% duty cycle cause the motor to stand still in the motor speed and direction
control circuit presented in this chapter?
The motor attempts to move forward and reverse for equal amounts of time. This causes
it to remain stationary.

62. What is asynchronous serial data?

Data that are sent a bit at a time without any clocking pulses

63. What is baud rate?

The number of transmitted bits per second including data, start, stop and any other bits
that are transferred.

64. Program the 16550 for operation using six data bits, even parity, one stop bit, and a baud
rate of 19,200 using a 18.432 MHz clock. (Assume that the I/O ports are numbered 20H
and 22H.)
LINE EQU 023H
LSB EQU 020H
MSB EQU 021H
FIFO EQU 022H
MOV AL,10001010B ;enable baud divisor
OUT LINE,AL
MOV AL,60 ;program baud rate
OUT LSB,AL
MOV AL,0
OUT MSB,AL
MOV AL,00011001B ;program 7-data, odd
OUT LINE,AL ;parity, one stop
MOV AL,00000111B ;enable transmitter and
OUT FIFO,AL ;and receiver

OBF
ACK
STB
RD
65. If the 16550 is to generate a serial signal at a baud rate of 2400 baud and the baud rate
divisor is programmed for 16, what is the frequency of the signal?
 614,400 Hz

66. Describe the following terms: simplex, half-duplex, and full-duplex.

Simplex = receiving or sending data;
half-duplex = receiving and sending data; but only one direction at a time;
full-duplex = receiving and sending data at the same time.

67. How is the 16550 reset?

The MR input pin resets the device.

68. Write a procedure for the 16550 that transmits 16 bytes from a small buffer in the data
segment address (DS is loaded externally) by SI (SI is loaded externally).
SENDS PROC NEAR
MOV CX,16
.REPEAT
.REPEAT
IN AL, LSTAT ;get line status register
TEST AL,20H ;test TH bit
.UNTIL !ZERO?
LODSB ;get data
OUT DATA,AL ;transmit data
.UNTILCXZ
RET
SENDS ENDP

69. The DAC0830 converts an 8-bit digital input to an analog output in approximately
__​1.0 μs​____.

70. What is the step voltage at the output of the DAC0830 if the reference voltage is -2.55 V?
0.01V

71. Interface a DAC0830 to the 8086 so that it operates at I/O port 400H.
72. Develop a program for the interface of question 71 so the DAC0830 generates a triangular
voltage wave-form. The frequency of this wave-form must be approximately 100 Hz.
73. The ADC080X requires approximately __​100 μs​____ to convert an analog voltage into a
digital code.

74. What is the purpose of the INTR pin on the ADC080X?

INTR indicates that the converter has completed a conversion.

75. The pin on the ADC080X is used for what purpose?

Start conversion
76. Interface an ADC080X at I/O port 0260H for data and 0270H to test the INTR pin.
77. Develop a program for the ADC080X in question 76 so that it reads an input voltage once
per 100 ms and stores the results in a memory array that is 100H bytes long.
78. Rewrite Example 11–29 using C++ with inline assembly code.

CHAPTER 12
1. What is interrupted by an interrupt?
An interrupt interrupts the currently executing program

2. Define the term interrupt.

Eveniment asincron...gargara de la SO

3. What is called by an interrupt?

The interrupt service procedure is called by an interrupt.

4. Why do interrupts free up time for the microprocessor?

Sunt asincrone that’s why

5. List the interrupt pins found on the microprocessor.

NMI, INTR, and INTA

6. List the five interrupt instructions for the microprocessor.

BOUND, INTO, INT, INT 3, and IRET

7. What is an interrupt vector?

The interrupt vector is the address of the interrupt service procedure.

8. Where are the interrupt vectors located in the microprocessor’s memory?

Locations from 00000H to 003FFH are used for the interrupt pointer table

9. How many different interrupt vectors are found in the interrupt vector table?
256

10. Which interrupt vectors are reserved by Intel?

11. Explain how a type 0 interrupt occurs.
INT 0 occurs for a divide error
12. Where is the interrupt descriptor table located for protected mode operation?
13. Each protected mode interrupt descriptor contains what information?
 A real mode interrupt vector is 4 bytes in length and contains the segment and offset
address of the interrupt service procedure, while a protected mode interrupt vector is 8 bytes in
length and contains the selector and 32-bit offset address of the interrupt service procedure
14. Describe the differences between a protected and real mode interrupt.
15. Describe the operation of the BOUND instruction.
The BOUND instruction tests the contents of a 16-bit register with two numbers stored
in the memory. If the register contains a number that is outside of the boundaries set by the
memory data, INT 5 occurs
16. Describe the operation of the INTO instruction.
17. What memory locations contain the vector for an INT 44H instruction?
INT 44H is stored at vector locations 110H–113H.

18. Explain the operation of the IRET instruction.

Este echivalentul ret-ului dintr-o functie normala doar ca este folosit in rutine de
intrerupere.

19. Where is the IRETQ instruction used?

20. What is the purpose of interrupt vector type number 7?
INT 7 is used to emulate a coprocessor

21. List the events that occur when an interrupt becomes active.
22. Explain the purpose of the interrupt flag (IF).
The I flag controls whether the INTR pin si enabled or disabled

23. Explain the purpose of the trap flag (TF).

Single step-execution mode for CPU (din amintire)
If this flag is set, the processor enters the single step execution mode by generating
internal interrupts after the execution of each instruction

24. How is IF cleared and set?

CLI and STI clear and set the interrupt flag.

25. How is TF cleared and set?

26. The NMI interrupt input automatically vectors through which vector type number?
INT 2
27. Does the signal activate for the NMI pin?

28. The INTR input is ___________-sensitive.

level

29. The NMI input is ___________-sensitive.

vector
30. When the INTA signal becomes a logic 0, it indicates that the microprocessor is waiting for
an interrupt ___________ number to be placed on the data bus (D0–D7).
Acknowledge cycle

31. What is an FIFO?

O coada...ghici ciuperca ce e

32. Develop a circuit that places interrupt type number CCH on the data bus in response to the
INTR input.

33. Develop a circuit that places interrupt type number 86H on the data bus in response to the
INTR input.
34. Explain why pull-up resistors on D0–D7 cause the microprocessor to respond with interrupt
vector type number FFH for the pulse.
The pull-ups force the inputs of the data bus to FFH when the interrupt acknowledge
cycle executes.

35. What is a daisy-chain?

Vezi labu

36. Why must interrupting devices be polled in a daisy-chained interrupt system?

Since the signals are ORed together to generate the interrupt, the only way to
determine which device caused the interrupt is to ask (poll) the devices.

37. What is the 8259A?

Programmable interrupt controller

38. How many 8259As are required to have 64 interrupt inputs?

9

39. What is the purpose of the IR0–IR7 pins on the 8259A?

Deserveste pentru diferite cereri de intrerupere

40. When are the CAS2–CAS0 pins used on the 8259A?

The CAS pins are used to cascade the 8259. Conectezi mai multe maxim 64
41. Where is a slave INT pin connected on the master 8259A in a cascaded system?
42. What is an OCW?
43. What is an ICW?
The ICW is the initialization control word.
44. Where is the vector type number stored in the 8259A?
45. How many ICWs are needed to program the 8259A when operated as a single master in a
system?
3
46. What is the purpose of ICW1?
47. Where is the sensitivity of the IR pins programmed in the 8259A?
LTIM in ICW1
48. Explain priority rotation in the 8259A.
49. What is a nonspecific EOI?
The nonspecific end of interrupt is used to clear the most recent interrupt request.
50. At which interrupt vectors is the master 8259A found in the personal computer?
51. What is the purpose of IRR in the 8259A?
The interrupt request register can be used to determine the levels found on the interrupt
inputs.
52. At which interrupt vectors is the slave 8259A found in the personal computer?
INT 70H through INT 77H

CHAPTER 13
1. Which microprocessor pins are used to request and acknowledge a DMA transfer?
HOLD and HLDA

2. Explain what happens whenever a logic 1 is placed on the HOLD input pin.
If HOLD signal is a logic 1, the microprocessor stops executing software and places
address, data, and control bus at high-impedance

3. A DMA read transfers data from ____________ to ____________.

Memory to I/O

4. A DMA write transfers data from ____________ to ____________.

I/O to Memory

5. The DMA controller selects the memory location used for a DMA transfer through what bus
signals?
A0–A7 and D0–D7 (where address bits A8–15 appear).
6. The DMA controller selects the I/O device used during a DMA transfer by which pin?
!IOR, !IOW
7. What is a memory-to-memory DMA transfer?
A memory-to-memory DMA transfer occurs when one channel addresses the source
address and another channel address a destination address. Data are then transferred from
source to destination.

8. Describe the effect on the microprocessor and DMA controller when the HOLD and HLDA
pins are at their logic 1 levels.
If HOLD signal is a logic 1, the microprocessor stops executing software and places
address, data, and control bus at high-impedance. HLDA iti spune doar ca se facu ACK-ul

9. Describe the effect on the microprocessor and DMA controller when the HOLD and HLDA
pins are at their logic 0 levels.
The DMA controller is in its hold state and the microprocessor operates normally

10. The 8237 DMA controller is a(n) ____________ channel DMA controller.
four-channel
11. If the 8237 DMA controller is decoded at I/O ports 2000H –200FH, what ports are used to
program channel 1?
2002H and 2003H
12. Which 8237 DMA controller register is programmed to initialize the controller?
13. How many bytes can be transferred by the 8237 DMA controller?
64K
14. Write a sequence of instructions that transfer data from memory location 21000H –210FFH
to 20000H –200FFH by using channel 2 of the 8237 DMA controller. You must initialize the
8237 and use the latch described in Section 12–1 to hold A19 –A16.
15. Write a sequence of instructions that transfers data from memory to an external I/O device
by using Channel 3 of the 8237. The memory area to be transferred is at location 20000H –
20FFFH.
16. What is a pen drive?
17. The 3 1/2 disk is known as a(n) ____________ floppy disk.
Micro
18. Data are recorded in concentric rings on the surface of a disk known as a(n) ____________.
19. A track is divided into sections of data called ____________.
Sectors
20. On a double-sided disk, the upper and lower tracks together are called a(n) ____________.
21. Why is NRZ recording used on a disk memory system?
NRZ recording is used because it erases old data when it records new data
22. Draw the timing diagram generated to write a 1001010000 using MFM encoding.
23. Draw the timing diagram generated to write a 1001010000 using RLL encoding.
24. What is a flying head?
25. Why must the heads on a hard disk be parked?
 The disk heads must be parked over a landing zone when power is removed so the
heads do not damage the surface of the disk
26. What is the difference between a voice coil head position mechanism and a stepper motor
head positioning mechanism?
27. What is a WORM?
A write once optical disk such as a CD-R or DVD-R.
28. What is a CD-ROM?
Un periferic
29. How much data can be stored on a common DVD, an HD-DVD, and a Blu-ray DVD?
4.7G bytes
30. What is the difference between a TTL monitor and an analog monitor?
31. What are the three primary colors of light?
Red, green, and blue
32. What are the three secondary colors of light?
33. What is a pixel?
The smallest video picture element
34. A video display with a resolution of 1280 × 1024 contains ____________ lines, with each
line divided into ____________ pixels.
35. Explain how a TTL RGB monitor can display 16 different colors.
By using 2 levels of brightness for each of the three primary colors
36. What are the DVI-D and HDMI connectors?
37. Explain how an analog RGB monitor can display an infinite number of colors.
Because the analog signal are continuously variable an infinite number of colors are
possible.
38. If an analog RGB video system uses 8-bit DACs, it can generate ____________ different
colors.
39. If a video system uses a vertical frequency of 60 Hz and a horizontal frequency of 32,400
Hz, how many raster lines are generated?
540