Design of High Speed Ddr3 Sdram Controller

DESIGN OF HIGH SPEED DDR3 SDRAM CONTROLLER
CHAPTER 1
INTRODUCTION OF DDR3 SDRAM
DEPT OF ECE, SBIT, KMM 1

1.1 DDR3 SDRAM:
In electronic engineering, DDR3 SDRAM or double-data-rate three

synchronous dynamic random access memories is a random access
memory technology used for high bandwidth storage of the working data
of a computer or other digital electronic devices. DDR3 is part of the
SDRAM family of technologies and is one of the many DRAM (dynamic
random access memory) implementations. DDR3 SDRAM is an
improvement over its predecessor, DDR2 SDRAM.
The primary benefit of DDR3 is the ability to transfer I/O data at

eight times the data rate of the memory cells it contains, thus enabling
higher bus rates and higher peak rates than earlier memory
technologies. However, there is no corresponding reduction in latency,
which is therefore proportionally higher. In addition, the DDR3 standard
allows for chip capacities of 512 megabits to 8 gigabits, effectively
enabling a maximum memory module size of 16 gigabytes.
The DDR3 SDRAM is not very much different from the previous
generation DDR memory in terms of its design and working principles. In
fact, it is true: DDR3 SDRAM is a sort of third reincarnation of DDR
SDRAM principles. Therefore, we are comparing DDR3 and DDR2
SDRAM side by side here.

Fig 1.1: comparison of DDR3 and DDR2 SDRAM
Courtesy: http://www.ijettjournal.org
The frequencies of DDR3 memory could be raised beyond those of

DDR2 due to doubling of the data pre-fetch, which was moved from the
info storage device to the input/output buffer. While DDR2 SDRAM uses
4-bit samples, DDR3 SDRAM uses 8-bit pre-fetch also known as 8n-
prefetch. In other words, DDR3 SDRAM technology implies doubling of
the internal bus width between the actual DRAM core and the
input/output buffer. As a result, the increase in the efficient data
transfer rate provided by DDR3 SDRAM doesn’t require faster operation
of the memory core. Only external buffers start working faster. As for the
core frequency of the memory chips, it appears 8 times lower than that of
the external memory bus and DDR3 buffers (this frequency was 4 times
lower than that of the external bus by DDR2). So, DDR3 memory can
almost immediately hit higher actual frequencies than DDR2 SDRAM,

without any modifications or improvements of the semiconductor

manufacturing process. However, the above described technique also has
another side to it: unfortunately, it increases not only memory
bandwidth, but also memory latencies. As a result, we shouldn’t always
expect DDR3 SDRAM to work faster than DDR2 SDRAM, even if it
operates at higher frequencies than DDR2.
The final DDR3 SDRAM specification released by JEDEC recently

describes a few modifications of this memory with frequencies from 800
to 1600MHz
However, DDR3 SDRAM offers a few other useful improvements

that will encourage not only the manufacturers but also the end users to
make up their minds in favor of the new technology. Among these
advantages I would like to first of all mention lower voltage of the DDR3
SDRAM modules that dropped down to 1.5V. It is 20% lower than the
voltage of DDR2 SDRAM modules, which eventually results into almost
30% reduction in power consumption compared with DDR2 memory
working at the same clock speeds. More advanced memory chips
manufacturing technologies also contribute to this positive effect.
Fig 1.2: Operating frequencies of DDR2 and DDR3 SDRAM

The BGA chip packaging also underwent a few modifications, and now it
features more contact pins. This simplifies the chip mounting procedure
and increases mechanical
1.2 DDR3 Based Lookup Circuit for High-Performance

Network Processing:
With the development of network systems, packet processing
techniques are becoming more important to deal with the massive high-
throughput packets of the internet. Accordingly, advances in memory
architectures are required to meet the emerging bandwidth demands.
Content Addressable Memory (CAM) based techniques are widely used in
network equipment for fast table look up. However, in comparison to
Random Access Memory (RAM) technology, CAM technology is restricted
in terms of memory density, hardware cost and power dissipation.
Recently, a Hash-CAM circuit, which combines the merits of the hash
algorithm and the CAM function, was proposed to replace pure CAM
based lookup circuits with comparable performance, higher memory
density and lower cost. Most importantly, off-chip high density low-cost
DDR memory technology has now become an attractive alternative for
the proposed Hash-CAM based lookup circuit. However, DDR technology
is optimized for burst access for cached processor platforms. As such,
efficient DDR Bandwidth utilization is a major challenge for lookup
functions that exhibit short and random memory access patterns. The
extreme low-cost and high memory density features of the DDR
technology allow a trade-off between memory utilization and memory-
bandwidth utilization by customizing the memory access. This, however,
requires a custom purpose DDR memory controller that is optimized to
achieve the best read efficiency and highest memory bandwidth. The
objective of this work was to investigate advanced DDR3 SDRAM

controller architectures and derive a customized architecture for the

abovementioned problem.
DDR3 SDRAM is the 3rd generation memories, featuring higher
performance and lower power consumption. In comparison with earlier
generations, DDR1/2 SDRAM, DDR3 SDRAM is a higher density device
and achieves higher bandwidth due to the further increase of the clock
rate and reduction in power consumption benefiting from 1.5V power
supply at 90 nm fabrication technology. With 8 individual banks, DDR3
memory is more flexible to be accessed with fewer bank conflicts.
The proposed Hash-CAM based look up circuit is shown in Figure 1.3.
Fig 1.3: Proposed Hash-CAM based look up circuit

The original data and reference address information are stored in

the DDR3 SDRAM lookup request (data input) for a given content is
pipelined and processed by the Hash circuit to generate an address. This
address value is forwarded to DDR3 SDRAM Interface where it is
translated into instructions and addresses that are recognized by the
DDR3 memory as an access.
The stored data & addresses in the memory are read back to the
Hash-CAM circuit in order to validate the match. In the case of
corresponding reference address is reference address is returned.

1.3 TYPES OF MEMORY CONTROLLERS:
1.3.1 DOUBLE DATA RATE-SYNCHRONOUS DYNAMIC

RANDOM ACCESS MEMORY (DDR SDRAM) CONTROLLER
Double Data Rate-SDRAM, or simply DDR1, was designed to
replace SDRAM. DDR1 was originally referred to as DDR-SDRAM or
simple DDR. When DDR2 was introduced, DDR became referred to as
DDR1. Names of components constantly change as newer technologies
are introduced, especially when the newer technology is based on a
previous e one. The principle applied in DDR is exactly as the name
implies “double data rate”. The DDR actually doubles the rate data is
transferred by using both the rising and falling edges of a typical digital
pulse. Earlier memory technology such as SDRAM transferred data after
one complete digital pulse. DDR transfers data twice as fast by
transferring data on both the rising and falling edges of the digital pulse.
Look at figure below.
Fig 1.4: Data transfer rate in SDRAM Family

DDR DIGITAL PULSE

As shown in the above figure, DDR can transfer twice the amount
of data per single digital pulse by using both the rising edge, and the
falling edge of the digital signal. DDR can transfer twice the data as
SDRAM.
RANDOM ACCESS MEMORY (DDR2 SDRAM) CONTROLLER
DDR2 is the next generation of memory developed after DDR.
DDR2 increased the data transfer rate referred to as bandwidth by
increasing the operational frequency to match the high FSB frequencies
and by doubling the prefetch buffer data rate. There will be more about
the memory prefetch buffer data rate later in this section.
DDR2 is a 240 pin DIMM design that operates at 1.8 volts. The
lower voltage counters the heat effect of the higher frequency data
transfer. DRR operates at 2.5 volts and is a 188 pin DIMM design. DDR2
uses a different motherboard socket than DDR, and is not compatible
with motherboards designed for DDR. The DDR2 DIMM key will not align
with DDR DIMM key. If the DDR2 is forced into the DDR socket, it will
damage the socket and the memory will be exposed to a high voltage
level. Also be aware that DDR is 188 pin DIMM design and DDR2 is a
240 pin DIMM design.
RANDOM ACCESS MEMORY (DDR3 SDRAM) CONTROLLER
DDR3 was the next generation memory introduced in the summer
of 2007 as the natural successor to DDR2. DDR3 increased the pre-fetch
buffer size to 8-bits an increased the operating frequency once again
resulting in high data transfer rates than its predecessor DDR2. In

addition, to the increased data transfer rate memory chip voltage level
was lowered to 1.5 V to counter the heating effects of the high frequency.
By now we can see the trend of memory to increase pre-fetch
buffer size and chip operating frequency, and lowering the operational
voltage level to counter heat. The physical DDR3 is also designed with
240 pins, but the notched key is in a different position to prevent the
insertion into a motherboard RAM socket designed for DDR2.
DDR3 is both electrical and physically incompatible with previous
versions of RAM. In addition to high frequency and lower applied voltage
level, the DDR3 has a memory reset option which DDR2 and DDR1 do
not have. The memory reset allows the memory to be cleared by a
software reset action. Other memory types do not have this feature which
means the memory state is uncertain after a system reboot. The memory
reset feature insures that the memory will be clean or empty after a
system reboot. This feature will result in a more stable memory system.
DDR3 uses the same 240-pin design as DDR2, but the memory module
key notch is at a different location.

COMPARISION OF DDR1, DDR2 AND DDR3

Table 1.1 Comparision of DDR1, DDR2 and DDR3
1.4 MEMORY TYPES
1.4.1 STATIC RANDOM ACCESS MEMORY

Static RAM uses a completely different technology. In static RAM, a form
of flip-flop holds each bit of memory. A flip-flop for a memory cell takes
four or six transistors along with some wiring, but never has to be
refreshed. This makes static RAM significantly faster than dynamic RAM.
However, because it has more parts, a static memory cell takes up a lot
more space on a chip than a dynamic memory cell. Therefore, you get
less memory per chip.

Static random access memory uses multiple transistors, typically
four to six, for each memory cell but doesn't have a capacitor in each
cell. It is used primarily for cache. So static RAM is fast and expensive,
and dynamic RAM is less expensive and slower. So, the static RAM is
used to create the CPU's speed-sensitive cache, while dynamic RAM
forms the larger system RAM space.
1.4.2 DYNAMIC RANDOM ACCESS MEMORY
Dynamic random access memory has memory cells with a paired

transistor and capacitor requiring constant refreshing. DRAM works by
sending a charge through the appropriate column (CAS) to activate the
transistor at each bit in the column. When writing, the row lines contain
the state of charge that the capacitor should take on. When reading, the
sense-amplifier determines the level of charge in the capacitor. If it is
more than 50 percent, it reads it as a ‘1’; otherwise it reads it as a ‘0’.
The counter tracks the refresh sequence based the order in which rows
have been accessed. The length of time necessary to do all this is so
short that it is expressed in nanoseconds.
A memory chip rating of 70ns means that it takes 70 nanoseconds

to completely read and recharge each cell. One of the most common
types of computer memory is DRAM. It can only hold data for a short
period of time and must be refreshed periodically. DRAMs are measured
by storage capability and access time. Storage is rated in megabytes (8
MB, 16 MB, etc). Access time is rated in nanoseconds (60ns, 70ns, 80ns,
etc) and represents the amount of time to save or return information.
With a 60ns DRAM, it would require 60 billionths of a second to save or
return information. The lower the nano speed, the faster the memory
operates. DRAM chips require two CPU wait states for each execution.
Can only execute either a read or write operation at one time. The

capacitor in a dynamic RAM memory cell is like a leaky bucket. It needs

to be refreshed periodically or it will discharge to ‘0’. This refresh
operation is where dynamic RAM gets its name. Dynamic RAM has to be
dynamically refreshed all of the time or it forgets what it is holding. The
downside of all of this refreshing is that it takes time and slows down the
memory.
Memory cells are etched onto a silicon wafer in an array of

columns (bit lines) and rows (word lines). The intersection of a bit line
and word line constitutes the address of the memory cell. Memory cells
alone would be worthless without some way to get information in and out
of them. So the memory cells have a whole support infrastructure of
other specialized circuits.
These circuits perform functions such as:
 Identifying each row and column (row address select and

column address select)
 Keeping track of the refresh sequence (counter)
 Reading and restoring the signal from a cell (sense

amplifier)
 Telling a cell whether it should take a charge or not (write

enable)
Other functions of the memory controller include a series of tasks

that include identifying the type, speed and amount of memory and
checking for errors. The traditional RAM type is DRAM (dynamic RAM).
The other type is SRAM (static RAM). SRAM continues to remember its
content, while DRAM must be refreshed every few milliseconds.

DRAM consists of micro capacitors, while SRAM consists of off/on

switches. Therefore, SRAM can respond much faster than DRAM. SRAM
can be made with a rise time as short as 4 ns. DRAM is by far the
cheapest to build. Newer and faster DRAM types are developed
continuously.
1.4.3 CONTENT-ADDRESSABLE MEMORY (CAM)

Content-addressable memory (CAM) is a special type of computer
memory used in certain very high speed searching applications. It is also
known as associative memory, associative storage, or associative array,
although the last term is more often used for a programming data
structure. Unlike standard computer memory (random access memory or
RAM) in which the user supplies a memory address and the RAM returns
the data word stored at that address, a CAM is designed such that the
user supplies a data word and the CAM searches its entire memory to
see if that data word is stored anywhere in it. If the data word is found,
the CAM returns a list of one or more storage addresses where the word
was found (and in some architecture, it also returns the data word, or
other associated pieces of data).
1.5 ORGANIZATION OF THESIS:

Chapter 1 describes: introduction to DDR3 SDRAM.
Chapter 2 describes: introduction to verilog language and to the Xilinx
synthesis.
Chapter 3 describes: about aim and objective of our project.
Chapter 4 describes: design implementation of our project.
Chapter 5 describes: flowchart, source code and sample outputs of the
project.
Chapter 6 describes: advantages of our project.
Chapter 7 describes: Result, Conclusion and Future Scope of our
project.

CHAPTER 2
LITERATURE SURVEY

2.1 INTRODUCTION TO VERILOG:

In the semiconductor and electronic design industry, Verilog is
a hardware description language (HDL) used to model electronic
systems. Verilog HDL is most commonly used in the design, verification,
and implementation of digital logic chips at the register-transfer
level of abstraction. It is also used in the verification of
analog and mixed-signal circuits. This design process is only possible
because Verilog is a language that can be understood by system
designers, RTL level designers, test engineers, simulators, synthesis
tools, and machines. Because of this important role in design, Verilog
has become an IEEE standard. The standard is used by users as well as
tool developers.
The Verilog HDL satisfies all requirements for design and synthesis
of digital systems. The language supports hierarchical description of
hardware from system to gate or even switch level. Verilog has strong
support at all levels for timing specification and violation detection.
Timing and concurrency required for hardware modeling are specially
emphasized.
In Verilog, a hardware component is described by the module
declaration language construct. Description of a module specifies a
component’s input and output list as well as internal component busses
and registers. Within a module, concurrent assignments, component
instantiations, and procedural blocks can be used to describe a
hardware component. Several modules can hierarchically be instantiated
to form other hardware structures. Leaves of a hierarchical design
specification may be modules, primitives, or user defined primitives.
For simulating a design, it is expected that all leaves of the

hierarchy are individually compiled. Many Verilog tools and

environments exist that provide simulation, fault simulation, formal

verification, and synthesis. Simulation environments provide graphical
front-end programs and waveform editing and display tools. Synthesis
tools are based on a subset of Verilog. For synthesizing a design, target
hardware, e.g., specific FPGA or ASIC, must be known.
OVERVIEW OF VERILOG:
Hardware description languages such as Verilog differ from

software programming languages because they include ways of
describing the propagation of time and signal dependencies (sensitivity).
There are two assignment operators, a blocking assignment (=), and a
non-blocking (<=) assignment. The non-blocking assignment allows
designers to describe a state-machine update without needing to declare
and use temporary storage variables (in any general programming
language we need to define some temporary storage spaces for the
operands to be operated on subsequently; those are temporary storage
variables). Since these concepts are part of Verilog's language semantics,
designers could quickly write descriptions of large circuits in a relatively
compact and concise form. At the time of Verilog introduction (1984),
Verilog represented a tremendous productivity improvement for circuit
designers who were already using graphical capture software and
specially-written software programs to document and simulate electronic
circuits.
The designers of Verilog wanted a language with syntax similar to

the C programming language, which was already widely used in
engineering software development. Verilog is case-sensitive, has a
basic preprocessor (though less sophisticated than that of ANSI C/C++),
and equivalent control flow keywords (if/else, for, while, case, etc.), and

compatible operator precedence. Syntactic differences include variable

declaration (Verilog requires bit-widths on net/reg types, demarcation of
procedural blocks (begin/end instead of curly braces {}), and many other
minor differences.
A Verilog design consists of a hierarchy of modules. Modules

encapsulate design hierarchy, and communicate with other modules
through a set of declared input, output, and bidirectional ports.
Internally, a module can contain any combination of the following:
net/variable declarations (wire, reg, integer, etc.), concurrent and
sequential statement blocks, and instances of other modules (sub-
hierarchies). Sequential statements are placed inside a begin/end block
and executed in sequential order within the block. But the blocks
themselves are executed concurrently, qualifying Verilog as a dataflow
language.
Verilog concept of 'wire' consists of both signal values (4-state: "1,

0, floating, undefined") and strengths (strong, weak, etc.). This system
allows abstract modeling of shared signal lines, where multiple sources
drive a common net. When a wire has multiple drivers, the wire's
(readable) value is resolved by a function of the source drivers and their
strengths.
A subset of statements in the Verilog language is synthesizable.

Verilog modules that conform to a synthesizable coding style, known as
RTL (register-transfer level), can be physically realized by synthesis
software. Synthesis software algorithmically transforms the (abstract)
Verilog source into a net list, a logically equivalent description consisting
only of elementary logic primitives (AND, OR, NOT, flip-flops, etc.) that
are available in a specific FPGA or VLSI technology. Further
manipulations to the net list ultimately lead to a circuit fabrication

blueprint (such as a photo mask set for an ASIC or a bit stream file for

an FPGA.
VERILOG EVOLUTION:
In 1987 VHDL became an IEEE standard hardware description

language. Because of its Department of Defence (DOD) support, VHDL
was adapted by the U.S. government for related projects and contracts.
In an effort for popularizing Verilog, in 1990, OVI (Open Verilog
International) was formed and Verilog was placed in public domain. This
created a new line of interest in Verilog for the users and EDA vendors.
In 1993, efforts for standardization of this language started.
Already having simulation tools, synthesizers, fault simulation
programs, timing analyzers, and many of their design tools developed for
Verilog, this standardization helped further acceptance of Verilog in
electronic design communities.
The wording for this process was "Automated Integrated Design

Systems" (later renamed to Gateway Design Automation in 1985) as a
hardware modeling language. Gateway Design Automation was
purchased by Cadence Design Systems in 1990. Cadence now has full
proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-
simulator that would become the de-facto standard (of Verilog logic
simulators) for the next decade. Originally, Verilog was intended to
describe and allow simulation; only afterwards was support for synthesis
added.
VERILOG ATTRIBUTES:
Verilog is a hardware description language for describing hardware
from transistor level to behavioral. The language supports timing
constructs for switch level timing simulation and at the same time, it has

features for describing hardware at the abstract algorithmic level. A

Verilog description may consist of a mix of modules at various
abstraction levels with different degrees of detail.
SWITCH LEVEL:
Features of the language that make it ideal for switch level
modelling and simulation includes primitive unidirectional and
bidirectional switches with parameters for delay and charge storage.
GATE LEVEL:
Gate level primitives with predefined parameters provide a
convenient platform for net list representation and gate level simulation.
For more detailed and special purpose gate simulations, gate
components may be defined at the behavioral level. Verilog also provides
utilities for defining primitives with special functionalities. A simple 4-
value logic system is used in Verilog for signal values. However, for more
accurate logic modelling, Verilog signals also include 16 levels of strength
in addition to the four values.
BEHAVIORAL LEVEL:
Procedural blocks of Verilog enable algorithmic representations of
hardware structures. Constructs similar to those in software
programming languages are provided for describing hardware at this
level.
2.2 INTRODUCTION TO MODELSIM:
Modelsim is a useful tool that allows you to stimulate the inputs of
our modules and view both outputs and internal signals. It allows us to
do both behavioural and timing simulation; however, this document will
focus on behavioural simulation. Keep in mind that these simulations
are based on models and thus the results are only as accurate as the
constituent models. Modelsim /VHDL, Modelsim /VLOG, Modelsim

/LNL, and Modelsim /PLUS are produced by Model Technology™

Incorporated.
Modelsim is a registered trademark of Model Technology
Incorporated. Model Technology is a trademark of Mentor Graphics
Corporation. PostScript is a registered trademark of Adobe Systems
Incorporated.
STANDARDS SUPPORTED BY MODELSIM:
Modelsim VHDL supports the IEEE 1076-1987 and 1076-1993
VHDL, the 1164-1993 Standard Multi value Logic System for VHDL
Interoperability, and the 1076.2-1996 Standard VHDL Mathematical
Packages standards. Any design developed with Modelsim will be
compatible with any other VHDL system that is compliant with either
IEEE Standard 1076-1987 or 1076-1993. Modelsim Verilog is based on
IEEE STD 1364-1995 and a partial implementation of 1364-2001,
Standard Hardware Description Language Based on the Verilog
Hardware Description Language. The Open Verilog International Verilog
LRM version 2.0 is also applicable to a large extent. Both PLI
(Programming Language Interface) and VCD (Value Change Dump) are
supported for Modelsim PE and SE users.
MODELSIM - ADVANCED SIMULATION AND DEBUG:
Mentor Graphics was the first to combine single kernel simulator

(SKS) technology with a unified debug environment for Verilog, VHDL,
and System C. The combination of industry-leading, native SKS
performance with the best integrated debug and analysis environment
make Modelsim the simulator of choice for both ASIC and FPGA designs.
The best standards and platform support in the industry make it easy to
adopt in the majority of process and tool flows.

2.3 INTRODUCTION TO XILINX:
Xilinx is a supplier of programmable logic devices. It is known for

inventing the field programmable gate array (FPGA) and as the first
semiconductor company with a fables manufacturing model. Founded in
Silicon Valley in 1984, the company is headquartered in San Jose,
California, U.S.A.; Dublin, Ireland; Singapore; and Tokyo, Japan. The
company has corporate offices throughout North America, Asia and
Europe.
FOUNDATION OF XILINX:
Xilinx was founded in 1984 by two semiconductor engineers, Ross

Freeman and Bernard Vonderschmitt, who were both working for
integrated circuit and solid-state device manufacturer Zilog Corp. While
working for Zilog, Freeman wanted to create chips that acted like a blank
tape, allowing users to program the technology themselves. At the time,
the concept was paradigm-changing.
"The concept required lots of transistors and, at that time,

transistors were considered extremely precious – people thought that
Ross's idea was pretty far out", said Xilinx Fellow Bill Carter, who when
hired in 1984 as the first IC designer was the company's eighth
employee. Big semiconductor manufacturers were enjoying strong profits
by producing massive volumes of generic circuits. Designing and
manufacturing dozens of different circuits for specific markets offered
lower profit margins and required greater manufacturing complexity. [4]
What became known as the FPGA would allow circuits produced in
quantity to be tailored by individual market segments.

Xilinx competitors emerged in the FPGA market in the mid-1990s.

Despite the competition, Xilinx’s sales grew to $135 million in 1991,
$178 million in 1992 and $250 million in 1993. The Company reached
$550 million in revenue in 1995, one decade after having sold its first
product. According to market research firm iSuppli, Xilinx has led the
programmable logic device market share since the late 1990s. Over the
years, Xilinx expanded operations to India, Asia and Europe. Xilinx’s
sales rose from $560 million in 1996 to nearly $2 billion by the end of its
fiscal year 2010.[11] Moshe Gavrielov – an EDA and ASIC industry veteran
who was appointed as president and CEO in early 2008 – introduced
targeted design platforms to provide solutions that combine FPGAs with
software, IP cores, boards and kits to address focused target
applications.[12] These targeted design platforms are an alternative to
costly application-specific integrated circuits (ASICs) and application-
specific standard products (ASSPs).

CHAPTER 3
PROBLEM DEFINITION OF
DDR3 SDRAM CONTROLLER

3.1 AIM OF THE DDR3 SDRAM CONTROLLER:

The DDR3SDRAM controller is designed to achieve the
decreased memory access time by best write /read efficiency
and highest memory bandwidth and it can also interface with Look
up table based Hash CAM circuit.
DDR3 SDRAM is a random access memory interface technology
used for high bandwidth storage of the working data of a computer or
other digital electronic devices. DDR3 is part of the SDRAM family of
technologies and is one of the many DRAM (dynamic random access
memory) implementations. DDR3 SDRAM is the 3rd generation of
DDR memories, featuring higher performance and lower power
consumption.
3.2 OBJECTIVE OF THE DDR3 SDRAM CONTROLLER:

The Objective of the Double Data Rate 3(DDR) Synchronous
Dynamic Random Access Memory (SDRAM) is quickly becoming the
memory of choice mainly because of its ability to double the throughput
when compared to conventional Single Data Rate (SDR) SDRAM. As
processors gain speed, memory modules also need to support them so
that the overall system performance is maintained. It is used to establish
Synchronization between high speed processors and high capacity
memory modules.

CHAPTER 4
DEISGN IMPLEMENTATION OF
DDR3 SDRAM CONTROLLER

4.1 INTRODUCTION OF DDR3SDRAM CONTROLLER

The DDR3 SDRAM uses double data rate architecture to achieve
high-speed operation. The double data rate architecture is 8n-prefetch
architecture with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for the DDR3
SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at
the internal DRAM core and eight corresponding n-bit-wide, one-half-
clock cycle data transfers at the I/O pins. The differential data strobe
(DQS, DQS#) is transmitted externally, along with data, for use in data
capture at the DDR3 SDRAM input receiver. DQS is center-aligned with
data for WRITEs. The read data is transmitted by the DDR3 SDRAM and
edge-aligned to the data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#).
The crossing of CK going HIGH and CK# going LOW is referred to as the
positive edge of CK. Control, command, and address signals are
registered at every positive edge of CK. Input data is registered on the
first rising edge of DQS after the WRITE preamble, and output data is
referenced on the first rising edge of DQS after the READ preamble. Read
and write accesses to the DDR3 SDRAM are burst-oriented. Accesses
start at a selected location and continue for a programmed number of
locations in a programmed sequence. Accesses begin with the
registration of an ACTIVATE command, which is then followed by a
READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be
accessed. The address bits registered coincident with the READ or
WRITE commands are used to select the bank and the starting column
location for the burst access. DDR3 SDRAM use READ and WRITE

operations. An auto pre-charge function may be enabled to provide a

self-timed row pre-charge that is initiated at the end of the burst access.
As with standard DDR SDRAM, the pipelined, multibank
architecture of DDR3 SDRAM allows for concurrent operation, thereby
providing high bandwidth by hiding row pre-charge and activation time.
A self refresh mode is provided, along with a power-saving, power-down
mode.
4.2 FUNCTIONAL BLOCK DIAGRAM OF DDR3SDRAM
CONTROLLER
Fig. 4.1: Functional Block Diagram of DDR3 SDRAM Controller

The functional block diagram of the DDR3 controller is shown in

Figure 4.1. The architecture of DDR3SDRAM controller consists of
Initialization FSM, Command FSM, data path, bank control, clock
counter, refresh counter, Address FIFO, command FIFO, Wdata FIFO
and R_data register.
Initialization FSM generates proper i-State to initialize the

modules in the design. Command FSM generates c-State to perform the
normal write, read and fast write, read operations. The data path module
performs the data latching and dispatching of the data between Hash
CAM unit and DDR3SDRAM banks. The Address FIFO gives the address
to the Command FSM so the bank control unit can open particular bank
and address location in that bank. The Wdata FIFO provides the data to
the data path module in normal and fast write operation. The R_data reg
gets the data from the data path module normal and fast read operation.
In this project the designed DDR3 controller provides interface to

the HASH CAM circuit and the DDR Memory Banks. If the data word is
found, the CAM returns a list of one or more storage addresses where the
word was found (and in some architecture, it also returns the data word,
or other associated pieces of data). Because a CAM is designed to search
its entire memory in a single operation, it is much faster than RAM in
virtually all search applications.
The DDR3 controller gets the address, data and control from the
HASH CAM circuit in to the Address FIFO. Write data FIFO and control
FIFO respectively.

4.2.1 ADDRESS FIFO

DDR3 SDRAM controller gets the address from the Address FIFO
so that controller can perform the read from the memory or write in to
the memory address location specified by the Address FIFO. Here the
Address FIFO width is 13 bit and stack depth is 8.
4.2.2 WRITE DATA FIFO

DDR3 SDRAM controller gets the data from the Write data FIFO in
write operation in to the memory address location specified by the
Address FIFO. Here the Address FIFO width is 64 bit and stack depth is
8.
4.2.3 CONTROL FIFO

DDR3 SDRAM controller gets the command from the Control FIFO
controller can perform the read from the memory or write in to the
memory address location specified by the Address FIFO. Here the Control
FIFO width is 2 bit and stack depth is 8. If the control FIFO gives the
“00” DDR3 controller performs the No operation. If the control FIFO gives
the “01” DDR3 controller performs the Normal read operation. If the
control is “10” DDR3 controller performs the Normal write operation and
if control is “11” DDR3 controller performs the Fast read operation.
4.2.4 READ DATA REGISTER

When DDR3 controller performs Normal read or Fast read
operation Read data register gets the data send to the Hash Cam circuit.

4.2.5 INITIALIZATION FINITE STATE MACHINE:
Fig 4.2: Initial FSM State Diagram

Before normal memory accesses can be performed, DDR3 needs to

be initialized by a sequence of commands. The INIT_FSM state machine
handles this initialization. Figure 4.2 shows the state diagram of the
INIT_FSM state machine. During reset, the INIT_FSM is forced to the
i_IDLE state. After reset, the sys_dly_200US signal will be sampled to
determine if the 200μs power/clock stabilization delay is completed.
After the power/clock stabilization is complete, the DDR initialization
sequence will begin and the INIT_FSM will switch from i_IDLE to i_NOP
state and in the next clock to I_PRE.
The initialization starts with the PRECHARGE ALL command. Next

a LOAD MODE REGISTER command will be applied for the extended
mode register to enable the DLL inside DDR, followed by another LOAD
MODE REGISTER command to the mode register to reset the DLL. Then
a PRECHAGE command will be applied to make all banks in the device to
idle state. Then two, AUTO REFRESH commands, and then the LOAD
MODE REGISTER command to configure DDR to a specific mode of
operation. After issuing the LOAD MODE REGISTER command and the
tMRD timing delay is satisfied, INIT_FSM goes to i_ready state and
remains there for the normal memory access cycles unless reset is
asserted. Also, signal sys_init_done is set to high to indicate the DDR
initialization is completed. The i_PRE, i_AR1, i_AR2, i_EMRS and i_MRS
states are used for issuing DDR commands. The LOAD MODE
REGISTER command configures the DDR by loading data into the mode
register through the address bus. The data present on the address bus
(ddr_add) during the LOAD MODE REGISTER command is loaded to the
mode register. The mode register contents specify the burst length, burst
type, CAS latency, etc. A PRECHARGE/AUTO PRECHARGE command
moves all banks to idle state. As long as all banks of the DDR are in idle
state, mode register can be reloaded with different value thereby
changing the mode of operation. However, in most applications the mode

register value will not be changed after initialization. This design
assumes the mode register stays the same after initialization.As
mentioned above, certain timing delays (tRP, tRFC, tMRD) need to be
satisfied before another non-NOP command can be issued. These SDRAM
delays vary from speed grade to speed grade and sometimes from vendor
to vendor. To accommodate this without sacrificing performance, the
designer needs to modify the HDL code for the specific delays and clock
period (tCK). According to these timing values, the number of clocks the
state machine will stay at i_tRP, i_tRFC1, i_tRFC2, i_tMRD states will be
determined after the code is synthesized. In cases where tCK is larger
than the timing delay, the state machine doesn’t need to switch to the
timing delay states and can go directly to the command states. The
dashed lines in Figure 3.3 show the possible state switching paths.
DIFFERENT STATES OF INITIAL FSM:
1. IDLE:
When reset is applied the initial FSM is forced to IDLE state
irrespective of which state it is actually in when system is in idle it
remains idle without performing any operations.
2. NO OPERATION (NOP):
The NO OPERATION (NOP) command is used to instruct the
selected DDR SDRAM to perform a NOP. This prevents unwanted
commands from being registered during idle or wait states. Operations
already in progress are not affected.

3. PRECHARGE (PRE):
The PRECHARGE command is used to deactivate the open row in a
particular bank or the open row in all banks as shown in Figure 4.2. The
value on the BA0, BA1 inputs selects the bank, and the A10 input
selects whether a single bank is precharged or whether all banks are
precharged.
4. AUTO REFRESH (AR):

AUTO REFRESH is used during normal operation of the DDR
SDRAM and is analogous to CAS#-before-RAS# (CBR) refresh in DRAMs.
This command is non persistent, so it must be issued each time a refresh
is required. All banks must be idle before an AUTO REFRESH command
is issued.
5. LOAD MODE REGISTER (LMR):

The mode registers are loaded via inputs A0–An. The LOAD MODE
REGISTER command can only be issued when all banks are idle, and a
subsequent executable command cannot be issued until tMRD is met.

4.2.6 COMMAND FSM STATE DIAGRAM:
Fig 4.3: Command FSM State Diagram for Normal write/read


The figure 4.3 shows the state diagram of CMD_FSM, which

handles read, write and refresh of the DDR. The CMD_FSM state
machine is initialized to c_idle during reset. After reset, CMD_FSM stays
in c_idle as long as sys_init_done is low which indicates the DDR
initialization sequence is not yet completed. From this state, a
READA/WRITEA/REFRESH cycle starts depending upon
sys_adsn/rd_wr_req_during_ref_req signals as shown in the state
diagram.
All rows are in the “closed” status after the DDR initialization. The
rows need to be “opened” before they can be accessed. However, only one
row in the same bank can be opened at a time. Since there are four
banks, there can be at most four rows opened at the same time. If a row
in one bank is currently opened, it needs to be closed before another row
in the same bank can be opened. ACTIVE command is used to open the
rows and PRECHARGE (or the AUTO PRECHARGE hidden in the WRITE
and READ commands as used in this design) is used to close the rows.
When issuing the commands for opening or closing the rows, both row
address and bank address need to be provided.
In this design, the ACTIVE command will be issued for each read
or write access to open the row. After a tRCD delay is satisfied, READA or
WRITEA commands will be issued with a high ddr_add[10] to enable the
AUTO REFRESH for closing the row after access. Therefore, the clocks
required for read/write cycle are fixed and the access can be random
over the full address range. Read or write is determined by the sys_r_wn
status sampled at the rising edge of the clock before the tRCD delay is
satisfied. If logic high is sampled, the state machine switches to
c_READA. If a logic low is sampled, the state machine switches to
c_WRITEA.
For read cycles, the state machine switches from, c_READA to c_cl
for CAS latency, then switches to crate for transferring data from DDR to
processor. The burst length determines the number of clocks the state
machine stays in c_rdata state. After the data is transferred, it switches
back to c_idle.
For write cycles, the state machine switches from c_WRITEA to

c_wdata for transferring data from bus master to DDR, then switches to
c_tDAL. Similar to read, the number of clocks the state machine stays in
c_wdata state is determined by the burst length. The time delay tDAL is
the sum of WRITE recovery time tWR and the AUTO PRECHARGE timing
delay tRP. After the clock rising edge of the last data in the burst
sequence, no commands other than NOP can be issued to DDR before
tDAL is satisfied.
The dashed lines indicate possible state switching paths when the
tCK period is larger than the timing delay specification.
COMMAND FSM WITH FAST READ OPERATION
Fast read can be achieved by switching banks. Bank control logic is used
to issue desired bank addresses at each cycle when a bank active
command or read command is issued. The state machine for this method
is given in Figure 4.4. The proposed controller provides the control
interface for switching between normal write/read mode and fast read
mode. Unlike other data processing techniques, the distinct
characteristic of the random data lookup is the uncertainty of the
incoming data. In this work, address FIFOs are applied to buffer the
row/column addresses separately for each read request. The “empty” flag
of the row address FIFO (addr_fifo_empty) is checked in order to evaluate
whether the next command is active (ACT) or read (RDA).
Fig 4.4: Command FSM Fast read with auto precharge


DIFFERENT STATES OF COMMAND FSM:

1. IDLE:
When reset is applied the command FSM is forced to IDLE state
irrespective of which state it is actually in when system is in idle it
remains idle without performing any operations.
2. ACTIVE (ACT):
The ACTIVE command is used to open (or activate) a row in a

particular bank for a subsequent access, like a read or a write, as shown
in Figure 4.4. The value on the BA0, BA1 inputs selects the bank, and
the address provided on inputs A0–An selects the row.
3. READ:
The READ command is used to initiate a burst read access to an

active row, as shown in Figure 4.3. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0–Ai (where Ai is
the most significant column address bit for a given density and
configuration) selects the starting column location .
4. WRITE:
The WRITE command is used to initiate a burst write access to an
active row as shown in Figure 4.4. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0–Ai (where Ai is
the most significant column address bit for a given density and
configuration) selects the starting column location.

Similar to the FP and EDO DRAM, row address and column

address are required to pinpoint the memory cell location of the SDRAM
access. Since SDRAM is composed of four banks, bank address needs to
be provided as well.
The SDRAM can be considered as a four by N array of rows. All

rows are in the “closed” status after the SDRAM initialization. The rows
need to be “opened” before they can be accessed. However, only one row
in the same bank can be opened at a time. Since there are four banks,
there can be at most four rows opened at the same time. If a row in one
bank is currently opened, it must be closed before another row in the
same bank can be opened. ACTIVE command is used to open the rows
and PRECHARGE (or the AUTO PRECHARGE hidden in the WRITE and
READ commands, as used in this design) is used to close the rows. When
issuing the commands for opening or closing the rows, both row address
and bank address need to be provided.
For sequential access applications and those with page memory

management, the proper address assignments and the use of the SDRAM
pipeline feature deliver the highest performance SDRAM controller.
However, this type of controller design is highly associated with the bus
master cycle specification and will not fit the general applications.
Therefore, this SDRAM controller design does not implement these
custom features to achieve the highest performance through these
techniques.
In this design, the ACTIVE command will be issued for each read
or write access to open the row. After a tRCD delay is satisfied, READ or
WRITE commands will be issued with a high sdr_A[10] to enable the
AUTO REFRESH for closing the row after access. So, the clocks required

for read/write cycle are fixed and the access can be random over the full
address range.
Read or write is determined by the sys_R_Wn status sampled at

the rising edge of the clock before tRCD delay is satisfied. If a logic high
is sampled, the state machine switches to c_READA. If a logic low is
sampled, the state machine switches to c_WRITEA.
For read cycles, the state machine switches from c_READA to c_cl
for CAS latency, then switches to c_rdata for transferring data from
SDRAM to bus master. The number of clocks the state machine stays in
c_rdata state is determined by the burst length. After the data is
transferred, it switches back to c_idle.
For write cycles, the state machine switches from c_WRITEA to

c_wdata for transferring data from bus master to SDRAM, then switches
to c_tDAL. Similar to read, the number of clocks the state machine stays
in c_wdata state is determined by the burst length. The time delay tDAL
is the sum of WRITE recovery time tWR and the AUTO PRECHARGE
timing delay tRP. After the clock rising edge of the last data in the burst
sequence, no commands other than NOP can be issued to SDRAM before
tDAL is satisfied.
As mentioned in the INIT_FSM section above, the dash lines

indicate possible state switching paths when tCK period is larger than
timing delay spec.

4.2.7 REFRESH CYCLE:
Similar to the other DRAMs, memory refresh is required. A SDRAM

refresh request is generated by activating sdr_REF_REQ signal of the
controller. The sdr_REF_ACK signal will acknowledge the recognition of
sdr_REF_REQ and will be active throughout the whole refresh cycle. The
sdr_REF_REQ signal must be maintained until the sdr_REF_ACK goes
active in order to be recognized as a refresh cycle. Note that no system
read/write access cycles are allowed when sdr_REF_ACK is active. All
system interface cycles will be ignored during this period. The
sdr_REF_REQ signal assertion needs to be removed upon receipt of
sdr_REF_ACK acknowledge,otherwise another refresh cycle will again be
performed.
Upon receipt of sdr_REF_REQ assertion, the state machine CMD_FSM

enters the c_AR state to issue an AUTO REFRESH command to the
SDRAM. After tRFC time delay is satisfied, CMD_FSM returns to c_idle.
4.2.8 DATA PATH CONTROL

Data path module performs the data latching and dispatching
based on the command fsm states. It provides interface between the
Read data register and the memory banks.
4.2.9 BANK CONTROL

The bank control controls the all the eight banks effectively
depending upon the istate and cstate by sending the required
control signals.

CHAPTER 5
FLOW CHART, SOURCE CODE
AND SAMPLE OUTPUTS OF DDR3
SDRAM CONTROLLER

5.1 FLOW CHART OF DDR3 SDRAM CONTROLLER:
Fig 5.1: Flow Chart of DDR3 SDRAM Controller

5.2 SOURCE CODE:

//TB DDR3
module TOP_tb();
reg sys_CLKX;
reg sys_CLK3X;
reg sys_RESET;
reg write_to_Add_fifo;
reg write_to_WD_fifo;
reg write_to_cntrl_fifo;
reg sys_DLY_200US;
reg [12:0] Address;
reg [1: 0] Control;
reg [63:0] Data_in;
reg [63:0] sdr_DQ_IN;
//--------------------------------------------------------------------//
// outputs //
//--------------------------------------------------------------------//
wire [63:0]final_out;
wire sys_CYC_END;
wire [1:0]ddr_R_Wn;
wire sys_REF_REQ;
wire sdr_CKE; //sdr clock enable
wire [3:0]sdr_CSn; // sdr chip select
wire [3:0]sdr_RASn; // sdr row address
wire [3:0]sdr_CASn; // sdr column select
wire [3:0]sdr_WEn; // sdr write enable
wire [2:0]ddr_BA;
wire [12:0]ddr_A;
wire [2:0] Bank;
wire Bank_sel_0;
wire Bank_sel_1;
wire Bank_sel_2;
wire Bank_sel_3;
wire Bank_sel_4;
wire Bank_sel_5;
wire Bank_sel_6;
wire Bank_sel_7;
DDR3_top DDR3_CONTROLLER ( .sys_CLKX(sys_CLKX),

.sys_CLK3X(sys_CLK3X),
.sys_RESET(sys_RESET),
.write_to_Add_fifo(write_to_Add_fifo),
.write_to_WD_fifo(write_to_WD_fifo),
.write_to_cntrl_fifo(write_to_cntrl_fifo),
.sys_DLY_200US(sys_DLY_200US),
.Address(Address),
.Control(Control),
.Data_in(Data_in),
.sdr_DQ_IN(sdr_DQ_IN),
.final_out(final_out),
.sys_CYC_END(sys_CYC_END),
.ddr_R_Wn(ddr_R_Wn),

.sys_REF_REQ(sys_REF_REQ),
.sdr_CKE(sdr_CKE), //sdr clock enable
.sdr_CSn(sdr_CSn), // sdr chip select
.sdr_RASn(sdr_RASn), // sdr row address
.sdr_CASn(sdr_CASn), // sdr column select
.sdr_WEn(sdr_WEn), // sdr write enable
.ddr_BA(ddr_BA),
.ddr_A(ddr_A),
.Bank(Bank),
.Bank_sel_0(Bank_sel_0),
.Bank_sel_7(Bank_sel_7));
initial
begin
sys_CLKX=1'b1;
sys_CLK3X=1'b1;
end
always
begin
#50 sys_CLKX <= ~ sys_CLKX;
#25 sys_CLK3X <= ~ sys_CLK3X;
end
initial
begin
sys_RESET = 1'b1;
write_to_Add_fifo = 1'b1;
write_to_WD_fifo = 1'b1;
write_to_cntrl_fifo = 1'b1;
sys_DLY_200US = 1'b1;
Address = 13'b0001001010101;
Control = 2'b10;
Data_in = 64'b
00000111110000000011000101010101010000000000000000111100010100010;
sdr_DQ_IN = 64'b
1010000000100010000100001010001001000000101010101010100000011110;
#100 sys_RESET = 1'b0;
#100 Control = 2'b01;
#300 Address = 13'b 0001001010101;
Data_in = 64'b
10000101010001010000010100010110101001001000000100010101010100011;
#4600 sdr_DQ_IN = 64'b
1010000011110000000001010100000000001010000000000000100000011110;
Control = 2'b11;
#1000 sdr_DQ_IN =64'b
0000000010101001000000000000000101010100010100101010100000011110 ;
#700 Control = 2'b10;
end
endmodule

//DDR3 TOP MODULE

`define i_IDLE (5'b00000)
`define i_NOP (5'b00001)
`define i_PRE (5'b00010)
`define i_tRP (5'b00011)
`define i_EMRS (5'b00100)
`define i_AR1 (5'b00101)
`define i_tRFC1 (5'b00110)
`define i_MRS (5'b01001)
`define i_tMRD (5'b01010)
`define i_ready (5'b01011)
`define c_idle (5'b00000)

`define c_ACTIVE (5'b01100)
`define c_tRCD (5'b01101)
`define c_READA (5'b01110)
`define c_tRC (5'b01111)
`define c_rdata (5'b10000)
`define c_WRITEA (5'b10001)
`define c_wdata (5'b10010)
`define c_tDAL (5'b10011)
`define c_tWL (5'b10100)
module DDR3_top ( sys_CLKX,

sys_CLK3X,
sys_RESET,
sys_DLY_200US,
Address,
add_fifo_empty,
write_to_Add_fifo,
Control,
write_to_cntrl_fifo,
Data_in,
sdr_DQ_IN,
write_to_WD_fifo,
sys_CYC_END,
final_out,
ddr_R_Wn,
sys_REF_REQ,
sdr_CKE, //sdr clock enable
sdr_CSn, // sdr chip select
sdr_RASn, // sdr row address
sdr_CASn, // sdr column select
sdr_WEn, // sdr write enable
ddr_BA,
ddr_A,
Bank,
Bank_sel_0,
Bank_sel_1,
Bank_sel_2,
Bank_sel_3,
Bank_sel_4,
Bank_sel_5,

Bank_sel_6,
Bank_sel_7
);
//---------------------------------------------------------------//
// CAS Latency
parameter Latency_2 = 3'b010;
// Burst Length
parameter Length_1 = 3'b000;
//-----------------------------------------------------Control---------//
// User modifiable parameters //
//--------------------------------------------------------------//
/****************************
* Mode register setting
****************************/
parameter MR_CAS_Latency = Latency_3;
parameter MR_Burst_Length = Length_4;
//----------------------------------------------------------------//
// SDRAM AC timing spec (User Specifications) //
//-----------------------------------------------------------------//
parameter tCK = 100; // clock peroid
parameter tMRD = 2*tCK; // load mode register peroid
parameter tRP = 210; // precharge peroid
parameter tRFC = 180; // auto refresh period
parameter tRCD = 190; // delay before read/write is sampled
parameter tWR = tCK + 7; // write recovery time
parameter tDAL = tWR + tRP; // sum of write recovery, precharge
//-----------------------------------------------------Control-----------//
// Clock count definition for meeting SDRAM AC timing spec //
//----------------------------------------------------------------//
reg [2:0] NUM1_CLK_tMRD = tMRD/tCK;
reg [2:0] NUM1_CLK_tRP = tRP/tCK;
reg [2:0] NUM1_CLK_tRFC1 = tRFC/tCK;
reg [7:0] NUM2_CLK_tMRD = tMRD%tCK;

reg [7:0] NUM2_CLK_tRP = tRP%tCK;
reg [7:0] NUM2_CLK_tRFC1 = tRFC%tCK;
reg [2:0] NUM1_CLK_tRCD = tRCD/tCK;

reg [2:0] NUM1_CLK_tDAL = tDAL/tCK;
reg [2:0] NUM1_CLK_tRFC = tRFC/tCK;
reg [7:0] NUM2_CLK_tRCD = tRCD%tCK;

reg [7:0] NUM2_CLK_tDAL = tDAL%tCK;
reg [7:0] NUM2_CLK_tRFC = tRFC%tCK;

reg [2:0] NUM_CLK_tRC = (MR_CAS_Latency == Latency_2) ? 2 :

(MR_CAS_Latency == Latency_3) ? 3 : 2; // default
reg [2:0] NUM_CLK_tWL = (MR_CAS_Latency == Latency_2) ? 2 :
reg [3:0] NUM_CLK_READ = (MR_Burst_Length == Length_1) ? 1 :

(MR_Burst_Length == Length_2) ? 2 :
(MR_Burst_Length == Length_4) ? 4 : 4; // default
reg [3:0] NUM_CLK_WRITE = (MR_Burst_Length == Length_1) ? 1 :

//-----------------------------------------------------------------//
// inputs //
//-----------------------------------------------------------------//
input sys_CLKX,sys_CLK3X;
input sys_RESET,add_fifo_empty;
input write_to_Add_fifo,write_to_WD_fifo,write_to_cntrl_fifo;
input sys_DLY_200US;
input [12:0] Address;
input [1: 0] Control;
input [63:0] Data_in;
input [63:0] sdr_DQ_IN;
//--------------------------------------------------------------------//
// outputs //
//--------------------------------------------------------------------//
output [63:0]final_out;
output sys_CYC_END;
output [1:0]ddr_R_Wn;
output sys_REF_REQ;
output sdr_CKE; //sdr clock enable
output [3:0]sdr_CSn; // sdr chip select
output [3:0]sdr_RASn; // sdr row address
output [3:0]sdr_CASn; // sdr column select
output [3:0]sdr_WEn; // sdr write enable
output [2:0]ddr_BA;
output [12:0]ddr_A;
output [2:0] Bank;
output Bank_sel_0;
output Bank_sel_1;
output Bank_sel_2;
output Bank_sel_3;
output Bank_sel_4;
output Bank_sel_5;
output Bank_sel_6;
output Bank_sel_7;
//-------------------------------------------------------------------//
// Wires //
//-------------------------------------------------------------------//
wire [1:0]command;
wire [1: 0]Control;

wire [12:0]sys_A;
wire [63:0]Data_in,sys_D_IN,sys_D_OUT;
wire [12:0]sdr_A;
wire [2 :0]sdr_BA;
wire [63:0]sdr_DQ_IN,sdr_DQ_OUT;
wire sys_D_VALID,sdrclk_DQS,sys_INIT_DONE;
wire Add_Rd_En,Data_Rd_En,Cnt_Rd_En;
wire [1:0]sdr_R_Wn;
wire sys_REF_ACK;
wire write_to_Add_fifo,write_to_WD_fifo,write_to_cntrl_fifo;
wire Add_stack_full,Add_stack_almost_full,Add_stack_half_full,Add_
stack_almost_empty,Add_stack_empty;
wire Data_stack_full,Data_stack_almost_full,Data_stack_half_full,Data_
stack_almost_empty,Data_stack_empty;
wire cntrl_stack_full,cntrl_stack_almost_full,cntrl_stack_half_full,cntrl_
stack_almost_empty,cntrl_stack_empty;
wire [4:0] istate;
wire [4:0] cstate;
wire [4:0] clkCNT;
//wire Add_stack_empty;
//-------------------------------------------------------------------//
// Instantiation of Components //
//-------------------------------------------------------------------//
Add_FIFO Address_FIFO (.clk(sys_CLKX), //i
.rst(sys_RESET), //i
.Address_in(Address),//i
.write_to_Add_fifo(write_to_Add_fifo),//i
.read_from_Add_fifo(Add_Rd_En),
.Address_out(sys_A), //i
.Add_stack_full(Add_stack_full),
.Add_stack_almost_full(Add_stack_almost_full),
.Add_stack_half_full(Add_stack_half_full),
.Add_stack_almost_empty(Add_stack_almost_empty),
.Add_stack_empty(Add_stack_empty));
WR_Data_FIFO Write_Data_FIFO (.clk(sys_CLKX),
.rst(sys_RESET),
.Data_in(Data_in),
.write_to_WD_fifo(write_to_WD_fifo),
.read_from_WD_fifo(Data_Rd_En),
.Data_out(sys_D_IN),
.Data_stack_full(Data_stack_full),
.Data_stack_almost_full(Data_stack_almost_full),
.Data_stack_half_full(Data_stack_half_full),
.Data_stack_almost_empty(Data_stack_almost_empty),
.Data_stack_empty(Data_stack_empty));
Cntrl_FIFO Control_FIFO (.clk(sys_CLKX),
.rst(sys_RESET),
.control_in(Control),
.write_to_cntrl_fifo(write_to_cntrl_fifo),
.read_from_cntrl_fifo(Cnt_Rd_En),
.control_out(command),
.cntrl_stack_full(cntrl_stack_full),
.cntrl_stack_almost_full(cntrl_stack_almost_full),

.cntrl_stack_half_full(cntrl_stack_half_full),
.cntrl_stack_almost_empty(cntrl_stack_almost_empty),
.cntrl_stack_empty(cntrl_stack_empty));
RD_D_reg Read_Data_Register (.clock(sys_CLKX),
.RD_REG_data_in(sys_D_OUT),
.enable(sys_D_VALID),
.RD_REG_data_out(final_out));
Inti_fsm Initialization_FSM (.sys_CLKX(sys_CLKX),
.sys_DLY_200US(sys_DLY_200US),//i
.sys_ADSn(sys_ADSn), //i
.sys_INIT_DONE(sys_INIT_DONE), //i
.istate(istate));
clk_counter Clock_counter ( .sys_CLKX(sys_CLKX),
.clkCNT(clkCNT),
.iState(istate),
.cState(cstate));
ref_counter Refresh_counter (.sys_CLKX(sys_CLKX),
.sdr_REF_REQ(sdr_REF_REQ),
.sys_INIT_DONE(sys_INIT_DONE),
.sys_REF_ACK(sys_REF_ACK),
.cState(cstate));
cmd_fsm Command_FSM (.sys_CLKX(sys_CLKX),
.sys_ADSn(sys_ADSn), //i
.sdr_REF_REQ(sdr_REF_REQ),
.sys_A(sys_A), //i
.sdr_A(sdr_A),
.sdr_BA(sdr_BA),
.command(command),
.addr_fifo_empty(add_fifo_empty),
.Data_Rd_En(Data_Rd_En),
.cstate(cstate),
.sys_INIT_DONE(sys_INIT_DONE),//o
.sys_CYC_END(sys_CYC_END),//o
.Cnt_Rd_En(Cnt_Rd_En),
.Add_Rd_En(Add_Rd_En),
.sdr_R_Wn(sdr_R_Wn));
Datapath Datapath_control (.sys_CLKX(sys_CLKX),
.sys_D_VALID(sys_D_VALID),
.sdrclk_DQS(sdrclk_DQS),
.sys_D_IN(sys_D_IN),
.sdr_DQ_IN(sdr_DQ_IN),
.sys_D_OUT(sys_D_OUT),
.sdr_DQ_OUT(sdr_DQ_OUT),
.cstate(cstate));
Bank_cntl Bank_control (.sys_CLKX(sys_CLKX),

.sdr_A(sdr_A),
.sdr_BA(sdr_BA),
.sys_REF_ACK(sys_REF_ACK),
.sdr_CKE(sdr_CKE),
.sdr_CSn(sdr_CSn),
.sdr_RASn(sdr_RASn),
.sdr_CASn(sdr_CASn),
.sdr_WEn(sdr_WEn),
.ddr_BA(ddr_BA),
.ddr_A(ddr_A),
.iState(istate),
.cState(cstate),
.sdr_R_Wn(sdr_R_Wn),
.ddr_R_Wn(ddr_R_Wn),
.Bank(Bank),
.Bank_sel_7(Bank_sel_7));
endmodule
//ADDRESS FIFO
module Add_FIFO(clk,
rst,
Address_in,
write_to_Add_fifo,
read_from_Add_fifo,
Address_out,
Add_stack_full,
Add_stack_almost_full,
Add_stack_half_full,
Add_stack_almost_empty,
Add_stack_empty);
parameter stack_width=13;
parameter stack_height=8;
parameter stack_ptr_width=3;
parameter AE_level=2;
parameter AF_level=6;
parameter HF_level=4;
input[stack_width-1:0] Address_in;
input write_to_Add_fifo,read_from_Add_fifo;
input clk,rst;
output [stack_width-1:0] Address_out;
output Add_stack_full,Add_stack_almost_full,Add_stack_half_full;
output Add_stack_almost_empty,Add_stack_empty;
reg[stack_ptr_width-1:0] read_ptr,write_ptr;

reg[stack_ptr_width:0] ptr_gap;
reg[stack_width-1:0] Address_out;
reg[stack_width-1:0] stack[stack_height-1:0];
assign Add_stack_full=(ptr_gap==stack_height);
assign Add_stack_almost_full=(ptr_gap==AF_level);
assign Add_stack_half_full=(ptr_gap==HF_level);
assign Add_stack_almost_empty=(ptr_gap==AE_level);
assign Add_stack_empty=(ptr_gap==0);
always @(posedge clk )

if(rst)begin
Address_out<=0;
read_ptr<=0;
write_ptr<=0;
ptr_gap<=0;
end
else if(write_to_Add_fifo &&(!Add_stack_full)&&(!read_from_Add_fifo))
begin
stack[write_ptr]<=Address_in;
write_ptr<=write_ptr+1;
ptr_gap<=ptr_gap+1;
end
else if((!write_to_Add_fifo)&&(!Add_stack_empty)&&read_from_Add_fifo)begin
Address_out<=stack[read_ptr];
read_ptr<=read_ptr+1;
ptr_gap<=ptr_gap-1;
end
else if(write_to_Add_fifo &&read_from_Add_fifo&&Add_stack_empty)begin
ptr_gap<=ptr_gap+1;
end
else if(write_to_Add_fifo &&read_from_Add_fifo&&Add_stack_full)begin
ptr_gap<=ptr_gap-1;
end
else if(write_to_Add_fifo&&read_from_Add_fifo&&(!Add_stack_full)&&(!
Add_stack_empty))
begin
end
endmodule

//CONTROL FIFO
module
Cntrl_FIFO(clk,rst,control_in,write_to_cntrl_fifo,read_from_cntrl_fifo,control_out,cntrl_st
ack_full,
cntrl_stack_almost_full,cntrl_stack_half_full,cntrl_stack_almost_empty,cntrl_stack_emp
ty);
output [stack_width-1:0] control_out;
input[stack_width-1:0] control_in;
input write_to_cntrl_fifo,read_from_cntrl_fifo;
input clk,rst;
output cntrl_stack_full,cntrl_stack_almost_full,cntrl_stack_half_full;
output cntrl_stack_almost_empty,cntrl_stack_empty;
reg[stack_width-1:0] control_out;
assign cntrl_stack_full=(ptr_gap==stack_height);
assign cntrl_stack_almost_full=(ptr_gap==AF_level);
assign cntrl_stack_half_full=(ptr_gap==HF_level);
assign cntrl_stack_almost_empty=(ptr_gap==AE_level);
assign cntrl_stack_empty=(ptr_gap==0);
always @(posedge clk or posedge rst)

if(rst)begin
control_out<=0;
read_ptr<=0;
write_ptr<=0;
ptr_gap<=0;
end
else if(write_to_cntrl_fifo &&(!cntrl_stack_full)&&(!read_from_cntrl_fifo))begin
stack[write_ptr]<=control_in;
ptr_gap<=ptr_gap+1;
end
else if((!write_to_cntrl_fifo)&&(!cntrl_stack_empty)&&read_from_cntrl_fifo)begin
control_out<=stack[read_ptr];
ptr_gap<=ptr_gap-1;
end
else if(write_to_cntrl_fifo &&read_from_cntrl_fifo&&cntrl_stack_empty)begin
ptr_gap<=ptr_gap+1;
end

else if(write_to_cntrl_fifo &&read_from_cntrl_fifo&&cntrl_stack_full)begin

ptr_gap<=ptr_gap-1;
end
else if(write_to_cntrl_fifo&&read_from_cntrl_fifo&&(!cntrl_stack_full)&&(!
cntrl_stack_empty))
begin
end
endmodule
//WR DATA REG
module
WR_Data_FIFO(clk,rst,Data_in,write_to_WD_fifo,read_from_WD_fifo,Data_out,Data_stac
k_full,
Data_stack_almost_full,Data_stack_half_full,Data_stack_almost_empty,Data_stack_emp
ty);
input clk,rst;
input[stack_width-1:0] Data_in;
input write_to_WD_fifo,read_from_WD_fifo;
output [stack_width-1:0] Data_out;

output Data_stack_full,Data_stack_almost_full,Data_stack_half_full;
output Data_stack_almost_empty,Data_stack_empty;
reg[stack_width-1:0] Data_out;
assign Data_stack_full=(ptr_gap==stack_height);
assign Data_stack_almost_full=(ptr_gap==AF_level);
assign Data_stack_half_full=(ptr_gap==HF_level);
assign Data_stack_almost_empty=(ptr_gap==AE_level);
assign Data_stack_empty=(ptr_gap==0);
always @(posedge clk or posedge rst)

if(rst)begin
Data_out<=0;
read_ptr<=0;

write_ptr<=0;
ptr_gap<=0;
end
else if(write_to_WD_fifo &&(!Data_stack_full)&&(!read_from_WD_fifo))begin
stack[write_ptr]<=Data_in;
ptr_gap<=ptr_gap+1;
end
else if((!write_to_WD_fifo)&&(!Data_stack_empty)&&read_from_WD_fifo)begin
Data_out<=stack[read_ptr];
ptr_gap<=ptr_gap-1;
end
else if(write_to_WD_fifo &&read_from_WD_fifo&&Data_stack_empty)begin
ptr_gap<=ptr_gap+1;
end
else if(write_to_WD_fifo &&read_from_WD_fifo&&Data_stack_full)begin
ptr_gap<=ptr_gap-1;
end
else if(write_to_WD_fifo&&read_from_WD_fifo&&(!Data_stack_full)&&(!
Data_stack_empty))
begin
end
endmodule
//RD DATA REG
module RD_D_reg(clock,sys_RESET,RD_REG_data_in ,enable, RD_REG_data_out);
input clock,enable,sys_RESET;
input [63:0] RD_REG_data_in;
output reg [63:0] RD_REG_data_out;
always @(posedge clock)

begin
if (sys_RESET)
RD_REG_data_out <= 64'b0;
else if (enable)
RD_REG_data_out <= RD_REG_data_in;
else
RD_REG_data_out <= 64'b0;
end
endmodule

//INITIALIZATION FSM

`define i_PRE (5'b00010)// precharge state
`define i_tRP (5'b00011)// precharge period
`define i_EMRS (5'b00100) //Extended load mode register
`define i_AR1 (5'b00101) //Auto refresh
`define i_tRFC1 (5'b00110) //Auto refresh cycle period
`define i_MRS (5'b01001) // load mode register
`define i_tMRD (5'b01010) // load mode register period

module Inti_fsm
(sys_CLKX,sys_RESET,sys_DLY_200US,sys_ADSn,sys_INIT_DONE,sys_REF_REQ,istate)
;
input sys_CLKX;
input sys_RESET;
input sys_DLY_200US;
output reg sys_ADSn;

output reg sys_REF_REQ ;
output reg sys_INIT_DONE;
output wire [4:0]istate;
reg [4:0]presentstate,nextstate;
reg load_mrs_done ;
reg load_mrs_af ;
//-----------------------------------------------------------------//
//-----------------------------------------------------------------//

//----------------------------------------------------------------//
//----------------------------------------------------------------//


//-------------------------------------------------------------------------------------------------
always @ (posedge sys_CLKX)

begin
if (sys_RESET)
begin
presentstate = 5'b00000;
end
else
presentstate = nextstate;
end
assign istate = presentstate;
always @ (posedge sys_CLKX )

begin
case (presentstate)
5'b00000 : //i_IDLE
begin
if (sys_DLY_200US)
begin
load_mrs_done = 1'b0;
load_mrs_af = 1'b0;
sys_INIT_DONE = 1'b0;
sys_ADSn = 1'b1;
nextstate = 5'b00001;
end
else nextstate = 5'b00000;
end
5'b00001: //i_NOP
begin
if (sys_DLY_200US) nextstate = 5'b00010; // wait for 100 us delay by checking
sys_DLY_100US
end
5'b00010: //i_PRE
begin

if ((NUM1_CLK_tRP == 0 && NUM2_CLK_tRP >= 0) || (NUM1_CLK_tRP == 1

&& NUM2_CLK_tRP == 0))
begin
if (load_mrs_done)
nextstate = 5'b00101; // i_AR1
else
nextstate = 5'b00100; // i_EMRS
end
else
begin
nextstate = 5'b00011; //i_tRP
NUM1_CLK_tRP = NUM1_CLK_tRP - 1;
end
end
5'b00011: //i_tRP
begin
begin // wait until tRP satisfied
if (load_mrs_done)
nextstate = 5'b00101; // i_AR1
else
nextstate = 5'b00100; // i_EMRS
end
else
begin
nextstate = 5'b00011; //i_tRP
NUM1_CLK_tRP = NUM1_CLK_tRP - 1;
end
end
5'b00100: // i_EMRS
begin
if ((NUM1_CLK_tMRD == 0 && NUM2_CLK_tMRD >= 0) ||
(NUM1_CLK_tMRD == 1 && NUM2_CLK_tMRD == 0))
nextstate = 5'b01001; // i_MRS
else
begin
nextstate = 5'b01010; //i_tMRD
NUM1_CLK_tMRD = NUM1_CLK_tMRD - 1;
end
end
5'b00101 :// i_AR1

begin
if ((NUM1_CLK_tRFC1 == 0 && NUM2_CLK_tRFC1 >= 0) ||
(NUM1_CLK_tRFC1 == 1 && NUM2_CLK_tRFC1 == 0))
nextstate = 5'b00111; //i_AR2 // auto referesh
else
begin
nextstate = 5'b00110; //i_tRFC1
NUM1_CLK_tRFC1 = NUM1_CLK_tRFC1 - 1;
end

end
5'b00110 : //i_tRFC1
begin
if ((NUM1_CLK_tRFC1 == 0 && NUM2_CLK_tRFC1 >= 0) || (NUM1_CLK_tRFC1
== 1 && NUM2_CLK_tRFC1 == 0))
nextstate = 5'b00111; //i_AR2 // wait until tRFC
satisfied
else
begin
nextstate = 5'b00110; //i_tRFC1
end
end
5'b00111 : //i_AR2
begin
if ((NUM1_CLK_tRFC2 == 0 && NUM2_CLK_tRFC2 >= 0) ||
(NUM1_CLK_tRFC2 == 1 && NUM2_CLK_tRFC2 == 0))
nextstate = 5'b01001; //i_MRS
else
begin
nextstate = 5'b01000; // i_tRFC2
end
end
5'b01000 : // i_tRFC2
begin
load_mrs_af = 1'b1; // auto referesh
if ((NUM1_CLK_tRFC2 == 0 && NUM2_CLK_tRFC2 >=
0) || (NUM1_CLK_tRFC2 == 1 && NUM2_CLK_tRFC2 == 0))
begin
nextstate = 5'b01001; // i_MRS
end
else
begin
nextstate = 5'b01000; // i_tRFC2
end
end
5'b01001 : //i_MRS
begin
load_mrs_done = 1'b1; // load mode register
if ((NUM1_CLK_tMRD == 0 && NUM2_CLK_tMRD >= 0) || (NUM1_CLK_tMRD ==

1 && NUM2_CLK_tMRD == 0))
begin
if(load_mrs_af)
nextstate = 5'b01011; //i_ready
else
nextstate = 5'b00010; //i_PRE
end

else
begin
end
end
5'b01010 : //i_tMRD
begin
if ((NUM1_CLK_tMRD == 0 && NUM2_CLK_tMRD >= 0) || (NUM1_CLK_tMRD
== 1 && NUM2_CLK_tMRD == 0))
begin // wait until tMRD satisfied
if(load_mrs_done)
begin
if(load_mrs_af)
nextstate = 5'b01011; // i_ready
else
nextstate = 5'b00010; // i_PRE
end
else
nextstate = 5'b01001; //i_MRS
end
else
begin
end
end
5'b01011 : //i_ready
begin // stay at this state for normal operation
nextstate = 5'b01011; //i_ready
sys_ADSn = 1'b0;
end
default :
begin
nextstate = 5'b00000; //i_IDLE
sys_ADSn = 1'b1;
end
endcase
end

begin
// i_AR1 i_tRFC1 i_AR2 i_tRFC2
if ((presentstate ==5'b00101) |(presentstate ==5'b00110) | (presentstate ==
5'b00111) |(presentstate ==5'b01000))
sys_REF_REQ = 1'b1;
else
sys_REF_REQ = 1'b0;
end
endmodule

//CLOCK COUNTER


module clk_counter (sys_CLKX,sys_RESET,clkCNT,iState,cState);
input sys_CLKX;
input sys_RESET;
output reg [4:0] clkCNT;

input [4:0]iState;
input [4:0]cState;
reg syncResetClkCNT;
//---------------------------------------------------------------//
// CAS Latency
// Burst Length
//--------------------------------------------------------------//
// User modifiable parameters //
//--------------------------------------------------------------//
/****************************
* Mode register setting
****************************/

//-----------------------------------------------------------------//
//-----------------------------------------------------------------//
//----------------------------------------------------------------//
//----------------------------------------------------------------//







//-------------------------------------------------------------------------------------------------

begin : syncResetClkCNT1
case (iState)

5'b00000 : //i_IDLE
begin
syncResetClkCNT <= 1'b1;
end
5'b00001 :
5'b00010 : //i_NOP
begin
else
end
5'b00011 : //i_PRE
begin
else
end
5'b00100: // i_EMRS
begin
else
end
5'b00101 : //i_AR1
begin
== 1 && NUM2_CLK_tRFC1 == 0))
else
end
5'b00110 : //i_tRFC1
begin
== 1 && NUM2_CLK_tRFC1 == 0))
else
end
5'b00111 : //i_AR2
begin


== 1 && NUM2_CLK_tRFC2 == 0))
else
end
5'b01000 : //i_tRFC2
begin
== 1 && NUM2_CLK_tRFC2 == 0))

else
end
5'b01001 : //i_MRS
begin
== 1 && NUM2_CLK_tMRD == 0))
else
end
5'b01010 : // i_tMRD
begin
== 1 && NUM2_CLK_tMRD == 0))
else
end
5'b01011 : //i_ready
begin
case (cState)
5'b01100 : //c_ACTIVE
begin
else
end
5'b01101 : //c_tRCD
begin
if ((NUM1_CLK_tRCD == 1'b0 && NUM2_CLK_tRCD >= 1'b0) ||
(NUM1_CLK_tRCD == 1'b1 && NUM2_CLK_tRCD == 1'b0))
else

end
5'b01110 : //c_READA
5'b01111 : //c_tRC
begin
if(NUM_CLK_tRC == 1)
else
end
5'b10000 : //c_rdata
begin
if (NUM_CLK_READ == 1)
else
end
5'b10001 : //c_WRITEA
5'b10010 : //c_tWL
begin
if(NUM_CLK_tWL == 1'b1)
else
end
5'b10011 : //c_wdata
begin
if(NUM_CLK_WRITE == 1'b1)
else
end
5'b10100 : //c_tDAL
begin
if ((NUM1_CLK_tDAL == 0 & NUM2_CLK_tDAL >= 0)
| (NUM1_CLK_tDAL == 1'b1 & NUM2_CLK_tDAL == 1'b0))
else
end
default :
endcase
end

default :
endcase
end

begin : clk_counter1
if (sys_RESET)
clkCNT <= 4'b0;
else if (syncResetClkCNT)
clkCNT <= clkCNT + 4'b1;
else
clkCNT <= 4'b1;
end
endmodule
//REFRESH COUNTER

module ref_counter
(sys_CLKX,sys_RESET,sys_REF_REQ,sys_INIT_DONE,sys_REF_ACK,sdr_REF_REQ,cSta
te);
input sys_CLKX;
input sys_RESET;
input sys_REF_REQ;//from initialization fsm
input sdr_REF_REQ; //from command fsm
input sys_INIT_DONE;
input [4:0]cState;
output reg sys_REF_ACK;
always@(posedge sys_CLKX)
begin :REFRESH
if (sys_RESET)
sys_REF_ACK <= 1'b0;
else
begin
case (cState)
5'b10001 : //c_WRITEA
begin
if (sys_REF_REQ == 1'b1 | sdr_REF_REQ == 1'b1)


else
end
5'b01110 : //c_READA
begin
else
end
5'b11001 : //c_RDA0
begin
else
end
5'b11101 : //c_RDAn-1
begin
else
end
5'b11111 : //c_RDAn
begin
else
end
default :
begin
end
endcase
end
end
endmodule
//COMMAND FSM
// **** for normal write or read operation


// *******fast read operation
`define c_wait0 (5'b10101)

`define c_ACT0 (5'b10110)
`define c_tRRD (5'b10111)
`define c_tRCD0 (5'b11000)
`define c_RDA0 (5'b11001)
`define c_RDexit (5'b11010)
`define c_ACTn (5'b11011)
`define c_tRCdn-1 (5'b11100)
`define c_RDAn-1 (5'b11101)
`define c_tRCdn (5'b11110)
`define c_RDAn (5'b11111)
//---------------------------------------------------------------------------------------------------------
module cmd_fsm (sys_CLKX,
sys_RESET,
sys_ADSn,
sys_A,
sdr_A,
sdr_BA,
Add_Rd_En,
Data_Rd_En,
Cnt_Rd_En,
sys_INIT_DONE,
addr_fifo_empty,
sys_CYC_END,
command,
sdr_R_Wn,
sdr_REF_REQ,
cstate);
input sys_CLKX;
input sys_RESET;
input [1:0] command; // from control fifo
input sys_ADSn; // from initialization fsm
input [12:0]sys_A; // from Adress fifo
input sys_INIT_DONE; // from initialization fsm
input addr_fifo_empty; // from Adress fifo
output reg [1:0] sdr_R_Wn; // to bank control

output reg [12:0] sdr_A; // to bank control
output reg [2 :0] sdr_BA; // to bank control
output reg sys_CYC_END; // to indicates write cycle or read cycle is completed
output reg sdr_REF_REQ; // to refresh counter
output reg Cnt_Rd_En; // to enable the control fifo
output reg Add_Rd_En ; // to enable the Adress fifo
output reg Data_Rd_En; // to enable the WR_data fifo
output wire[4 :0] cstate; // to the data path module
reg [4 :0] presentstate,nextstate;
//--------function ------- command --------------------//

parameter NO_Operation = 2'b00;
parameter Write = 2'b01;
parameter Read = 2'b10;

parameter Fast_Read = 2'b11;
// CAS Latency
// Burst Length
/
**************************************************************************************************
****
* User modifiable parameters
**************************************************************************************************
*****/
//-----------------------------------------------------------------//
//-----------------------------------------------------------------//
parameter tRCD0 = 190; // delay before read/write is sampled IN FAST READ
parameter tRRD = 190; // delay before read is sampled
parameter tRTP = tCK + 11; // read peroid when precharge
parameter tDAL = tWR + tRP; // sum of write recovery, precharge peroid
parameter tRAL = tRTP + tRP; // sum of read peroid when precharge, precharge
peroid
//----------------------------------------------------------------//
//----------------------------------------------------------------//

reg [2:0] NUM1_CLK_tRCD0 = tRCD0/tCK;
reg [2:0] NUM1_CLK_tRRD = tRRD/tCK;
reg [2:0] NUM1_CLK_tRAL = tRAL/tCK;
reg [7:0] NUM2_CLK_tRCD0 = tRCD0%tCK;

reg [7:0] NUM2_CLK_tRRD = tRRD%tCK;

reg [7:0] NUM2_CLK_tRAL = tRAL%tCK;




//-------------------------------------------------------------------------------------------------

begin
if (sys_RESET)
presentstate = 5'b00000;
else
presentstate = nextstate;
end
assign cstate = presentstate;

begin
case (presentstate)
5'b00000 : // c_idle, wait until sys_INIT_DONE asserted

begin
if ((!sys_ADSn) && (sys_INIT_DONE))
begin
nextstate = 5'b01100; //c_ACTIVE
end
else if (command == 2'b11)
nextstate = 5'b10101; // c_wait0 (5'b10101)
else
end
5'b01100: //c_ACTIVE
begin
if ((NUM1_CLK_tRCD == 0 && NUM2_CLK_tRCD >= 0) || (NUM1_CLK_tRCD
== 1 && NUM2_CLK_tRCD == 0))
begin
if (command == 2'b01)
begin
nextstate = 5'b01110; //c_READA
end

begin
nextstate = 5'b10001; // c_WRITEA
end
begin
nextstate = 5'b10101; // c_wait0 (5'b10101)
end
end
else
nextstate = 5'b01101; // c_tRCD
end
5'b01101 : // c_tRCD
begin
== 1 && NUM2_CLK_tRCD == 0))
begin
if(command == 2'b01)
begin
nextstate = 5'b01110; //c_READA
end
if(command == 2'b10) // c_WRITEA
begin
end
if(command == 2'b11) // c_Fast Read
begin
end
end
else
begin
NUM1_CLK_tRCD = NUM1_CLK_tRCD - 1;
nextstate = 5'b01101; // c_tRCD
end
end
5'b01110 : //c_READA **** assert col/bank addr for read with auto-precharge
begin
nextstate = 5'b01111; //c_tRC
end
5'b01111 : //c_tRC ***** CASn latency
begin
case (NUM_CLK_tRC)
1 : begin
nextstate = 5'b10000; // c_rdata

end
default : begin
nextstate = 5'b01111; //c_tRC
NUM_CLK_tRC = NUM_CLK_tRC - 1;
end
endcase
end
5'b10000 : // c_rdata ******read cycle data phase

begin
case (NUM_CLK_READ)
1 : begin
NUM_CLK_READ = 2'd2;
end
default : begin
nextstate = 5'b10000; // c_rdata
NUM_CLK_READ = NUM_CLK_READ - 1;
end
endcase
end
5'b10001 : // c_WRITEA**** assert col/bank addr for write with auto-precharge
begin
nextstate = 5'b10010; // C_tWL
end
5'b10010 : // C_tWL CASn latency

begin
case (NUM_CLK_tWL)
1 : nextstate = 5'b10011; //c_wdata
default : begin
nextstate = 5'b10010; // C_tWL
NUM_CLK_tWL = NUM_CLK_tWL - 1;
end
endcase
end
5'b10011 : //c_wdata
begin
case (NUM_CLK_WRITE)
1 : begin
nextstate = 5'b10100 ; // c_tDAL
NUM_CLK_WRITE = 2'd2;
end
default : begin
nextstate = 5'b10011; //c_wdata

NUM_CLK_WRITE = NUM_CLK_WRITE - 1;
end
endcase
end
5'b10100 : // c_tDAL wait until (tWR + tRP) satisfied before issuing next
begin
if ((NUM1_CLK_tDAL == 0 && NUM2_CLK_tDAL >= 0) || (NUM1_CLK_tDAL == 1
&& NUM2_CLK_tDAL == 0))
begin
nextstate = 5'b00000; //c_idle

end
else
begin
NUM1_CLK_tDAL = NUM1_CLK_tDAL - 1;
nextstate = 5'b10100; // c_tDAL
end
end
//************************************** Fast Read operation

*****************************************************
5'b10101: //c_wait0
begin
== 1 && NUM2_CLK_tRCD == 0))
begin
if (!addr_fifo_empty)
nextstate = 5'b10110; //c_ACT0
else nextstate = 5'b10101; // c_wait0

end
end
5'b10110:// c_ACT0
begin
nextstate = 5'b10111; //c_tRRD
end
5'b10111: //c_tRRD
begin
if ((NUM1_CLK_tRRD == 0 && NUM2_CLK_tRRD >= 0) || (NUM1_CLK_tRRD
== 1 && NUM2_CLK_tRRD >= 0))
begin
if(addr_fifo_empty)
nextstate = 5'b11000; //c_tRCD0
else if (!addr_fifo_empty)
nextstate = 5'b11011; //c_ACTn
else nextstate = 5'b10111; //c_tRRD

end
end
5'b11000: //c_tRCD0
begin


== 1 && NUM2_CLK_tRCD >= 0))
begin
nextstate = 5'b11001;//c_RDA0
end
end
5'b11001 : //c_RDA0
begin
case (NUM_CLK_READ)
1 : begin
nextstate = 5'b11010; //c_RDexit
end
default : begin
nextstate = 5'b11001; //c_RDA0
end
endcase
end
5'b11010 : // c_RDexit wait until (tRTP + tRP) satisfied before issuing next
begin
if ((NUM1_CLK_tRAL == 0 && NUM2_CLK_tRAL >= 0) || (NUM1_CLK_tRAL == 1
&& NUM2_CLK_tRAL == 0))
begin
nextstate = 5'b00000; //c_idle
end
else
begin
NUM1_CLK_tRAL = NUM1_CLK_tRAL - 1;
nextstate = 5'b11010; // c_RDexit
end
end
5'b11011:// c_ACTn
begin
nextstate = 5'b11100; //c_tRCdn-1 Read Cycle delay
end
5'b11100:// c_tRCdn-1
begin
== 1 && NUM2_CLK_tRCD == 0))
nextstate = 5'b11101; //c_RDAn-1
else nextstate = 5'b11100; // c_tRCdn-1

end
5'b11101: //c_RDAn-1
begin
if(addr_fifo_empty)
begin

case (NUM_CLK_READ)
1 : begin
nextstate = 5'b11111; //c_RDAn
end
default : begin
nextstate = 5'b11101; //c_RDAn-1
end
endcase
end
else nextstate = 5'b11011;// c_ACTn
end
5'b11111: //c_RDAn
begin
case (NUM_CLK_READ)
1 : begin
nextstate = 5'b11010; //c_RDexit
end
default : begin
nextstate = 5'b11111; //c_RDAn
end
endcase
end
default : nextstate = 5'b00000;

endcase
end
//************************************** End of Fast Read operation
*****************************************************
begin
sdr_BA = sys_A[2 : 0];
sdr_A = sys_A;
end
//***********************************************************************************************
***************
begin
sdr_R_Wn =command ;
end
//************** REFRESH REQUEST

GENERATION**************************************************************

begin
// C_wdata //c_rdata

if ((presentstate == 5'b10011) |(presentstate == 5'b10000))

sdr_REF_REQ = 1'b1;
else
sdr_REF_REQ = 1'b0;
end
//******************** sys_CYC_END generation
***********************************************************

begin
if (sys_RESET)
sys_CYC_END = 1'b1;
else
begin
case (presentstate)
5'b00000 : sys_CYC_END = 1'b0;
5'b10011 : // C_wdata
case (NUM_CLK_WRITE)
1 : sys_CYC_END = 1'b1;
default :sys_CYC_END = 1'b0;
endcase
5'b10000 : //c_rdata
case (NUM_CLK_READ)
1 : sys_CYC_END = 1'b1;
default :sys_CYC_END = 1'b0;
endcase
default:
sys_CYC_END = 1'b0;
endcase
end
end
//******************** Signals to fifo generation ***************************
begin
case (presentstate)
5'b10000 : //c_rdata
begin
Add_Rd_En = 1'b1;
Cnt_Rd_En = 1'b0;
Data_Rd_En = 1'b0;
end

5'b10011 : //c_wdata
begin
Add_Rd_En = 1'b1;
Cnt_Rd_En = 1'b0;
Data_Rd_En = 1'b1;
end
5'b01100 : //c_ACTIVE
begin
Add_Rd_En = 1'b0;
Cnt_Rd_En = 1'b1;
Data_Rd_En = 1'b0;
end
default :
begin
Add_Rd_En = 1'b0;
Cnt_Rd_En = 1'b0;
Data_Rd_En = 1'b0;
end
endcase
end
endmodule
//DATA PATH CONTROL
module Datapath ( sys_CLKX,

sys_CLK3X,
sys_RESET,
sys_D_VALID,
sdrclk_DQS,
sys_D_IN,
sdr_DQ_IN,
sys_D_OUT,
sdr_DQ_OUT,
cstate);
input sys_CLKX;
input sys_CLK3X;
input sys_RESET;
input [4 :0]cstate;
input [63:0]sys_D_IN; // from wr data fifo
input [63:0]sdr_DQ_IN; // from memory
output reg sys_D_VALID; // data valid

output reg sdrclk_DQS;
output reg [63:0]sys_D_OUT; // to read_data_reg
output reg [63:0]sdr_DQ_OUT; // to memory
reg enableSysD ;
always @ (posedge sys_CLK3X)

begin
if (sys_RESET)
begin
sys_D_OUT <=64'b0;
sdr_DQ_OUT <=64'b0;

end
//c_wdata
if((cstate == 5'b10011 ) && (!sys_RESET)) //Write Cycle Data Path
begin
sdr_DQ_OUT <= sys_D_IN;
end
// c_rdata c_RDA0 c_RDAn-1 c_RDAn

// if ((cstate == 5'b10000 |cstate ==5'b11001 |(5'b11101)| (5'b11111)) && (!
sys_RESET))// Read Cycle Data Path
if (((cstate == 5'b10000) | (cstate == 5'b11001)| (cstate ==5'b11101)| (cstate

==5'b11111)) && (!sys_RESET))
begin
sys_D_OUT <= sdr_DQ_IN;
end
end

begin
// c_RDA0 c_RDAn-1 c_RDAn
// if (cstate == 5'b10011 |cstate == 5'b10000 |cstate == 5'b11001 |cstate
==5'b11101) |cstate ==5'b11111)
if ((cstate == 5'b10011) | (cstate == 5'b10000)| (cstate == 5'b11001)| (cstate
==5'b11101)| (cstate ==5'b11111))
sdrclk_DQS <= 1'b0;
else
sdrclk_DQS <= 1'b1;
end

begin
// C_wdata c_rdata c_RDA0 c_RDAn-1 c_RDAn
// if (cstate == 5'b10011 |cstate == 5'b10000 |cstate == 5'b11001 |cstate
==5'b11101) |cstate ==5'b11111)
if ((cstate == 5'b10011) | (cstate == 5'b10000)| (cstate == 5'b11001)| (cstate
==5'b11101)| (cstate ==5'b11111))
enableSysD <= 1'b1;

else
enableSysD <= 1'b0;
end
always @ (posedge sys_CLK3X) //sys_D_VALID Generation

begin
sys_D_VALID <= enableSysD;
end
endmodule

//BANK CONTROL


module Bank_cntl(sys_CLKX,sys_CLK3X,sys_RESET,sdr_A,sdr_BA,sys_REF_ACK,Bank,
sdr_CKE,sdr_CSn,sdr_RASn,sdr_CASn,sdr_WEn,ddr_BA,ddr_A,Bank_sel_0,Bank_sel_1,
Bank_sel_2,
Bank_sel_3,Bank_sel_4,Bank_sel_5,Bank_sel_6,Bank_sel_7,iState,cState,sdr_R_Wn,ddr
_R_Wn);
input sys_CLKX;
input sys_CLK3X;
input sys_RESET;
input [2: 0]sdr_BA; // from command fsm
input [12:0]sdr_A;
input sys_REF_ACK;
input [1:0] sdr_R_Wn;
input [4:0] iState;
input [4:0] cState;
output reg [1:0]ddr_R_Wn;
// output reg sys_REF_REQ;

output reg sdr_CKE; //sdr clock enable
output reg [3: 0] sdr_CSn; // sdr chip select
output reg [3: 0] sdr_RASn; // sdr row address select
output reg [3: 0] sdr_CASn; // sdr column address select
output reg [3: 0] sdr_WEn; // sdr write enable
output reg [2: 0] ddr_BA;

output reg [12:0] ddr_A;

output reg [2: 0] Bank;
output reg Bank_sel_0;
parameter IDLE = 4'b1111;

parameter NOP = 4'b0111;
parameter ACTIVE = 4'b0011;
parameter READ = 4'b0101;
parameter WRITE = 4'b0100;
parameter PRECHARGE = 4'b0010;
parameter AUTO_REFRESH = 4'b0001;
parameter LOAD_MODE_REGISTER = 4'b0000;
always @(posedge sys_CLK3X)

begin
case (iState)
5'b00000: //i_IDLE
begin
sdr_CSn <= IDLE;
sdr_RASn<= IDLE;
sdr_CASn<= IDLE;
sdr_WEn <= IDLE;
sdr_CKE <= 1'b0;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;
end
// i_tRP | i_tRFC1 | i_tRFC2 | i_tMRD |i_NOP
5'b00011 |5'b00110 |5'b01000 |5'b01010 |5'b00001 :
begin
sdr_CSn <= NOP;
sdr_RASn<= NOP;
sdr_CASn<= NOP;
sdr_WEn <= NOP;
sdr_CKE <= 1'b1;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;
end
5'b00010: //i_PRE
begin
sdr_CSn <= PRECHARGE;
sdr_RASn<= PRECHARGE;
sdr_CASn<= PRECHARGE;
sdr_WEn <= PRECHARGE;
sdr_CKE <= 1'b1;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;

end
5'b00100: //i_EMRS
begin
sdr_CSn <= LOAD_MODE_REGISTER;
sdr_RASn<= LOAD_MODE_REGISTER;
sdr_CASn<= LOAD_MODE_REGISTER;
sdr_WEn <= LOAD_MODE_REGISTER;
sdr_CKE <= 1'b1;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;
end
//i_AR1 |i_AR2
5'b00101 | 5'b00111:
begin
sdr_CSn <= AUTO_REFRESH;
sdr_RASn<= AUTO_REFRESH;
sdr_CASn<= AUTO_REFRESH;
sdr_WEn <= AUTO_REFRESH;
sdr_CKE <= 1'b1;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;
end
5'b01001 : //i_MRS
begin
sdr_CSn <= LOAD_MODE_REGISTER;
sdr_RASn<= LOAD_MODE_REGISTER;
sdr_CASn<= LOAD_MODE_REGISTER;
sdr_WEn <= LOAD_MODE_REGISTER;
sdr_CKE <= 1'b1;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;
end
5'b01011 : //i_ready
begin
case (cState)
//c_idle | c_tRCD | c_tWL | c_rdata | c_wdata | c_tDAL
5'b00000 |5'b01101 |5'b10010 |5'b10000 | 5'b10011 | 5'b10100 :
begin
sdr_CSn <= NOP;
sdr_RASn<= NOP;
sdr_CASn<= NOP;
sdr_WEn <= NOP;
sdr_CKE <= 1'b1;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;
end
5'b01100 : //c_ACTIVE
begin
sdr_CSn <= ACTIVE;
sdr_RASn<= ACTIVE;

sdr_CASn<= ACTIVE;
sdr_WEn <= ACTIVE;
sdr_CKE <= 1'b1;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;
end
5'b01110 : //c_READA
begin
sdr_CSn <= READ;
sdr_RASn<= READ;
sdr_CASn<= READ;
sdr_WEn <= READ;
sdr_CKE <= 1'b1;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;
end
5'b10001 : //c_WRITEA
begin
sdr_CSn <= WRITE;
sdr_RASn<= WRITE;
sdr_CASn<= WRITE;
sdr_WEn <= WRITE;
sdr_CKE <= 1'b1;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;
end
default :
begin
sdr_CSn <= NOP;
sdr_RASn<= NOP;
sdr_CASn<= NOP;
sdr_WEn <= NOP;
sdr_CKE <= 1'b1;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;
end
endcase
end
default: begin
sdr_CSn <= NOP;
sdr_RASn<= NOP;
sdr_CASn<= NOP;
sdr_WEn <= NOP;
sdr_CKE <= 1'b1;
ddr_BA <= sdr_BA;
ddr_A <= sdr_A;
end
endcase
end
always @(posedge sys_CLK3X)
begin

if(sys_RESET)
begin
Bank_sel_0 <= 1'b0;
Bank_sel_1 <= 1'b0;
Bank_sel_2 <= 1'b0;
Bank_sel_3 <= 1'b0;
Bank_sel_4 <= 1'b0;
Bank_sel_5 <= 1'b0;
Bank_sel_6 <= 1'b0;
Bank_sel_7 <= 1'b0;
end
else if(sdr_BA == 3'b000)
begin
Bank <=3'b000;
Bank_sel_0 <= 1'b1;
end
begin
Bank <=3'b001;
Bank_sel_1 <= 1'b1;
end
begin
Bank <=3'b010;
Bank_sel_2 <= 1'b1;
end
begin
Bank <=3'b011;
Bank_sel_3 <= 1'b1;
end
begin
Bank <=3'b100;
Bank_sel_4 <= 1'b1;
end
begin
Bank <=3'b101;
Bank_sel_5 <= 1'b1;
end
begin
Bank <=3'b110;
Bank_sel_6 <= 1'b1;
end
begin

Bank <=3'b111;
Bank_sel_7 <= 1'b1;
end
else
begin
Bank_sel_0 <= 1'b0;
Bank_sel_1 <= 1'b0;
Bank_sel_2 <= 1'b0;
Bank_sel_3 <= 1'b0;
Bank_sel_4 <= 1'b0;
Bank_sel_5 <= 1'b0;
Bank_sel_6 <= 1'b0;
Bank_sel_7 <= 1'b0;
end
end
begin
ddr_R_Wn <=sdr_R_Wn ;
end
endmodule

5.3 SAMPLE OUTPUTS OF DDR3 SDRAM CONTROLLER:

No Operation State
Read State

Write State
Fast Read State

Fig 5.2: Simulation Results
Fig 5.3: Schematic View
Fig 5.4: RTL Schematic View

CHAPTER 6
ADVANTAGES OF DDR3 SDRAM
CONTROLLER

6.1 ADVANTAGES:
1. Higher bandwidth performance, effectively up to 2400MHz.
2. Longer battery life in laptops.
3. Enhanced low power features with improved thermal design (cooler).
4. Compared with DDR SDRAM the voltage of DDR3 SDRAM was lowered
from 2.5V to 1.5V. This improves power consumption and reduces power
dissipation, enables more dense memory configurations for higher
capacities
5. DDR3 SDRAM achieves nearly twice the bandwidth of the preceding

single data rate DDR2 SDRAM by double pumping (transferring data on
the rising and falling edges of the clock signal) without increasing the
clock frequency.
6. DDR SDRAM is expensive than DDR3 SDRAM, and most

manufacturers have dropped its support from their chipsets.
7. Low manufacturing cost.
8. Low-voltage, 1.5V DDR3 reduced chip count provides significant

power savings.

CHAPTER 7
RESULT, CONCLUSION AND
FUTURE SCOPE

7.1 RESULT AND CONCLUSION:

In this project we have designed a High speed DDR3 SDRAM
Controller with 64-bit data transfer which synchronizes the
transfer of data between DDR RAM and External peripheral devices
like host computer, laptops and so on. The advantages of this
controller compared to SDR SDRAM, DDR1 SDRAM and DDR2
SDRAM is that it synchronizes the data transfer, and the data
transfer is twice as fast as previous, the production cost is also very
low.
We have successfully designed using Verilog HDL and

simulated using ModelSim, synthesized using Xilinx tool.
7.2 FUTURE SCOPE:

1. DDR4 SDRAM is the 4th generation of DDR SDRAM.
2. DDR3 SDRAM standards are still being developed and improved.
Table 7.1: DDR SDRAM Standards
DDR SDRAM Standard Frequency (MHz) Voltage
DDR 400-533 2.5
DDR2 667-800 1.8
DDR3 1066 to ... 1.5
3. Higher frequencies enable higher rates of data transfer.
4. Reduced power consumption due to 90mm fabrication technology.
5. Pre-fetch buffer can be doubled to 16 bits to further increase

performance.

BIBILOGRAPHY
1. A. J. McAuley, et al, “Fast Routing Table Lookup Using CAMs”,
Proceedings on 12th Annual Joint Conference of the IEEE Computer and
Communications Societies (INFOCOM), Vol.3, March 1993, pp.1382 –
1391.
2. X. Yang, et al, “High Performance IP Lookup Circuit Using DDR
SDRAM”, IEEE International SOC Conference (SOCC), Sept. 2008, pp.
371-374.
3. G. Allan, “The Love/Hate Relationship with DDR SDRAM Controllers”,
MOSAID Technologies Whitepaper, 2006.
4. H. Kim, et al, “High-Performance and Low-Power Memory- Interface
Architecture for Video Processing Application”, IEEE Transactions on
Circuit and Systems for Video Technology, Vol. 11, Nov. 2001, pp. 1160-
1170.
5. E. G. T. Jaspers, et al, “Bandwidth Reduction for Video Processing in
Consumer Systems”, IEEE Transactions on Consumer Electronics, Vol.
47, No. 4, Nov. 2001, pp. 885- 894.
6. N. Zhang, et al, “High Performance and High Efficiency Memory
Management System for H.264/AVC Application in the Dual-Core
Platform”, ICASE, Oct. 2006, pp. 5719-5722.
7. J. Zhu, et al, “”High Performance Synchronous DRAMs Controller in
H. 264 HDTV Decoder”, Proceedings of International Conference on
Solid-State and Integrated Circuits Technology, Vol. 3, Oct. 2004, pp.
1621-1624.
8. “High-Performance DDR3 SDRAM Interface in Virtex-5 Devices”,
Xilinx, XAPP867 (v1.0), Sept 24, 2007.
9. T. Mladenov, “Bandwidth, Area Efficient and Target Device
Independent DDR SDRAM Controller”, Proceedings of World Academy of
Science, Engineering and Technology, Vol. 18, De. 2006, pp. 102-106.

10. DDR3 SDRAM Specification (JESD79-3A), JEDEC Standard, JEDEC

Solid State Technology Association, Sept. 2007.
11. www.altera.com/literature/ug/ug_altmemphy.pdf, External DDR
Memory PHY Interface Mega function User Guide (ALTMEMPHY)
accessed on 23 Feb. 2009.

APPENDIX
There are now two industry standard hardware description
languages, VHDL and Verilog. Verilog is easier to understand and use.
For several years it has been the language of choice for industrial
applications that required both simulation and synthesis. It lacks,
however, constructs needed for system level specifications. VHDL is more
complex, thus difficult to learn and use. However it offers a lot more
flexibility of the coding styles and is suitable for handling very complex
designs.
Verilg-HDL is a Hardware Description Language used to describe
digital circuit and system operation. It is one of the two IEEE standard
HDLs in use today:
 Verilg-HDL IEEE Standard 1364-2001
 VHDL IEEE Standard 1076-2002
Verilog-HDL was released in 1983 by Gateway Design System
Corporation, together with a Verilog-HDL Simulator. In 1985 the
language and simulator were enhanced-with the introduction of the
Gateway Design System Corporation. In early 1990, Verilog-HDL and
Verilg-XL were separated to become two separate products. Verilog-HDL,
until then a proprietary language, was released into the public domain.
This was to facilitate the dissemination of knowledge relating to Verilog-
HDL and to compete with VHDL, with VHDL already existing as a non-
proprietary language. Additionally, in 1990, open Verilog International
(OVI) was formed as an industry consortium, consisting of a Computer
Aided Engineering (CAE) vendors and Verilog-HDL users, in order to
control the language specification. In 1995, Verilog-HDL was reviewed
and then adopted as an IEEE standard-IEEE Standard 1364. In 2001,
the standars was reviewed, the latest version of the standard now being
IEEE Std 1364-2001. Within Verilog-HDL, the module describes the
design. All functions and procedures are contained within the module

statement for the design. A design will consist of one or more

interconnected modules, and each of these modules has an interface port
to the other modules in order to describe how they are interconnected.
The modules are contained within ASCII text files. For design
maintenance and ease of understanding, it is common to place one
design module per file, although this is not a requirement. The top level
module specifies the overall system in which other modules are used.
Where modules are contained in separate text files, then these are
included in the top level design, or next level up in the multi-level
hierarchical designs.
Verilog-HDL uses wire and reg data types. Net data types are wire,
whilst register data types are reg. A wire has a circuit equivalent of an
electrical wire that connects circuit elements. A reg is updated under the
control of a procedural flow-a reg type variable stores the last value that
was procedurally assigned to it. The reg and wire data objects may have
the following possible values:
0 logical zero or false.
1 logical 1 or true.
x unknown logical value.
Z high impedance output of a tri state gate.
The reg variables are initialized to x at the start of the simulation.
Any unconnected wire variables have an x value. The size of a wire or a
register (single bit or multi-bit) can be specified in the module
declaration. For example:
reg [7:0] C;
reg [7:0] A, B;
wire [3:0] DataOut;
wire DataIn;

specifies registers A, B and C to be 8-bits wide, with the most significant

bit being the 7th bit. The wire DataOut is 4-bits wide and DataIn is 1-bit
wide.
Verilog-HDL is close to the C++ programming language. The
language is case sensitive and comments are created on a single line by
starting the line with a // , or by /* to */ where comments span across
several lines. A number of keywords, e.g. module, are defined and typed
in all lower case letters. Spaces are important in the language. Numbers
can be specified in the traditional form of a series of digits, but also in
the following form:
<size><base format><number>
Where <size> contains decimal digits that specify the size of the
number in the number of bits. The <size> is optional. The <base format>
is a single character ' followed by one of the following characters b. d, o
and h, which stand for binary, decimal, ocatal and hex, respectively. The
<number> part contains digits that are legal for the <base format>. For
example:
549 // decimal number.
'h8FF // hex number.
'o752 // octal number.
4'b0101 // 4-bit binary number “0101”.
3'b11x // 3-bit binary number with least
// significant bit unknown.
5'd3 // 5-bit decimal number.

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DESIGN OF HIGH SPEED DDR3 SDRAM CONTROLLER

DEPT OF ECE, SBIT, KMM 1

1.1 DDR3 SDRAM:

In electronic engineering, DDR3 SDRAM or double-data-rate three

The primary benefit of DDR3 is the ability to transfer I/O data at

DEPT OF ECE, SBIT, KMM 2

Fig 1.1: comparison of DDR3 and DDR2 SDRAM

The frequencies of DDR3 memory could be raised beyond those of

DEPT OF ECE, SBIT, KMM 3

without any modifications or improvements of the semiconductor

The final DDR3 SDRAM specification released by JEDEC recently

However, DDR3 SDRAM offers a few other useful improvements

Fig 1.2: Operating frequencies of DDR2 and DDR3 SDRAM

DEPT OF ECE, SBIT, KMM 4

1.2 DDR3 Based Lookup Circuit for High-Performance

DEPT OF ECE, SBIT, KMM 5

controller architectures and derive a customized architecture for the

Fig 1.3: Proposed Hash-CAM based look up circuit

The original data and reference address information are stored in

DEPT OF ECE, SBIT, KMM 6

1.3 TYPES OF MEMORY CONTROLLERS:

1.3.1 DOUBLE DATA RATE-SYNCHRONOUS DYNAMIC

Fig 1.4: Data transfer rate in SDRAM Family

DEPT OF ECE, SBIT, KMM 7

DDR DIGITAL PULSE

DEPT OF ECE, SBIT, KMM 8

DEPT OF ECE, SBIT, KMM 9

COMPARISION OF DDR1, DDR2 AND DDR3

1.4 MEMORY TYPES

1.4.1 STATIC RANDOM ACCESS MEMORY

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Static random access memory uses multiple transistors, typically

1.4.2 DYNAMIC RANDOM ACCESS MEMORY

Dynamic random access memory has memory cells with a paired

A memory chip rating of 70ns means that it takes 70 nanoseconds

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capacitor in a dynamic RAM memory cell is like a leaky bucket. It needs

Memory cells are etched onto a silicon wafer in an array of

These circuits perform functions such as:

 Identifying each row and column (row address select and

 Keeping track of the refresh sequence (counter)

 Reading and restoring the signal from a cell (sense

 Telling a cell whether it should take a charge or not (write

Other functions of the memory controller include a series of tasks

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DRAM consists of micro capacitors, while SRAM consists of off/on

1.4.3 CONTENT-ADDRESSABLE MEMORY (CAM)

1.5 ORGANIZATION OF THESIS:

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2.1 INTRODUCTION TO VERILOG:

For simulating a design, it is expected that all leaves of the

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environments exist that provide simulation, fault simulation, formal

Hardware description languages such as Verilog differ from

The designers of Verilog wanted a language with syntax similar to

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compatible operator precedence. Syntactic differences include variable