I C-Master Core Specification: Author: Richard Herveille
I C-Master Core Specification: Author: Richard Herveille
I C-Master Core Specification: Author: Richard Herveille
I C-Master Core
Specification
Author: Richard Herveille
[email protected]
Rev. 0.9
July 3, 2003
This page has been intentionally left blank
Revision History
1
Introduction
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of
data exchange between devices. It is most suitable for applications requiring occasional
communication over a short distance between many devices. The I2C standard is a true
multi-master bus including collision detection and arbitration that prevents data
corruption if two or more masters attempt to control the bus simultaneously.
Only 100Kbps and 400Kbps modes are supported directly. For High speed special IOs
are needed. If these IOs are available and used, then High speed is also supported.
FEATURES
• Compatible with Philips I2C standard
• Multi Master Operation
• Software programmable clock frequency
• Clock Stretching and Wait state generation
• Software programmable acknowledge bit
• Interrupt or bit-polling driven byte-by-byte data-transfers
• Arbitration lost interrupt, with automatic transfer cancelation
• Start/Stop/Repeated Start/Acknowledge generation
• Start/Stop/Repeated Start detection
• Bus busy detection
• Supports 7 and 10bit addressing mode
• Operates from a wide range of input clock frequencies
• Static synchronous design
• Fully synthesizable
2
IO ports
2.1 Core Parameters
Parameter Type Default Description
ARST_LVL Bit 1’b0 Asynchronous reset level
2.1.1 ARST_LVL
The asynchronous reset level can be set to either active high (1’b1) or active low (1’b0).
The core features a WISHBONE RevB.3 compliant WISHBONE Classic interface. All
output signals are registered. Each access takes 2 clock cycles.
arst_i is not a WISHBONE compatible signal. It is provided for FPGA implementations.
Using [arst_i] instead of [wb_rst_i] can result in lower cell-usage and higher
performance, because most FPGAs provide a dedicated asynchronous reset path. Use
either [arst_i] or [wb_rst_i], tie the other to a negated state.
The I2C interface uses a serial data line (SDA) and a serial clock line (SCL) for data
transfers. All devices connected to these two signals must have open drain or open
collector outputs. Both lines must be pulled-up to VCC by external resistors.
The tri-state buffers for the SCL and SDA lines must be added at a higher hierarchical
level. Connections should be made according to the following figure:
scl_pad_i
scl_pad_o SCL
scl_padoen_o
sda_pad_i
sda_pad_o SDA
sda_padoen_o
For FPGA designs the compiler can automatically insert these buffers using the following
VHDL code:
Verilog code:
3
Registers
3.1 Registers list
Name Address Width Access Description
PRERlo 0x00 8 RW Clock Prescale register lo-byte
PRERhi 0x01 8 RW Clock Prescale register hi-byte
CTR 0x02 8 RW Control register
TXR 0x03 8 W Transmit register
RXR 0x03 8 R Receive register
CR 0x04 8 W Command register
SR 0x04 8 R Status register
The core responds to new commands only when the ‘EN’ bit is set. Pending commands
are finished. Clear the ‘EN’ bit only when no transfer is in progress, i.e. after a STOP
command, or when the command register has the STO bit set. When halted during a
transfer, the core can hang the I2C bus.
The STA, STO, RD, WR, and IACK bits are cleared automatically. These bits are always
read as zeros.
Please note that all reserved bits are read as zeros. To ensure forward compatibility, they
should be written as zeros.
4
Operation
4.1 System Configuration
The I2C system uses a serial data line (SDA) and a serial clock line (SCL) for data
transfers. All devices connected to these two signals must have open drain or open
collector outputs. The logic AND function is exercised on both lines with external pull-up
resistors.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line
on a byte-by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for
each data bit with the MSB being transmitted first. An acknowledge bit follows each
transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA
line may be changed only during the low period of SCL and must be held stable during
the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a
command (see START and STOP signals).
different transfer direction (e.g. from writing to a device to reading from a device)
without releasing the bus.
The core generates a START signal when the STA-bit in the Command Register is set
and the RD or WR bits are set. Depending on the current status of the SCL line, a START
or Repeated START is generated.
Note: The core supports 10bit slave addresses by generating two address transfers. See
the Philips I2C specifications for more details.
The core treats a Slave Address Transfer as any other write action. Store the slave
device’s address in the Transmit Register and set the WR bit. The core will then transfer
the slave address on the bus.
If the master, as the receiving device, does not acknowledge the slave, the slave releases
the SDA line for the master to generate a STOP or Repeated START signal.
To write data to a slave, store the data to be transmitted in the Transmit Register and set
the WR bit. To read data from a slave, set the RD bit. During a transfer the core set the
TIP flag, indicating that a Transfer is In Progress. When the transfer is done the TIP flag
is reset, the IF flag set and, when enabled, an interrupt generated. The Receive Register
contains valid data after the IF flag has been set. The user may issue a new write or read
command when the TIP flag is reset.
5
Architecture
The I2C core is built around four primary blocks; the Clock Generator, the Byte
Command Controller, the Bit Command Controller and the DataIO Shift Register.
All other blocks are used for interfacing or for storing temporary values.
Prescale clock
Register generator
WISHBONE
Interface Command
Register Byte Bit SCL
Command Command
Controller Controller SDA
Status
Register
Transmit
Register DataIO
Shift
Receive Register
Register
generation of a START signal, the reading of a byte from the slave device, and the
generation of a STOP signal. It does this by dividing each byte operation into separate
bit-operations, which are then sent to the Bit Command Controller.
Idle state
Read / Write No
bit set ?
Yes
START
bit set ?
No
Yes
START signal state
START No
generated ?
Yes
Read
bit set ?
No
Yes
READ state WRITE state
Byte No Byte No
Read ? Written ?
Yes Yes
ACK state
A B C D
Start SCL
SDA
SDA
Stop SCL
SDA
Write SCL
SDA
Read SCL
SDA
6
Programming examples
Example 1
Write 1 byte of data to a slave.
I2C Sequence:
1) generate start command
2) write slave address + write bit
3) receive acknowledge from slave
4) write data
5) receive acknowledge from slave
6) generate stop command
Commands:
1) write 0xA2 (address + write bit) to Transmit Register, set STA bit, set WR bit.
-- wait for interrupt or TIP flag to negate --
2) read RxACK bit from Status Register, should be ‘0’.
write 0xAC to Transmit register, set STO bit, set WR bit.
-- wait for interrupt or TIP flag to negate --
3) read RxACK bit from Status Register, should be ‘0’.
SCL
Please note that the time for the Interrupt Service Routine is not shown here. It is
assumed that the ISR is much faster then the I2C cycle time, and therefore not visible.
Example 2
Read a byte of data from an I2C memory device.
I2C sequence:
1) generate start signal
2) write slave address + write bit
3) receive acknowledge from slave
4) write memory location
5) receive acknowledge from slave
6) generate repeated start signal
7) write slave address + read bit
8) receive acknowledge from slave
9) read byte from slave
10) write no acknowledge (NACK) to slave, indicating end of transfer
11) generate stop signal
Commands:
1) write 0x9C (address + write bit) to Transmit Register, set STA bit, set WR bit.
-- wait for interrupt or TIP flag to negate --
2) read RxACK bit from Status Register, should be ‘0’.
write 0x20 to Transmit register, set WR bit.
-- wait for interrupt or TIP flag to negate --
3) read RxACK bit from Status Register, should be ‘0’.
write 0x9D (address + read bit) to Transmit Register, set STA bit, set WR bit.
-- wait for interrupt or TIP flag to negate --
4) set RD bit, set ACK to ‘1’ (NACK), set STO bit
SCL
SCL
Please note that the time for the Interrupt Service Routine is not shown here. It is
assumed that the ISR is much faster then the I2C cycle time, and therefore not visible.
Appendix A
Synthesis results
Synthesis tool: Synplify Pro