EXPERIMENT NO 2.

Simplifying Logic Circuits: Universal Logic Gates

Learning Objectives:
•To apply De Morgan’s theorem in NAND and NOR gates.
•To differentiate the implementation of basic logic gates using the universal gates NAND and NOR
•To introduce Karnaugh Map in simplifying logic circuit design
Materials
Logisim, Logic Simulator
Gates: NAND, NOR, AND, OR, NOT gates
Input: 1-bit input pin
Output: 1-bit output pin
Procedures:
1 Refer to the video lecture for the discussion of the concept of universal logic gates.
2 Simulate the NAND implementation of INVERTER circuit in Logisim
2.1 Create a project and name it Exp2
2.2 Add a circuit and name it NAND-INV. At the Main Menu, click Project, then Add Circuit as show

2.3 From the toolbox at the left side of the window, click Gates. Choose the NAND gate symbol and p
Modify the number of inputs to 2 as shown in the image. At the same property toolbox, change the

2.5 From the top, choose the input pin as shown in the image. Change the label in the Property as show

2.6 At the same menu, choose the output pin as shown below. Change the Label to "O"
 2.7 Wire the input pins to the inputs of the gate and the output pin to the output pin of the gate.
2.8 Refer to the truth table and simulate the output using the inputs.
3 Simulate the NAND implementation of logic AND in Logisim
3.1 Use the project Exp2
3.2 Add a circuit and name it NAND-AND. At the Main Menu, click Project, then Add Circuit as sho

3.3 From the toolbox at the left side of the window, click Gates. Choose the NAND gate symbol and p
Modify the number of inputs to 2 as shown in the image. At the same property toolbox, change the

3.4 From the top, choose the input pin as shown in the image. Change the label to A.

3.5 From the top, add another input pin as shown in the image. Change the label to B.

3.6 At the same menu, choose the output pin as shown below. Change the Label to "O"

3.7 Add another NAND gate and connect as shown.

Label it accordingly.
 3.8 Wire the input pins to the inputs of the gate and the output pin to the output pin of the gate.
3.9 Refer to the truth table and simulate the output using the inputs.
4 Simulate the NAND implementation of logic OR in Logisim
4.1 Use the project Exp2
4.2 Add a circuit and name it NAND-AND. At the Main Menu, click Project, then Add Circuit as sho

4.3 From the toolbox at the left side of the window, click Gates. Choose the NAND gate symbol and p
Modify the number of inputs to 2 as shown in the image. At the same property toolbox, change the

4.4 From the top, choose the input pin as shown in the image. Change the label to A.

4.5 Add another NAND gate that will serve as INVERTER. Therefore, both inputs of the NAND are c
4.6 Connect the NAND (A.A)' to the one of th input of NAND (A.B )'
4.7 From the top, add another input pin as shown in the image. Change the label to B.

4.5 Add another NAND gate that will serve as INVERTER. Therefore, both inputs of the NAND are c
4.6 Connect the NAND (A.A)' to the one of th input of NAND (A.B )'
4.6 At the same menu, choose the output pin as shown below. Change the Label to "O"
4.8 Wire the input pins to the inputs of the gate and the output pin to the output pin of the gate.
4.9 Refer to the truth table and simulate the output using the inputs.
5 Simulate the NOR implementation of INVERTER circuit in Logisim
5.1 Use the project Exp2
 5.2 Add a circuit and name it NOR-INV. At the Main Menu, click Project, then Add Circuit as shown

5.3 From the toolbox at the left side of the window, click Gates. Choose the NOR gate symbol and pla
Modify the number of inputs to 2 as shown in the image. At the same property toolbox, change the

5.4 From the top, choose the input pin as shown in the image. Change the label in the Property as show

5.5 At the same menu, choose the output pin as shown below. Change the Label to "O"

5.6 Wire the input pins to the inputs of the gate and the output pin to the output pin of the gate.
5.7 Refer to the truth table and simulate the output using the inputs.
6 Simulate the NOR implementation of logic OR in Logisim
6.1 Use the project Exp2
6.2 Add a circuit and name it NOR-OR. At the Main Menu, click Project, then Add Circuit as shown i

6.3 From the toolbox at the left side of the window, click Gates. Choose the NAND gate symbol and p
Modify the number of inputs to 2 as shown in the image. At the same property toolbox, change the
 6.4 From the top, choose the input pin as shown in the image. Change the label to A.

6.5 From the top, add another input pin as shown in the image. Change the label to B.

6.6 At the same menu, choose the output pin as shown below. Change the Label to "O"

6.7 Add another NOR gate and connect as shown.

Label it accordingly.

6.8 Wire the input pins to the inputs of the gate and the output pin to the output pin of the gate.
6.9 Refer to the truth table and simulate the output using the inputs.
7 Simulate the NOR implementation of logic AND in Logisim
7.1 Use the project Exp2
7.2 Add a circuit and name it NOR-AND. At the Main Menu, click Project, then Add Circuit as show

7.3 From the toolbox at the left side of the window, click Gates. Choose the NAND gate symbol and p
Modify the number of inputs to 2 as shown in the image. At the same property toolbox, change the
 7.4 From the top, choose the input pin as shown in the image. Change the label to A.

7.5 Add another NAND gate that will serve as INVERTER. Therefore, both inputs of the NAND are c
7.6 Connect the NAND (A.A)' to the one of th input of NAND (A.B )'
7.7 From the top, add another input pin as shown in the image. Change the label to B.

7.8 Add another NAND gate that will serve as INVERTER. Therefore, both inputs of the NAND are c
7.9 Connect the NAND (A.A)' to the one of the input of NAND (A.B )'
7.A At the same menu, choose the output pin as shown below. Change the Label to "O"
7.B Wire the input pins to the inputs of the gate and the output pin to the output pin of the gate.
7.C Refer to the truth table and simulate the output using the inputs.
8 Video record the NAND and NOR implementations of the basic gate with the basic gate beside it..
9 Upload the file in your drive (google or onedrive) using the file format: SurnameFirstName-EXP2-Proc5
10 Map the Long Equation of the given example in the video lecture to the GATES given in the GATES sprea
11 Map the simplified Equation of the given example in the video lecture to the GATES given in the GATES
12 Answer the questions in answer in the EXP2 spreadsheet.
13 Write the challenges you have encountered in performing experiment and what you have done to resolve it
You will also get to assess your peer/classmates Discussion using the following rubric:
9.1 How did the discussion make use of the behavior of the logic gates?
9.2 How did the discussion resolve your encountered challenge?
9.3 Did the discussion made the function of logic gates more understandable?
14 Write your Conclusion in the Blog link located at the experiment module. The blog will conclude the achie
15 Upload this excel file to the BB exam link.
 2.
ersal Logic Gates

al gates NAND and NOR

t, then Add Circuit as shown in Fig. 2.2

e NAND gate symbol and place in the workspace.

roperty toolbox, change the Label to (A.A)'

abel in the Property as shown.

Label to "O"
tput pin of the gate.

ct, then Add Circuit as shown in Fig. 2.2

e NAND gate symbol and place in the workspace.

roperty toolbox, change the Label to (A.B)'

Label to "O"
tput pin of the gate.

ct, then Add Circuit as shown in Fig. 2.2

e NAND gate symbol and place in the workspace.

roperty toolbox, change the Label to (A.B)'

h inputs of the NAND are connected to input pin A. Label the NAND gate (A.A)'

h inputs of the NAND are connected to input pin A. Label the NAND gate (B.B)'

Label to "O"
tput pin of the gate.
then Add Circuit as shown in Fig. 2.2

e NOR gate symbol and place in the workspace.

roperty toolbox, change the Label to (A.A)'

abel in the Property as shown.

Label to "O"

tput pin of the gate.

hen Add Circuit as shown in Fig. 2.2

e NAND gate symbol and place in the workspace.

roperty toolbox, change the Label to (A.B)'
Label to "O"

tput pin of the gate.

, then Add Circuit as shown in Fig. 2.2

e NAND gate symbol and place in the workspace.

roperty toolbox, change the Label to (A.B)'
h inputs of the NAND are connected to input pin A. Label the NAND gate (A.A)'

h inputs of the NAND are connected to input pin A. Label the NAND gate (B.B)'

Label to "O"
tput pin of the gate.

asic gate beside it..

eFirstName-EXP2-Proc5
given in the GATES spreadsheet.
ATES given in the GATES spreadsheet.

you have done to resolve it in the Discussion link located in the experiment module.

log will conclude the achievement of the learning objectives.

 Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 1 1 1 0 0
WIRE WIRE

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE
 WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE

WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE

WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE
 WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE
 WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 0 0
WIRE WIRE

WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE

WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE
 WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE
 WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE

WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE

WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE
 WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE
 Experiment N
UNIVERSAL LOGI
Learning Objectives TOTAL
To apply De Morgan’s theorem in NAND and NOR gates.
To differentiate the implementation of basic logic gates using the universal gates NAND and NOR
To introduce Karnaugh Map in simplifying logic circuit design
Experiment Question and Answer
INSTRUCTION: Answer the following question as required.
1 From the video lecture Design Problem, map the SOP function in GATES spreadsheet
2 From No.1 SOP function, implement the circuit using NAND and the GATES spreadsheet
3 From No.1 SOP function, implement the circuit using NOR and the GATES spreadsheet
4 Given the truth table below write the space at the rightmost the simplified equation
a
b
c
d
e
f
g

5.Choose from the choic

a
b
c
d
e
f
g

CHOICES
1 5

2 6
 3 7

6 Build the circuit of the simplified equation in Question No 5

7 Given the function F(W,X,Y,Z) = ∑(1,3,4,6,8,9,10,11,13,15), which type of canonical
form can be derived?
8 What will be the canonical expression of function given in No.7 W'X'Y'Z+W'X'YZ+W'XY'Z'+W
9 Derive the complementing standard form of Question No7 F(W,X,Y,Z)=(W+X+Y+Z
10 Using K-Map derive the simplified POS of Question No 7 Color Code
Show THE K-MAP solution at the space provided Equation
Use colors to group YZ Color Code
POS OO O1 11 1O Equation
WX OO O O Color Code
O1 O O Equation
11 O O POS
1O

B'D'+A
'B'C+A
BD+A
11 Given the K-Map, derive the canonical SOP BC
CD
SOP OO O1 11 1O minterm of Group A
AB OO 1 O 1 1 minterm of Group B
O1 O O O O minterm of Group C
11 O 1 1 1 minterm of Group D
1O 1 O O 1

12 Given the following equation, derive the simplified canonical form, Logism Circuit and GATES connection
F(X,Y,Z)= XY+X'Z+Y'
 Experiment No 2
VERSAL LOGIC GATES
32
and NOR

Write the Equation here

A'BC+ABC+ABC'+ABC
((((A'BC)')')')((((ABC)')')')((((ABC')')')')((((ABC)')')')
(((A+B'+C')' + (A'+B'+C)'+(A'+B'+C)'+(A'+B'+C')')')'

B'D' + C + BD + A FORMAT: SPACE BEFORE & AFTER " + "

B' + C'D' + C D FORMAT: SPACE BEFORE & AFTER " + "
C' + D + B FORMAT: SPACE BEFORE & AFTER " + "
B'D' + B'C + CD' + BC'D + A FORMAT: SPACE BEFORE & AFTER " + "
B'D' + CD' FORMAT: SPACE BEFORE & AFTER " + "
C'D' + BC' + BD' + A FORMAT: SPACE BEFORE & AFTER " + "
BC' + BD' + A FORMAT: SPACE BEFORE & AFTER " + "

.Choose from the choices below the K-Map of output a-g

5
7
1
6
3
4
2

PASTE THE LOGISIM CIRCUIT HERE

 SOP

X'Y'Z+W'X'YZ+W'XY'Z'+W'XYZ'+WX'Y'Z'+WX'Y'Z+WX'YZ'+WX'YZ+WXY'Z+WXYZ'
F(W,X,Y,Z)=(W+X+Y+Z)(W+X+Y'+Z)(W+X'+Y+Z')(W+X'+Y'+Z')(W'+X'Y+Z)
green
(W+X+Z)
yellow
(W+X+Z')
red
(W'+X'+Z)
(W+X+Z)(W+X+Z')(W'+X'+Z)

A'BD'
A'BC
ABD
ABC

t and GATES connection

XYZ + XYZ' + X'YZ + X'Y'Z + XY'Z + X'Y'Z'+ XY'Z'
Paste Circuit Here
 A'BC+ABC+ABC'+ABC
Output INPUTS
WIRE WIRE A B AB C
I/O VCC 0 0 0 1 I/O VCC 1 1 1 1 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 1 0 1 0 1 0 GND I/O 0 1 0 0 1 0
WIRE A A' B B' C C' WIRE A' B A'B C A'BC

Output INPUTS
WIRE WIRE A B AB C'
I/O VCC 0 0 0 1 I/O VCC 1 1 1 1 0
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 1 1 1 1 1 1
WIRE WIRE A B AB C ABC

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE
ABC WIRE ABC ABC ABC +A'BC +A'BC + ABC' + WIRE
1 I/O VCC 1 1 1 1 0 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 0 0 1 0 1 GND I/O 0 1 1 1
WIRE A'BCABC' A'BC + ABC' WIRE

ABC' WIRE WIRE

0 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE

WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE
 WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE
 WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 0 0
WIRE WIRE

WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE

WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE
 WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE
 WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE

WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE

WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE
 WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE
 ((((A'BC)')')')((((ABC)')')')((((ABC')')')')((((ABC)')')')
Output INPUTS
WIRE (A'BC)'A'BC (ABC)' ABC (ABC')'ABC' WIRE A' B C
I/O VCC 0 1 0 1 1 0 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 1 0 1 0 1 0 GND I/O 1 1 1 1 1 1
WIRE A A' B B' C C' WIRE A B AB C ABC

Output INPUTS
WIRE WIRE A B AB C'
I/O VCC 0 0 0 1 I/O VCC 1 1 1 1 0
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE
C')')')')((((ABC)')')')

A'BC WIRE WIRE (A'BC)(ABC)'((A'BC)

1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 0 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 1 1 0 1
WIRE WIRE ((A'BC)((ABC')((((A'BC)')')'(((ABC)')')'(((ABC'
NAND

ABC' WIRE WIRE

0 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE

WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE
 WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE
 (ABC')(ABC)'((ABC')')'((ABWIRE WIRE
1 0 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 0 0
(((A'BC)')')'(((ABC)')')'(((ABC')')')'(((ABWIRE WIRE

WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE

WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE
 WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE
 WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE

WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE

WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE
 WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE
 (((A+B'+C')' + (A'+B'+C)'+(A'+B'+C)'+(A'+B'+C')')')'
Output INPUTS
WIRE (A+B'+C
A+B'+(A'+B'+A'+B'+C WIRE
I/O VCC 0 1 0 1 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 1 0 1 0 1 0 GND I/O 0 1 0 0 0
WIRE A A' B B' C C' WIRE

Output INPUTS
WIRE (A'+B'+A'+B'+C (A'+B'+A'+B'+C' WIRE
I/O VCC 0 1 0 1 0 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE
+C)'+(A'+B'+C')')')'

WIRE A B' A+B' C' A+B'+C' WIRE

1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 0 0 0 1 1 GND I/O 0 1 1 1
WIRE A' B' A'+B' C A'+B'+C WIRE

WIRE A' B' A'+B' C A'+B'+C WIRE

1 I/O VCC 0 0 0 0 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 0 0 0 0 0 GND I/O 0 1 1 1
WIRE A' B' A'+B' C' A'+B'+C' WIRE

WIRE (A+B'+(A'+B'+C)' (A'+B'(A+B'+C')' + (A' WIRE

1 I/O VCC 0 0 0 0 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE (A+B'+(A'+B'+C')' WIRE
DesignProbNOR
 WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE
 WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 0 0
WIRE WIRE

WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE

WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE
 WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE
 WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE

WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE

WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE
 WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE