Assignment 1

Question 1
a. Distinguish between combinational logic and sequential logic. [2]
Combinational circuits are defined as the time independent circuits which do not
depends upon previous inputs to generate any output are termed as combinational
circuits. Combinational circuits don’t have capability to store any state and so speed is
fast. Examples of combinational logic are Encoder, Decoder, Multiplexer, De-multiplexer.
Block diagram of combinational circuit:

While Sequential circuits are those which are dependent on clock cycles and depends
on present as well as past inputs to generate any output. Sequential circuits have
capability to store any state or to retain earlier state and so speed is slow. Examples –of
sequential logic circuits are Flip-flops, Counters
Block diagram of Sequential circuit:

b. What do you understand by the term de-multiplexing? [2]

The process of getting information from one input and transmitting the same over one of
many outputs is called demultiplexing.
c. Which of the shift registers mode can be used as a de-multiplexer? Describe how it
achieves the de-multiplexing function. [3]
Serial In - Parallel Out Shift Registers : data bits are entered serially, the register is first
cleared, forcing all four outputs to zero. The input data is then applied sequentially to the
D input of the first flip-flop on the left (FF0). During each clock pulse, one bit is
transmitted from left to right. The difference is the way in which the data bits are taken
out of the register. Once the data are stored, each bit appears on its respective output line,
and all bits are available simultaneously
 A serial to parallel converter is the one needed for reconstructing the parallel data from
the incoming serial data stream. In this technique, serial data from the incoming serial
data stream is given as the input to the DEMUX at regular intervals. A counter is attached
to the control input of the demux. This counter directs the data signal output of the demux
where these data signals are stored. When all data signals have been stored. The output of
the demux can be retrieved and read out in parallel. Henceforth the Serial in – Parallel
Out Shift Register is the ideal shift register for a demultiplexer.
d. Give 2 factors that determines the length of temporary storage period of data bits in
a shift register. [2]
- The number of flip flops in the chain determines the length of the shift register.
- Clock frequnce.

e. State the shift register which offers the longest period of data storage. [1]
FIFO Shift register
f. Design a 4 – stage shift register required in (e) above. [6]
g. A clock pulse connected to a 4 - stage SISO shift register has a period of 15 x 10-3
seconds. Calculate the total temporary storage time that can be achieved with this
shift register.[4]

Question 2

a. Briefly describe the function of a decoder and give one of its practical applications.
[4]
The decoder is an electronic device that is used to convert digital signal to an analogue
signal. It allows single input line and produces multiple output lines.  The decoders are
used in many communication projects that are used to communicate between two
devices. The decoder allows N- inputs and generates 2 power N-numbers of outputs.
For example, if we give 3 inputs that will produce 4 outputs by using 4 by 2 decoder.

b. Design a combinational logic circuit to decode a binary code 11001011. [4]

c. In a particular digital electronic system an encoder is required to generate a correct
3 bit binary code for any base 10 number between 1 and 7.
i. Deduce a truth table which can summarize the operation of the required
encoder. [4]
No INPUTS OUTPUTS
D7 D6 D5 D4 D3 D2 D1 Y3 Y2 Y1
1 0 0 0 0 0 0 1 0 0 1
2 0 0 0 0 0 1 0 0 1 0
3 0 0 0 0 1 0 0 0 1 1
4 0 0 0 1 0 0 0 1 0 0
5 0 0 1 0 0 0 0 1 0 1
6 0 1 0 0 0 0 0 1 1 0
7 1 0 0 0 0 0 0 1 1 1

ii. Determine the corresponding Boolean function for each of the outputs in you
truth table [3]
- Y2 = D4 + D5 + D6 + D7
- Y1 = D2 + D3 + D6 + D7
- Y0 = D1 + D3 + D5 + D7

iii. Hence design a combinational logic circuit of the encoder. [5]

Question 3
a. Distinguish between digital and analogue signals. [2]
Analog Digital

An analog signal is a continuous signal Digital signals are time separated signals which
that represents physical measurements. are generated using digital modulation.

It is denoted by sine waves It is denoted by square waves

 It uses a continuous range of values Digital signal uses discrete 0 and 1 to represent
that help you to represent information. information.

Temperature sensors, FM radio signals, Computers, CDs, DVDs are some examples of
Photocells, Light sensor, Resistive Digital signal.
touch screen are examples of Analog
signals.

0 time 0 time

. Analogue signal Digital signal

A B C A B C AB+ C A+ BC ( AB+ C).( A+ BC )

0 0 0 1 1 1 1 1 1
0 0 1 1 1 0 1 1 1
0 1 0 1 0 1 1 1 1
0 1 1 1 0 0 0 1 0
1 0 0 0 1 1 1 1 1
1 0 1 0 1 0 0 0 0
1 1 0 0 0 1 1 0 0
1 1 1 0 0 0 0 0 0
b. Apply de Morgen’s theorems to verify the following Boolean expression:

= [5]
RHS
LHS
 A B C A B C ( A+ B )C A (B+C ) C ( A+ B )+ A (B+C )
0 0 0 1 1 1 1 1 1
0 0 1 1 1 0 0 1 1
0 1 0 1 0 1 1 1 1
0 1 1 1 0 0 0 0 0
1 0 0 0 1 1 1 0 1
1 0 1 0 1 0 0 0 0
1 1 0 0 0 1 0 0 0
1 1 1 0 0 0 0 0 0

LHS ¿ RHS

c. Design a combinational logic circuit of an encoder that can encode all even numbers
between 7 and 19 to their binary form. [13]

No INPUTS OUTPUTS
D7 D6 D5 D4 D3 D2 D1 Y3 Y2 Y1
8 0 0 0 0 0 0 1 0 0 1
10 0 0 0 0 0 1 0 0 1 0
12 0 0 0 0 1 0 0 0 1 1
14 0 0 0 1 0 0 0 1 0 0
16 0 0 1 0 0 0 0 1 0 1
18 0 1 0 0 0 0 0 1 1 0

Question 4
a. Convert the following:
i. 3B7D16 to decimal form. [3]
163 * 3 + 162 * B +161 *7 + 160 * D
12288 + 2816 +122 +13
= 15229

ii. 96510 to octal number system. [3]

 8 √ 965 120 r5
15 r0
1 r7
0 r1
= 17058

iii. 4768 to binary number system. [3]

4 7 6
100 111 110

= 1001111102

b. The diagram below is showing a combinational logic circuit.

i. Deduce a truth table that summarizes the operation of this circuit. [5]
A B C c A⊕ B (A⊕B).c (A⊕B) + c ((A⊕B).c ) + ((A⊕B) + c)
0 0 0 1 0 0 1 1
0 0 1 0 0 0 0 0
0 1 0 1 1 1 1 1
0 1 1 0 1 0 1 1
1 0 0 1 1 1 1 1
1 0 1 0 1 0 1 1
1 1 0 1 0 0 1 1
1 1 1 0 0 0 0 0

ii. Hence determine a simplified Boolean expression for this circuit. [6]
(A⊕B) + c
Or
((A⊕B).c ) + ((A⊕B) + c)
A
B
Q
C
Question 5
a. Which clocked flip flops would you use to design a shift register? Explain your
choice.[3]
The JK Flip-flop
The JK flip-flop is the most used of all the flip-flop designs because it avoids the combinations
with the input sequence of S = R = 1 as it is able to modify to achieve different switching
functions. In other words the JK flip-flop is often considered to be a universal device.
The beauty of the JK flip-flop is that when both “J” and “K” are HIGH at logic “1”, the flip-flop
toggles, that is changes from “0” to “1” or from “1” to “0” producing its own complement state.

From the above JK Flip-flop Circuit, If the J and K inputs are both HIGH, logic “1” then
the Q output will change state (Toggle) for as long as the clock input, (CLK) is HIGH. Thus the
output will be unstable creating a race-around problem with this basic JK circuit. This problem is
avoided by ensuring that the clock input is at logic “1” only for a very short time.

b. Give a shift register that can be used as a de-multiplexer. [1]

Serial-In Parallel-Out shift Register (SIPO
c. With the aid of a diagram, describe fully the operation of a 4 stage shift register you
gave in (b) above. [5]
d. Given that the clock pulses used in the shift register above has a period of 8 x 10 -3
seconds, calculate the temporary storage time that can be achieved with this shift
register. [4]
e. Give a detailed diagram of SR flip flop. With the aid of a truth table describe fully,
the operation of this flip flop.
[7]
SR Flip-flop:
SR flip flop can be built with NAND gate or with NOR gate. Either of them will have the
input and output complemented to each other. Here we are using NAND gates for
demonstrating the SR flip flop.
Whenever the clock signal is LOW, the inputs S and R are never going to affect the
output. The clock has to be high for the inputs to get active. Thus, SR flip-flop is a
controlled Bi-stable latch where the clock signal is the control signal. Again, this gets
divided into positive edge triggered SR flip flop and negative edge triggered SR flip-
flop. Thus, the output has two stable states based on the inputs which have been
discussed below.

Truth table of SR Flip-Flop:

CLK
INPUT OUTPUT
State

R
Clock S’ Q Q’
’

LOW x x 0 1

HIGH 0 0 0 1

HIGH 1 0 1 0
 HIGH 0 1 0 1

HIGH 1 1 1 0

 S-R Flip Flop using NAND Gate

The circuit of the S-R flip flop using NAND Gate and its truth table is shown
below.

S-R Flip Flop using NAND Gate

Like the NOR Gate S-R flip flop, this one also has four states. They are

S=1, R=0—Q=0, Q’=1

This state is also called the SET state.

S=0, R=1—Q=1, Q’=0

This state is known as the RESET state.
In both the states you can see that the outputs are just compliments of each
other and that the value of Q follows the compliment value of S.

S=0, R=0—Q=1, & Q’ =1 [Invalid]

If both the values of S and R are switched to 0 it is an invalid state because the
values of both Q and Q’ are 1. They are supposed to be compliments of each
other. Normally, this state must be avoided.

S=1, R=1—Q & Q’= Remember

If both the values of S and R are switched to 1, then the circuit remembers the
value of S and R in their previous state.