JOMO KENYATTA UNIVERSITY OF AGRICULTUE AND TECHNOLOGY

SCHOOL OF ELECTRICAL, ELECTRONIC AND INFORMATION ENGINEERING

DEPARTMENT OF ELECTRICAL ENGINEERING

CLASS: EEE B1
UNIT: EEE2305 (DIGITAL ELECTRONICS I)
TASK: LABORATORY REPORT 2
GROUP 6 MEMBERS:
S/N REGISTRATION NAME
NUMBER
1 ENE211-0007/2018 WAHOME TERESA
WAMUYU
2 ENE211-0032/2018 CHERUTOI KIPTALLAM
ALFRED
3 ENE211-0053/2018 FRANCIS EDMOND
OTIENO
4 ENE211-0155/2018 NYAWIRA JULIUS
MWANGI
5 ENE211-0272/2018 RONO ISAAC
KIPCHUMBA
 1. REPORT TITLE
Combinational Logic Circuits Design
2. OBJECTIVES
The following were the key aims of this laboratory experiment:
i. Use of Boolean algebra
ii. To minimize combinational logic circuits using Karnaugh maps
iii. To implement Boolean expressions into logic circuits
3. INTRODUCTION
It would prove daunting to describe the operation of a device based on natural language. While
truth tables can be employed to show the possible outputs for various input combinations, they
are not viable at certain levels of intricacy. For more complex problems, therefore, it is easy and
convenient to express a logical function using Boolean algebra.
Each input can be represented by a variable, say the alphabetical letters A, B, C, and D. The
same goes for outputs, which can be represented by letters like F or Y. The basic operands used
in Boolean expressions are the AND (logical multiplication), OR (logical addition) XOR
(exclusive logical addition), and NOT (logical complementation/inversion). The AND, OR, and
XOR operations can take two or more variables. Conversely, NOT takes a single Boolean
operand.
Fig. 1.0: AND Truth Table, Gate and Boolean Expression

Fig. 1.1: OR Gate, Expression and Truth Table

Fig. 1.2: The NOT Operation

There also exist universal logic gates namely the NAND and NOR gates. This approach was
employed successfully in the lab experiment detailed in this report. With an adequate knowledge
of universal gates, a basic logical function can be implemented with no need for the physical
basic gates. Other logic gates also include the exclusive OR (XOR) and the exclusive NOR
(XNOR) gates.
Fig. 1.3: Implementation of Basic Operations Using the Universal Gates

The AND operation is denoted by a dot such that Y=A∙ 𝐵 implies Y equals A “AND” B. More
often, an AND operation will be written without the dot so that it becomes Y=AB. The OR
operation involving three variables can be written as Y=A+B+C. This is read as Y equals A OR
B OR C. A NOT operation can be implied by an asterisk, a bar sign or an accent symbol on top
of the inverted variable. It’s common to find the bar symbol, which shall also be used to a great
degree in this report. As such, Y equals “B AND NOT A OR C AND NOT A AND NOT D” can
be easily seen as Y= 𝐵𝐴̅ + 𝐶𝐴̅𝐷 ̅.
By looking at a truth table and asking oneself “when is Y TRUE (logic 1), one can figure out the
corresponding rows. This approach will always give a Sum-of-Products (SOP) form of a Boolean
expression for a given combination of inputs. The function in the last part of the paragraph above
could be derived from a truth table and it’s a typical example of the Sum-of-Products (SOP) form
of Boolean expressions.
Prior to circuit implementation, a Boolean expression must be simplified using standard
methods. It is this simplified expression that is realized by use of logic gates. With the Boolean
expression in place, circuit implementation can be carried out using combinational logic circuits.
A combinational logic circuit is a circuit whose present outputs rely on the inputs at that instant
in time. As such, it has no memory capabilities. With the sequential logic counterparts, it is
possible to achieve the memory capabilities. Simply put, the output of a sequential logic circuit
depends on the present inputs together with previous inputs and/or outputs.
From the foregoing discussion, the design requirements for combinational logic circuits follow
that you need at least:
• A set of statements
• Boolean expressions
• Truth tables
Combinational Logic Circuit Design Process
To come up with a combinational logic circuit, the detailed process below could be followed:
1. Statement of the problem
Any given problem, say as expressed in natural language, can be written down and
understood. From here, the input and output variables must be thoroughly understood.
2. Derivation of a truth table
Once a problem is understood, the input and output variables should be related by means of a
truth table.
3. Derivation of Boolean expressions
After producing a relevant truth table, Boolean expressions must be obtained from it. This
implies an expression of the output in terms of the input variables so that the function is the
unsimplified version.
4. Simplification of Boolean Expressions
The original expressions must be minimized so as to use fewer gates. In effect, the costs of
design and power consumption are considerably lowered. It is also a fundamental step
because it increases circuit reliability. Simplification follows various approaches, which
include algebraic means and utilization of Karnaugh maps (K-Maps).
 5. Circuit Implementation
Once a minimized expression is obtained, the ultimate step is to realize it into a circuit using
available digital kits and components. AND-OR-NOT logic are applicable, just as the option
of universal gates is also viable.
4. EXPERIMENTAL PROCEDURE
This part covers the main apparatus used in the experiment together with a detailed outline of the
steps so involved.
Apparatus
• Logiator kit Model S1-850A
• Jumper wires
Procedure
i. The following function was given as derived from some process:
𝑌 = 𝐵̅ 𝐶 + 𝐴𝐶̅ + 𝐴𝐵𝐶̅ + 𝐴𝐶𝐷
ii. The truth table for the function was then drawn.
iii. The logic function in (i) was next simplified using Boolean algebra.
iv. The simplified Boolean expression in (ii) was obtained into a logic circuit.
v. The expression in the problem was further simplified using Karnaugh Map (K-Map)
method.
vi. The Boolean expression in (iv) was again implemented into a logic circuit.
vii. The procedure above was repeated with a NAND-NAND logic network.
5. RESULTS AND ANALYSIS

Truth Table for the Function Given

A B C D 𝐵̅ 𝐶 𝐴𝐶̅ 𝐴𝐵𝐶̅ 𝐴𝐶𝐷 Y
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0
0 0 1 0 1 0 0 0 1
0 0 1 1 1 0 0 0 1
0 1 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0 0
0 1 1 0 0 0 0 0 0
0 1 1 1 0 0 0 0 0
1 0 0 0 0 1 0 0 1
1 0 0 1 0 1 0 0 1
1 0 1 0 1 0 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 0 0 1 1 0 1
1 1 0 1 0 1 1 0 1
1 1 1 0 0 0 0 0 0
1 1 1 1 0 0 0 1 1
Algebraic Simplification

Y=B̅C+AC̅ +ABC̅ +ACD

= B̅C+AC̅ (1+B) +ACD
=B̅C+AC̅ +ACD
= B̅C+A (C̅ +CD)
= B̅C +A ((C̅ +C) (C̅+D)
= B̅C +A (C̅+D)
= B̅C +AC̅ +AD

Simplification Using K-Map Method

Simplifying using the Karnaugh map, the expression is written in standard Sum of Products
form.
Y= (A+A̅) B̅C (D+D̅) + A (B+B̅) C̅(D+D̅) + ABC̅(D+D̅) + A(B+B̅) CD
= AB̅CD +AB̅CD̅ + A̅B̅CD +A̅B̅CD̅ +ABC̅D + ABC̅D̅ +AB̅C̅D + AB̅C̅D̅ + ABC̅D + ABC̅D̅
+ABCD +AB̅CD
= AB̅CD + AB̅CD̅ + A̅B̅CD+ A̅B̅CD̅ + ABC̅D + ABC̅D̅ + AB̅C̅D AB̅C̅D̅ + ABCD

A̅B̅ A̅B AB AB̅ A̅B̅

C̅D̅ 0 0 1 1
C̅D 0 0 1 1
CD 1 0 1 1
CD̅ 1 0 0 1

Y = B̅C +AC̅ +AD

Observation from the Logiator
The LED switched ON to indicate a HIGH state of the output whenever the toggle switches
corresponded to each input combination in the truth table. For all the outputs indicating a LOW
(0), the LED remained OFF.
Logic Circuit Representation for the Simplified Expression

6. CONCLUSION
Use of both Boolean algebra and the Karnaugh map resulted in the same simplified expressions
which when implemented using the Logiator gave the same output. Furthermore, implementation
of the logic circuit using NAND gates alone gave the same output. The upside of utilizing a
NAND network is that it allowed implementation using a single integrated circuit. Otherwise, it
would have prompted use of different Integrated circuits with AND, NOT and OR gates. Thus,
the universal NAND network also saved on costs.

7. REFERENCES
(1) Maini, A.K. (2007). Digital Electronics: Principles, Devices and Applications. First
Edition. John Wiley & Sons Ltd.
(2) MIT Open Courseware (2021). Combinational Logic. Retrieved from:
https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-
computation-structures-spring-2017/c4/c4s1/