HT32F52231-41 52331-41 Datasheetv170

HT32F52231/HT32F52241
HT32F52331/HT32F52341
Datasheet
32-Bit Arm® Cortex®-M0+ Microcontroller,

up to 64 KB Flash and 8 KB SRAM with 1 MSPS ADC,
USART, UART, SPI, I2C, MCTM, GPTM, SCTM, BFTM,
SCI, CRC, RTC, WDT, and USB2.0 FS
Revision: V1.70 Date: October 11, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table of Contents
1 General Description................................................................................................. 6
2 Features.................................................................................................................... 7
Core........................................................................................................................................ 7
On-chip Memory..................................................................................................................... 7
Table of Contents
Flash Memory Controller – FMC............................................................................................. 7
Reset Control Unit – RSTCU.................................................................................................. 8
Clock Control Unit – CKCU..................................................................................................... 8
Power Management – PWRCU.............................................................................................. 8
External Interrupt/Event Controller – EXTI............................................................................. 9
Analog to Digital Converter – ADC......................................................................................... 9
I/O Ports – GPIO..................................................................................................................... 9
Motor Control Timer – MCTM............................................................................................... 10
PWM Generation and Capture Timers – GPTM................................................................... 10
Single Channel Generation and Capture Timers – SCTM.................................................... 11
Basic Function Timer – BFTM.............................................................................................. 11
Watchdog Timer – WDT........................................................................................................ 11
Real Time Clock – RTC........................................................................................................ 12
Inter-integrated Circuit – I2C................................................................................................. 12
Serial Peripheral Interface – SPI.......................................................................................... 12
Universal Synchronous Asynchronous Receiver Transmitter – USART............................... 13
Universal Asynchronous Receiver Transmitter – UART....................................................... 13
Smart Card Interface – SCI (HT32F52331/52341 only)....................................................... 14
Cyclic Redundancy Check – CRC........................................................................................ 14
Universal Serial Bus Device Controller – USB (HT32F52331/52341 only).......................... 15
Debug Support...................................................................................................................... 15
Package and Operation Temperature................................................................................... 15
3 Overview................................................................................................................. 16
Device Information................................................................................................................ 16
Block Diagram...................................................................................................................... 17
Memory Map......................................................................................................................... 18
Clock Structure..................................................................................................................... 21
4 Pin Assignment...................................................................................................... 22
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5 Electrical Characteristics...................................................................................... 32
Absolute Maximum Ratings.................................................................................................. 32
Recommended DC Operating Conditions............................................................................ 32
On-Chip LDO Voltage Regulator Characteristics.................................................................. 32
Power Consumption............................................................................................................. 33
Reset and Supply Monitor Characteristics............................................................................ 35
Table of Contents
External Clock Characteristics.............................................................................................. 36
Internal Clock Characteristics............................................................................................... 37
PLL Characteristics............................................................................................................... 37
Memory Characteristics........................................................................................................ 37
I/O Port Characteristics......................................................................................................... 38
ADC Characteristics............................................................................................................. 39
SCTM/GPTM/MCTM Characteristics.................................................................................... 40
I2C Characteristics................................................................................................................ 41
SPI Characteristics............................................................................................................... 42
USB Characteristics.............................................................................................................. 44
6 Package Information............................................................................................. 45
24-pin SSOP (150mil) Outline Dimensions........................................................................... 46
28-pin SSOP (150mil) Outline Dimensions........................................................................... 47
SAW Type 33-pin (4mm×4mm) QFN Outline Dimensions.................................................... 48
48-pin LQFP (7mm×7mm) Outline Dimensions.................................................................... 49
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List of Tables
Table 1. Features and Peripheral List....................................................................................................... 16
Table 2. Register Map .............................................................................................................................. 19
Table 3. HT32F52231/52241 Series Pin Assignment for 24/28SSOP, 33QFN, 48LQFP Package........... 28
Table 4. HT32F52331/52341 Series Pin Assignment for 33QFN, 48LQFP Package............................... 29
Table 5. HT32F52231/52241 Pin Description........................................................................................... 30
List of Tables
Table 6. HT32F52331/52341 Pin Description........................................................................................... 31
Table 7. Absolute Maximum Ratings......................................................................................................... 32
Table 8. Recommended DC Operating Conditions................................................................................... 32
Table 9. LDO Characteristics.................................................................................................................... 32
Table 10. HT32F52231/52241 Power Consumption Characteristics........................................................ 33
Table 11. HT32F52331/52341 Power Consumption Characteristics........................................................ 34
Table 12. VDD Power Reset Characteristics.............................................................................................. 35
Table 13. LVD/BOD Characteristics.......................................................................................................... 35
Table 14. High Speed External Clock (HSE) Characteristics.................................................................... 36
Table 15. Low Speed External Clock (LSE) Characteristics..................................................................... 36
Table 16. High Speed Internal Clock (HSI) Characteristics...................................................................... 37
Table 17. Low Speed Internal Clock (LSI) Characteristics........................................................................ 37
Table 18. PLL Characteristics................................................................................................................... 37
Table 19. Flash Memory Characteristics................................................................................................... 37
Table 20. I/O Port Characteristics............................................................................................................. 38
Table 21. ADC Characteristics.................................................................................................................. 39
Table 22. SCTM/GPTM/MCTM Characteristics........................................................................................ 40
Table 23. I2C Characteristics..................................................................................................................... 41
Table 24. SPI Characteristics.................................................................................................................... 42
Table 25. USB DC Electrical Characteristics............................................................................................ 44
Table 26. USB AC Electrical Characteristics............................................................................................. 44
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List of Figures
Figure 1. Block Diagram........................................................................................................................... 17
Figure 2. Memory Map.............................................................................................................................. 18
Figure 3. Clock Structure.......................................................................................................................... 21
Figure 4. HT32F52231/52241 24-pin SSOP Pin Assignment................................................................... 22
Figure 5. HT32F52231/52241 28-pin SSOP Pin Assignment................................................................... 23
List of Figures
Figure 6. HT32F52231/52241 33-pin QFN Pin Assignment..................................................................... 24
Figure 7. HT32F52231/52241 48-pin LQFP Pin Assignment................................................................... 25
Figure 8. HT32F52331/52341 33-pin QFN Pin Assignment..................................................................... 26
Figure 9. HT32F52331/52341 48-pin LQFP Pin Assignment................................................................... 27
Figure 10. ADC Sampling Network Model................................................................................................ 40
Figure 11. I2C Timing Diagrams................................................................................................................ 41
Figure 12. SPI Timing Diagrams – SPI Master Mode............................................................................... 42
Figure 13. SPI Timing Diagrams – SPI Slave Mode with CPHA=1........................................................... 43
Figure 14. USB Signal Rise Time and Fall Time and Cross-point Voltage (VCRS) Definition.................. 44
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1 General Description
The HOLTEK HT32F522x1/523x1 devices are high performance, low power consumption 32-
bit microcontrollers based around an Arm® Cortex®-M0+ processor core. The Cortex®-M0+ is a
next-generation processor core which is tightly coupled with Nested Vectored Interrupt Controller
(NVIC), SysTick timer, and including advanced debug support.
The devices operate at a frequency of up to 40MHz for HT32F52231/52241 and 48MHz for
General Description
HT32F52331/52341 with a Flash accelerator to obtain maximum efficiency. It provides up to
64KB of embedded Flash memory for code/data storage and 8 KB of embedded SRAM memory
for system operation and application program usage. A variety of peripherals, such as ADC, I2C,
USART, UART, SPI, MCTM, GPTM, SCTM, CRC-16/32, RTC, WDT, SCI, USB2.0 FS, SW-DP
(Serial Wire Debug Port), etc., are also implemented in the device series. Several power saving
modes provide the flexibility for maximum optimization between wakeup latency and power
consumption, an especially important consideration in low power applications.
The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control and so on.
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2 Features
Core
■■ 32-bit Arm® Cortex®-M0+ processor core
■■ Up to 40MHz operating frequency for HT32F52231/52241 or 48MHz for HT32F52331/52341
Features
■■ 0.93 DMIPS/MHz (Dhrystone v2.1)
■■ Single-cycle multiplication
■■ Integrated Nested Vectored Interrupt Controller (NVIC)
■■ 24-bit SysTick timer
The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area optimized,
low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb®
instruction sets; single-cycle I/O port; hardware multiplier and low latency interrupt respond time.
On-chip Memory
■■ Up to 64 KB on-chip Flash memory for instruction/data and options storage
■■ 8 KB on-chip SRAM
■■ Supports multiple boot modes
The Arm® Cortex®-M0+ processor accesses and debug accesses share the single external interface
to external AHB peripheral. The processor accesses take priority over debug accesses. The
maximum address range of the Cortex® -M0+ is 4 GB since it has a 32-bit bus address width.
Additionally, a pre-defined memory map is provided by the Cortex™-M0+ processor to reduce
the software complexity of repeated implementation by different device vendors. However, some
regions are used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+
Technical Reference Manual for more information. Figure 2 shows the memory map of the
HT32F52231/52241 and HT32F52331/52341 series of devices, including code, SRAM, peripheral,
and other pre-defined regions.
Flash Memory Controller – FMC

■■ Flash accelerator for maximum efficiency
■■ 32-bit word programming with In System Programming Interface (ISP) and In Application
Programming (IAP)
■■ Flash protection capability to prevent illegal access
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer
for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower
than the CPU, a wide access interface with a pre-fetch buffer and cache are provided for the Flash
Memory in order to reduce the CPU waiting time which will cause CPU instruction execution
delays. Flash Memory word program/page erase functions are also provided.
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Reset Control Unit – RSTCU

■■ Supply supervisor:
●● Power On Reset / Power Down Reset – POR/PDR
●● Brown-out Detector – BOD
●● Programmable Low Voltage Detector – LVD
The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an
APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
Features
A system reset resets the processor core and peripheral IP components with the exception of the
SW-DP controller. The resets can be triggered by an external signal, internal events and the reset
generators.
Clock Control Unit – CKCU

■■ External 4 to 16MHz crystal oscillator
■■ External 32,768 Hz crystal oscillator
■■ Internal 8MHz RC oscillator trimmed to ±2 % accuracy at 3.3V operating voltage and 25°C operating
temperature
■■ Internal 32 kHz RC oscillator
■■ Integrated system clock PLL
■■ Independent clock divider and gating bits for peripheral clock sources
The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low
Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock
Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers, APB clock divider and
gating circuitry. The AHB, APB and Cortex®-M0+ clocks are derived from the system clock (CK_
SYS) which can come from the HSI, HSE or PLL. The Watchdog Timer and Real Time Clock (RTC)
use either the LSI or LSE as their clock source.
Power Management – PWRCU

■■ Single VDD power supply: 2.0V to 3.6V
■■ Integrated 1.5V LDO regulator for CPU core, peripherals and memories power supply
■■ VDD power supply for RTC.
■■ Two power domains: VDD, 1.5 V
■■ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
Power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many
types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.
These operating modes reduce the power consumption and allow the application to achieve the best
trade-off between the conflicting demands of CPU operating time, speed and power consumption.
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External Interrupt/Event Controller – EXTI

■■ Up to 16 EXTI lines with configurable trigger source and type
■■ All GPIO pins can be selected as EXTI trigger source
■■ Source trigger type includes high level, low level, negative edge, positive edge, or both edge
■■ Individual interrupt enable, wakeup enable and status bits for each EXTI line
■■ Software interrupt trigger mode for each EXTI line
Features
■■ Integrated deglitch filter for short pulse blocking
The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate
a wake-up event or interrupt requests independently. Each EXTI line can also be masked
independently.
Analog to Digital Converter – ADC

■■ 12-bit SAR ADC engine
■■ Up to 1 Msps conversion rate
■■ Up to 12 external analog input channels
A 12-bit multi-channel ADC is integrated in the device. There are multiplexed channels, which
include 12 external analog signal channels and 2 internal channels which can be measured. If
the input voltage is required to remain within a specific threshold window, an Analog Watchdog
function will monitor and detect these signals. An interrupt will then be generated to inform the
device that the input voltage is not within the preset threshold levels. There are three conversion
modes to convert an analog signal to digital data. The ADC can be operated in one shot, continuous
and discontinuous conversion modes.
I/O Ports – GPIO

■■ Up to 40 GPIOs
■■ Port A, B, C are mapped as 16 external interrupts – EXTI
■■ Almost all I/O pins have a configurable output driving current.
There are up to 40 General Purpose I/O pins, GPIO, named from PA0 ~ PA15 to PC0 ~ PC7 for
the implementation of logic input/output functions. Each of the GPIO ports has a series of related
control and configuration registers to maximize flexibility and to meet the requirements of a wide
range of applications.
The GPIO ports are pin-shared with other alternative functions to obtain maximum functional
flexibility on the package pins. The GPIO pins can be used as alternative functional pins by
configuring the corresponding registers regardless of the input or output pins. The external
interrupts on the GPIO pins of the device have related control and configuration registers in the
External Interrupt Control Unit, EXTI.
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Motor Control Timer – MCTM

■■ One 16-bit up, down, up/down auto-reload counter
■■ 16-bit programmable prescaler allowing counter clock frequency division by any factor between
1 and 65536
■■ Input Capture function
■■ Compare Match Output
Features
■■ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
■■ Single Pulse Mode Output
■■ Complementary Outputs with programmable dead-time insertion
■■ Supports 3-phase motor control and hall sensor interface
■■ Break input to force the timer’s output signals into a reset or fixed condition
The Motor Control Timer consists of a single 16-bit up/down counter, four 16-bit CCRs (Capture/
Compare Registers), single one 16-bit counter-reload register (CRR), single 8-bit repetition counter
and several control/status registers. It can be used for a variety of purposes including measuring
the pulse widths of input signals or generating output waveforms such as compare match outputs,
PWM outputs or complementary PWM outputs with dead-time insertion. The MCTM is capable of
offering full functional support for motor control, hall sensor interfacing and brake input.
PWM Generation and Capture Timers – GPTM

■■ One 16-bit up, down, up/down auto-reload counter
1 and 65536
■■ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
■■ Encoder interface controller with two inputs using quadrature decoder
The General Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/Compare
Registers (CCRs), one 16-bit Counter Reload Register (CRR) and several control/status registers.
They can be used for a variety of purposes including general time measurement, input signal pulse
width measurement, output waveform generation such as single pulse generation, or PWM output
generation. The GPTM supports an Encoder Interface using a decoder with two inputs.
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Single Channel Generation and Capture Timers – SCTM

■■ One 16-bit up and auto-reload counter
■■ One channel for each timer
1 and 65536
Features
■■ PWM waveform generation with Edge-aligned
The Single-Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Register
(CCR), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be
used for a variety of purposes including general timer, input signal pulse width measurement or
output waveform generation such as single pulse generation or PWM output.
Basic Function Timer – BFTM

■■ One 32-bit compare/match count-up counter - no I/O control features
■■ One shot mode - counting stops after a match condition
■■ Repetitive mode - restart counter after a match condition
The Basic Function Timer is a simple count-up 32-bit counter designed to measure time intervals
and generate a one shot or repetitive interrupts. The BFTM operates in two functional modes,
repetitive or one shot mode. In the repetitive mode the BFTM restarts the counter when a compare
match event occurs. The BFTM also supports a one shot mode which forces the counter to stop
counting when a compare match event occurs.
Watchdog Timer – WDT

■■ 12-bit down counter with 3-bit prescaler
■■ Reset event for the system
■■ Programmable watchdog timer window function
■■ Register write protection function
The Watchdog Timer is a hardware timing circuit that can be used to detect system failures due
to software malfunctions. It includes a 12-bit count-down counter, a prescaler, a WDT delta value
register, WDT operation control circuitry and a WDT protection mechanism. If the software does
not reload the counter value before a Watchdog Timer underflow occurs, a reset will be generated
when the counter underflows. In addition, a reset is also generated if the software reloads the
counter when the counter value is greater than the WDT delta value. This means the counter must
be reloaded within a limited timing window using a specific method. The Watchdog Timer counter
can be stopped while the processor is in the debug mode. There is a register write protect function
which can be enabled to prevent it from changing the Watchdog Timer configuration unexpectedly.
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Real Time Clock – RTC

■■ 24-bit up-counter with a programmable prescaler
■■ Alarm function
■■ Interrupt and Wake-up event
The Real Time Clock, RTC, includes an APB interface, a 24-bit count-up counter, a control
register, a prescaler, a compare register and a status register. Most of the RTC circuits are located in
Features
the Backup Domain except for the APB interface. The APB interface is located in the VDD15 power
domain. Therefore, it is necessary to be isolated from the ISO signal that comes from the power
control unit when the VDD15 power domain is powered off, that is when the device enters the Power-
Down mode. The RTC counter is used as a wakeup timer to generate a system resume signal from
the Power-Down mode.
Inter-integrated Circuit – I2C

■■ Supports both master and slave modes with a frequency of up to 1MHz
■■ Provide an arbitration function and clock synchronization
■■ Supports 7-bit and 10-bit addressing modes and general call addressing
■■ Supports slave multi-addressing mode with maskable address
The I2C is an internal circuit allowing communication with an external I2C interface which is an
industry standard two line serial interface used for connection to external hardware. These two
serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2C module
provides three data transfer rates: (1) 100kHz in the Standard mode, (2) 400kHz in the Fast mode
and (3) 1MHz in the Fast plus mode. The SCL period generation register is used to setup different
kinds of duty cycle implementations for the SCL pulse.
The SDA line which is connected directly to the I2C bus is a bi-directional data line between the
master and slave devices and is used for data transmission and reception. The I 2C also has an
arbitration detect function and clock synchronization to prevent situations where more than one
master attempts to transmit data to the I2C bus at the same time.
Serial Peripheral Interface – SPI

■■ Supports both master and slave mode
■■ Frequency of up to (fPCLK/2)MHz for the master mode and (fPCLK/3)MHz for the slave mode
■■ FIFO Depth: 8 levels
■■ Multi-master and multi-slave operation
The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function
in both master and slave mode. The SPI interface uses 4 pins, which are the serial data input and
output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device
acts as a master device which controls the data flow using the SEL and SCK signals to indicate the
start of data communication and the data sampling rate. To receive a data byte, the streamed data
bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data
transmission is carried out in a similar way but in a reverse sequence. The mode fault detection
provides a capability for multi-master applications.
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Universal Synchronous Asynchronous Receiver Transmitter – USART

■■ Supports both asynchronous and clocked synchronous serial communication modes
■■ Asynchronous operating baud rate up to (fPCLK/16)MHz and synchronous operating rate up to
(fPCLK/8)MHz
■■ Full duplex communication
■■ Fully programmable serial communication characteristics including:
Features
●● Word length: 7, 8, or 9-bit character
●● Parity: Even, odd, or no-parity bit generation and detection
●● Stop bit: 1 or 2 stop bit generation
●● Bit order: LSB-first or MSB-first transfer
■■ Error detection: Parity, overrun, and frame error
■■ Auto hardware flow control mode – RTS, CTS
■■ IrDA SIR encoder and decoder
■■ RS485 mode with output enable control
■■ FIFO Depth: 8×9 bits for both receiver and transmitter
The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full
duplex data exchange using synchronous or asynchronous data transfer. The USART is used to
translate data between parallel and serial interfaces, and is commonly used for RS232 standard
communication. The USART peripheral function supports four types of interrupt including Line
Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt
and Time Out Interrupt. The USART module includes a transmitter FIFO, (TX_FIFO) and receiver
FIFO (RX_FIFO). The software can detect a USART error status by reading the Line Status
Register, LSR. The status includes the type and the condition of transfer operations as well as
several error conditions resulting from Parity, Overrun, Framing and Break events.
Universal Asynchronous Receiver Transmitter – UART

■■ Asynchronous serial communication operating baud-rate up to fPCLK/16MHz
■■ Full duplex communication
■■ Fully programmable serial communication characteristics including:
●● Word length: 7, 8, or 9-bit character
●● Parity: Even, odd, or no-parity bit generation and detection
●● Stop bit: 1 or 2 stop bit generation
●● Bit order: LSB-first or MSB-first transfer
■■ Error detection: Parity, overrun, and frame error
The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data
exchange using asynchronous transfer. The UART is used to translate data between parallel and
serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral
function supports Line Status Interrupt. The software can detect a UART error status by reading
the Line Status Register, LSR. The status includes the type and the condition of transfer operations
as well as several error conditions resulting from Parity, Overrun, Framing and Break events.
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Smart Card Interface – SCI (HT32F52331/52341 only)

■■ Supports ISO 7816-3 standard
■■ Character mode
■■ Single transmit buffer and single receive buffer
■■ 11-bit ETU (elementary time unit) counter
■■ 9-bit guard time counter
Features
■■ 24-bit general purpose waiting time counter
■■ Parity generation and checking
■■ Automatic character retry on parity error detection in transmission and reception modes
The Smart Card Interface is compatible with the ISO 7816-3 standard. This interface includes
Card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal
Timer Counters and corresponding control logic circuits to perform all the necessary Smart Card
operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication
with the external Smart Card. The overall functions of the Smart Card interface are controlled
by a series of registers including control and status registers together with several corresponding
interrupts which are generated to get the attention of the microcontroller for SCI transfer status.
Cyclic Redundancy Check – CRC

■■ Support CRC16 polynomial: 0x8005,
X16+X15+X2+1
■■ Support CCITT CRC16 polynomial: 0x1021,
X16+X12+X5+1
■■ Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7,
X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1
■■ Supports 1’s complement, byte reverse & bit reverse operation on data and checksum
■■ Supports byte, half-word & word data size
■■ Programmable CRC initial seed value
■■ CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit
data
■■ Supports PDMA to complete a CRC computation of a block of memory
The CRC calculation unit is an error detection technique test algorithm which is used to verify data
transmission or storage data correctness. A CRC calculation takes a data stream or a block of data
as its input and generates a 16- or 32-bit output remainder. Ordinarily, a data stream is suffixed by
a CRC code and used as a checksum when being sent or stored. Therefore, the received or restored
data stream is calculated by the same generator polynomial as described above. If the new CRC
code result does not match the one calculated earlier, then this means that the data stream contains
a data error.
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Universal Serial Bus Device Controller – USB (HT32F52331/52341 only)

■■ Complies with USB 2.0 full-speed (12 Mbps) specification
■■ On-chip USB full-speed transceiver
■■ 1 control endpoint (EP0) for control transfer
■■ 3 single-buffered endpoints for bulk and interrupt transfer
■■ 4 double-buffered endpoints for bulk, interrupt and isochronous transfer
Features
■■ 1,024 bytes EP-SRAM used as the endpoint data buffers
The USB device controller is compliant with the USB 2.0 full-speed specification. There is one
control endpoint known as Endpoint 0 and seven configurable endpoints. A 1024-byte SRAM
is used as the endpoint buffer. Each endpoint buffer size is programmable using corresponding
registers, which provides maximum flexibility for various applications. The integrated USB full-
speed transceiver helps to minimize the overall system complexity and cost. The USB functional
block also contains the resume and suspend feature to meet the requirements of low-power
consumption.
Debug Support
■■ Serial Wire Debug Port – SW-DP
■■ 4 comparators for hardware breakpoint or code / literal patch
■■ 2 comparators for hardware watchpoints
Package and Operation Temperature

■■ 24/28-pin SSOP, 33-pin QFN, 48-pin LQFP for HT32F52231/52241
■■ 33-pin QFN, 48-pin LQFP package for HT32F52331/52341
■■ Operation temperature range: -40°C to +85°C
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HT32F52231/HT32F52241/HT32F52331/HT32F52341
3 Overview
Device Information
Table 1. Features and Peripheral List
Peripherals HT32F52231 HT32F52241 HT32F52331 HT32F52341
Main Flash (KB) 32 63 32 63.5
Overview
Option Bytes Flash (KB) 1 1 0.5 0.5
SRAM (KB) 4 8 4 8
MCTM 1
GPTM 1
Timers
SCTM 4
BFTM 2
RTC 1
WDT 1
USB — 1
Communication
SPI 2
USART 1
UART 2
I2C 2
SCI (ISO7816-3) — 1
CRC-16/32 1
EXTI 16
12-bit ADC 1
Number of channels 12 Channels
GPIO Up to 40 Up to 38
CPU frequency Up to 40MHz Up to 48MHz
Operating voltage 2.0 V ~ 3.6 V
Operating temperature -40° C ~ +85° C
24/28-pin SSOP
Package 33-pin QFN, 48-pin LQFP
33-pin QFN, 48-pin LQFP
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Block Diagram
SWCLK SWDIO PA ~ PB[15:0]; PC[7:0] BOOT

AF AF
Powered by VDD15 VDD

POR
/PDR VSS
Flash Memory Flash
Overview
SW-DP
Interface Memory HSE XTALIN
AF
IO Port
GPIO 4 ~ 16 MHz XTALOUT
Cortex®-M0+
HSI
Processor FMC
Control Registers
CRC
CKCU/RSTCU
Control Registers 8 MHz
AHB
System
-16/32 USB
Control/Data
Peripherals CLDO
Registers
LDO
Clock and reset control

Bus Matrix
NVIC 1.5 V CAP.
SRAM BOD
SRAM
Controller LVD
Interrupt request
Powered by VDD
AHB to APB USB

Bridge Device PLL
HT32F52331/41 only
DP
AF
DM
Power control
TX, RX
AF
RTS/TXE USART
CTS/SCK
WDT
MOSI, MISO
AF
AF
TX, RX UART0
UART0~ 1 SPI1
SPI1~~00 SCK, SEL
SDA
AF
I2C0 ~ 1
AFIO SCL
AF
EXTI GPTM CH3 ~ CH0
CH0 ~CH2
AF
CH0N ~ CH2N MCTM BFTM0 ~ 1

CH3, BRK
APB
CLK, DIO SCTM0 ~

AF
SCTM0 ~ 3
AF
DET SCI SCTM3
HT32F52331/41 only
AF
RTC RTCOUT
ADC_IN0 12-bit
AF
ADC
...
ADC_IN11
SAR ADC VDD
PWRCU VSS
AF
LSI LSE WAKEUP

VDDA 32 kHz 32,768 Hz
VSSA nRST
Powered by VDDA Powered by VDD15 Powered by VDD
AF
X32KIN
X32KOUT
Power supply:
Bus:
Control signal:
Alternate function: AF
Figure 1. Block Diagram
Rev. 1.70 17 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
Memory Map
0xFFFF_FFFF
0x400F_FFFF
Reserved
Reserved 0x400B_6000
0x400B_0000 GPIO A ～ C
0xE010_0000 0x400A_C000 Reserved
Private peripheral bus 0x400A_A000 USB SRAM Note
0xE000_0000 AHB
0x400A_8000 USB Note
Overview
0x4008_C000 Reserved
0x4008_A000 CRC
0x4008_8000 CKCU/RSTCU
0x4008_2000 Reserved
0x4008_0000 FMC
Reserved Reserved
0x4007_8000
0x4007_7000 BFTM1
0x4007_6000 BFTM0
0x4007_5000 SCTM3
0x4007_4000 SCTM1
0x4010_0000 0x4006_F000 Reserved
512 KB 0x4006_E000 GPTM
AHB peripherals
0x4008_0000 0x4006_B000 Reserved
Peripheral
0x4006_A000 RTC & PWRCU
APB peripherals 512 KB
0x4000_0000 0x4006_9000 Reserved
0x4006_8000 WDT
0x4004_A000 Reserved
0x4004_9000 I2C1
0x4004_8000 I2C0
Reserved 0x4004_5000 Reserved
SRAM 0x4004_4000 SPI1 APB
0x4004_3000 SCI Note
0x2000_2000 0x4004_1000 UART1
Up to 0x4003_5000 SCTM2
8 KB on-chip SRAM 8 KB 0x4003_4000 SCTM0
0x2000_0000 0x4002_D000 Reserved
0x4002_C000 MCTM
Reserved
0x1FF0_0400 0x4002_5000 Reserved
0x4002_4000 EXTI
Option byte alias 1 KB
0x1FF0_0000 0x4002_3000 Reserved
0x4002_2000 AFIO
Reserved
0x1F00_0800 0x4001_1000 Reserved
0x4001_0000 ADC
Code Boot loader 2 KB
0x1F00_0000 0x4000_5000 Reserved
0x4000_4000 SPI0
Reserved
0x0001_0000 0x4000_2000 Reserved
0x4000_1000 UART0
0x4000_0000 USART
Up to
64 KB on-chip Flash Up to Note: HT32F52331/HT32F52341 only
64 KB
0x0000_0000
Figure 2. Memory Map
Rev. 1.70 18 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table 2. Register Map

Start Address End Address Peripheral Bus
0x4000_0000 0x4000_0FFF USART0
0x4000_1000 0x4000_1FFF UART0
0x4000_2000 0x4000_3FFF Reserved
0x4000_4000 0x4000_4FFF SPI0
0x4001_0000 0x4001_0FFF ADC
Overview
0x4002_2000 0x4002_2FFF AFIO
0x4002_4000 0x4002_4FFF EXTI
0x4002_5000 0x4002_BFFF Reserved
0x4002_C000 0x4002_CFFF MCTM
0x4002_D000 0x4003_3FFF Reserved
0x4003_4000 0x4003_4FFF SCTM0
0x4003_5000 0x4003_5FFF SCTM2
0x4004_1000 0x4004_1FFF UART1
0x4004_2000 0x4004_2FFF Reserved APB
0x4004_3000 0x4004_3FFF SCI Note
0x4004_4000 0x4004_4FFF SPI1
0x4004_8000 0x4004_8FFF I2C0
0x4004_9000 0x4004_9FFF I2C1
0x4004_A000 0x4006_7FFF Reserved
0x4006_8000 0x4006_8FFF WDT
0x4006_A000 0x4006_AFFF RTC/PWRCU
0x4006_B000 0x4006_DFFF Reserved
0x4006_E000 0x4006_EFFF GPTM
0x4006_F000 0x4007_3FFF Reserved
0x4007_4000 0x4007_4FFF SCTM1
0x4007_5000 0x4007_5FFF SCTM3
0x4007_6000 0x4007_6FFF BFTM0
0x4007_7000 0x4007_7FFF BFTM1
0x4007_8000 0x4007_FFFF Reserved
Rev. 1.70 19 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
Start Address End Address Peripheral Bus

0x4008_0000 0x4008_1FFF FMC
0x4008_8000 0x4008_9FFF CKCU/RSTCU
0x4008_A000 0x4008_BFFF CRC
0x4008_C000 0x400A_7FFF Reserved
0x400A_8000 0x400A_BFFF USB Note AHB
0x400A_C000 0x400A_FFFF Reserved
Overview
0x400B_0000 0x400B_1FFF GPIOA
0x400B_2000 0x400B_3FFF GPIOB
0x400B_4000 0x400B_5FFF GPIOC
0x400B_6000 0x400F_FFFF Reserved
Note: HT32F52331/HT32F52341 only.
Rev. 1.70 20 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
Clock Structure
Prescaler Divider
CK_REF
1 ~ 32 2
HSI Auto CK_LSE CKREFPRE
CKREFEN
Trimming
Controller USB REF Pulse fCK_USB = 48 MHz
CK_USB
Overview
USBEN
8 MHz PLLSRC HT32F52331/52341 only
HSI RC PLLEN f CK_PLL,max = 48 MHz
STCLK
8 (to SysTick)
1 CK_PLL
HSIEN PLL
0 SW[2:0]
fCK_SYS,max = 40 MHz for CK_GPIO
4-16 MHz HT32F52231/52241 GPIOAEN
( to GPIO port)
HSE XTAL 00x fCK_SYS,max = 48 MHz for GPIODEN
HT32F52331/52241
CK_HSI
011
HSEEN CK_HSE CK_SYS AHB Prescaler FCLK
010 ( free running clock)
1,2,4,8,16,32
111
110
HCLKC
CM0PEN ( to Cortex®-M0+)
(control by HW)
CK_AHB
Clock
Monitor
CK_CRC
CRCEN ( to CRC)
32.768 kHz CK_LSE

LSE OSC WDTSRC
LSEEN(Note1) HCLKF
1 CK_WDT ( to Flash)
0 CM0PEN
FMCEN
32 kHz CK_LSI
WDTEN
LSI RC
RTCSRC(Note1)
HCLKS
LSIEN(Note1) ( to SRAM)
CM0PEN
1 CK_RTC
0 SRAMEN
RTCEN(Note1) HCLKBM
( to Bus Matrix)
CKOUTSRC[2:0] CM0PEN
BMEN
000 CK_REF
001 CK_AHB/16
010 CK_SYS/16 HCLKAPB
CKOUT ( to APB Bridge)
011 CK_HSE/16
CM0PEN
100 CK_HSI/16
101 CK_LSE APBEN
110 CK_LSI
PCLK
Legend: 00
HSE = High Speed External clock Peripherals PCLK/2 01 PCLK (AFIO, ADC,
Clock
HSI = High Speed Internal clock SPIx, USART, UARTx,
Prescaler PCLK/4 SPIEN
LSE = Low Speed External clock 10 I2Cx, MCTM, GPTM,
1,2,4,8
SCTMx, BFTMx, EXTI,
LSI = Low Speed Internal clock PCLK/8 11
SCIEN
SCI, WDT, RTC)
ADC
Prescaler CK_ADC IP
1,2,3,4,8,...
ADCEN
Figure 3. Clock Structure
Rev. 1.70 21 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
4 Pin Assignment
HT32F52231/HT32F52241
24 SSOP-A
AF0 AF0 AF1

(Default) (Default)
Pin Assignment
PB7 1 33V 33V 24 PB4
PB8 2 33V P33 3.3 V Digital Power Pad 33V 23 PB3
VDDA 3 AP 33V 22 PB2

AP 3.3 V Analog Power Pad
PA0 4 33V 33V 21 PB1
PA1 5 33V P15 1.5 V Power Pad 33V 20 PB0
PA2 6 33V 33V 19 SWDIO PA13

33V 3.3 V Digital & Analog IO Pad
PA3 7 33V 33V 18 SWCLK PA12
PA4 8 33V 33V 3.3 V Digital I/O Pad 33V 17 PA9_BOOT
PA5 9 33V 33V 16 XTALOUT PB14
CLDO 10 P15 33V 15 XTALIN PB13
VDD 11 P33 33V 14 RTCOUT PB12
VSS 12 P33 33V 13 nRST
Figure 4. HT32F52231/52241 24-pin SSOP Pin Assignment
Rev. 1.70 22 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
HT32F52231/HT32F52241
28 SSOP-A
AF0 AF0 AF1

(Default) (Default)
PB7 1 33V 33V 28 PB4
Pin Assignment
PB8 2 33V P33 3.3 V Digital Power Pad 33V 27 PB3
VDDA 3 AP 33V 26 PB2

PA0 4 33V 33V 25 PB1
PA1 5 33V P15 1.5 V Power Pad 33V 24 PB0
PA2 6 33V 33V 23 PA15

PA3 7 33V 33V 22 PA14
PA4 8 33V 33V 3.3 V Digital I/O Pad 33V 21 SWDIO PA13
PA6 10 33V 33V 19 PA9_BOOT
PA7 11 33V 33V 18 XTALOUT PB14
CLDO 12 P15 33V 17 XTALIN PB13
VDD 13 P33 33V 16 RTCOUT PB12
VSS 14 P33 33V 15 nRST
Figure 5. HT32F52231/52241 28-pin SSOP Pin Assignment
Rev. 1.70 23 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
HT32F52231/HT32F52241
33 QFN-A
(Default)
VDDA
VSSA
PB8
PB7
PB5
PB4
PB3
PB2
AF0
AF0 AF0 AF1
32 31 30 29 28 27 26 25
(Default) (Default)
Pin Assignment
AP AP 33V 33V 33V 33V 33V 33V
PA0 1 33V 33V 24 PB1

P33 3.3 V Digital Power Pad
PA1 2 33V 33V 23 PB0
PA2 3 33V 33V 22 PA15
P15 1.5 V Power Pad

PA3 4 33V 33V 21 PA14
PA4 5 33V 33V 3.3 V Digital & Analog IO Pad 33V 20 SWDIO PA13
PA5 6 33V 33V 3.3 V Digital I/O Pad 33V 19 SWCLK PA12
PA9_
PA6 7 33V VDD VDD Domain Pad 33V 18
BOOT
PA7 8 33V 33 VSS 33V 17 XTALOUT PB14
VDD VDD VDD VDD

P15 P33 P33 33V
33V 33V 33V 33V
9 10 11 12 13 14 15 16
X32KOUT
RTCOUT
(Default)
XTALIN
X32KIN
CLDO
nRST
VDD
VSS
AF0
PB10
PB11
PB12
PB13
AF1
Figure 6. HT32F52231/52241 33-pin QFN Pin Assignment
Rev. 1.70 24 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
HT32F52231/HT32F52241
48 LQFP-A
(Default)
VDDA
VSSA
PC3
PC2
PC1
AF0
PB8
PB7
PB6
PB5
PB4
PB3
PB2
AF0 AF0 AF1
48 47 46 45 44 43 42 41 40 39 38 37
Pin Assignment
(Default) (Default)
AP AP 33V 33V 33V 33V 33V 33V 33V 33V 33V 33V
PA0 1 33V P33 36 VSS_2
PA1 2 33V P33 35 VDD_2

P33 3.3 V Digital Power Pad
PA2 3 33V 33V 34 PB1
PA3 4 33V 33V 33 PB0

PA4 5 33V 33V 32 PA15

P15 1.5 V Power Pad
PA5 6 33V 33V 31 PA14


33V 3.3 V Digital I/O Pad
PC4 9 33V 33V 28 PA11
PC5 10 33V 33V 27 PA10

VDD VDD Domain Pad
PA9_
PC6 11 33V 33V 26
BOOT
PC7 12 33V 33V 25 PA8
VDD VDD VDD VDD VDD

P15 P33 P33 33V 33V 33V 33V
33V 33V 33V 33V 33V
13 14 15 16 17 18 19 20 21 22 23 24
XTALOUT
X32KOUT
RTCOUT
(Default)
XTALIN
X32KIN
VDD_1
VSS_1
CLDO
nRST
PB15
PC0
PB9
AF0
PB10
PB11
PB12
PB13
PB14
AF1
Figure 7. HT32F52231/52241 48-pin LQFP Pin Assignment
Rev. 1.70 25 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
HT32F52331/HT32F52341
33 QFN-A
(Default)
VDDA
VSSA
PB8
PB7
PB5
PB4
PB3
PB2
AF0
AF0 AF0 AF1
32 31 30 29 28 27 26 25
(Default) (Default)
Pin Assignment
AP AP 33V 33V 33V 33V 33V 33V
PA0 1 33V P33 3.3 V Digital Power Pad 33V 24 PB1
PA1 2 33V 33V 23 PB0

PA2 3 33V 33V 22 PA15
P15 1.5 V Power Pad
PA3 4 33V 33V 21 PA14
33V 3.3 V Digital I/O Pad
VDD VDD Domain Pad PA9_
USBDM 7 USB 33V 18
BOOT
USBDP 8 USB USB USB PHY Pad 33 VSS 33V 17 XTALOUT PB14
VDD VDD VDD VDD

P15 P33 P33 33V
33V 33V 33V 33V
9 10 11 12 13 14 15 16
X32KOUT
RTCOUT
(Default)
XTALIN
X32KIN
CLDO
nRST
VDD
VSS
AF0
PB10
PB11
PB12
PB13
AF1
Figure 8. HT32F52331/52341 33-pin QFN Pin Assignment
Rev. 1.70 26 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
HT32F52331/HT32F52341
48 LQFP-A
(Default)
VDDA
VSSA
PC3
PC2
PC1
AF0
PB8
PB7
PB6
PB5
PB4
PB3
PB2
AF0 AF0 AF1
48 47 46 45 44 43 42 41 40 39 38 37
(Default) (Default)
Pin Assignment
AP AP 33V 33V 33V 33V 33V 33V 33V 33V 33V 33V
PA0 1 33V P33 36 VSS_2
PA1 2 33V P33 3.3 V Digital Power Pad P33 35 VDD_2
PA2 3 33V 33V 34 PB1

PA3 4 33V 33V 33 PB0
PA4 5 33V P15 1.5 V Power Pad 33V 32 PA15
PA5 6 33V 33V 31 PA14

PA7 8 33V 33V 3.3 V Digital I/O Pad 33V 29 SWCLK PA12
PC4 9 33V 33V 28 PA11

USB USB PHY Pad
PC5 10 33V 33V 27 PA10
PA9_
USBDM 11 USB VDD VDD Domain Pad 33V 26
BOOT
USBDP 12 USB 33V 25 PA8
VDD VDD VDD VDD VDD

P15 P33 P33 33V 33V 33V 33V
33V 33V 33V 33V 33V
13 14 15 16 17 18 19 20 21 22 23 24
XTALOUT
X32KOUT
(Default)
RTCOUT
XTALIN
X32KIN
VDD_1
VSS_1
CLDO
nRST
PB15
AF0
PC0
PB9
PB10
PB11
PB12
PB13
PB14
AF1
Figure 9. HT32F52331/52341 48-pin LQFP Pin Assignment
Rev. 1.70 27 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table 3. HT32F52231/52241 Series Pin Assignment for 24/28SSOP, 33QFN, 48LQFP Package
HT32F52231/52241 Alternate Function Mapping
Package
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
48 33 28 24 System GPTM USART System
GPIO ADC N/A SPI IC
2
N/A N/A N/A N/A N/A SCTM N/A
LQFP QFN SSOP SSOP Default /MCTM /UART Other
1 1 4 4 PA0 ADC_IN2 GT_CH0 SPI1_SCK USR_RTS I2C1_SCL
2 2 5 5 PA1 ADC_IN3 GT_CH1 SPI1_MOSI USR_CTS I2C1_SDA
3 3 6 6 PA2 ADC_IN4 GT_CH2 SPI1_MISO USR_TX
4 4 7 7 PA3 ADC_IN5 GT_CH3 SPI1_SEL USR_RX
5 5 8 8 PA4 ADC_IN6 GT_CH0 SPI0_SCK UR1_TX I2C0_SCL
Pin Assignment
6 6 9 9 PA5 ADC_IN7 GT_CH1 SPI0_MOSI UR1_RX I2C0_SDA
7 7 10 PA6 ADC_IN8 GT_CH2 SPI0_MISO
8 8 11 PA7 ADC_IN9 GT_CH3 SPI0_SEL
9 PC4 ADC_IN10 USR_TX SCTM0
10 PC5 ADC_IN11 USR_RX SCTM1
11 PC6 MT_CH2 UR0_TX I2C0_SCL
12 PC7 MT_CH2N UR0_RX I2C0_SDA
13 9 12 10 CLDO
14 10 13 11 VDD_1
15 11 14 12 VSS_1
16 12 15 13 nRST
17 PB9 MT_CH3
18 13 X32KIN PB10 GT_CH0 SPI1_SEL USR_TX SCTM2
19 14 X32KOUT PB11 GT_CH1 SPI1_SCK USR_RX SCTM3
20 15 16 14 RTCOUT PB12 SPI0_MISO UR0_RX SCTM0 WAKEUP
21 16 17 15 XTALIN PB13 UR0_TX I2C0_SCL
22 17 18 16 XTALOUT PB14 UR0_RX I2C0_SDA
23 PB15 MT_CH0 SPI0_SEL I2C1_SCL
24 PC0 MT_CH0N SPI0_SCK I2C1_SDA SCTM3
25 PA8 USR_TX SCTM2
PA9_
26 18 19 17 SPI0_MOSI SCTM3 CKOUT
BOOT
27 PA10 MT_CH1 SPI0_MOSI USR_RX
28 PA11 MT_CH1N SPI0_MISO SCTM0
29 19 20 18 SWCLK PA12
30 20 21 19 SWDIO PA13
31 21 22 PA14 MT_CH0 SPI1_SEL USR_RTS I2C1_SCL
32 22 23 PA15 MT_CH0N SPI1_SCK USR_CTS I2C1_SDA SCTM1
33 23 24 20 PB0 MT_CH1 SPI1_MOSI USR_TX I2C0_SCL
34 24 25 21 PB1 MT_CH1N SPI1_MISO USR_RX I2C0_SDA SCTM2
35 VDD_2
36 33 VSS_2
37 25 26 22 PB2 MT_CH2 SPI0_SEL UR1_TX
38 26 27 23 PB3 MT_CH2N SPI0_SCK UR1_RX SCTM1
39 27 28 24 PB4 MT_BRK SPI0_MOSI UR1_TX SCTM0
40 28 PB5 GT_CH2 SPI0_MISO UR1_RX
41 PC1 MT_CH0 SPI1_SEL UR1_TX
42 PC2 MT_CH0N SPI1_SCK
43 PC3 MT_BRK SPI1_MOSI UR1_RX
44 PB6 GT_CH3 SPI1_MISO UR0_TX
45 29 1 1 PB7 ADC_IN0 MT_CH1 SPI0_MISO UR0_TX I2C1_SCL
46 30 2 2 PB8 ADC_IN1 MT_CH1N SPI0_SEL UR0_RX I2C1_SDA
47 31 3 3 VDDA
48 32 VSSA
Note: The pin number 33 of the 33-pin QFN package is located at the bottom metal of the QFN package.
Rev. 1.70 28 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table 4. HT32F52331/52341 Series Pin Assignment for 33QFN, 48LQFP Package

HT32F52331/52341 Alternate Function Mapping
Package
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
48 33 System GPTM USART System
GPIO ADC N/A SPI I2C SCI N/A N/A N/A N/A SCTM N/A
LQFP QFN Default /MCTM /UART Other
1 1 PA0 ADC_IN2 GT_CH0 SPI1_SCK USR_RTS I2C1_SCL SCI_CLK
2 2 PA1 ADC_IN3 GT_CH1 SPI1_MOSI USR_CTS I2C1_SDA SCI_DIO
3 3 PA2 ADC_IN4 GT_CH2 SPI1_MISO USR_TX
4 4 PA3 ADC_IN5 GT_CH3 SPI1_SEL USR_RX
5 5 PA4 ADC_IN6 GT_CH0 SPI0_SCK UR1_TX I2C0_SCL SCI_CLK
Pin Assignment
6 6 PA5 ADC_IN7 GT_CH1 SPI0_MOSI UR1_RX I2C0_SDA SCI_DIO
7 PA6 ADC_IN8 GT_CH2 SPI0_MISO SCI_DET
8 PA7 ADC_IN9 GT_CH3 SPI0_SEL
9 PC4 ADC_IN10 USR_TX SCTM0
10 PC5 ADC_IN11 USR_RX SCTM1
11 7 USBDM
12 8 USBDP
13 9 CLDO
14 10 VDD_1
15 11 VSS_1
16 12 nRST
17 PB9 MT_CH3
18 13 X32KIN PB10 GT_CH0 SPI1_SEL USR_TX SCTM2
19 14 X32KOUT PB11 GT_CH1 SPI1_SCK USR_RX SCTM3
20 15 RTCOUT PB12 SPI0_MISO UR0_RX SCTM0 WAKEUP
21 16 XTALIN PB13 UR0_TX I2C0_SCL
22 17 XTALOUT PB14 UR0_RX I2C0_SDA
23 PB15 MT_CH0 SPI0_SEL I2C1_SCL
24 PC0 MT_CH0N SPI0_SCK I2C1_SDA SCTM3
25 PA8 USR_TX SCI_CLK SCTM2
26 18 PA9_BOOT SPI0_MOSI SCI_DIO SCTM3 CKOUT
27 PA10 MT_CH1 SPI0_MOSI USR_RX SCI_DET
28 PA11 MT_CH1N SPI0_MISO SCI_DET SCTM0
29 19 SWCLK PA12
30 20 SWDIO PA13
31 21 PA14 MT_CH0 SPI1_SEL USR_RTS I2C1_SCL SCI_CLK
32 22 PA15 MT_CH0N SPI1_SCK USR_CTS I2C1_SDA SCI_DIO SCTM1
33 23 PB0 MT_CH1 SPI1_MOSI USR_TX I2C0_SCL
34 24 PB1 MT_CH1N SPI1_MISO USR_RX I2C0_SDA SCTM2
35 VDD_2
36 33 VSS_2
37 25 PB2 MT_CH2 SPI0_SEL UR1_TX
38 26 PB3 MT_CH2N SPI0_SCK UR1_RX SCTM1
39 27 PB4 MT_BRK SPI0_MOSI UR1_TX SCTM0
40 28 PB5 GT_CH2 SPI0_MISO UR1_RX
41 PC1 MT_CH0 SPI1_SEL UR1_TX
42 PC2 MT_CH0N SPI1_SCK
43 PC3 MT_BRK SPI1_MOSI UR1_RX
44 PB6 GT_CH3 SPI1_MISO UR0_TX SCI_CLK
45 29 PB7 ADC_IN0 MT_CH1 SPI0_MISO UR0_TX I2C1_SCL SCI_DET
46 30 PB8 ADC_IN1 MT_CH1N SPI0_SEL UR0_RX I2C1_SDA SCI_DIO
47 31 VDDA
48 32 VSSA
Note: The pin number 33 of the 33-pin QFN package is located at the bottom metal of the QFN package.
Rev. 1.70 29 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table 5. HT32F52231/52241 Pin Description

Pin number IO Description
Pin Type Output
Structure
48LQFP 33QFN 28SSOP 24SSOP Name (Note1)
(Note2) Driving Default function (AF0)
1 1 4 4 PA0 AI/O 33V 4/8/12/16 mA PA0

2 2 5 5 PA1 AI/O 33V 4/8/12/16 mA PA1
3 3 6 6 PA2 AI/O 33V 4/8/12/16 mA PA2
4 4 7 7 PA3 AI/O 33V 4/8/12/16 mA PA3
5 5 8 8 PA4 AI/O 33V 4/8/12/16 mA PA4
6 6 9 9 PA5 AI/O 33V 4/8/12/16 mA PA5
Pin Assignment
7 10 PA6 AI/O 33V 4/8/12/16 mA PA6
8 11 PA7 AI/O 33V 4/8/12/16 mA PA7
9 PC4 AI/O 33V 4/8/12/16 mA PC4
10 PC5 AI/O 33V 4/8/12/16 mA PC5
11 7 PC6 AI/O — — PC6
12 8 PC7 AI/O — — PC7
Core power LDO 1.5 V output
13 9 12 10 CLDO P — — It is recommended to connect a 1 μF capacitor as close as
possible between this pin and VSS_1.
14 10 13 11 VDD_1 P — — Voltage for digital I/O
15 11 14 12 VSS_1 P — — Ground reference for digital I/O
External reset pin and external wakeup pin in the Power-
16 12 15 13 nRST Note 3
I 33V_PU —
Down mode
17 PB9 Note 3 I/O (VDD) 33V 4/8/12/16 mA PB9
18 13 PB10 Note 3 AI/O (VDD) 33V 4/8/12/16 mA X32KIN
19 14 PB11 Note 3 AI/O (VDD) 33V 4/8/12/16 mA X32KOUT
20 15 16 14 PB12 Note 3 I/O (VDD) 33V 4/8/12/16 mA RTCOUT
21 16 17 15 PB13 AI/O 33V 4/8/12/16 mA XTALIN
22 17 18 16 PB14 AI/O 33V 4/8/12/16 mA XTALOUT
23 PB15 I/O 33V 4/8/12/16 mA PB15
24 PC0 I/O 33V 4/8/12/16 mA PC0
25 PA8 I/O 33V 4/8/12/16 mA PA8
26 18 19 17 PA9 I/O 33V_PU 4/8/12/16 mA PA9_BOOT
27 PA10 I/O 33V 4/8/12/16 mA PA10
28 PA11 I/O 33V 4/8/12/16 mA PA11
29 19 20 18 PA12 I/O 33V_PU 4/8/12/16 mA SWCLK
30 20 21 19 PA13 I/O 33V_PU 4/8/12/16 mA SWDIO
31 21 22 PA14 I/O 33V 4/8/12/16 mA PA14
32 22 23 PA15 I/O 33V 4/8/12/16 mA PA15
33 23 24 20 PB0 I/O 33V 4/8/12/16 mA PB0
34 24 25 21 PB1 I/O 33V 4/8/12/16 mA PB1
35 VDD_2 P — — Voltage for digital I/O
36 33 VSS_2 P — — Ground reference for digital I/O
37 25 26 22 PB2 I/O 33V 4/8/12/16 mA PB2
38 26 27 23 PB3 I/O 33V 4/8/12/16 mA PB3
39 27 28 24 PB4 I/O 33V 4/8/12/16 mA PB4
40 28 PB5 I/O 33V 4/8/12/16 mA PB5
41 PC1 I/O 33V 4/8/12/16 mA PC1
42 PC2 I/O 33V 4/8/12/16 mA PC2
43 PC3 I/O 33V 4/8/12/16 mA PC3
44 PB6 I/O 33V 4/8/12/16 mA PB6
45 29 1 1 PB7 AI/O 33V 4/8/12/16 mA PB7
46 30 2 2 PB8 AI/O 33V 4/8/12/16 mA PB8
47 31 3 3 VDDA P — — Analog voltage for ADC and Comparator
48 32 VSSA P — — Ground reference for the ADC and Comparator
Note: 1. I = input, O = output, A = Analog port, P = power supply, PU = pull-up, VDD = VDD Power
2. 33V = 3.3V tolerant.
3. These pins are located at the VDD power domain.
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HT32F52231/HT32F52241/HT32F52331/HT32F52341
Table 6. HT32F52331/52341 Pin Description

Pin number Type IO Structure Output Description
Pin Name
48LQFP 33QFN
(Note1) (Note2)
Driving Default function (AF0)
1 1 PA0 AI/O 33V 4/8/12/16 mA PA0
2 2 PA1 AI/O 33V 4/8/12/16 mA PA1
3 3 PA2 AI/O 33V 4/8/12/16 mA PA2
4 4 PA3 AI/O 33V 4/8/12/16 mA PA3
5 5 PA4 AI/O 33V 4/8/12/16 mA PA4
6 6 PA5 AI/O 33V 4/8/12/16 mA PA5
Pin Assignment
7 PA6 AI/O 33V 4/8/12/16 mA PA6
8 PA7 AI/O 33V 4/8/12/16 mA PA7
9 PC4 AI/O 33V 4/8/12/16 mA PC4
10 PC5 AI/O 33V 4/8/12/16 mA PC5
11 7 USBDM AI/O — — USB Differential data bus conforming to the Universal Serial Bus standard.
12 8 USBDP AI/O — — USB Differential data bus conforming to the Universal Serial Bus standard.
Core power LDO 1.5 V output
13 9 CLDO P — — It is recommended to connect a 1 μF capacitor as close as possible
between this pin and VSS_1.
14 10 VDD_1 P — — Voltage for digital I/O
16 12 nRST Note 3 I 33V_PU -- External reset pin and external wakeup pin in the Power-Down mode
17 PB9 Note 3 I/O (VDD) 33V 4/8/12/16 mA PB9
18 13 PB10 Note 3 AI/O (VDD) 33V 4/8/12/16 mA X32KIN
19 14 PB11 Note 3 AI/O (VDD) 33V 4/8/12/16 mA X32KOUT
20 15 PB12 Note 3 I/O (VDD) 33V 4/8/12/16 mA RTCOUT
21 16 PB13 AI/O 33V 4/8/12/16 mA XTALIN
22 17 PB14 AI/O 33V 4/8/12/16 mA XTALOUT
23 PB15 I/O 33V 4/8/12/16 mA PB15
24 PC0 I/O 33V 4/8/12/16 mA PC0
25 PA8 I/O 33V 4/8/12/16 mA PA8
26 18 PA9 I/O 33V_PU 4/8/12/16 mA PA9_BOOT
27 PA10 I/O 33V 4/8/12/16 mA PA10
28 PA11 I/O 33V 4/8/12/16 mA PA11
29 19 PA12 I/O 33V_PU 4/8/12/16 mA SWCLK
30 20 PA13 I/O 33V_PU 4/8/12/16 mA SWDIO
31 21 PA14 I/O 33V 4/8/12/16 mA PA14
32 22 PA15 I/O 33V 4/8/12/16 mA PA15
33 23 PB0 I/O 33V 4/8/12/16 mA PB0
34 24 PB1 I/O 33V 4/8/12/16 mA PB1
35 VDD_2 P — — Voltage for digital I/O
37 25 PB2 I/O 33V 4/8/12/16 mA PB2
38 26 PB3 I/O 33V 4/8/12/16 mA PB3
39 27 PB4 I/O 33V 4/8/12/16 mA PB4
40 28 PB5 I/O 33V 4/8/12/16 mA PB5
41 PC1 I/O 33V 4/8/12/16 mA PC1
42 PC2 I/O 33V 4/8/12/16 mA PC2
43 PC3 I/O 33V 4/8/12/16 mA PC3
44 PB6 I/O 33V 4/8/12/16 mA PB6
45 29 PB7 AI/O 33V 4/8/12/16 mA PB7
46 30 PB8 AI/O 33V 4/8/12/16 mA PB8
47 31 VDDA P — — Analog voltage for ADC and Comparator
48 32 VSSA P — — Ground reference for the ADC and Comparator
Note: 1. I = input, O = output, A = Analog port, P = power supply, PU = pull-up, VDD = VDD Power
2. 33V = 3.3V tolerant.
3. These pins are located at the VDD power domain.
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HT32F52231/HT32F52241/HT32F52331/HT32F52341
5 Electrical Characteristics
Absolute Maximum Ratings

The following table shows the absolute maximum ratings of the device. These are stress ratings
only. Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note
that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the
Electrical Characteristics
absolute maximum rating conditions for extended periods may affect device reliability.
Table 7. Absolute Maximum Ratings
Symbol Parameter Min Max Unit
VDD External Main Supply Voltage VSS - 0.3 VSS + 3.6 V
VDDA External Analog Supply Voltage VSSA - 0.3 VSSA + 3.6 V
VIN Input Voltage on I/O VSS - 0.3 VDD + 0.3 V
TA Ambient Operating Temperature Range -40 +85 °C
TSTG Storage Temperature Range -55 +150 °C
TJ Maximum Junction Temperature — +125 °C
PD Total Power Dissipation — 500 mW
VESD Electrostatic Discharge Voltage - Human Body Mode -4000 +4000 V
Recommended DC Operating Conditions

Table 8. Recommended DC Operating Conditions
TA = 25°C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VDD I/O OPerating Voltage — 2.0 3.3 3.6 V
VDDA Analog Operating Voltage — 2.5 3.3 3.6 V
On-Chip LDO Voltage Regulator Characteristics

Table 9. LDO Characteristics
VDD ≥ 2.0V Regulator input @
Internal Regulator Output
VLDO ILDO = 35mA and voltage vari- 1.425 1.5 1.57 V
Voltage
ant = ±5%, After trimming.
VDD = 2.0V Regulator input @
ILDO Output Current — 30 35 mA
VLDO = 1.5V
External Filter Capacitor The capacitor value is depen-
CLDO Value For Internal Core Power dent on the core power cur- — 1 — μF
Supply rent consumption
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Power Consumption
Table 10. HT32F52231/52241 Power Consumption Characteristics
VDD = 3.3V, HSE = 8MHz, PLL = 40MHz,
fHCLK = 40MHz, fPCLK = 48MHz, — 12 — mA
All peripherals enabled
Supply Current All peripherals disabled
(Run Mode) VDD = 3.3V, HSE off, PLL off, LSI on,
fHCLK = 32kHz, fPCLK = 32kHz, — 45 — μA
VDD = 3.3V, HSE off, PLL off, LSI on,
All peripherals disabled
IDD fHCLK = 0MHz, fPCLK = 40MHz, — 7.5 — mA
Supply Current All peripherals enabled
(Sleep Mode) VDD = 3.3V, HSE = 8MHz, PLL = 40MHz,
Supply Current VDD = 3.3V, All clock off (HSE/PLL/fHCLK),
— 35 — μA
(Deep-sleep1 Mode) LDO in low power mode, LSI on, RTC on
— 5 — μA
(Deep-sleep2 Mode) LDO off (DMOS on), LSI on, RTC on
VDD = 3.3V, LDO off, DMOS off, LSE on,
— 2.8 — μA
Supply Current LSI on, RTC on
(Power-down Mode) VDD = 3.3V, LDO off, DMOS off, LSE off,
— 1.5 — μA
LSI on, RTC off
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Table 11. HT32F52331/52341 Power Consumption Characteristics

fHCLK = 48MHz, fPCLK = 48MHz, — 8.5 — mA
Supply Current
(Run Mode) VDD = 3.3V, HSE off, PLL off, LSI on,
VDD = 3.3V, HSE off, PLL off, LSI on,
IDD fHCLK = 0MHz, fPCLK = 48MHz, — 10 — mA
Supply Current All peripherals enabled
(Sleep Mode) VDD = 3.3V, HSE = 8MHz, PLL = 48MHz,
fHCLK = 0MHz, fPCLK = 48MHz, — 2.5 — mA
— 35 — μA
(Deep-Sleep1 Mode) LDO in low power mode, LSI on, RTC on
— 5 — μA
(Deep-Sleep2 Mode) LDO off (DMOS on), LSI on, RTC on
VDD = 3.3V, LDO off, DMOS off, LSE on,
— 2.8 — μA
Supply Current LSI on, RTC on
(Power-Down Mode) VDD = 3.3V, LDO off, DMOS off, LSE off,
— 1.5 — μA
LSI on, RTC off
Note: 1. HSE means high speed external oscillator. HSI means 8MHz high speed internal oscillator.
2. LSE means 32.768kHz low speed external oscillator. LSI means 32kHz low speed internal
oscillator.
3. RTC means real time clock.
4. Code = while (1) { 208 NOP } executed in Flash.
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HT32F52231/HT32F52241/HT32F52331/HT32F52341
Reset and Supply Monitor Characteristics

Table 12. VDD Power Reset Characteristics
Power on Reset Threshold
VPOR 1.66 1.79 1.90 V
(Rising Voltage on VDD)
TA = -40°C~ +85°C
Power down Reset Threshold
VPDR 1.49 1.64 1.78 V
(Falling Voltage on VDD)
VPORHYST POR Hysteresis — — 150 mV
tPOR Reset Delay Time VDD = 3.3V — 0.1 0.2 ms
Note: 1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
3. If the LDO is turned on, the VDD POR has to be in the de-assertion condition. When the
VDD POR is in the assertion state then the LDO will be turned off.
Table 13. LVD/BOD Characteristics

TA = -40°C ~ 85°C
Voltage of Brown Out
VBOD After factory-trimmed 2.02 2.1 2.18 V
Detection
(VDD Falling edge)
LVDS = 000 2.17 2.25 2.33 V
LVDS = 001 2.32 2.4 2.48 V
LVDS = 010 2.47 2.55 2.63 V
Voltage of Low Voltage TA = -40°C ~ 85°C LVDS = 011 2.62 2.7 2.78 V
VLVD
Detection (VDD Falling edge) LVDS = 100 2.77 2.85 2.93 V
LVDS = 101 2.92 3.0 3.08 V
LVDS = 110 3.07 3.15 3.23 V
LVDS = 111 3.22 3.3 3.38 V
VLVDHTST LVD Hysteresis VDD = 3.3V — — 100 — mV
tsuLVD LVD Setup time VDD = 3.3V — — — 5 μs
tatLVD LVD Active Delay Time VDD = 3.3V — — — — μs
IDDLVD Operation Current NOTE3 VDD = 3.3V — — 5 15 μA
Note: 1. Data based on characterization results only, not tested in production.
2. Guaranteed by design, not tested in production.
3. Bandgap current is not included.
4. LVDS field is in the PWRCU LVDCSR register
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HT32F52231/HT32F52241/HT32F52331/HT32F52341
External Clock Characteristics

Table 14. High Speed External Clock (HSE) Characteristics
VDD Operation Range — 2.0 — 3.6 V
High Speed External Oscillator
fHSE — 4 — 16 MHz
Frequency (HSE)
VDD = 3.3V, RESR = 100Ω
CLHSE Load capacitance — — 22 pF
@ 16MHz
Internal Feedback Resistor between
RFHSE — — 1 — MΩ
XTALIN and XTALOUT pins
VDD = 3.3V, CL = 12pF
@ 16MHz, HSEDR = 0
RESR Equivalent Series Resistance* — — 160 Ω
VDD = 2.4V, CL = 12pF
@ 16MHz, HSEDR = 1
DHSE HSE Oscillator Duty Cycle — 40 — 60 %
IDDHSE HSE Oscillator Current Consumption VDD = 3.3V @ 16MHz — TBD — mA
IPWDHSE HSE Oscillator Power Down Current VDD = 3.3V — — 0.01 μA
tSUHSE HSE Oscillator STartup Time VDD = 3.3V — — 4 ms
Table 15. Low Speed External Clock (LSE) Characteristics

fCK_LSE LSE Frequency VBAK = 2.0V ~ 3.6V — 32.768 — kHz
RF Internal Feedback Resistor — 10 MΩ
RESR Equivalent Series Resistance VBAK = 3.3V 30 — TBD kΩ
Recommended Load
CL VBAK = 3.3V 6 — TBD pF
Capacitances
FCK_LSE = 32.768kHz,
Oscillator Supply Current RESR = 50KΩ, CL >= 7pF
— 3.3 6.3 μA
(High Current Mode) VBAK = 2.0V ~ 2.7V
TA = -40°C ~ +85°C
IDDLSE FCK_LSE = 32.768kHz,
Oscillator Supply Current RESR = 50KΩ, CL < 7pF
— 1.8 3.3 μA
(Low Current Mode) VBAK = 2.0V ~ 3.6V
TA = -40°C ~ +85°C
Power Down Current — — — 0.01 μA
Startup Time fCK_LSI = 32.768kHz,
tsuLSE 500 — — ms
( Low Current Mode) VBAK = 2.0V ~ 3.6V
Note: The following guidelines are recommended to increase the stability of the crystal circuit of the
HSE / LSE clock in the PCB layout:
●● The crystal oscillator should be located as close as possible to the MCU to keep the trace
lengths as short as possible to reduce any parasitic capacitance.
●● Shield lines in the vicinity of the crystal by using a ground plane to isolate signals and
reduce noise.
●● Keep any high frequency signal lines away from the crystal area to prevent any crosstalk
adverse effects.
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HT32F52231/HT32F52241/HT32F52331/HT32F52341
Internal Clock Characteristics

Table 16. High Speed Internal Clock (HSI) Characteristics
fHSI HSI Frequency VDD = 3.3V @ 25°C — 8 — MHz
VDD = 3.3V, TA = 25°C -2 — 2 %
Factory Calibrated HSI Oscilla- VDD = 2.5V ~ 3.6V, -3 — 3 %
ACCHSI TA = -40°C ~ +85°C
tor FRequency Accuracy
VDD = 2.0V ~ 3.6V
-4 — 4 %
TA = -40°C ~ +85°C
Duty Duty Cycle fHSI = 8MHz 35 — 65 %
Oscillator Supply Current — 300 500 μA
IDDHSI fHSI = 8MHz
Power down Current — — 0.05 μA
tsuHSI Startup Time fHSI = 8MHz — — 10 μs
Table 17. Low Speed Internal Clock (LSI) Characteristics

Low Speed Internal Oscillator VDD = 3.3V,
fLSI 21 32 43 kHz
Frequency (LSI) TA = -40°C ~ +85°C
After factory-trimmed,
ACCLSI LSI Frequency Accuracy -10 — +10 %
VDD = 3.3V, TA = 25°C
IDDLSI LSI Oscillator Operating Current VDD = 3.3V, TA = 25°C — 0.4 0.8 μA
tSULSI LSI Oscillator Startup Time VDD = 3.3V, TA = 25°C — — 100 μs
PLL Characteristics
Table 18. PLL Characteristics
fPLLIN PLL Input Clock — 4 — 16 MHz
fCK_PLL PLL Output Clock — 16 — 48 MHz
tLOCK PLL Lock Time — — 200 — μs
Memory Characteristics
Table 19. Flash Memory Characteristics
Number of Guaranteed Program/Erase
NENDU TA = -40°C ~ +85°C 10 — — K cycles
Cycles Before Failure. (Endurance)
tRET Data Retention Time TA = -40°C ~ +85°C 10 — — Years
tPROG Word Programming Time TA = -40°C ~ +85°C 20 — — μs
tERASE Page Erase Time TA = -40°C ~ +85°C 2 — — ms
tMERASE Mass Erase Time TA = -40°C ~ +85°C 10 — — ms
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HT32F52231/HT32F52241/HT32F52331/HT32F52341
I/O Port Characteristics

Table 20. I/O Port Characteristics
3.3V IO VI = VSS, On-chip — — 3 μA
IIL Low Level Input Current pull-up resister
Reset pin disabled. — — 3 μA
3.3V IO VI = VDD, On-chip — — 3 μA
IIH High Level Input Current pull-down resister
Reset pin disabled. — — 3 μA
VDD ×
3.3V IO - 0.5 — V
0.35
VIL Low Level Input Voltage
VDD ×
Reset pin - 0.5 — V
0.35
VDD × VDD +
3.3V IO — V
0.65 0.5
VIH High Level Input Voltage
VDD × VDD +
Reset pin — V
0.65 0.5
VDD ×
3.3V IO — — mV
Schmitt Trigger Input 0.12
VHYS
Voltage Hysteresis VDD ×
Reset pin — — mV
0.12
3.3V IO 4mA drive, VOL = 0.4V 4 — — mA
Low Level Output Current 3.3V IO 8mA drive, VOL = 0.4V 8 — — mA
IOL
(GPIO Sink Current) 3.3V IO 12mA drive, VOL = 0.4V 12 — — mA
3.3V IO 16mA drive, VOL = 0.4V 16 — — mA
3.3V I/O 4mA drive, VOH = VDD - 0.4V 4 — — mA
High Level Output Current 3.3V I/O 8mA drive, VOH = VDD - 0.4V 8 — — mA
IOH
(GPIO Source Current) 3.3V I/O 12mA drive, VOH = VDD - 0.4V 12 — — mA
3.3V I/O 16mA drive, VOH = VDD - 0.4V 16 — — mA
3.3V 4mA drive IO, IOL = 4mA — — 0.4 V
VOL Low Level Output Voltage
VDD -
3.3V 4mA drive IO, IOH = 4mA — — V
0.4
VDD -
3.3V 8mA drive IO, IOH = 8mA — — V
0.4
VOH High Level Output Voltage
VDD -
3.3V 12mA drive IO, IOL = 12mA — — V
0.4
VDD -
3.3V 16mA drive IO, IOL = 16mA — — V
0.4
RPU Internal Pull-up Resistor 3.3V I/O — 46 — kΩ
RPD Internal Pull-down Resistor 3.3V I/O — 46 — kΩ
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HT32F52231/HT32F52241/HT32F52331/HT32F52341
ADC Characteristics
Table 21. ADC Characteristics
VDDA Operating Voltage — 2.5 3.3 3.6 V
VADCIN A/D Converter Input Voltage Range — 0 — VREF+ V
VREF+ A/D Converter Reference Voltage — — VDDA VDDA V
IADC Current Consumption VDDA = 3.3V — 1 TBD mA
IADC_DN Power Down Current Consumption VDDA = 3.3V — — 0.1 μA
fADC A/D Converter Clock — 0.7 — 16 MHz
fS Sampling Rate — 0.05 — 1 MHz
1/fADC
tDL Data Latency — — 12.5 —
Cycles
1/fADC
tS&H Sampling & Hold Time — — 3.5 —
Cycles
1/fADC
tADCCONV A/D Converter Conversion Time — — 16 —
Cycles
RI Input Sampling Switch Resistance — — — 1 kΩ
No pin/pad capacitance
CI Input Sampling Capacitance — 16 — pF
included
tSU Startup Up Time — — — 1 μs
N Resolution — — 12 — bits
INL Integral Non-linearity Error fS = 750kHz, VDDA = 3.3V — ±2 ±5 LSB
DNL Differential Non-linearity Error fS = 750kHz, VDDA = 3.3V — ±1 — LSB
EO Offset Error — — — ±10 LSB
EG Gain Error — — — ±10 LSB
Note: 1. Guaranteed by design, not tested in production.
2. Due to the A/D Converter input channel and GPIO pin-shared function design limitation, the
VDDA supply power of the A/D Converter has to be equal to the VDD supply power of the MCU
in the application circuit.
3. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input
stage where CI is the storage capacitor, RI is the resistance of the sampling switch and RS
is the output impedance of the signal source VS. Normally the sampling phase duration is
approximately, 3.5/fADC. The capacitance, CI, must be charged within this time frame and it
must be ensured that the voltage at its terminals becomes sufficiently close to VS for accu-
racy. To guarantee this, RS is not allowed to have an arbitrarily large value.
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HT32F52231/HT32F52241/HT32F52331/HT32F52341
SAR ADC
sample
RS
VS CI
RI
Figure 10. ADC Sampling Network Model
The worst case occurs when the extremities of the input range (0V and V REF ) are sampled
consecutively. In this situation a sampling error below ¼ LSB is ensured by using the following
equation:
3.5
RS   RI
f ADC C I ln( 2 N  2 )
Where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe
margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for
in this simple model.
If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations
between consecutive sampling phases, RS may be larger than the value indicated by the equation
above.
SCTM/GPTM/MCTM Characteristics
Table 22. SCTM/GPTM/MCTM Characteristics
fTM Timer Clock Source for GPTM and MCTM — — — 48 MHz
tRES Timer Resolution Time — 1 — — fTM
fEXT External Single Frequency on Channel 1 ~ 4 — — — 1/2 fTM
RES Timer Resolution — — — 16 bits
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I2C Characteristics
Table 23. I2C Characteristics
Standard mode Fast mode Fast mode plus
Symbol Parameter Unit
Min Max Min Max Min Max
fSCL SCL Clock Frequency — 100 — 400 — 1000 kHz
tSCL(H) SCL Clock High Time 4.5 — 1.125 — 0.45 — μs
tSCL(L) SCL Clock Low Time 4.5 — 1.125 — 0.45 — μs
tFALL SCL and SDA Fall Time — 1.3 — 0.34 — 0.135 μs
tRISE SCL and SDA Rise Time — 1.3 — 0.34 — 0.135 μs
tSU(SDA) SDA Data Setup Time 500 — 125 — 50 — ns
SDA data hold time (Note 5) 0 — 0 — 0 — ns
tH(SDA)
SDA data hold time (Note 6) 100 — 100 — 100 — ns
tVD(SDA) SDA data valid time — 1.6 — 0.475 — 0.25 μs
tSU(STA) START Condition Setup Time 500 — 125 — 50 — ns
tH(STA) START Condition Hold Time 0 — 0 — 0 — ns
tSU(STO) STOP Condition Setup Time 500 — 125 — 50 — ns
2. To achieve 100 kHz standard mode, the peripheral clock frequency must be higher than 2MHz.
3. To achieve 400 kHz fast mode, the peripheral clock frequency must be higher than 8MHz.
4. To achieve 1MHz fast mode plus, the peripheral clock frequency must be higher than 20MHz.
5. The above characteristic parameters of the I2C bus timing are based on: COMB_FILTER_En
= 0 and SEQ_FILTER = 00.
6. The above characteristic parameters of the I2C bus timing are based on: COMB_FILTER_En
= 1 and SEQ_FILTER = 00.
tFALL tRISE
SCL
tSCL(L) tSCL(H)
tVD(SDA)
tH(STA) tSU(STO)
tH(SDA) tSU(SDA)
SDA
tSU(STA)
Figure 11. I2C Timing Diagrams
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SPI Characteristics
Table 24. SPI Characteristics
SPI Master Mode
fSCK SPI master output SCK Master mode, SPI peripheral
— — fPCLK/2 MHz
(1/tSCK) clock frequency clock frequency fPCLK
tSCK(H) tSCK/2 tSCK/2
SCK clock high and low time — ns
tSCK(L) -2 +1
tV(MO) Data output valid time — — — 5 ns
tH(MO) Data output hold time — 2 — — ns
tSU(MI) Data input setup time — 5 — — ns
tH(MI) Data input hold time — 5 — — ns
SPI Slave Mode
fSCK SPI master output SCK Slave mode, SPI peripheral
— — fPCLK/3 MHz
(1/tSCK) clock frequency clock frequency fPCLK
SPI slave input SCK clock
DutySCK 30 — 70 %
duty cycle
tSU(SEL) SEL enable setup time — 3 tPCLK — — ns
tH(SEL) SEL enable hold time — 2 tPCLK — — ns
tA(SO) Data output access time — — — 3 tPCLK ns
tDIS(SO) Data output disable time — — — 10 ns
tV(SO) Data output valid time — — — 25 ns
tH(SO) Data output hold time — 15 — — ns
tSU(SI) Data input setup time — 5 — — ns
tH(SI) Data input hold time — 4 — — ns
Note: tSCK= 1/fSCK; tPCLK= 1/fPCLK. SPI output (input) clock frequency fSCK; SPI peripheral clock frequency fPCLK.
tSCK
SCK (CPOL = 0)
tSCK(H) tSCK(L)
SCK (CPOL = 1)
tV(MO) tH(MO)
MOSI DATA VALID DATA VALID DATA VALID
tSU(MI ) tH(MI ) CPHA = 1
MISO DATA VALID DATA VALID DATA VALID
tV(MO) tH(MO)
MOSI DATA VALID DATA VALID DATA VALID
tSU(MI ) tH(MI ) CPHA = 0
MISO DATA VALID DATA VALID DATA VALID
Figure 12. SPI Timing Diagrams – SPI Master Mode
Rev. 1.70 42 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
SEL
tSU(SEL) tH(SEL)
tSCK
SCK
(CPOL=0)
tSCK(H) tSCK(L)
SCK
(CPOL=1)
tSU(SI) tH(SI)
MOSI MSB/LSB IN LSB/MSB IN
tA(SO) tV(SO) tH(SO) tDIS(SO)
MISO MSB/LSB OUT LSB/MSB OUT
Figure 13. SPI Timing Diagrams – SPI Slave Mode with CPHA=1
Rev. 1.70 43 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
USB Characteristics
The USB interface is USB-IF certified – Full Speed.
Table 25. USB DC Electrical Characteristics
VDD USB Operating Voltage — 3.0 — 3.6 V
VDI Differential Input Sensitivity | USBDP - USBDM | 0.2 — — V
VCM Common Mode Voltage Range — 0.8 — 2.5 V
VSE Single-ended Receiver Threshold — 0.8 — 2.0 V
VOL Pad Output Low Voltage 0 — 0.3 V
VOH Pad Output High Voltage 2.8 — 3.6 V
RL of 1.5kΩ to VDD33
Differential Output Signal Cross-point
VCRS 1.3 — 2.0 V
Voltage
ZDRV Driver Output Resistance — — 10 — Ω
CIN Transceiver Pad Capacitance — — — 20 pF
2. The USB functionality is ensured down to 2.7V but for not the full USB electrical characteris-
tics which will experience degradation in the 2.7V to 3.0V VDD voltage range.
3. RL is the load connected to the USB driver USBDP.
Rise Time Fall Time
Tr Tf
90% 90%
VCRS
10% 10%
Figure 14. USB Signal Rise Time and Fall Time and Cross-point Voltage (VCRS) Definition
Table 26. USB AC Electrical Characteristics

tr Rise time CL = 50pF 4 — 20 ns
tf Fall time CL = 50pF 4 — 20 ns
tr/f Rise time / fall time matching tr/f = tr / tf 90 — 110 %
Rev. 1.70 44 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
6 Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website
for the latest version of the Package/Carton Information.
Package Information
Additional supplementary information with regard to packaging is listed below. Click on the
relevant section to be transferred to the relevant website page.
• Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• The Operation Instruction of Packing Materials
• Carton information
Rev. 1.70 45 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
24-pin SSOP (150mil) Outline Dimensions

Package Information

Dimensions in inch
Symbol
Min. Nom. Max.
A — 0.236 BSC —
B — 0.154 BSC —
C 0.008 — 0.012
C’ — 0.341 BSC —
D — — 0.069
E — 0.025 BSC —
F 0.004 — 0.010
G 0.016 — 0.050
H 0.004 — 0.010
α 0° — 8°
Dimensions in mm
Symbol
Min. Nom. Max.
A — 6.000 BSC —
B — 3.900 BSC —
C 0.200 — 0.300
C’ — 8.660 BSC —
D — — 1.750
E — 0.635 BSC —
F 0.100 — 0.250
G 0.410 — 1.270
H 0.100 — 0.250
α 0° — 8°
Rev. 1.70 46 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
28-pin SSOP (150mil) Outline Dimensions

Package Information

Dimensions in inch
Symbol
Min. Nom. Max.
A — 0.236 BSC —
B — 0.154 BSC —
C 0.008 — 0.012
C’ — 0.390 BSC —
D — — 0.069
E — 0.025 BSC —
F 0.004 — 0.0098
G 0.016 — 0.050
H 0.004 — 0.010
α 0° — 8°
Dimensions in mm
Symbol
Min. Nom. Max.
A — 6.000 BSC —
B — 3.900 BSC —
C 0.200 — 0.300
C’ — 9.900 BSC —
D — — 1.750
E — 0.635 BSC —
F 0.100 — 0.250
G 0.410 — 1.270
H 0.100 — 0.250
α 0° — 8°
Rev. 1.70 47 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
SAW Type 33-pin (4mm×4mm) QFN Outline Dimensions
Package Information
33
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.028 0.030 0.031
A1 0.000 0.001 0.002
A3 — 0.008 BSC —
b 0.006 0.008 0.010
D — 0.157 BSC —
E — 0.157 BSC —
e — 0.016 BSC —
D2 0.104 0.106 0.108
E2 0.104 0.106 0.108
L 0.014 0.016 0.018
K 0.008 — —
Dimensions in mm
Symbol
Min. Nom. Max.
A 0.700 0.750 0.800
A1 0.000 0.020 0.050
A3 — 0.203 BSC —
b 0.150 0.200 0.250
D — 4.000 BSC —
E — 4.000 BSC —
e — 0.400 BSC —
D2 2.650 2.700 2.750
E2 2.650 2.700 2.750
L 0.350 0.400 0.450
K 0.200 — —
Rev. 1.70 48 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
48-pin LQFP (7mm×7mm) Outline Dimensions

Package Information

Dimensions in inch
Symbol
Min. Nom. Max.
A — 0.354 BSC —
B — 0.276 BSC —
C — 0.354 BSC —
D — 0.276 BSC —
E — 0.020 BSC —
F 0.007 0.009 0.011
G 0.053 0.055 0.057
H — — 0.063
I 0.002 — 0.006
J 0.018 0.024 0.030
K 0.004 — 0.008
α 0° ― 7°
Dimensions in mm
Symbol
Min. Nom. Max.
A — 9.000 BSC —
B — 7.000 BSC —
C — 9.000 BSC —
D — 7.000 BSC —
E — 0.500 BSC —
F 0.170 0.220 0.270
G 1.350 1.400 1.450
H — — 1.600
I 0.050 — 0.150
J 0.450 0.600 0.750
K 0.090 — 0.200
α 0° ― 7°
Rev. 1.70 49 of 50 October 11, 2018

HT32F52231/HT32F52241/HT32F52331/HT32F52341
Package Information
Copyright© 2018 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw/en/home.
Rev. 1.70 50 of 50 October 11, 2018

HT32F52231-41 52331-41 Datasheetv170

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HT32F52231/HT32F52241

32-Bit Arm® Cortex®-M0+ Microcontroller,

Revision: V1.70 Date: October 11, 2018

Rev. 1.70 2 of 50 October 11, 2018

Rev. 1.70 3 of 50 October 11, 2018

Rev. 1.70 4 of 50 October 11, 2018

Rev. 1.70 5 of 50 October 11, 2018

Rev. 1.70 6 of 50 October 11, 2018

Flash Memory Controller – FMC

Rev. 1.70 7 of 50 October 11, 2018

Reset Control Unit – RSTCU

Clock Control Unit – CKCU

Power Management – PWRCU

Rev. 1.70 8 of 50 October 11, 2018

External Interrupt/Event Controller – EXTI

Analog to Digital Converter – ADC

I/O Ports – GPIO

Rev. 1.70 9 of 50 October 11, 2018

Motor Control Timer – MCTM

PWM Generation and Capture Timers – GPTM

Rev. 1.70 10 of 50 October 11, 2018

Single Channel Generation and Capture Timers – SCTM

Basic Function Timer – BFTM

Watchdog Timer – WDT

Rev. 1.70 11 of 50 October 11, 2018

Real Time Clock – RTC

Inter-integrated Circuit – I2C

Serial Peripheral Interface – SPI

Rev. 1.70 12 of 50 October 11, 2018

Universal Synchronous Asynchronous Receiver Transmitter – USART

Universal Asynchronous Receiver Transmitter – UART

Rev. 1.70 13 of 50 October 11, 2018

Smart Card Interface – SCI (HT32F52331/52341 only)

Cyclic Redundancy Check – CRC

Rev. 1.70 14 of 50 October 11, 2018

Universal Serial Bus Device Controller – USB (HT32F52331/52341 only)

Package and Operation Temperature

Rev. 1.70 15 of 50 October 11, 2018

Rev. 1.70 16 of 50 October 11, 2018

SWCLK SWDIO PA ~ PB[15:0]; PC[7:0] BOOT

Powered by VDD15 VDD

Flash Memory Flash

GPIO 4 ~ 16 MHz XTALOUT

Clock and reset control

NVIC 1.5 V CAP.

AHB to APB USB

CH0N ~ CH2N MCTM BFTM0 ~ 1

CLK, DIO SCTM0 ~

DET SCI SCTM3

LSI LSE WAKEUP

Figure 1. Block Diagram

Rev. 1.70 17 of 50 October 11, 2018

Figure 2. Memory Map

Rev. 1.70 18 of 50 October 11, 2018

Table 2. Register Map

Rev. 1.70 19 of 50 October 11, 2018

Start Address End Address Peripheral Bus

Note: HT32F52331/HT32F52341 only.

Rev. 1.70 20 of 50 October 11, 2018