NVP6134C Datasheet

NVP6134C
Datasheet
4-CH Universal RX(up to 5M NRT) and 5-CH Audio Codec
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REVISION HISTORY
NVP6134C Data sheet
Rev. Date. Description Note
REV 0.0 2016-06-08 Initial Draft -
REV 1.0 2016-10-12 Adding AHD 4M/5M NRT -
-
-
-
-
© Copyright Nextchip Corporations, Ltd., 2016

All Rights Reserved.
Printed in Korea 2016
Nextchip and the Nextchip Logo are trademarks of Nextchip Corporation in Korea and/or other countries.
Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document are NOT intended for
use in implantation or other life support application where malfunction may result in injury or death to persons. The information contained in
this document does not affect or change Nextchip's product specification or warranties. Nothing in this document shall operate as an express
or implied license or indemnity under the intellectual property rights of Nextchip or third parties. All information contained in this document was
obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will Nextchip be liable for
damages arising directly or indirectly from any use of the information contained in this document.
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Product Overview
NVP6134C includes Universal 4-Channel RX and 5-Channel Audio Codec. It delivers high quality CVBS, 1M, 2M and 3/4/5M NRT image. It
accepts separate CVBS, COMET, Universal 1M, 2M and 3/4/5M NRT inputs from Camera and the other video signal sources. It digitizes and
decodes CVBS, COMET, Universal 1M/2M and 3/4/5M NRT Analog video signal into digital video components which represents 8-bit
BT.656/BT.1120 4:2:2 byte interleave format with 74.25,148.5 and 297MHz multiplexed.
NVP6134C includes Clock PLL, so each output byte interleave function available. Especially, It is able to use same transmission cable with
conventional one for COMET(SD level), 1M(HD level), 2M(FHD level) and 3/4/5M NRT, and they provide the superior-image quality by
minimizing the interference when separating Y and C.
5-Channel Audio Codec is 4-Channel Voice/1-Channel Mic PCM Codec which handles voice band signals(300Hz~3400Hz) with 8bit/16bit
linear PCM, 8bit G.711(u-law, a-law) PCM. Built-in audio controller can generate digital outputs for recording/mixing and accepts digital input
for playback.
4-Channel Universal Coaxial Communication Protocol communicates between controller(DVR) and camera on the video signal through
coaxial cable.
Features 2. Audio Codec

- 4-Ch Voice / 1-Ch Mic Record, 1-Ch Playback
1. Video Decoder - 10bit pipe-line ADC / 1*DAC
 Input Formats - In/output Analog PGA Control
- 4CH Video Input - Linear PCM (8bit/16bit, 8K/16K/32K)
: CVBS / COMET - G.711 a-law/u-law (8bits, 8K/16K/32K)
: Universal 1M, 2M and 3/4/5M NRT - Input Mixing, Digital Volume, Mute Detection
- SSP/DSP/I2S Interface (Master/Slave mode)
 Output Formats - Cascade mode (up to 4 cascade support)
- Output in BT.656/BT.1120 4:2:2 byte interleave format with : 18-Channel recording (with 2 channel mic recording), mixing
37.125/74.25/148.5/297MHz output, playback
- Support Sync Separate BT.601 Format (CLK/ H,V-SYNC/ 8’bit
DATA) 3. MISC
- Built in Clock PLL
 Image Signal Processor - Single 27M Oscillator for all video standards
-. Support Video Standard Auto-Detection up to 5M NRT for Each CH - Built in 4-Ch Motion Detector(32x24)
-. Support 2*Video Output Port, Each Port Video Output Format - Support Coaxial Protocols for All Video Standard
Selectable - Support Each Channel MPP Pin and IRQ Pin
-. On Chip Analog CLAMP/Anti-aliasing Filter and EQ Filter - Support I2C serial Interface
-. Accepts CVBS,COMET, 720P@25p/30p/50p/60p,
1080P@25p/30p, 1536P@18p, 1440@15p, [email protected] 4. Operating Voltage
-. Robust Sync detection for weak and unstable signals - 3.3V/1.2V Supply Voltage
-. High-performance adaptive comb filter and Notch Filter
-. Programmable H/V Peaking filter for Luminance 5. Power Consumption
-. CTI (Chrominance Transient Improvement) - T.B.D.
-. Color compensation for PAL
-. IF compensation filter 6. Ordering information
-. Robust No-video detection
-. Programmable Brightness, Contrast, Saturation and Hue DEVICE PACKAGE TEMPERATURE RANGE
-. Programmable Picture Quality Control
-. Programmable Gamma Correction NVP6134C 76e-QFN 0 ~ 70 ℃
7. Related Products
- HI3520D-V300 / HI3521A / HI3531A
Functional block diagram
Video Decoder
Video Decoder 4Ch
4Ch
VIN1~4
VIN1~4
CVBS/COMET,
CVBS/COMET, Anti- Y
Analog Clamp/EQ YC Output
Universal 1M/2M/
Universal 1M/2M/ EQ Aliasing ADC
Clamp Control Processor Formatter
3/4/5M NRT
3/4/5M NRT Filter Seperator
Gamma Motion
MPP1~4 Coaxial AGC Detector
MPP1~4
Communicator WPD
C
Processor
SCL/SDA
SCL/SDA I2C Time
PLL HPLL VDO1~2[7:0]
VDO1~2[7:0]
Interface Multiplexer
ACC
FSC Lock
Audio Decoder
Audio Decoder 5Ch/Encoder
5Ch/Encoder 1Ch
1Ch
ACLK_REC
ACLK_REC
AIN1~4
AIN1~4 Decimation NR Volume
AFE Compressor ASYNC_REC
ASYNC_REC
MICIN
MICIN Filter Filter Control
ADATA_REC
ADATA_REC
Mute Cascade ADATA_CASO

ADATA_CASO
Detector TX
Interpolation ACLK_PB
ACLK_PB
DAC Volume
AOUT
AOUT Filter + Control Expander ASYNC_PB
ASYNC_PB
ADATA_PB
ADATA_PB
Cascade ADATA_CASI
ADATA_CASI
RX
2016.10.12 (REV 1.0) NVP6134C Data sheet

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TABLE OF CONTENTS
Revision History .........................................................................................................................................................2
Table of Contents ........................................................................................................................................................4
Contents of Tables ......................................................................................................................................................6
Contents of Figures ....................................................................................................................................................7
Chapter 1 PIN INFORMATION ................................................................................................................................8
1.1 PIN ASSIGNMENTS ...................................................................................................................................8
1.2 PIN DESCRIPTION ....................................................................................................................................9
Chapter 2 UNIVERSAL RX(1M,2M, and 3/4/5M_NRT) ........................................................................................ 11
2.1 FUNCTIONAL OVERVIEW ...................................................................................................................... 11
2.2 VIDEO INPUT FORMATS ........................................................................................................................12
2.3 ANALOG FRONT END (CLAMP, ANTI-ALIASING FILTER, EQ FILTER) ................................................13
2.4 GENLOCK (ROBUST SYNC DETECTION, ROBUST NO-VIDEO DETECTION) ...................................13
2.5 YCS (Y/C SEPARATOR) ..........................................................................................................................14
2.6 LUMA PROCESSING ...............................................................................................................................14
2.7 CHROMA PROCESSING .........................................................................................................................14
2.8 DATA OUTPUT ORDER & DIRECTION CONTROL ................................................................................16
2.9 OUTPUT FORMAT ...................................................................................................................................17
2.9.1 ITU-R BT.656/BT.1120 FORMAT ...................................................................................................17
2.9.2 ITU-R BT.601 FORMAT .................................................................................................................17
2.9.3 VIDEO OUTPUT TIMING INFORMATION ....................................................................................18
2.10 OUTPUT MODE .......................................................................................................................................20
2.10.1 SINGLE OUTPUT MODE ..............................................................................................................20
2.10.2 2-MULTIPLEX OUTPUT MODE ....................................................................................................21
2.10.3 4-MULTIPLEX OUTPUT MODE ....................................................................................................22
2.11 297MHz INTERFACE AND MULTI STANDARD OUTPUT MODE ...........................................................25
2.12 Video Frame Control .................................................................................................................................25
2.13 MOTION DETECTOR...............................................................................................................................26
Chapter 3 AUDIO CODEC.....................................................................................................................................27
3.1 Record Output ..........................................................................................................................................27
3.1.1 Data Output Interface ....................................................................................................................28
3.1.2 2/4/8/16-Channels Data Output(256 fs) .........................................................................................29
3.1.3 2/4/8/16-Channels Audio Data Output with 4-Channels Mic Data(320 fs) ....................................30
3.1.4 ADATA_SP Output .........................................................................................................................31
3.2 Playback Output .......................................................................................................................................32
3.3 Audio Detection ........................................................................................................................................32
3.4 Cascade Operation ...................................................................................................................................32
Chapter 4 COAXIAL PROTOCOL .........................................................................................................................33
4.1 PELCO PROTOCOL ................................................................................................................................33
4.2 A-CP(AHD-Coaxial protocol) ....................................................................................................................34
Chapter 5 I2C INTERFACE ...................................................................................................................................36
Chapter 6 REGISTER DESCRIPTION ..................................................................................................................37
6.1 REGISTER ADDRESS .............................................................................................................................37
6.1.1 BANK0 Register(0x00~0x1F) : VIDEO ..........................................................................................37
6.1.5 BANK0 Register(0x80~0xA3) : VIDEO_ENABLE & Delay ............................................................41
6.1.6 BANK0 Register(0xA8~0xF5) : STATUS .......................................................................................42
6.1.7 BANK1 Register(0x00~0x1E) : AUDIO ..........................................................................................43
6.1.8 BANK1 Register(0x20~0x44) : AUDIO ..........................................................................................44
6.1.9 BANK1 Register(0x80~0x9F) : IP Power Down ............................................................................45
6.1.10 BANK1 Register(0xB0~0xBF) : MPP.............................................................................................45
6.1.11 BANK1 Register(0xC2~0xCE) : OUTPUT PORT ..........................................................................45
6.1.12 BANK2 Register(0x00~0x1F) : MOTION .......................................................................................46
6.1.13 BANK3~4 Register(0x00~0x7F / 0x80~0xFF ) : COAXIAL ...........................................................47
6.1.14 BANK3~4 Register(0x00~0x1F / 0x80~0x9F ) : COAXIAL CH1~4 ...............................................48
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6.1.15 BANK3~4 Register(0x20~0x5D / 0xA0~0xDD ) : COAXIAL CH1~4 .............................................49
6.1.16 BANK3~4 Register(0x60~0x7F / 0xE0~0xFF ) : COAXIAL CH1~4 ..............................................50
6.2 Register Detail Description .......................................................................................................................51
6.2.1 VIDEO Registers............................................................................................................................51
6.2.2 Enable Registers ...........................................................................................................................60
6.2.3 State Registers ..............................................................................................................................62
6.2.4 AUDIO Registers ...........................................................................................................................67
6.2.5 Power Down Registers ..................................................................................................................76
6.2.6 MPP Control Registers ..................................................................................................................77
6.2.7 Video Output Control Registers .....................................................................................................78
6.2.8 MOTION Registers ........................................................................................................................80
6.2.9 COAXIAL Registers .......................................................................................................................81
Chapter 7 Guide Note ...........................................................................................................................................87
7.1 Video Format Setting Register .................................................................................................................87
7.2 Each Format FSC Setting Register ..........................................................................................................87
7.3 When Auto Detection, Video Format Classifier ........................................................................................88
7.4 Coaxial Setting Register ...........................................................................................................................88
Chapter 8 ELECTRICAL CHARACTERISTICS ....................................................................................................89
8.1 ABSOLUTE MAXIMUM RATINGS ...........................................................................................................89
8.2 RECOMMENDED OPERATING CONDITION .........................................................................................89
8.3 DC CHARACTERISTICS .........................................................................................................................89
8.4 AC CHARACTERISTICS ..........................................................................................................................90
Chapter 9 AUDIO SYSTEM APPLICATIONS .......................................................................................................91
9.1 AUDIO 4-Channel Mode ...........................................................................................................................91
9.2 AUDIO 8-Channel Mode ...........................................................................................................................91
9.3 AUDIO 16-Channel Mode .........................................................................................................................92
Chapter 10 PACKAGE INFORMATION ...............................................................................................................93

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Contents of Tables
Table 1.1 NVP6134C PIN Description ............................................................................................................10
Table 2.1 NVP6134C INPUT VIDEO IMAGE FORMATS ...............................................................................12
Table 2.2 Data Output Pin Order Control ........................................................................................................16
Table 2.3 Output Clock and Data Direction Control ........................................................................................16
Table 2.4 1Port 1-Channel Normal mode or X-Format Setting .......................................................................20
Table 3.1 Sampling & PCM coding setting ......................................................................................................27
Table 3.2 Record Output Interface configuration ............................................................................................28

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CONTENTS OF FIGURES
Figure 1.1 Pin Assignments ..............................................................................................................................8
Figure 2.1 Universal RX Video Processing of NVP6134C .............................................................................. 11
Figure 2.2 Anti-aliasing Filter characteristic ....................................................................................................13
Figure 2.3 Band Split Filter Characteristic ......................................................................................................14
Figure 2.4 Peaking Filter Characteristic ..........................................................................................................14
Figure 2.5 Chroma Process ............................................................................................................................15
Figure 2.6 Chroma Low Pass filter Characteristic...........................................................................................15
Figure 2.7 Region of active is constant ...........................................................................................................17
Figure 2.8 BT.601 Interface .............................................................................................................................17
Figure 2.9 AHD720P@30P/25P, 60P/50P Horizontal Timing Diagram ...........................................................18
Figure 2.10 AHD720P@30P/25P, 60P/50P Vertical Timing Diagram .............................................................18
Figure 2.11 AHD1080P@30P/25P Horizontal Timing Diagram ......................................................................19
Figure 2.12 AHD1080P@30P/25P Vertical Timing Diagram ..........................................................................19
Figure 2.13 Block Diagram of Single-Channel Output ....................................................................................20
Figure 2.14 Block Diagram of of Multiplexed 2-Channels Output ...................................................................21
Figure 2.15 Block Diagram of Multiplexed 4-Channels Output .......................................................................22
Figure 2.16 NVP6134C generate 297MHz(1Port 4-CH) data output..............................................................23
Figure 2.17 NVP6134C Select Channel ID .....................................................................................................23
Figure 2.18 Method for Control Video Frame .................................................................................................25
Figure 2.19 Motion Block Mapping..................................................................................................................26
Figure 3.1 Timing of I2S mode ........................................................................................................................28
Figure 3.2 Timing of DSP mode ......................................................................................................................28
Figure 3.3 Timing of SSP mode ......................................................................................................................29
Figure 3.4 audio 2/4/8/16 channels data output <I2S mode, 256fs> ..............................................................29
Figure 3.5 audio 2/4/8/16channels data output <DSP/SSP mode, 256fs> .....................................................29
Figure 3.6 audio 2/4/6/8/16 channels data output(with 2 channels mic) <I2S mode, 320fs> .........................30
Figure 3.7 audio 2/4/8/16 channels data output(with 2 channels mic) <DSP/SSP mode, 320fs> ..................30
Figure 3.8 ADATA_SP Output <I2S mode> ....................................................................................................31
Figure 3.9 ADATA_SP Output <DSP/SSP mode> ..........................................................................................31
Figure 3.10 Consist of Cascade System using 4-NVP6134C .........................................................................32
Figure 4.1 Coaxitron Active line ......................................................................................................................33
Figure 4.2 Description of One Coaxitron Bit ...................................................................................................33
Figure 4.3 Coaxitron Bit Timing.......................................................................................................................33
Figure 4.4 Data Structure of Coaxitron Origins (VBI 18th) .............................................................................34
Figure 4.5 A-CP Active line .............................................................................................................................34
Figure 4.6 Description of A-CP One Data Bit ..................................................................................................35
Figure 4.7 Data A-CP Bit Timing .....................................................................................................................35
Figure 4.8 Data Structure of Coaxitron Origins (VBI 17th) .............................................................................35
Figure 5.1 I2C Timing Diagram .......................................................................................................................36
Figure 5.2 I2C Slave Address Configuration ...................................................................................................36
Figure 8.1 SCL and SDA Timing Diagram.......................................................................................................90
Figure 9.1 AUDIO 4-channel Mode .................................................................................................................91
Figure 9.2 AUDIO 8-channel Mode .................................................................................................................91
Figure 9.3 AUDIO 16-channel Mode ...............................................................................................................92
Figure 10.1 NVP6134C 76Pin Package Information ......................................................................................93

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Chapter 1
PIN INFORMATION
1.1 PIN ASSIGNMENTS
ADATA_CASI
ASYNC_PB
ADATA_PB
ACLK_PB
VDD3A
VDD3A
VDD1D
VDD3D
MPP1
MPP2
MPP3
MPP4
RSTB
TEST
VIN1
SDA
SCL
SA1
SA0
76 75 74 73 72 71 70 68 67 66 65 64 63 62 61 60 59 58
69
57
VIN2 ACLK_REC
1
56
VDD1A ASYNC_REC
2
55
VDD1A VDD1D
3
54
VDD3A ADATA_REC
4
53
VDD3A ADATA_SP
5
52
VIN3 ADATA_CASO
6
51
IRQ
7
N.C
50
VDD3D
8
VIN4
NVP6134C
49
VDD1A VDO2_7
9
76eQFN 9X9
48
10
VDD1A VDO2_6
47
11
VDD3D VDO2_5
46
12
VDD1D VDO2_4
13
45
VDD3A VDO2_3
14
44
N.C VDO2_2
15
43
N.C VDO2_1
16
N.C 42 VDO2_0
17
41
MICIN VCLK2
18
40
AIN1 VDD1D
39
19
VDD1A VDO1_7
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
VDD1PLL
VREF
AOUT
AIN2
AIN3
AIN4
VDD3A
VDD1D
SYS_CLK
N.C
VCLK1
VDO1_0
VDO1_1
VDO1_2
VDO1_3
VDD3D
VDO1_4
VDO1_5
VDO1_6
Figure 1.1 Pin Assignments

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1.2 PIN DESCRIPTION
Module Name
NAME IO DESCRIPTION PIN NO.
System Service
RSTB DI System Reset(Active Low) 62
SYS_CLK DI Oscillator Input (27MHz) 28
TEST I Chip Test mode selection PIN (Normally Connect to Ground) 73
Analog Input Interface
VIN1 AI Analog Video Input 1 76
AIN1 AI Analog Audio Input1 18
MICIN AI Analog Mic Input 17
ETC
IRQ O Interrupt Request Output 51
ACLK_REC B Clock for Record (M:output, S:Input) 57
ASYNC_REC B Sync for Record(M:output, S:Input) 56
ADATA_REC O Audio Digital Data for Record 54
ADATA_SP O Audio Digital Data for Speaker 53
ADATA_CASO O Audio Digital Data for Cascade Output 52
ADATA_CASI I Audio Digital Data for Cascade Input 61
ACLK_PB B Clock for Playback (M:output, S:Input) 60
ASYNC_PB B Sync for Playback (M:output, S:Input) 59
ADATA_PB I Audio Digital Data for Playback 58
MPP1 O Coaxial Output1 69
DIGITAL Video Interface
VCLK1 O Video Output Clock1 30
VDO1[7] O Video Data Output 1[7] 39
VCLK2 O Video Output Clock2 41

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AUDIO DAC
AOUT AO Analog Audio Output 24
VREF AO Audio DAC Voltage Reference Output 25
I2C Interface
SCL I I2C Interface Clock (3.3V tolerant) 64
SDA B I2C Interface R/W Data (3.3V tolerant) 63
SA0 I Pin1 for Slave Address 70
SA1 I Pin2 for Slave Address 71
Power
VDD1PLL P PLL Analog Power (1.2V) 26
12, 27, 40,
VDD1D P Digital Power (Digital1.2V)
55, 72
VDD3D P Digital Power (Digital 3.3V) 11, 35, 50, 65
2, 3, 9,
VDD1A P Analog Power (Analog 1.2V)
10, 19
4, 5, 13, 23,
VDD3A P Analog Power (Analog 3.3V)
74, 75
No Connect Pin
7, 14, 15,
NC NC Open
16, 29
Ground
PAD_GND G Exposed Pad 77
Table 1.1 NVP6134C PIN Description

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Chapter 2
UNIVERSAL RX(1M,2M, and 3/4/5M_NRT)
NVP6134C is a 4-Channel Universal RX which delivers high quality images. It accepts separate 4-Channel Universal Inputs from Camera and
the other video signal sources.
It digitizes and decodes 4-Channel Universal 1M, 2M and 3/4/5M NRT video formats into digital component video which represents 8-bit ITU-R
BT.656/1120 4:2:2 format and Sync Separate BT.601 Format with 27/36/37.125MHz, 54/72/74.25MHz and 108/144/148.5/297MHz multiplexed.
54/72/74.25/108/144/148.5/297MHz multiplex function is available, because it is in the range of Clock PLL.
NVP6134C includes 4-Channel analog processing circuit that comprises anti-aliasing filter, ADC, CLAMP and Equalizer filter. It shows the best
image quality by adaptive high performance comb filter and vertical peaking filter. It also supports programmable Saturation, Hue, Brightness,
Contrast and several function such as CTI, Programmable peaking filter and various compensation filters.
2.1 FUNCTIONAL OVERVIEW

The Universal 1M, 2M and 3/4/5M NRT RX separates luminance and chrominance signals from Universal Inputs. Figure 2.1 show the block
diagram of the NVP6134C video processing.
Analog Luma
CLAMP Anti Format Processing CLK
& Aliasing ADC Genlock Auto YCS
8Bit-BT.601/ BT.656/
Equalizer Filter Detector Chroma BT.1120 Data
filter Processing
Universal Output
Inputs Formatter
V_SYNC(BT.601)
H_SYNC(BT.601)
I2C
Figure 2.1 Universal RX Video Processing of NVP6134C
The First step to decode Universal RX is to digitize the entire video signal using an A/D converter (ADC). Video inputs are usually AC-coupled
and have a 75 Ohm AC and DC input impedance. As a result, the video signal must be DC restored every scan line during horizontal sync to
position the sync tips at known voltage level using the AGC/CLAMP logic.(AGC)
NVP6134C decides the attenuated image signal level via cable by EQ pattern; compensates the attenuated image signals by equalizer
compensation filter. (EQ Pattern)
The video signal also is low-pass filtered in Anti aliasing Filter to remove any high-frequency components that may result in aliasing.
Vertical sync and horizontal sync information are recovered in Genlock block.
In regard to various video formats, NVP6134C has the auto detection module for these video formats which uses different H/V Sync length
according to each formats. (Video Standard Auto Detection)
When composite video signal is decoded, the luminance and chrominance are separated by YCS(Y/C Separator).
The quality of decoded image is strongly dependent on the signal quality of separated Y and C. To achieve best quality of image, Adaptive
Comb Filter is used.
The color demodulator in chroma processing block accepts modulated chrominance data from Adaptive Comb Filter which generate Cb/Cr color
difference data. During active video period, the chrominance data is demodulated using sin and cos subcarrier data.

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2.2 VIDEO INPUT FORMATS
NVP6134C supports Universal Video Formats. Table 2.1 show various Video Formats and Register Setting Value (VIDEO_FORMAT,
0x08~0B[4:0], Bank0/ AHD_MD, 0x81~84[3:0], Bank0/ SPL_MD, 0x85~89[3:0], Bank0 ) to support them.
SPL_MD AHD_MD VIDEO_FORMAT

FORMAT HZ HxV Fsc(MHz) ( Bank0, ( Bank0, ( Bank0,
0x85~89[3:0] ) 0x81~84[3:0] ) 0x08~0B[4:0] )
720x240
NTSC-M,J 59.94 3.579545 0x00
960x240
720x240
NTSC-4.43 59.94 4.43361875 0x11
960x240
720x288
PAL-B,D,G,H,I 50 4.43361875 0x1D
960x288
0x0 0x0
720x240
PAL-M 59.94 3.57561149 0x16
960x240
720x288
PAL-Nc 50 3.58205625 0x1F
960x288
720x240
PAL-60 60 4.433619 0x15
960x240
AHD_5M_12.5P 12.5 2592x1944 Flexible
AHD_4M_15P 15 2560x1440 Flexible 0x4 0x4
AHD_3M_18P 18 2048x1536 Flexible
AHD_1080_30 30 1920x1080 Flexible 0x2
AHD_1080_25 25 1920x1080 Flexible 0x3 Don’t care
AHD_720_60 60 1280x720 Flexible 0x4

0x0
AHD_720_50 50 1280x720 Flexible 0x5
AHD_720_30 30 1280x720 Flexible 0x6
AHD_720_25 25 1280x720 Flexible 0x7
Table 2.1 NVP6134C INPUT VIDEO IMAGE FORMATS

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2.3 ANALOG FRONT END (CLAMP, ANTI-ALIASING FILTER, EQ FILTER)
NVP6134C includes 4 Channel Analog Processing circuits that comprise anti-aliasing filter, EQ Filter, ADC and CLAMP. Because its design is
dedicated for video application, Analog Processing circuit does not require external reference circuit. External coupling capacitance only is
needed for NVP6134C. Figure 2.2 demonstrates the bode plot of Anti-aliasing Filter. Anti-aliasing Filter is controlled by Register and include
bypass mode that don’t have AFE filtering.
Figure 2.2 Anti-aliasing Filter characteristic
2.4 GENLOCK (ROBUST SYNC DETECTION, ROBUST NO-VIDEO DETECTION)

NVP6134C provides a fully digital Genlocking circuitry. The digital Genlocking Circuitry use the locking method of the timing control signals such
as horizontal sync, vertical sync, and the color subcarrier.
NVP6134C uses the proprietary Genlock mechanism for video application system.
It supports very Robust Sync Detection & Robust No-Video Detection, and it is also showed reliable operation in Non-standard signal and
Weak-signal.

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2.5 YCS (Y/C SEPARATOR)
The YCS is used to separate Y and C signal from Universal standard video signal. Therefore, The output image is sharper and clearer
compared to other device. To achieve this, BSF(Band Split Filter) is used. Figure 2.3. shows partial Characteristic of BSF. According to Input
signal format, BSF characteristic can be selected.
Figure 2.3 Band Split Filter Characteristic
NVP6134C can also separate Y signal from C signal out of input CVBS using the Notch Filter. And according to internal criteria in the
NVP6134C, the Notch and Comb filters can be mixed for use. In special case, use the Notch filter to separate Y signal from C signal to have a
good-quality image.
2.6 LUMA PROCESSING

The high-frequency range of Y/C separated data has a relatively smaller magnitude than the low-frequency range. The high-frequency range
makes the image more distinct and remarkable, but may induce worse coding efficiencies when video signal is compressed.
Figure 2.4. shows Peaking Filter Characteristic. NVP6134C provides the peaking filter and Gain control for emphasizing or depressing the high-
frequency area to avoid this problem. The Peaking filter is applied to this purpose and its characteristics can be controlled by register
(Y_PEAK_MODE, 0x18[7:4] / 0x19[7:4] / 0x1A[7:4] / 0x1B[7:4], Bank0) via I2C interface.
Figure 2.4 Peaking Filter Characteristic
2.7 CHROMA PROCESSING

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The Chroma Processing mainly consists of 3 parts: demodulation, filtering, and ACC(Automatic Chroma-gain Control). The Chroma
Demodulator receives modulated chroma from YC separator, and generates demodulated color difference data. Demodulated data must be low-
pass filtered to reduce anti-aliasing artifacts.
Figure 2.5. shows chroma demodulation and filtering process. Chroma LPF frequency characteristics is demonstrated in Figure 2.6.
Users can select the chroma filter through I2C interface (CLPF_SEL, 0x21/25/29/2D[3:0], Bank0).
Figure 2.5 Chroma Process
Figure 2.6 Chroma Low Pass filter Characteristic

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2.8 DATA OUTPUT ORDER & DIRECTION CONTROL
NVP6134C can change the order of the output pin in the All Output Mode as shown in Table 2.2. (OUT_DATA_x_INV, 0xCB[2:1] Bank1)
Furthermore, as Clock and Data pins control direction so may it does nothing with interconnected back-end device and how control related
control register as shown in Table 2.3. ( VCLK_x_EN, 0xCA[6:5] Bank1 / VDO_x_EN, 0xCA[2:1] Bank1 )
Address (Bank1) state Data Output of Port X
0 VDO_1 [7:0]
0xCB[1], OUT_DATA_1_INV
1 VDO_1 [0:7]
0 VDO_2 [7:0]
0xCB[2], OUT_DATA_2_INV
1 VDO_2 [0:7]
Table 2.2 Data Output Pin Order Control
Address (Bank1) state Data Output of Port X
0 HI-Z
0xCA[5], VCLK_1_EN
1 Output VCLK_1 Enable
0 HI-Z
0xCA[6], VCLK_2_EN
1 Output VCLK_2 Enable
0 HI-Z
0xCA[1], VDO_1_EN
1 Output DATA1 Enable
0 HI-Z
0xCA[2], VDO_2_EN
1 Output DATA2 Enable
Table 2.3 Output Clock and Data Direction Control

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2.9 OUTPUT FORMAT
NVP6134C supports a format of standard ITU-R BT.656/1120. Ports of 2 is synchronized by each output clock(VCLK_A~VCLK_B). Phase of
clock is controlled by VCLK_SEL(BANK1, 0xCD[7:4]/0xCE[7:4]) and VCLK_DLY_SEL(BANK1, 0xCD[3:0]/0xCE[3:0]).
2.9.1 ITU-R BT.656/BT.1120 FORMAT

Codes of SAV and EAV are injected into data stream of ITU-R BT.656/1120 to indicate a start and a end of active. Note that a number of pixel for
1H active line is always constant regardless of the actual incoming line length. Therefore, variance of analog input signal is applied to a blank
section except codes of EAV and SAV. Figure 2.7 shows data stream of ITU-R BT.656/1120 format. If length of 1H of analog input signal
increase or decrease, number of pixel of 'A' increase or decrease.
VCLK
VDO[7:0] FF’h 00’h 00’h XY’h 80’h 10’h 80’h 10’h FF’h 00’h 00’h XY’h Cb Y Cr Y Cb Y Cr Y
EAV Code A SAV Code Active number of pixel Data
HACTIVE
Figure 2.7 Region of active is constant
2.9.2 ITU-R BT.601 FORMAT

NVP6134C support a standard format of ITU-R BT.601. BT.601 Interface consist of 4 component, 8bit-Video Data, Video Clock, H-SYNC and
V-Sync(Figure2.8). NVP6134C can output H/V-SYNC through MPP1~4 pin and Support up to AHD 1080@25/30P two channels.
Figure 2.8 BT.601 Interface

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2.9.3 VIDEO OUTPUT TIMING INFORMATION
The NVP6134C output timing is like with SD resolution. But some synchronous signals difference with SD resolution as Field information that
does not separated EVEN/ODD field. There is next sentence shown timing diagram point of video output.
2.9.3.1 AHD720P @ 30P/25P, 60P/50P H/V Timing
H Blank Signal
Next
Start of Digital Line Start of Digital Active Line
Line
EAV Code Blanking SAV Code

C C C C C 4:2:2
CH1 Y Y Y Y Y
FF 00 00 XY 80 10 80 10 80 10 FF 00 00 XY B
0
R
1
B
2
R
3
R
1279
FF Digital
DATA 0 0 2 2 1278 Video
4 732 / 1392 4 2560
3300 / 3960
CH1 CLK
74.25MHz for 720P @25/30P
148.5MHz for 720P @50/60P
Figure 2.9 AHD720P@30P/25P, 60P/50P Horizontal Timing Diagram
Figure 2.10 AHD720P@30P/25P, 60P/50P Vertical Timing Diagram

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2.9.3.2 AHD1080P @ 30P/25P H/V Timing
H Blank Signal
Next
Start of Digital Line Start of Digital Active Line
Line
EAV Code Blanking SAV Code

C C C C C 4:2:2
CH1 Y Y Y Y Y
FF 00 00 XY 80 10 80 10 80 10 FF 00 00 XY B
0
R
1
B
2
R
3
R
1919
FF Digital
DATA 0 0 2 2 1918 Video
4 552 / 1432 4 3840
4400 / 5280
CH1 CLK
@148.5MHz
Figure 2.11 AHD1080P@30P/25P Horizontal Timing Diagram
Figure 2.12 AHD1080P@30P/25P Vertical Timing Diagram

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2.10 OUTPUT MODE
The NVP6134C output to the back-end devices whether transferring a channel by a port or 2/4-channels multiplexed output by a port. It is that
as much as possible multiplexed channels by a port’s output frequency same to sum of multiplexed video’s frequency. The NVP6134C supports
Variable Output Data Rate.
2.10.1 SINGLE OUTPUT MODE

Codes of SAV and EAV are injected into data stream of ITU-Basically, a video channel output through a port. NVP6134C output 2-clocks that
VCLK1~2 and output 2-data that VDO1~2. There is timing as shown in Figure 2.13. For VCLK1~2 phase adjustment can be made against
VDO1~VDO2 using "Clock Delay Control" Registers(Bank1 0xCD ~ CE).
ADDRESS
REGISTER NAME BITS VALUE DESCRIPTION
Bank Addr
VPORT_x_SEQy
0xC2 VPORT_1_SEQ1 [3:0] 0x0 : Select the type of output video signal through each video output port
(x = VDO output port number, y= channel count for 1-port)
0 : Nomal Display of Channel 1 8 : H_half Display of Channel 1

0xC4 VPORT_2_SEQ1 [3:0] 0x1 2 : Nomal Display of Channel 3 A : H_half Display of Channel 3
3 : Nomal Display of Channel 4 B : H_half Display of Channel 4
1 Etc.: Don’t use

VPORT_x_CH_OUT_SEL
: Select the output form of the data generated in case that the system is not
0xC8 VPORT_1_CH_OUT_SEL [7:4] 0x0
set at No Video. (x = VDO output port number)
0 : 1-Port 1CH data

2 : 1-Port 2CH time-mixed data
Etc.: Don’t use
Table 2.4 1Port 1-Channel Normal mode or X-Format Setting
ch1~4 ch1
Muxing
ch1~4 ch2
Muxing VDOx
time
ch1~4 ch3
Muxing multiplexer VCLKx
ch1~4 ch4
Muxing
VPORTx_SEQx
* Channel 1 data
All Port
(VDO1~VDO2) CH1-a CH1-b
CHx_OUT_SEL
VCLK1~VCLK2
data of CH1
0
data of mixed CH1,2 VDOx
2
data of mixed CH1,2,3,4
8
CHx_OUT_SEL
Figure 2.13 Block Diagram of Single-Channel Output

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2.10.2 2-MULTIPLEX OUTPUT MODE
In the 2-Multiplex Output Mode, NVP6134C outputs multiplexed 2-channels video through one port. Also, NVP6134C supports the 1Port 2-
Channel X-Format Mode. X-Format lowers the Horizontal Frequency in half.
1Port-2CH Normal or Horizontal half mode Setting Value is as below.(Table2. 5)
ADDRESS VALUE
REGISTER NAME BITS Normal X_ DESCRIPTION
Bank Addr
MODE MODE
VPORT_1_SEQ1 [3:0] VPORT_x_SEQy

0xC2 0x10 0x98 : Select the type of output video signal through each video output port
VPORT_1_SEQ2 [7:4] (x = VDO output port number, y= channel count for 1-port)

VPORT_2_SEQ1 [3:0] 1 : Nomal Display of Channel 2 9 : H_half Display of Channel 2
0xC4 0x32 0xBA 2 : Nomal Display of Channel 3 A : H_half Display of Channel 3
3 : Nomal Display of Channel 4 B : H_half Display of Channel 4
VPORT_2_SEQ2 [7:4]
1 Etc.: Don’t use
VPORT_x_CH_OUT_SEL
: Select the output form of the data generated in case that the system is
not set at No Video. (x = VDO output port number)
0 : 1-Port 1CH data

Etc.: Don’t use
Figure2.14 shown as multiplexed with 2-channels video output to VDO1~VDO2. For VCLK1~VCLK2 phase adjustment can be made against
VDO1~VDO2 using "Clock Delay Control" Register(Bank1 0xCD ~ CE).
ch1~4 ch1
Muxing
ch1~4 ch2
Muxing
VDOx
ch1~4 ch3 time
Muxing multiplexer
VCLKx * Channel 1,2 data muxed
ch1~4 ch4
Muxing
All Port
CH1 CH2 CH1 CH2
VPORTx_SEQx (VDO1~VDO2)
Dual Edge Clock

(VCLK1~VCLK2)
CHx_OUT_SEL
Single Edge Clock
(VCLK1~VCLK2)
data of CH1
0
2 Separated data 1 CH1 CH1
data of mixed CH1,2,3,4
8
Separated data 2 CH2 CH2 CH2
CHx_OUT_SEL
Figure 2.14 Block Diagram of of Multiplexed 2-Channels Output

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2.10.3 4-MULTIPLEX OUTPUT MODE
In the 4-Multiplex Output Mode, NVP6134C outputs multiplexed 4-channels video through one port. Also, NVP6134C supports the 1Port 4-
Channels X-Format Mode. X-Format lowers the Horizontal Frequency in half.
1Port-4CH Normal or Horizontal half mode Setting Value is as below. (Table 2.6)
ADDRESS VALUE
REGISTER NAME BITS Normal X_ DESCRIPTION
Bank Addr
MODE MODE
VPORT_1_SEQ1 [3:0] 0x10 0x98

0xC2 VPORT_x_SEQy
VPORT_1_SEQ2 [7:4] 0x32 0xBA : Select the type of output video signal through each video output port
(x = VDO output port number, y= channel count for 1-port)
VPORT_1_SEQ3 [3:0] 0x10 0x98

0xC3
VPORT_1_SEQ4 [7:4] 0x32 0xBA

VPORT_2_SEQ1 [3:0] 0x10 0x98
0xC4
2 : Nomal Display of Channel 3 A : H_half Display of Channel 3
VPORT_2_SEQ2 [7:4] 0x32 0xBA B : H_half Display of Channel 4
3 : Nomal Display of Channel 4
1
VPORT_2_SEQ3 [3:0] 0x10 0x98
Etc.: Don’t use
0xC5
VPORT_2_SEQ4 [7:4] 0x32 0xBA
VPORT_x_CH_OUT_SEL
0xC8 VPORT_1_CH_OUT_SEL [3:0] 0x8 : Select the output form of the data generated in case that the system is
not set at No Video. (x = VDO output port number)
0 : 1-Port 1CH data
0xC9 0x8 8 : 1-Port 4CH time-mixed data

VPORT_2_CH_OUT_SEL [7:4]
Etc.: Don’t use
NVP6134C support the 297MHz 1Port 4CH HD Data Out Mode. Four Channels HD data stream represents 8bit BT.656/1120 4:2:2 format with
297MHz multiplexed. Figure2.15 shown as multiplexed with 4-channels video output to VDO1~VDO2. For VCLK1~VCLK2 phase adjustment
can be made against VDO1~VDO2 using "Clock Delay Control" Register.
ch1~4 ch1
Muxing
ch1~4 ch2 * Channel 1,2,3,4 data muxed

VDOx
Muxing
time
ch1~4 ch3 All Port
Muxing multiplexer VCLKx CH1 CH2 CH3 CH4
(VDO1~VDO2)
ch1~4 ch4
Muxing Dual Edge Clock
(VCLK1~VCLK2)
VPORTx_SEQx
Single Edge Clock

CHx_OUT_SEL (VCLK1~VCLK2)
data of CH1 Separated data 1 CH1

0
2
data of mixed CH1,2,3,4 Separated data 2 CH2 CH2
8
CHx_OUT_SEL Separated data 3 CH3 CH3
Separated data 4 CH4 CH4
Figure 2.15 Block Diagram of Multiplexed 4-Channels Output

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￭ Example of 297MHz 1Port 4-Channels Data Output Mode with Channel ID
1. In case of VDO1 output port and VCLK1 output clock use.
2. Set VDO1 output(CH_OUT_SEL1, BANK1, 0xC8[7:4] = 0x8) and VCLK1 output (VCLK1_SEL, BANK1,0xCD[7:4] = 0x4 or 0x5) .
3. Set Channel ID Type (Refer to CHID_TYPE(Bank0, 0x54[2:0]) Register Description)
4. And then NVP6134C generate 297MHz(1Port 4CH) data output (Figure 2.16)
If you want to confirm the 297MHz Data using FPGA or Other device, Execute 5~11 item in next page.
297MHz data output

CH1 VIN1
VDO1
CH2 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4
VIN2
CH3 VCLK1
VIN3 NVP
DECODER Dual edge
CH4 VIN4
clock
27MHz OSC
PLL
74.25MHz data
CH1 CH1 CH1 CH1
297MHz data output

CH2 CH1 CH2 CH1
CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4
CH3 CH1 CH3 CH1
CH4 CH1 CH4 CH1
Figure 2.16 NVP6134C generate 297MHz(1Port 4-CH) data output
5. FPGA or equivalent devices which is input 297MHz time multiplexed data output, need to align with same channel data.
(74.25MHz 1,2,3,4 channel). Figure2.17. shows how to use Channel ID as a example.
vertical blank vertical active vertical blank vertical active
CHID_TYPE
(0x54[2:0],BANK0 = 0x1)
horizontal blank horizontal active
EAV SAV
CHID_VIN1 (0x55[3:0],BANK0 = 0x0) FF 00 00 0xD0 FF 00 00
0xC0
EAV SAV 7 6 5 4 3 2 1 0
0xC1
1 F V H CHID_VINx
EAV SAV
0xC2 EAV or SAV
EAV SAV
0xC3
CH3 CH3 CH3 CH3 CH3 CH3

297MHz DATA FF CH4 CH1 CH2 00 CH4 CH1 CH2 00 CH4 CH1 CH2 D2 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 CH2
(0xC8[7:4],BANK1 = 0x8)
148.5MHz Dual Edge clock
(0xCD[6:4],BANK1= 0x4)
CH_ID Counter 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 3 0 1 2 3 0 1 2 3 0 1
Detect(ff,00,00) & CH_ID
EAV/SAV check Change!!
CH1 : 74.25MHz output FF 00 00 D2 CH1 CH1 CH1
CH2 : 74.25MHz output CH4 CH4 CH4 CH4 CH2 CH2
CH3 : 74.25MHz output CH1 CH1 CH1 CH1 CH3 CH3
CH4 : 74.25MHz output CH2 CH2 CH2 CH2 CH4 CH4 CH4
Wrong sorting Right sorting

Application
or FPGA, etc.
Figure 2.17 NVP6134C Select Channel ID

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6. CHID_TYPE(BANK0, 0x54[2:0]=001) mode described in top of Figure2.17.
7. To generate 2bit digit, Design 2bit counter with VCLK1 (The 2bit digit means each channel).
8. Using 2bit digit, Convert from 297MHz Data to 74.25MHz Data (Wrong sorting part in Figure2.17.) and then Define the 2bit digit
( 0 : Ch1 data, 1 : Ch2 data, 2 : Ch3 data, 3 : Ch4 data).
namely, 297MHz data output separate only with 74.25MHz, 4channel data, is not align with channel data where becomes mapping
in counter value.
9. For mapping between separated each channel data and specified counter value, Select channel among separated each channel
(1CH selected in Figure2.17.). If selected channel data become Right sorting condition, other 3 channel is sorted automatically.
10. Check the 1ch data output when 2bit counter value is only '0' and then Search the EAV/SAV[3:0] after FF 00 00 Code.
11. If the EAV/SAV[3:0] is '2', make a counter reset to '3' (Refer to Blue color in Figure2.17.)
12. Become Right sorting part.

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2.11 297MHz INTERFACE AND MULTI STANDARD OUTPUT MODE
NVP6134C supports the frequency of output data up to 297MHz at maximum. Two Channel FHD data stream represents 8bit BT.656/1120 4:2:2
format with 297MHz multiplexed 1-port. Also, NVP6134C can output 2ch or 4ch signals with different standards(CVBS, 720p, 1080p,
3/4/5M_NRT) through 1-port.
Avaliable output combinations are as below.
(1) 1-port 2-Channel combination
a. CVBS + 720P, CVBS + 720P, CVBS + 3M_NRT
b. 720P + 1080P, 720P + 3M_NRT
c. 1080P + 3M_NRT
(2) 1-port 4-Channel combination

a. CVBS 2CH + 720P 2CH
b. CVBS 2CH + 1080P_X 2CH
c. CVBS + 720P + 1080P_X 2CH
d. 720P 4CH
e.1080P_X 4CH
2.12 Video Frame Control

The NVP6134C supports that a frame control of video output. So it is function that the decoder’s output masking by the EAV/SAV make to
blank region. If set to FRM_NRT_ON is High, so output finally which set by FRM_NRT_SEQ[29:0] that each a bit of FRM_NRT_SEQ[29:0]
match to each a frame. And the FRM_NRT_SEQ rotates continuous then to end from
FRM_NRT_SEQ[0] to FRM_NRT_SEQ[29]. If the FRAME_NRT_SEQ bit set to Low, a apply frame has blank region. So, It received back-end
device nothing to do because is not active region.
SAV SAV SAV SAV
CH CH CH CH
FRM#1 FRM#2 FRM#3 FRM#4
1 1 1 1
FRAME_NRT_SEQ [0] = HIGH [1] = HIGH [2] = HIGH [3] = HIGH [29:4]
SAV SAV
CH CH CH CH
FRM#1 BLANK FRM#3 BLANK
1 1 1 1
FRAME_NRT_SEQ [0] = HIGH [1] = LOW [2] = HIGH [3] = LOW [29:4]
Figure 2.18 Method for Control Video Frame

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2.13 MOTION DETECTOR
NVP6134C supports 4-Channels motion detection function. It supports the output of the detected motion information on the screen. The
function allows a screen such as the one shown in Figure 2.19. to be divided in 192 sections each of which can generate information on the
motion detection information.
For each section, motion detection can be controlled to be set at on/off. Once a motion is detected, the screen can be rendered dark or reversed
in the unit of field to have the spot of the motion generated to be indicated in the screen.
Figure 2.19 Motion Block Mapping

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Chapter 3
AUDIO CODEC
NVP6134C outputs PCM digital audio signals converted from analog audio input signals and analog audio signals converted from PCM digital
audio signals. NVP6134C has 5 channels ADC and 1 channel DAC for audio signal.
Audio data convert to G.711 PCM and Linear PCM data, and these converted data is outputted via DSP/SSP/I2S interfaces. The output data will
be saved at hard disk or any other storages. This process - to convert and save audio data into storage - is usually called as "Record Output".
The saved audio data is inputted to NVP6134C via DSP/SSP/I2S interfaces. The input audio data is outputted via audio DAC. This process is
named as "Playback Output".
NVP6134C selects one audio input signal among 5 analog audio input(4-Ch Audio/1-Ch mic) and this audio is outputted through audio ADC and
audio DAC. And it also supports directly mixed audio output signal which 5 analog audio inputs are mixed. This function usually is called by "Live
Output".
In addition, NVP6134C supports audio mute detection and cascade function up to 4 chips - audio 18 channels (16-Ch Audio/2-Ch mic)
3.1 Record Output
Analog audio data is converted to PCM data and this data is outputted to the other NVP6134C or other IC via DSP/SSP/I2S interfaces. Record
output is useful function to save compressed audio data into storage. Analog audio signal is finally outputted to ADATA_REC pin used for data of
each channel and ADATA_SP pin used for one mixed signal of each channel's data. The output data from ADATA_SP pin is either same data of
ADATA_REC pin or mixed signal of each channel's data.
PCM data is categorized based on sampling frequency, sampling data bit width and PCM method. G.711 (A-law/Mu-law), unsigned linear PCM
and linear PCM are supported. 8KHz / 16KHz and 8bit/16bit are used for sampling frequency and sampling data bit width, respectively. Refer
the following table when you set the register value.
BANK1
8K/8bit 8K/16bit 16K/8bit 16K/16bit 32K/8bit 32K/16bit
ADDR VALUE ADDR VALUE ADDR VALUE ADDR VALUE ADDR VALUE ADDR VALUE
0x00[0] 0 0x00[0] 0 0x00[0] 0 0x00[0] 0 0x00[0] 1 0x00[0] 1

Linear 0x07[3] 0 0x07[3] 0 0x07[3] 1 0x07[3] 1 0x07[3] 1 0x07[3] 1
PCM 0x07[2] 1 0x07[2] 0 0x07[2] 1 0x07[2] 0 0x07[2] 1 0x07[2] 0
0x08[5:4] 00 0x08[5:4] 00 0x08[5:4] 00 0x08[5:4] 00 0x08[5:4] 00 0x08[5:4] 00
0x00[0] 0 0x00[0] 0 0x00[0] 0 0x00[0] 0 0x00[0] 1 0x00[0] 1

Unsigned
0x07[3] 0 0x07[3] 0 0x07[3] 1 0x07[3] 1 0x07[3] 1 0x07[3] 1
Linear
0x07[2] 1 0x07[2] 0 0x07[2] 1 0x07[2] 0 0x07[2] 1 0x07[2] 0
PCM
0x08[5:4] 01 0x08[5:4] 01 0x08[5:4] 01 0x08[5:4] 01 0x08[5:4] 01 0x08[5:4] 01
0x00[0] 0 0x00[0] 0 0x00[0] 0 0x00[0] 0 0x00[0] 1 0x00[0] 1

0x07[3] 0 0x07[3] 0 0x07[3] 1 0x07[3] 1 0x07[3] 1 0x07[3] 1
G.711
0x07[2] 1 0x07[2] 0 0x07[2] 1 0x07[2] 0 0x07[2] 1 0x07[2] 0
U-law
0x08[5:4] 10 0x08[5:4] 10 0x08[5:4] 10 0x08[5:4] 10 0x08[5:4] 10 0x08[5:4] 10
0x08[6] 0 0x08[6] 0 0x08[6] 0 0x08[6] 0 0x08[6] 0 0x08[6] 0
0x00[0] 0 0x00[0] 0 0x00[0] 0 0x00[0] 0 0x00[0] 1 0x00[0] 1

0x07[3] 0 0x07[3] 0 0x07[3] 1 0x07[3] 1 0x07[3] 1 0x07[3] 1
G.711
0x07[2] 1 0x07[2] 0 0x07[2] 1 0x07[2] 0 0x07[2] 1 0x07[2] 0
A-law
0x08[5:4] 10 0x08[5:4] 10 0x08[5:4] 10 0x08[5:4] 10 0x08[5:4] 10 0x08[5:4] 10
0x08[6] 1 0x08[6] 1 0x08[6] 1 0x08[6] 1 0x08[6] 1 0x08[6] 1
Table 3.1 Sampling & PCM coding setting
DSP / SSP / I2S interfaces are supported as output data format. In addition, slave mode and master mode are also supported. At slave mode,
input clock and synchronized signal come from external ICs, however Master mode generates clock and synchronized signal in itself.

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3.1.1 Data Output Interface
NVP6134C outputs "Record Output" using ACLK_REC, ASYNC_REC, ADATA_REC and DATA_SP. ACLK_REC is a reference clock signal for
Record Output Data and ASYNC_REC is a reference synchronization signal for Record Output Data. ADATA_REC and ADATA_SP are
synchronized Record Output, data with reference clock and reference synchronized signal.
BANK1
DSP SSP I2S
ADDR VALUE ADDR VALUE ADDR VALUE
0x07[0] 1 0x07[0] 1 0x07[0] 0

Master 0x07[1] 0 0x07[1] 1 0x07[1] 0
0x07[7] 1 0x07[7] 1 0x07[7] 1
0x07[0] 1 0x07[0] 1 0x07[0] 0

Slave 0x07[1] 0 0x07[1] 1 0x07[1] 0
0x07[7] 0 0x07[7] 0 0x07[7] 0
Table 3.2 Record Output Interface configuration
ACLK_REC is a reference clock of Record Output Data and ASYNC_REC is reference synchronized signal. ACLK_REC and ASYNC_REC
signal support slave mode accepted external signals and master mode generating clock and synchronization signal in itself. And DSP/SSP/I2S
interfaces are supported by configuration of these pins defined by internal register setting value.
Figure 3.1, 3.2, 3.3 shows timing diagram of I2S, DSP, and SSP mode, respectively.
These figures show timing relation among ASYNC_REC, ACLK_REC and ADTA_REC, and ADATA_SP is outputted using same interface
method of ADATA_REC. Polarity of ACLK_REC clock is changed by setting of internal register value (RM_CLK, 0x07[6], BANK1).
1/fs
ASYNC_REC
ACLK_REC
ADATA_REC MSB MSB
data0 data1
Figure 3.1 Timing of I2S mode
1/fs
ASYNC_REC
ACLK_REC
ADATA_REC MSB MSB
data0 data1
Figure 3.2 Timing of DSP mode

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1/fs
ASYNC_REC
ACLK_REC
ADATA_REC MSB MSB
data0 data1
Figure 3.3 Timing of SSP mode
3.1.2 2/4/8/16-Channels Data Output(256 fs)

ADATA_REC supports up to 8 channel audio using single chip and up to 16 channels audio in cascade mode. In this case, the bit-rate of the
audio signal should be 256 fs(RM_BITRATE, 0x07[5:4], BANK1). The number of output channel is configured by internal register value
(R_MULTCH, 0x08[1:0], BANK1) and the order of output channel is configured by internal register value (R_SEQ, 0x09 ~ 0x12, / MIC_SEQ,
0x3C ~ 0x3D, BANK1).
Therefore, the order of audio output can be changed.
ASYNCR
ADATAR CH1 CH9

(R_MULTCH=0)
ADATAR CH1 CH2 CH9 CH10

(R_MULTCH=1)
ADATAR CH1 CH2 CH3 CH4 CH9 CH10 CH11 CH12

(R_MULTCH=2)
ADATAR
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16
(R_MULTCH=3)
Figure 3.4 audio 2/4/8/16 channels data output <I2S mode, 256fs>
ASYNCR
ADATAR
CH1 CH2
(R_MULTCH=0)
ADATAR
CH1 CH2 CH3 CH4
(R_MULTCH=1)
ADATAR
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
(R_MULTCH=2)
ADATAR
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16
(R_MULTCH=3)
Figure 3.5 audio 2/4/8/16channels data output <DSP/SSP mode, 256fs>

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3.1.3 2/4/8/16-Channels Audio Data Output with 4-Channels Mic Data(320 fs)
ADATA_REC supports up to 5 channels(4-Ch audio/1-Ch mic) using single chip and up to 18 channels(16-Ch audio/2-Ch mic) in cascade
mode. In this case, the bit-rate of the audio signal should be 320 fs(RM_BITRATE, 0x07[5:4], BANK1).
The number of output channel is configured by internal register value (R_MULTCH, 0x08[1:0], BANK1) and the order of output channel is
configured by internal register value (R_SEQ, 0x09 ~ 0x12, / MIC_SEQ, 0x3C ~ 0x3D, BANK1). Therefore, the order of audio output can be
changed.
ASYNCR
ADATAR
CH1 MIC1 N.A CH9 MIC2 N.A
(R_MULTCH=0)
ADATAR CH1 CH2 MIC1 N.A CH9 CH10 MIC2 N.A

(R_MULTCH=1)
ADATAR CH1 CH2 CH3 CH4 MIC1 N.A CH9 CH10 CH11 CH12 MIC2 N.A
(R_MULTCH=2)
ADATAR CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 MIC1 N.A CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 MIC2 N.A
(R_MULTCH=3)
* N.A = No Audio
Figure 3.6 audio 2/4/6/8/16 channels data output(with 2 channels mic) <I2S mode, 320fs>
ASYNCR
ADATAR
CH1 CH2 MIC1 N.A MIC2 N.A
(R_MULTCH=0)
ADATAR
CH1 CH2 CH3 CH4 MIC1 N.A MIC2 N.A
(R_MULTCH=1)
ADATAR
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 MIC1 N.A MIC2 N.A
(R_MULTCH=2)
ADATAR
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 MIC1 N.A MIC2 N.A
(R_MULTCH=3)
* N.A = No Audio
Figure 3.7 audio 2/4/8/16 channels data output(with 2 channels mic) <DSP/SSP mode, 320fs>

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3.1.4 ADATA_SP Output
ADATA_SP supports 3 kinds of output method. Firstly, the output data of ADATA_SP pin is the exactly same as those of ADATA_REC except
output data sequence. The order of output data is opposite. If the output data order of ADATA_REC is "CH1, CH2, CH9, CH10", the output data
order of ADATA_SP is "CH16, CH15, CH8, CH7". That is to say, two output pin - ADATA_SP and ADATA_REC are complement relationship.
Secondly, one of input signals is selected as output signal of ADATA_SP. The selectable input signal ranges from analog input signal to
ADATA_PB signal. Lastly, mixed data of input signal is selected as the output signal of ADATA_SP. The mixing gain of each channel's input
signal is determined by internal register setting value (MIX_RATIO, 0x16 ~ 0x21[7:0], BANK1).
The output configuration of ADATA_SP is determined by internal register setting. First and second configuration are determined by (R_ADATSP,
0x08[2], BANK1), and second and third configuration are determined by (L_CH_OUTSEL, 0x24[4:0], BANK1) and (R_CH_OUTSEL, 0x25[4:0],
BANK1). In this case, L_CH_OUTSEL and R_CH_OUTSEL select one of input channels or mixed data.
1/fs
ASYNC_REC
ADATA_REC CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16
ADATA_SP
L_CH_OUT R_CH_OUT
Figure 3.8 ADATA_SP Output <I2S mode>
1/fs
ASYNC_REC
ADATA_REC CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16
ADATA_SP
L_CH_OUT R_CH_OUT
Figure 3.9 ADATA_SP Output <DSP/SSP mode>

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3.2 Playback Output
Playback is to output stored audio data to external device through DAC after internal processing.
NVP6134C gives and takes a clock and synchronization signal through ACLK_PB and ASYNC_PB pin. In this case, interface is the exactly
same as Record data's interface. When multi-channel audio is supported, selective playback for intended channel is enable using register
setting (PB_SER, 0x14[4:0], BANK1). In case of single channel, PB_SEL should be set to "00000".
ACLK_PB and ASYNC_PB supports Master mode and Slave mode. In master mode, ACLK_PB and ASYNC_PB are outputted by NVP6134C,
and clock and synchronization signal come from external devices at slave mode. Master/Slave mode is selected by setting internal register
(PB_MASTER, 0x13[7], BANK1).
ADATA_PB accepts an audio data synchronized with ACLK_PB and ASYNC_PB. ACLK_PB and ASYNCP accept I2S/DSP/SSP mode input and
output, and I2S and DSP mode is set by internal register value (PB_SYNC, 0x13[0], BANK1). When DSP mode is selected, DSP/SSP mode is
set by (PB_SSP, 0x13[1], BANK1). The relation of clock, synchronized signal and data are the exactly same as that of record/mix output.
PB_CLK can be inverted for all modes using setting of register(PB_CLK, 0x13[6], BANK1).
3.3 Audio Detection

NVP6134C has an audio mute detection block for individual 5 channels. The mute detection scheme uses absolute/differential amplitude
detection method. The detection method and accumulated period are defined by the ADET_MODE(0x29[3], BANK1) and ADET_FILT (0x29[2:0],
BANK1) register. According to this control bits and its result (audio detected), Interrupt is generated through the interrupt pins.
3.4 Cascade Operation

NVP6134C supports cascade mode. Maximum 4-NVP6134C chips can be connected together for cascade mode and can be processed 18
channel audio encoding data(16-Ch Audio/2-Ch mic). Cascade is enabled by setting register(CHIP_STAGE, 0x06[1:0], BANK1). Figure 3.10
shows how to connect NVP6134C for the cascade mode. In this case, analog audio AOUT1 is assigned to AIN1-16 and MICIN1-2. 1 channel
audio or all channel mixed audio signal is selected as output signal set by MIX_OUTSEL(0x23[4:0], BANK1).
1 AIN1 ADATA_REC
2 AIN2
3 AIN3 ASYNC_REC
4 AIN4 DECODER_1
MICIN ACLK_REC
MIC 1 (First Stage)
AOUT 1 AOUT ADATA_PB

ADATA_CASI
ADATA_CASO
5 AIN1
6 AIN2
7 AIN3
8 AIN4 DECODER_2
MIC 2 MICIN (Middle Stage)
AOUT 2 AOUT
ADATA_CASI
ADATA_CASO
9 AIN1
10 AIN2
11 AIN3
12 AIN4 DECODER_3
(Middle Stage)
AOUT 3 AOUT
ADATA_CASI
ADATA_CASO
13 AIN1
14 AIN2
15 AIN3
16 AIN4 DECODER_4
(Last Stage)
AOUT 4 AOUT
Figure 3.10 Consist of Cascade System using 4-NVP6134C

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Chapter 4
COAXIAL PROTOCOL
NVP6134C includes Coaxial Protocol generator that sends control signal from a controller to a pan and tilt, receiver driver, or camera and lens
on the video signal. NVP6134C supports Protocol for CVBS/COMET(PELCO) & AHD(A-CP). It depends on Coaxial Cable impedance
characteristic. This document presents the concept of Coaxial Protocol. Coaxitron is Pelco’s name for a method of sending control signaling
from a controller to a pan and tilt, receiver driver, or camera and lens on the video signal (Known as “Up The Coax” or “UTC”)
4.1 PELCO PROTOCOL

There are two types of Coaxitron command structures. One type, Standard Coaxitron,. is a series of 15 pulses, or data bits, that are sent within
video line 18 of a video field. The other type, Extended Coaxitron, is a series of 32 pulses, where 16 pulses are sent in line 18 and 16 pulses in
line 19 of a video field. Refer to Figure 4.1. No pulses are sent when the system is in an idle state
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Figure 4.1 Coaxitron Active line
Coaxitron is a pulse width modulated (PWM) That is inserted into video vertical blanking interval. A 2us pulse represents a one(1) and a 1us
pulse represents a zero(0). There is a start bit (always high level), a data bit (low or high level) and a stop bit (always low level).
Refer to Figure 4.2. and Figure 4.3.
1us 1us 1us

Start Data Stop
3us
Figure 4.2 Description of One Coaxitron Bit
Start Bit Stop Bit
1us 1us
1us
Data Bit = 0 Data Bit = 0 Data Bit = 1
3us
Figure 4.3 Coaxitron Bit Timing

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NVP6134C is able to control coaxitron timing format on the video signal.
Start Active line of Coaxitron (BL_TXST, 0x03~04[3:0],0x83~84[3:0], BANK3~4) is 18th line on VBI. Pulse width of Coaxitron (BAUD, 0x00/0x80,
BANK3~4) is fixed 1us. The size of Coaxial Data (PELCO_TXDAT, 0x20~23,0xA0~A3, BANK3~4) is 4 bytes. Refer to Figure 4.4.
PELCO_TXDAT_01 PELCO_TXDAT_02
DATA BIT [0] [1] [2] [3] [4] [5] [6] [7] [0] [1] [2] [3] [4] [5] [6] [7]
BL_HSP
BAUD
Figure 4.4 Data Structure of Coaxitron Origins (VBI 18th)
4.2 A-CP(AHD-Coaxial protocol)

It is an acronym of AHD Coaxial Protocol. This term signifies the interactive communication protocol between Image Signal Processor.
As a major feature, A-CP Data located in the 17~20th line. Also Data is 8bit each line.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Figure 4.5 A-CP Active line

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A-CP is a pulse width modulated (PWM) That is inserted into video vertical blanking interval. A 1.8us pulse represents a one(1) and a 0.6us
pulse represents a zero(0). There is a start bit (always high level), a data bit (low or high level) and a stop bit (always low level).
Refer to Figure 4.6. and Figure 4.7.
0.6us 0.6us 0.6us

Start Data Stop
1.8us
Figure 4.6 Description of A-CP One Data Bit
Start Bit Stop Bit
0.6us 0.6us
0.6us
Data Bit = 0 Data Bit = 0 Data Bit = 1
1.8us
Figure 4.7 Data A-CP Bit Timing
Start Active line of Coaxitron (BL_TXST, 0x0D~0E[3:0],0x8D~8E[3:0], BANK3~4) is 17th line on VBI. Pulse width of Coaxitron (BAUD, 0x00/0x80,
BANK3~4) is fixed 0.6us. The size of Coaxial Data (TX_DATA, 0x10~17, 0x90~0x97, BANK3~4) is 4 bytes. Refer to Figure 4.8.
TX_DATA_01
DATA BIT [0] [1] [2] [3] [4] [5] [6] [7]
BL_HSP
BAUD
Figure 4.8 Data Structure of Coaxitron Origins (VBI 17th)

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Chapter 5
I2C INTERFACE
I2C interface requires 2 wires, SCL (I2C clock) & SDA (I2C R/W data). NVP6134C provides special device ID as slave addresses (SA0, SA1).
So any combination of 7 bit can be defined as slave address of NVP6134C. The Figure 5.1 shows read/write protocol of I2C interface. The 1st
byte transfers slave address and read/write information. For write mode, the 2nd byte transfers base register index and the 3rd byte transfers
date to be written.
For read mode, reading data is transferred during 2nd byte period. The brief I2C interface protocol is shown in Figure 5.2.
Figure 5.1 I2C Timing Diagram
Figure 5.2 I2C Slave Address Configuration

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Chapter 6
REGISTER DESCRIPTION
6.1 REGISTER ADDRESS
6.1.1 BANK0 Register(0x00~0x1F) : VIDEO
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
0x00 -RESERVED- PD_VCH1 0x01 0x00 0x00
0x08 AUTO_1 BSF_MODE_1 VIDEO_FORMAT_1 0x00 0x00 0x00
0x09 AUTO_2 BSF_MODE_2 VIDEO_FORMAT_2 0x00 0x00 0x00
0x0A AUTO_3 BSF_MODE_3 VIDEO_FORMAT_3 0x00 0x00 0x00
0x0B AUTO_4 BSF_MODE_4 VIDEO_FORMAT_4 0x00 0x00 0x00
0x0C BRIGHTNESS_1 0x08 0xED 0xED

B
0x0D BRIGHTNESS_2 0x08 0xED 0xED
A
0x0E BRIGHTNESS_3 0x08 0xED 0xED
N 0x0F BRIGHTNESS_4 0x08 0xED 0xED
0x10 CONTRAST_1 0x88 0x88 0x88

K
0
0x14 H_SHARPNESS_1 V_SHARPNESS_1 0x90 0x90 0x90
0x18 Y_PEAK_MODE_1 Y_FIR_MODE_1 0x00 0x20 0x20
0x19 Y_PEAK_MODE_2 Y_FIR_MODE_2 0x00 0x20 0x20
0x1A Y_PEAK_MODE_3 Y_FIR_MODE_3 0x00 0x20 0x20
0x1B Y_PEAK_MODE_4 Y_FIR_MODE_4 0x00 0x20 0x20

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ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
PAL_CM_
0x21 IF_FIR_SEL_1 CLPF_SEL_1 0x92 0x92 0x92
OFF_1
0x22 COLOROFF_1 C_KILL_1 0x0A 0x0B 0x0B
PAL_CM_
OFF_2
0x26 COLOROFF_2 C_KILL_2 0x0A 0x0B 0x0B
PAL_CM_
OFF_3
0x2A COLOROFF_3 C_KILL_3 0x0A 0x0B 0x0B
PAL_CM_
0x2D IF_FIR_SEL_4 CLPF_SEL_4 0x92 0x92 0x92
OFF_4
0x2E COLOROFF_4 C_KILL_4 0x0A 0x0B 0x0B
0x30 -RESERVED- Y_DELAY_1 0x12 0x10 0x10
B
A 0x33 -RESERVED- Y_DELAY_4 0x12 0x10 0x10
N 0x34 -RESERVED- PED_ON_1 -RESERVED- 0x02 0x04 0x02
K 0x35 -RESERVED- PED_ON_2 -RESERVED- 0x02 0x04 0x02
0 0x36 -RESERVED- PED_ON_3 -RESERVED- 0x02 0x04 0x02
0x37 -RESERVED- PED_ON_4 -RESERVED- 0x02 0x04 0x02
0x38 CTI_GAIN_1 0x0A 0x0A 0x0A
0x39 CTI_GAIN_2 0x0A 0x0A 0x0A
0x3A CTI_GAIN_3 0x0A 0x0A 0x0A
0x3B CTI_GAIN_4 0x0A 0x0A 0x0A
0x3C SATURATION_1 0x90 0x84 0x84
0x3D SATURATION_2 0x90 0x84 0x84
0x3E SATURATION_3 0x90 0x84 0x84
0x3F SATURATION_4 0x90 0x84 0x84

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ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
0x40 HUE_1 0x00 0x00 0x00
0x41 HUE_2 0x00 0x00 0x00
0x42 HUE_3 0x00 0x00 0x00
0x43 HUE_4 0x00 0x00 0x00
0x44 U_GAIN_1 0x00 0x00 0x00
0x45 U_GAIN_2 0x00 0x00 0x00
0x46 U_GAIN_3 0x00 0x00 0x00
0x47 U_GAIN_4 0x00 0x00 0x00
0x48 V_GAIN_1 0x00 0x00 0x00
0x49 V_GAIN_2 0x00 0x00 0x00
0x4A V_GAIN_3 0x00 0x00 0x00
0x4B V_GAIN_4 0x00 0x00 0x00
0x4C U_OFFSET_1 0x00 0x00 0x00
B 0x4D U_OFFSET_2 0x00 0x00 0x00
0x4E U_OFFSET_3 0x00 0x00 0x00

A
0x4F U_OFFSET_4 0x00 0x00 0x00
N
0x50 V_OFFSET_1 0x00 0x00 0x00
K
0x51 V_OFFSET_2 0x00 0x00 0x00
0
0x52 V_OFFSET_3 0x00 0x00 0x00
0x53 V_OFFSET_4 0x00 0x00 0x00
NOVID_INF_IN
0x54 FLD_INV_4 FLD_INV_3 FLD_INV_2 FLD_INV_1 CHID_TYPE_14 0x01 0xF1 0x01
_14
0x55 CHID_VIN2 CHID_VIN1 0x10 0x10 0x10
0x56 CHID_VIN4 CHID_VIN3 0x10 0x10 0x10
0x58 H_DELAY_1 0x80 0x8B 0x80
0x59 H_DELAY_2 0x80 0x8B 0x80
0x5A H_DELAY_3 0x80 0x8B 0x80
0x5B H_DELAY_4 0x80 0x8B 0x80
0x5C V_DELAY_1 0x00 0x9E 0x9E
0x5D V_DELAY_2 0x00 0x9E 0x9E
0x5E V_DELAY_3 0x00 0x9E 0x9E
0x5F V_DELAY_4 0x00 0x9E 0x9E

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ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
0x60 HBLK_END_1 0x00 0x00 0x00
0x61 HBLK_END_2 0x00 0x00 0x00
0x62 HBLK_END_3 0x00 0x00 0x00
0x63 HBLK_END_4 0x00 0x00 0x00
0x64 VBLK_END_1 0x00 0xC0 0xC0
0x68 H_CROP_S_1 0x00 0x00 0x00
0x69 H_CROP_S_2 0x00 0x00 0x00
0x6A H_CROP_S_3 0x00 0x00 0x00
0x6B H_CROP_S_4 0x00 0x00 0x00

B
0x6C H_CROP_E_1 0x00 0x00 0x00
A
0x6D H_CROP_E_2 0x00 0x00 0x00
N
0x6E H_CROP_E_3 0x00 0x00 0x00
K
0x6F H_CROP_E_4 0x00 0x00 0x00
0
0x70 V_CROP_S_1 0x00 0x00 0x00
0x71 V_CROP_S_2 0x00 0x00 0x00
0x72 V_CROP_S_3 0x00 0x00 0x00
0x73 V_CROP_S_4 0x00 0x00 0x00
0x74 V_CROP_E_1 0x00 0x00 0x00
0x75 V_CROP_E_2 0x00 0x00 0x00
0x76 V_CROP_E_3 0x00 0x00 0x00
0x77 V_CROP_E_4 0x00 0x00 0x00
0x78 BGDCOL_2 BGDCOL_1 0x88 0x88 0x88
0x79 BGDCOL_4 BGDCOL_3 0x88 0x88 0x88
0x7A DATA_OUT_MODE_2 DATA_OUT_MODE_1 0x11 0x11 0x11
0x7B DATA_OUT_MODE_4 DATA_OUT_MODE_3 0x11 0x11 0x11

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6.1.5 BANK0 Register(0x80~0xA3) : VIDEO_ENABLE & Delay
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
0x80 EACH_REG_SET 0x00 0x0F 0x0F
0x81 SD_MD_1 AHD_MD_1 0x03 0x02 0x03
0x82 SD_MD_2 AHD_MD_2 0x03 0x02 0x03
0x83 SD_MD_3 AHD_MD_3 0x03 0x02 0x03
0x84 SD_MD_4 AHD_MD_4 0x03 0x02 0x03
0x8E H_DLY_MSB_1 -RESERVED- 0x09 0x00 0x00
0x8F H_DLY_MSB_2 -RESERVED- 0x09 0x00 0x00
0x90 H_DLY_MSB_3 -RESERVED- 0x09 0x00 0x00
B 0x91 H_DLY_MSB_4 -RESERVED- 0x09 0x00 0x00
A 0x93 -RESERVED- HZOOM_ON_1 0x00 0x00 0x00
0x94 -RESERVED- HZOOM_ON_2 0x00 0x00 0x00

N
K
0
0x98 -RESERVED- H_ZOOM_DTO_1 0x07 0x00 0x00
0x99 -RESERVED- H_ZOOM_DTO_2 0x07 0x00 0x00
0x9A -RESERVED- H_ZOOM_DTO_3 0x07 0x00 0x00
0x9B -RESERVED- H_ZOOM_DTO_4 0x07 0x00 0x00
0xA0 DF_CDELAY_1 DF_YDELAY_1 0x00 0x00 0x00

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6.1.6 BANK0 Register(0xA8~0xF5) : STATUS
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
0xA8 NOVID_04 NOVID_03 NOVID_02 NOVID_01 R R R
0xA9 MOTION_04 MOTION_03 MOTION_02 MOTION_01 R R R
0xAC MUTE_08 MUTE_07 MUTE_06 MUTE_05 MUTE_04 MUTE_03 MUTE_02 MUTE_01 R R R
0xAD MUTE_16 MUTE_15 MUTE_14 MUTE_13 MUTE_12 MUTE_11 MUTE_10 MUTE_09 R R R
0xAE MUTEMIC_02 MUTEMIC_01 R R R
COAX_RX_ COAX_RX_ COAX_RX_ COAX_RX_

0xAF R R R
DONE_4 DONE_3 DONE_2 DONE_1
0xB0 NOVID_04B NOVID_03B NOVID_02B NOVID_01B R R R
0xB1 MOTION_04B MOTION_03B MOTION_02B MOTION_01B R R R
0xB4 MUTE_08B MUTE_07B MUTE_06B MUTE_05B MUTE_04B MUTE_03B MUTE_02B MUTE_01B R R R
0xB5 MUTE_16B MUTE_15B MUTE_14B MUTE_13B MUTE_12B MUTE_11B MUTE_10B MUTE_09B R R R

B MUTEMIC_ MUTEMIC_
0xB6 R R R
02B 01B
A COAX_RX_ COAX_RX_ COAX_RX_ COAX_RX_
0xB7 R R R
DONE_4B DONE_3B DONE_2B DONE_1B
N RD_STATE_
0xB8 STATE_HOLD 0x90 0x90 0x90
CLR
K 0xB9 IRQ_MSB IRQ_INV IRQ_SEL 0x00 0x00 0x00
0 0xE0 AGC_LOCK_04 AGC_LOCK_03 AGC_LOCK_02 AGC_LOCK_01 R R R
0xE1 CMP_LOCK_04 CMP_LOCK_03 CMP_LOCK_02 CMP_LOCK_01 R R R
0xE2 H_LOCK_04 H_LOCK_03 H_LOCK_02 H_LOCK_01 R R R
0xE7 BW_04 BW_03 BW_02 BW_01 R R R
0xE8 FSC_CHG_ FSC_LOCK_

-RESERVED- CKILL_01 NOVIDEO_01 R R R
DONE_01 DONE_01
0xE9 FSC_CHG_ FSC_LOCK_

DONE_02 DONE_02
0xEA FSC_CHG_ FSC_LOCK_

DONE_03 DONE_03
0xEB FSC_CHG_ FSC_LOCK_

DONE_04 DONE_04
0xF4 DEV_ID (NVP6134C = 0x90) R R R
0xF5 REV_ID (0x01) R R R

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6.1.7 BANK1 Register(0x00~0x1E) : AUDIO
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
EN_32K_
0x00 PD_AU_AFE PD_AU_DAC RM_PB_PIN PB_RM_PIN FILTER_ON 0x02 0x02 0x02
MODE
0x01 AIGAIN_01 0x00 0x08 0x08
0x02 AIGAIN_02 0x00 0x08 0x08
0x03 AIGAIN_03 0x00 0x08 0x08
0x04 AIGAIN_04 0x00 0x08 0x08
0x05 MIGAIN_01 0x00 0x08 0x08
CASCADE_
0x06 CAS_PB TRANS_MODE CAS_4CH CAS_PIN -RESERVED- CHIP_STAGE 0x1B 0x3B 0x3B
MODE
0x07 RM_MASTER RM_CLK RM_BITRATE RM_SAMRATE RM_BITWID RM_SSP RM_SYNC 0xC8 0xC8 0xC8
RM_BIT_
0x08 RM_LAW_SEL RM_FORMAT -RESERVED- R_ADATSP R_MULTCH 0x03 0x03 0x03
SWAP
0x09 R_SEQ_08[4] R_SEQ_07[4] R_SEQ_06[4] R_SEQ_05[4] R_SEQ_04[4] R_SEQ_03[4] R_SEQ_02[4] R_SEQ_01[4] 0x00 0x00 0x00
0x0A R_SEQ_02[3:0] R_SEQ_01[3:0] 0x10 0x10 0x10
0x0B R_SEQ_04[3:0] R_SEQ_03[3:0] 0x32 0x32 0x32
0x0C R_SEQ_06[3:0] R_SEQ_05[3:0] 0x54 0x54 0x54
B 0x0D R_SEQ_08[3:0] R_SEQ_07[3:0] 0x76 0x76 0x76
A 0x0E R_SEQ_16[4] R_SEQ_15[4] R_SEQ_14[4] R_SEQ_13[4] R_SEQ_12[4] R_SEQ_11[4] R_SEQ_10[4] R_SEQ_09[4] 0x00 0x00 0x00
N 0x0F R_SEQ_10[3:0] R_SEQ_09[3:0] 0x98 0x98 0x98
K 0x10 R_SEQ_12[3:0] R_SEQ_11[3:0] 0xBA 0xBA 0xBA
1 0x11 R_SEQ_14[3:0] R_SEQ_13[3:0] 0xDC 0xDC 0xDC
0x12 R_SEQ_16[3:0] R_SEQ_15[3:0] 0xFE 0xFE 0xFE
0x13 PB_MASTER PB_CLK PB_BITRATE PB_SAMRATE PB_BITWID PB_SSP PB_SYNC 0x08 0x08 0x08
PB_BIT_
0x14 - PB_SEL 0x00 0x00 0x00
SWAP
0x15 PB_FORMAT - PB_ LAW_SEL -RESERVED- 0x00 0x00 0x00
0x16 MIX_RATIO_02 MIX_RATIO_01 0x88 0x88 0x88
0x1A MIX_RATIO_10 MIX_RATIO_09 0x88 0x88 0x88
0x1B MIX_RATIO_12 MIX_RATIO_11 0x88 0x88 0x88
0x1C MIX_RATIO_14 MIX_RATIO_13 0x88 0x88 0x88
0x1D MIX_RATIO_16 MIX_RATIO_15 0x88 0x88 0x88
0x1E MIX_RATIO_M2 MIX_RATIO_M1 0x88 0x88 0x88

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6.1.8 BANK1 Register(0x20~0x44) : AUDIO
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
0x20 MIX_RATIO_P2 MIX_RATIO_P1 0x88 0x88 0x88
0x21 MIX_RATIO_P4 MIX_RATIO_P3 0x88 0x88 0x88
0x22 AOGAIN 0x00 0x08 0x08
0x23 MIX_DERATIO MIX_OUTSEL 0x19 0x19 0x19
0x24 L_CH_OUTSEL 0x18 0x19 0x19
0x25 R_CH_OUTSEL 0x16 0x19 0x19
B 0x26 MIX_MUTE_08 MIX_MUTE_07 MIX_MUTE_06 MIX_MUTE_05 MIX_MUTE_04 MIX_MUTE_03 MIX_MUTE_02 MIX_MUTE_01 0x00 0x00 0x00
A 0x27 MIX_MUTE_16 MIX_MUTE_15 MIX_MUTE_14 MIX_MUTE_13 MIX_MUTE_12 MIX_MUTE_11 MIX_MUTE_10 MIX_MUTE_09 0x00 0x00 0x00
MIX_MUTE_M MIX_MUTE_M
N 0x28 -RESERVED- MIX_MUTE_P4 MIX_MUTE_P3 MIX_MUTE_P2 MIX_MUTE_P1 0x00 0x00 0x00
2 1
K 0x29 AUTO_MUTE -RESERVED- ADET_MODE ADET_FILT 0x88 0x88 0x88
1 0x2A ADET_04 ADET_03 ADET_02 ADET_01 0xFF 0xFF 0xFF
0x2B ADET_M1 0xC0 0x40 0x40
0x38 -RESERVED- AUD_SW_RST -RESERVED- 0x08 0x08 0x08
0x3A A_DAC_GAIN 0xA2 0x03 0x03
0x3B A_GAIN_SEL(AFE) -RESERVED- 0x30 0x30 0x30
0x3C MIC_SEQ_01 0x00 0x10 0x10
0x3D MIC_SEQ_02 0x00 0x11 0x11

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6.1.9 BANK1 Register(0x80~0x9F) : IP Power Down
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
B 0x97 CH_RST4 CH_RST3 CH_RST2 CH_RST1 0x0F 0x0F 0x0F
A
0x98 PD_DEC4 PD_DEC3 PD_DEC2 PD_DEC1 0x00 0x00 0x00
N
K
0x9A AU_RST PD_AUD 0x00 0x00 0x00
1
6.1.10 BANK1 Register(0xB0~0xBF) : MPP
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
0xB1 MPP4_DIR MPP3_DIR MPP2_DIR MPP1_DIR 0x00 0x00 0x00
B 0xB2 MPP4_CLK MPP3_CLK MPP2_CLK MPP1_CLK 0x00 0x00 0x00
0xB3 MPP4_INV MPP3_INV MPP2_INV MPP1_INV 0x00 0x00 0x00

A
0xB4 MPP_CLK1_SEL MPP_CLK1_DLY_SEL 0x40 0x40 0x40

N

K

1
6.1.11 BANK1 Register(0xC2~0xCE) : OUTPUT PORT
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
0xC2 VPORT_1_SEQ2 VPORT_1_SEQ1 0x00 0x10 0x10

B
A
0xC8 VPORT_1_CH_OUT_SEL -RESERVED- 0x00 0x00 0x00
N
0xC9 -RESERVED- VPORT_2_CH_OUT_SEL 0x00 0x00 0x00
K
0xCA -RESERVED- VCLK_2_EN VCLK_1_EN -RESERVED- -RESERVED- VDO_2_EN VDO_1_EN -RESERVED- 0x00 0xFF 0xFF
1 OUT_DATA_2 OUT_DATA_1
0xCB -RESERVED- -RESERVED- 0x00 0x00 0x00
_INV _INV
0xCD VPORT_1_OCLK_SEL VPORT_1_OCLK _DLY_SEL 0x46 0x46 0x46
0xCE VPORT_2_OCLK_SEL VPORT_2_OCLK _DLY_SEL 0x46 0x46 0x46

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6.1.12 BANK2 Register(0x00~0x1F) : MOTION
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. FHD HD
CH1_MOTION
0x00 -RESERVED- CH1_MOTION_PIC -RESERVED- 0x0D 0xED 0x09
_OFF
0x01 CH1_MOD_TSEN 0x60 0x60 0x60
B 0x02 -RESERVED- CH1_MOD_PSEN 0x23 0x88 0x88
CH2_MOTION
A 0x07 -RESERVED- CH2_MOTION_PIC -RESERVED- 0x0D 0x0D 0x0D
_OFF
N 0x08 CH2_MOD_TSEN 0x60 0x60 0x60
CH3_MOTION
K 0x0E -RESERVED- CH3_MOTION_PIC -RESERVED- 0x0D 0x0D 0x0D
_OFF
2 0x0F CH3_MOD_TSEN 0x60 0x60 0x60
CH4_MOTION
0x15 -RESERVED- CH4_MOTION_PIC -RESERVED- 0x0D 0x0D 0x0D
_OFF
0x16 CH4_MOD_TSEN 0x60 0x60 0x60

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6.1.13 BANK3~4 Register(0x00~0x7F / 0x80~0xFF ) : COAXIAL
ADDRESS
REGISTER NAME
Bank Addr
3 0x00 ~ 0x7F Coaxial CH1
3 0x80 ~ 0xFF Coaxial CH2
4 0x00 ~ 0x7F Coaxial CH3
4 0x80 ~ 0xFF Coaxial CH4

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6.1.14 BANK3~4 Register(0x00~0x1F / 0x80~0x9F ) : COAXIAL CH1~4
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
0x00 CH1_BAUD 0x37 0x27 0x27
0x02 CH1_PELCO_BAUD 0x1B 0x1B 0x1B
0x03 CH1_BL_TXST[7:0] 0x05 0x0E 0x0E
0x04 CH1_BL_TXST[15:8] 0x00 0x00 0x00
0x05 CH1_ACT_LEN 0x00 0x03 0x03
0x07 CH1_PELCO_TXST[7:0] 0x00 0x0E 0x0E
0x08 CH1_PELCO_TXST[15:8] 0x00 0x00 0x00
CH1_COAX CH1_CNT CH1_TX_

0x09 0x00 0x08 0x08
_SW_RST _MODE START
0x0A CH1_TX_BYTE_LENGTH 0x08 0x03 0x03
CH1_PELCO CH1_LINE 0x06 0x10 0x10

0x0B -RESERVED- -RESERVED- CH1_PACKET_MODE
_8BIT _8BIT
CH1_PELCO_
0x0C 0x00 0x00 0x00
CTEN
0x0D CH1_BL_HSP[7:0] 0x46 0xB4 0x48

B
0x0E CH1_BL_HSP[15:8] 0x00 0x00 0x02
A
CH1_PELCO_
0x0F 0x00 0x00 0x00
SHOT
N
0x10 CH1_TX_DATA_01 0xAA 0x00 0x00
K
0x11 CH1_TX_DATA_02 0x1C 0x10 0x10
3
0x12 CH1_TX_DATA_03 0x18 0x18 0x18
/
0x13 CH1_TX_DATA_04 0xFF 0xFF 0xFF
4
0x14 CH1_TX_DATA_05 0xAA 0xAA 0xAA
0x15 CH1_TX_DATA_06 0x3C 0x3C 0x3C
0x18 CH1_TX_DATA_09 0xAA 0xAA 0xAA
0x19 CH1_TX_DATA_10 0x1B 0x1B 0x1B
0x1A CH1_TX_DATA_11 0x00 0x00 0x00
0x1B CH1_TX_DATA_12 0x00 0x00 0x00
0x1C CH1_TX_DATA_13 0xAA 0xAA 0xAA
0x1D CH1_TX_DATA_14 0x3B 0x3B 0x3B
0x1E CH1_TX_DATA_15 0x00 0x00 0x00
0x1F CH1_TX_DATA_16 0x00 0x00 0x00

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6.1.15 BANK3~4 Register(0x20~0x5D / 0xA0~0xDD ) : COAXIAL CH1~4
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
0x20 CH1_PELCO_TXDAT_01 0x00 0x00 0x00
0x22 CH1_PELC O_TXDAT_03 0x00 0x00 0x00
0x2C CH1_VSO_INV 0x00 0x00 0x00
0x2D CH1_HSO_INV 0x00 0x00 0x00

B
0x2F CH1_ EVEN_SUM 0x01 0x00 0x00
A
0x3A CH1_CLEAN 0x00 0x00 0x00
N
0x50 CH1_PELCO_8_00 R R R
K
3
/
4
CH1_
0x5C R R R
RX_DONE
0x5D CH1_RX_COAX_DUTY R R R

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6.1.16 BANK3~4 Register(0x60~0x7F / 0xE0~0xFF ) : COAXIAL CH1~4
ADDRESS [7] [6] [5] [4] [3] [2] [1] [0] Def. 30P 25P
0x60 CH1_DEVICE_ID 0x00 0x48 0x48
0x62 CH1_RX_AREA 0x00 0x06 0x06
CH1_DELAY CH1_COMM_O
0x63 N 0x00 0x01 0x01
_ON
0x64 CH1_DELAY_CNT 0x00 0x00 0x00
0x65 CH1_MSB 0x00 0x01 0x01
CH1_
0x66 -RESERVED- 0x00 0x80 0x80
A_DUTY_ON
CH1_
0x67 0x00 0x01 0x01
INT_MODE
0x68 CH1_RX_SZ 0x00 0x50 0x50
0x69 CH1_M_DUTY 0x00 0x00 0x00

B
0x6A CH1_RX_START_POSITION 0x00 0x00 0x00
A
0x6C CH1_PELCO16_00 [7:0] R R R
N
0x6D CH1_PELCO16_00 [15:8] R R R
K
0x6E CH1_PELCO16_01 [7:0] R R R
3
0x6F CH1_PELCO16_01 [15:8] R R R
/
0x70 CH1_PELCO16_02[7:0] R R R
4
0x71 CH1_PELCO16_02[15:8] R R R
0x72 CH1_PELCO16_03[7:0] R R R
0x73 CH1_PELCO16_03[15:8] R R R
0x74 CH1_PELCO16_04[7:0] R R R
0x75 CH1_PELCO16_04[15:8] R R R
0x76 CH1_PELCO16_05[7:0] R R R
0x77 CH1_PELCO16_0515:8] R R R
0x78 CH1_PELCO16_06[7:0] R R R
0x79 CH1_PELCO16_06[15:8] R R R
* Registers of Bank 5 ~ Bank 10 are not for users.

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6.2 Register Detail Description
6.2.1 VIDEO Registers
 Registers to Power Down Mode

ADDRESS VALUE
REGISTER NAME BITS DESCRIPTION
Bank Addr 30P 25P
0x00 PD_VCH1 [0]

PD_VCH1 : Power down for CH1 Video AFE
0x01 PD_VCH2 [0]
0 0x0 PD_VCH4 : Power down for CH4 Video AFE
0x02 PD_VCH3 [0]
0x03 PD_VCH4 [0] 0 : Normal Operation 1 : Power Down
 Registers to Control Comb Filter and Video Format

ADDRESS VALUE
Bank Addr 30P 25P
0x08 AUTO_1 AUTO_x : A register to set the Auto Detect Mode On/Off; When the AUTO
mode has a high value, the Auto_NT_x bit value of the STATUS
Register(BANK0, 0xEF]) is to be confirmed to distinguish NTSC-M/J and PAL-
0x09 AUTO_2
B/D/G/H standards. It does not support other standards, and when used in link
[7]
with the DVR controller, it cannot be used in the NON_REAL_TIME mode. (x
0x0A AUTO_3
= channel 1~4 ).
0 : Auto Detect OFF
0x0B AUTO_4 1 : Auto Detect ON
0x08 BSF_MODE_1 BSF_MODE_x : Selects the filter to make primary separation of the
brightness and color signals. (x = channel 1~4 )
0x09 BSF_MODE_2
[6:5]
0x0A BSF_MODE_3 00 : LPF Auto Mode 01 : Mode 1 (2.7~5.4MHz Cut-off)
SD : SD : 10 : Mode 2 (3.5~5.6MHz Cut-off) 11 : Manual(BANKA~B,0x60 ~ 0x72,
0xA0 0xDD
0 0x0B BSF_MODE_4 / / 0xD0 ~ 0xE2)
Others : Others :
0x00 0x00
0x08 VIDEO_FORMAT_1
VIDEO_FORMAT_x : A register to determine the video standards of the input
signal (x = channel 1~4 )
0x09 VIDEO_FORMAT_2
[4:0] 00000 : NTSC-M,J 10001 : NTSC-4.43
0x0A VIDEO_FORMAT_3 11101 : PAL-B,D,G,H,I 10110 : PAL-M
11111 : PAL-Nc 10101 : PAL-60
0x0B VIDEO_FORMAT_4 Others : None

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 Registers to Control Luminance
ADDRESS VALUE
Bank Addr 30P 25P
0x0C BRIGHTNESS_1 BRIGHTNESS_x : Brightness control; DC level of the Luma signal is

adjustable up to -128 ~ +127. BRIGHTNESS consists of 2's Complements.
0x0D BRIGHTNESS_2 (x = channel 1~4 )
0 [7:0] 0xED 0xED

0x0E BRIGHTNESS_3 00000001 : +1 01111111 : + 127
10000000 : - 128 11111111 : -1

0x0F BRIGHTNESS_4
 Registers to Control Contrast

ADDRESS VALUE
Bank Addr 30P 25P
CONTRAST_x : Contrast control, Gain level of the Luma signal is adjustable

0x10 CONTRAST_1
up to x2. MSB represents an integral number while the rest the decimal
fraction.
0x11 CONTRAST_2 (x = channel 1~4 )
0 [7:0] 0x88 0x88
0x12 CONTRAST_3 00000000 : ≒ x0 01000000 : ≒ x 0.5
10000000 : ≒ x1 11111111 : ≒ x2
0x13 CONTRAST_4
 Registers to Control Sharpness

ADDRESS VALUE
Bank Addr 30P 25P
0x14 H_SHARPNESS_1 H_SHARPNESS_x : Selects the H_Sharpness Value to calculate the

brightness information. It consists of four bits in total. MSB represents an
0x15 H_SHARPNESS_2 integral number while the rest the decimal fraction. (x = channel 1~4 )
[7:4]
0x16 H_SHARPNESS_3 0000 : x0 0100 : x 0.5
1000 : x1 1111 : x2
0x17 H_SHARPNESS_4 SD :
0x80
0 /
Others :
0x14 V_SHARPNESS_1 0x90 V_SHARPNESS_x : Selects the V_Sharpness Value to calculate the
brightness information. It consists of four bits in total. MSB represents an
0x15 V_SHARPNESS_2 integral number while the rest the decimal fraction. (x = channel 1~4 )
[3:0]
0x16 V_SHARPNESS_3 0000 : x1 0100 :x2
0x17 1000 : x3 1111 :x4

V_SHARPNESS_4
 Registers to Control Peaking Filter

ADDRESS VALUE
Bank Addr 30P 25P
0x18 Y_PEAK_MODE_1 [7:4]

Y_PEAK_MODE_x : Y Peaking Filter control (x = channel 1~4 )
SD :
0x19 Y_PEAK_MODE_2 [7:4] 0x0
0 /
0x1A Y_PEAK_MODE_3 [7:4] Others : 0000 : 0dB 0001 : 2dB
0x2
0010 : 3.5dB 0011 : 6dB
0x1B Y_PEAK_MODE_4 [7:4] 0100 ~ 1111 : Don’t use

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 Registers to Control Low Pass Filter
ADDRESS VALUE
Bank Addr 30P 25P
Y_FIR_MODE_x : Y Low Pass Filter control

0x18 Y_FIR_MODE_1 [3:0]
(x = channel 1~4 )
SD720H :
0x4
0x19 Y_FIR_MODE_2 [3:0] / 0000 : bypass 0101 : 8MHz
SD960H :
0 0001 : 6MHz 0110 : 8.5MHz
0x8
0x1A Y_FIR_MODE_3 [3:0] / 0010 : 6.5MHz 1000 : 9.5MHz
Others : 0011 : 7MHz 0111 : 9MHz
0x0
0100 : 7.5MHz etc : Manual(BANKA~BANKB,
0x1B Y_FIR_MODE_4 [3:0]
0x54~0x5A, 0xD4~0xDA)
 Registers to Control Chrominance

ADDRESS VALUE
Bank Addr 30P 25P
0x21 PAL_CM_OFF_1
PAL_CM_OFF_x (x = channel 1~4 )

0x25 PAL_CM_OFF_2
: PAL Compensation On/Off.
[7]
0x29 PAL_CM_OFF_3 0 : PAL Compensation applied 1 : PAL Compensation not applied.
0x2D PAL_CM_OFF_4
IF_FIR_SEL_x (x = channel 1~4 )

: IF Filter drive mode selected.
0x21 IF_FIR_SEL_1
000 : bypass 001 : mode1
010 : mode2 Others : mode3
0x25 IF_FIR_SEL_2
SD : SD :
0x82 0x02
0 [6:4]
Others : Others :
0x92 0x92
0x29 IF_FIR_SEL_3
0x2D IF_FIR_SEL_4
0x21 CLPF_SEL_1
CLPF_SEL_x (x = channel 1~4 )
: C low pass filter applied mode applied after color demodulation.
0x25 CLPF_SEL_2
[3:0] 0000 : Bypass 0001 : 0.6MHz cut off
0x29 CLPF_SEL_3 0010 : 1.0MHz cut off 0011 : 1.2MHz cut off
Others : Bypass
0x2D CLPF_SEL_4

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ADDRESS VALUE
Bank Addr 30P 25P
0x22 COLOROFF_1 [4]

COLOROFF_x (x = channel 1~4 )
: COLOR OFF
0x26 COLOROFF_2 [4]
0x2A COLOROFF_3 [4]

0 : Color ON 1 : Color OFF
0x2E COLOROFF_4 [4]
C_KILL_x[3] (x = channel 1~4 )

0x22 C_KILL_1 : Select to Color kill mode
0 : Not Y/C separation
0 0x0B 0x0B 1 : Color kill after Y/C separation
C_KILL_x[2:0] (x = channel 1~4 )

0x26 C_KILL_2
: color kill control.
000 : Burst Amplitude 10% Under & FSC Unlock
[3:0]
001 : Burst Amplitude 5% Under & FSC Unlock
010 : Burst Amplitude 10 % Under
0x2A C_KILL_3
011 : Burst Amplitude 5% Under
100 : Always color on
101 : Always color on.
110 : Always color off
0x2E C_KILL_4
111 : Always color off
 Registers to Control Y_DELAY

ADDRESS VALUE
Bank Addr 30P 25P
0x30 Y_DELAY_1
0x31 Y_DELAY_2
Y_DELAY_ ON_x (x = channel 1~4 )
0 [4:0] 0x10 0x10
: Y DELAY Control, controllable between 0x00 ~ 0x1F.
0x32 Y_DELAY_3
0x33 Y_DELAY_4
 Registers to Control Pedestal and Gamma

ADDRESS VALUE
Bank Addr 30P 25P
0x34 PED_ON_1
PED_ON_x : Select to Pedestal ON/OFF
(x = channel 1~4 )
0x35 PED_ON_2
0 [6] 0 0
0x36 PED_ON_3
0 : Pedestal OFF 1 : Pedestal ON
0x37 PED_ON_4

ADDRESS VALUE
Bank Addr 30P 25P
0x38 CTI_GAIN_1
CTI_GAIN_x[7:6]
: Adjust CTI Gain Delay
0x39 CTI_GAIN_2
0 [7:0] 0x0A 0x0A
CTI_GAIN_x[4:0]
0x3A CTI_GAIN_3
: Adjust gain level for CTI. (x = channel 1~4 )
0x3B CTI_GAIN_4 0x00 : No Gain 0x01 ~ 0x1F : More larger gain

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ADDRESS VALUE
Bank Addr 30P 25P
0x3C SATURATION_1 SATURATION_x

: Color Gain Value (Adjustable up to x2) (x = channel 1~4 )
0x3D SATURATION_2
[7:0] 0x84 0x84
0x3E SATURATION_3
00000000 : x0 10000000 : x1
11000000 : x 1.5 11111111 : x2
0x3F SATURATION_4
0x40 HUE_1 HUE_x

: Color HUE Control Value (360°/256 per HUE Value 1 unit)
0x41 HUE_2 (x = channel 1~4 )
[7:0] 0x00 0x00
0x42 HUE_3
00000000 : 0° 01000000 : 90°
10000000 : 180° 11111111 : 360°
0x43 HUE_4
0x44 U_GAIN_1 U_GAIN_x

: U Gain Value (Adjustable up to x2)
0x45 U_GAIN_2 (x = channel 1~4 )
[7:0] 0x00 0x00

0x46 U_GAIN_3
00000000 : x 0 10000000 : x1
11000000 : x 1.5 11111111 : x2
0x47 U_GAIN_4
1
0x48 V_GAIN_1 V_GAIN_x
: V Gain Value (Adjustable up to x2)
0x49 V_GAIN_2 (x = channel 1~4 )
[7:0] 0x00 0x00

0x4A V_GAIN_3
00000000 : x 0 10000000 : x1
11000000 : x 1.5 11111111 : x2
0x4B V_GAIN_4
0x4C U_OFFSET_1 U_OFFSET_x

: U offset value is adjustable up to ± 7. U offset consists of 2's complements.
0x4D U_OFFSET_2 (x = channel 1~4 )
[7:0] 0x00 0x00

0x4E U_OFFSET_3
0001 : +1 0111 : + 7
1000 : -8 1111 : - 1
0x4F U_OFFSET_4
0x50 V_OFFSET_1 V_OFFSET_x

: V offset value is adjustable up to ± 7. V offset consists of 2's complements.
0x51 V_OFFSET_2 (x = channel 1~4 )
[7:0] 0x00 0x00

0x52 V_OFFSET_3
0001 : +1 0111 : + 7
1000 : -8 1111 : - 1
0x53 V_OFFSET_4

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 Registers to Control Field Polarity
ADDRESS VALUE
Bank Addr 30P 25P
FLD_INV_4 [7] FLD_INV_x

: Field Polarity Control (x = channel 1~4 )
FLD_INV_3 [6]
0 0x54 0xF 0x0
FLD_INV_2 [5]
0 : not Inversion 1 : Inversion
FLD_INV_1 [4]
 Registers to Insert No Video Information

ADDRESS VALUE
Bank Addr 30P 25P
NOVID_INF_IN _14 (x = channel 1~4 )

: It can include a NO-Video information at MSB of EAV and SAV.
0 0x54 NOVID_INF_IN_14 [3] 0x0 0x0

0 : No information
1 : Put no-video information in EAV or SAV
 Registers to Control Channel ID

ADDRESS VALUE
Bank Addr 30P 25P
CHID_TYPE_x
0x54 CHID_TYPE_14 [2:0] 0x1 0x1
: It determines type of channel ID.(x = channel 1~4 )
CHID_VIN1 [3:0]
0x55 0x10 0x10
0 CHID_VIN_x
CHID_VIN2 [7:4]
: Register to put CHANNEL ID to distinguish channel. (0x0~0xF)
CHID_VIN3 [3:0] (x = channel 1~4 )
0x56 0x10 0x10
CHID_VIN4 [7:4]
 Registers to Control Video Output Timing

ADDRESS VALUE
Bank Addr 30P 25P
0x58 H_DELAY_1
0x59 H_DELAY_2 H_DELAY_x
[7:0] 0x8B 0x80 : Register to determine the Horizontal start position of output image to Hsync
extracted in analog input signal. (x = channel 1~4 )
0x5A H_DELAY_3
0x5B H_DELAY_4
0
V_DELAY_x[7:6]
0x5C V_DELAY_1 : Select to vblk_str_fld (x = channel 1~4 )
00 : evenfld 01 : !evenfld 10 : 0 11 : 1
0x5D V_DELAY_2
V_DELAY_x[5]
[7:0] 0x9E 0x9E
: V_DELAY_x[4:0] Control Enable (x = channel 1~4 )
0x5E V_DELAY_3
V_DELAY_x[4:0] (When V_DELAY_x[5] = 1)
: Register to determine the Vertical start position of output image to Vsync
0x5F V_DELAY_4
extracted in analog input signal. (x = channel 1~4 )

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ADDRESS VALUE
Bank Addr 30P 25P
0x60 HBLK_END_1
HBLK_END_x
0x61 HBLK_END_2
: Register to control Width of Horizontal Blanking, If user increments or
[7:0] 0x00 0x00
decrements the value of this register, then the Active region is changed.
0x62 HBLK_END_3 (x = channel 1~4 )
0x63 HBLK_END_4
VBLK_END_x[7:6]
0x64 VBLK_END_1
0 : Select to vblk_end_fld (x = channel 1~4 )
00 : evenfld 01 : !evenfld 10 : 0 11 : 1
0x65 VBLK_END_2 VBLK_END_x[5]

0xC0 0xC0
: VBLK_END_x[4:0] Control Enable
[7:0]
SD SD (x = channel 1~4 )
0x28 0x2D
0x66 VBLK_END_3
VBLK_END_x[4:0] (When VBLK_END_x[5] = 1)
: Register to control Width of Vertical Blanking. If user increments or
decrements the value of this register, then the Active region is changed.
0x67 VBLK_END_4
(x = channel 1~4 )

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ADDRESS VALUE
Bank Addr 30P 25P
0x68 H_CROP_S_1
0x69 H_CROP_S_2 H_CROP_S_x : Adjust the horizontal crop start point.

[7:0] 0x00 0x00
(x = channel 1~4 )
0x6A H_CROP_S_3
0x6B H_CROP_S_4
0x6C H_CROP_E_1
0x6D H_CROP_E_2 H_CROP_E_x : Adjust the horizontal crop end point.

[7:0] 0x00 0x00
(x = channel 1~4 )
0x6E H_CROP_E_3
0x6F H_CROP_E_4
0
0x70 V_CROP_S_1
0x71 V_CROP_S_2 V_CROP_S_x : Adjust the vertical crop start point.

[7:0] 0x00 0x00
(x = channel 1~4 )
0x72 V_CROP_S_3
0x73 V_CROP_S_4
0x74 V_CROP_E_1
0x75 V_CROP_E_2 V_CROP_E_x : Adjust the vertical crop end point.

[7:0] 0x00 0x00
(x = channel 1~4 )
0x76 V_CROP_E_3
0x77 V_CROP_E_4
 Registers to Control Back Ground Color

ADDRESS VALUE
Bank Addr 30P 25P
BGDCOL_x
: When No-Video, BackGround Color is used. (x = channel 1~4 )
BGDCOL_1 [3:0]
0000 : Blue
0x78 0001 : White (75%)

0010 : Yellow
0011 : Cyan
BGDCOL_2 [7:4] 0100 : Green
0101 : Magenta
0110 : Red
0 0x88 0x88 0111 : Blue
1000 : Black
1001 : Gray
BGDCOL_3 [3:0]
1010 : Red (NEXTCHIP*)
1011 : Yellow (NEXTCHIP*)
1100 : Magenta (NEXTCHIP*)
0x79
1101 : Green (NEXTCHIP*)
1110 : Blue (NEXTCHIP*)
BGDCOL_4 [7:4] 1111 : Cyan (NEXTCHIP*)

* These color information is exactly same as controllers provided by
NEXTCHIP

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 Registers to Control Data Out Mode
ADDRESS VALUE
Bank Addr 30P 25P
DATA_OUT_MODE_x
DATA_OUT_MODE_1 [3:0]
: It limits a level of output data, can change signals of Cb and Cr each.
0x7A (x = channel 1~4 )
DATA_OUT_MODE_2 [7:4] 0000 : Y(016~235), Cb(016~240), Cr(016~240)

0001 : Y(001~254), Cb(001~254), Cr(001~254)
0 0x11 0x11
0010 : Y(000~255), Cb(000~255), Cr(000~255)
0011 : Cb / Cr Change, 016~235
DATA_OUT_MODE_3 [3:0]
0100 : Cb / Cr Change, 001~254
0x7B 0101 : Cb / Cr Kill, 016~235
0110 : Cb / Cr Kill, 001~254
DATA_OUT_MODE_4 [7:4] Others : Background color output

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6.2.2 Enable Registers
 Registers For Each Channel Control

ADDRESS VALUE
Bank Addr 30P 25P
DEC_REG_EACH
: For each control CH1~CH4 register.
0 0x80 EACH_REG_SET [3:0] 0xF 0xF
0x0 : same control 0xF : each control
 Registers to Select AHD Mode

ADDRESS VALUE
Bank Addr 30P 25P
AHD_MD_x
0x81 AHD_MD_1
: AHD Mode Selection.
0: SD Mode
0x82 AHD_MD_2 2: 1080 30P MODE
3: 1080 25P MODE
[3:0] 0x2 0x3 4: 720 60P MODE
5: 720 50P MODE
0x83 AHD_MD_3 6: 720 30P MODE
7: 720 25P MODE
A: 720 30P_EX MODE
B: 720 25P_EX MODE
Etc.: Don’t use
0x84 AHD_MD_4
0
SD_MD
0x81 SD_MD_1
: SD Mode Selection.
0x82 SD_MD_2
0: SD NTSC Mode 1: SD PAL MODE
[7:4] 0x0 0x0
A: SD_EX NTSC MODE B: SD_EX PAL MODE
0x83 SD_MD_3
C: SD_2EX NTSC MODE D: SD_2EX PAL MODE
Etc.: Don’t use
0x84 SD_MD_4
 Registers to Control H_DELAY

ADDRESS VALUE
Bank Addr 30P 25P
0x8E H_DLY_MSB_1
0x8F H_DLY_MSB_2
HDLY_MSBS_0x
0 [7:4] 0x0 0x0
: MSB[3:0] Register of H_DELAY Register (Bank0 0x58~5B)
0x90 H_DLY_MSB_3
0x91 H_DLY_MSB_4
 Registers to Control Horizontal ZOOM

ADDRESS VALUE
Bank Addr 30P 25P
0x93 HZOOM_ON_1
HZOOM_ON_x ( x = channel number )
: This Register can be turned on or off Horizontal ZOOM.
0x94 HZOOM_ON_2
( * H_ZOOM can use only in SD MODE.)
[0] 0x0 0x0
0x95 HZOOM_ON_3 0: ZOOM OFF
1: ZOOM ON
0x96 HZOOM_ON_4
0
0x98 ZOOM_DTO_1 [3:0]
0x99 ZOOM_DTO_2 [3:0]

ZOOM_DTO _x ( x = channel 1~4 )
0x0 0x0
: H_ZOOM Step Control.
0x9A ZOOM_DTO_3 [3:0]
0x9B ZOOM_DTO_4 [3:0]

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 Registers to Control Y/C DELAY
ADDRESS VALUE
Bank Addr 30P 25P
0xA0 DF_YDELAY_4
0xA1 DF_YDELAY_3 DF_YDELAY_x ( x = channel 1~4 )
[3:0] 0x00 0x00 : Y(Luminance) delay control in the domain of 27MHz can be controlled
0xA2 DF_YDELAY_2 between 0x0 ~ 0xF.
0xA3 DF_YDELAY_1
0
0xA0 DF_CDELAY_4
0xA1 DF_CDELAY_3 DF_CDELAY_x ( x = channel 1~4 )
[7:4] 0x00 0x00 : C(Chrominance) delay control in the domain of 27MHz can be controlled
0xA2 DF_CDELAY_2 between 0x0 ~ 0xF.
0xA3 DF_CDELAY_1

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6.2.3 State Registers
 Registers to Status Registers (Read Only)

ADDRESS VALUE
Bank Addr 30P 25P
NOVID_01 [0] NOVID_0x

: Each Channel Video Decoder No Video detection Status.
NOVID_02 [1] (x = Channel number)
0xA8 Read Read
NOVID_03 [2]
0 : On Video 1 : No Video
NOVID_04 [3]
0
MOTION_01 [0] MOTION_0x
: Each Channel Motion detection Status (x = Channel number)
MOTION_02 [1]
0xA9 Read Read
MOTION_03 [2]
0 : No MOTION 1 : On MOTION
MOTION_04 [3]
 Registers to Status Registers (Read Only)

ADDRESS VALUE
Bank Addr 30P 25P
MUTE _01 [0]
MUTE _02 [1]
MUTE_03 [2]
MUTE_04 [3]
0xAC Read Read
MUTE_05 [4]
MUTE_06 [5]
MUTE_07 [6]
MUTE_0x
: Each Channel MUTE detection Status (x = Channel number)
MUTE_08 [7]
0 : On Audio
MUTE_09 [0]
1 : No Audio (MUTE)
MUTE_10 [1]
MUTE_11 [2]
0
MUTE_12 [3]
0xAD Read Read
MUTE_13 [4]
MUTE_14 [5]
MUTE_15 [6]
MUTE_16 [7]
MUTEMIC_01 [0] MUTEMIC_01~02

0xAE Read Read : Each Internal and External Mic Channel MUTE detection Status
MUTEMIC_02 [1] 0 : On Audio 1 : No Audio (MUTE)
COAX_RX_DONE_1 [0] COAX_RX_DONE_x

: COAXIAL_RX_Detecting Status ( x = channel number )
COAX_RX_DONE_2 [1]
0xAF Read Read
COAX_RX_DONE_3 [2]
0 : No Detecting
1 : COAXIAL_RX_Detecting
COAX_RX_DONE_4 [3]

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 Registers to Interrupt clear for Status Registers
ADDRESS VALUE
Bank Addr 30P 25P
NOVID_01B [0] NOVID_0xB

: Each Channel Video Decoder No Video detection Status with HOLD option
NOVID_02B [1] (x = Channel number)
0xB0 Read Read
NOVID_03B [2]
0 : On Video 1 : No Video
NOVID_04B [3]
0
MOTION_01B [0] MOTION_0xB
: Each Channel Motion detection Status with HOLD option
MOTION_02B [1] (x = Channel number)
0xB1 Read Read
MOTION_03B [2]
0 : No MOTION 1 : On MOTION
MOTION_04B [3]

ADDRESS VALUE
Bank Addr 30P 25P
MUTE_01B [0]
MUTE_02B [1]
MUTE_03B [2]
MUTE_04B [3]
0xB4 Read Read
MUTE_05B [4]
MUTE_06B [5]
MUTE_07B [6] MUTE_0xB

: Each Channel MUTE detection Status with HOLD option
MUTE_08B [7] (x = Channel number)
0 : On Audio
MUTE_09B [0]
0
MUTE_10B [1] 1 : No Audio (MUTE)
MUTE_11B [2]
MUTE_12B [3]
0xB5 Read Read
MUTE_13B [4]
MUTE_14B [5]
MUTE_15B [6]
MUTE_16B [7]
MUTEMIC_01~02B
MUTEMIC_01B [0]
0xB6 Read Read : Each Internal and External Mic 2 Channel MUTE detection Status
MUTEMIC_02B [1] 0 : On Audio 1 : No Audio (MUTE)

ADDRESS VALUE
Bank Addr 30P 25P
COAX_RX_DONE_1B [0]
COAX_RX_DONE_x
COAX_RX_DONE_2B [1] : COAXIAL_RX_Detecting Checking Status ( x = channel number )
1 0xB7 Read Read
0 : No Detecting
COAX_RX_DONE_3B [2]
1 : COAXIAL_RX_Detecting
COAX_RX_DONE_4B [3]

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ADDRESS VALUE
Bank Addr 30P 25P
RD_STATE_CLR
: Interrupt clear condition selection
RD_STATE_CLR [7] 0 : Interrupt clear when BANK0, 0xC0~0xC6 Addr Register Read
1 : Interrupt clear when BANK0, 0xB8~0xBE / 0xC0~0xC6 Addr Register
Read
0 0xB8 0x90 0x90
STATE_HOLD
: Interrupt Hold condition selection
STATE_HOLD [4]
0 : No Hold Option, State is Real Time update.
1 : Hold Option operation. State is Hold until cleared
 Registers to Control IRQ

ADDRESS VALUE
Bank Addr 30P 25P
IRQ_MSB
: Control output data of IRQ pin
IRQ_MSB [4]
0 : 1 item output for MPP signal
1 : 2~5 item OR output for MPP signal
IRQ_INV
IRQ_INV [3] : IRQ pin output signal inversion
0 : Not Inversion 1 : Inversion
IRQ_SEL
: Select IRQ pin output signals selection
When IRQ_MSB(BANK1,0xB9[4]) = 0,
0 : 0 (Zero)
1 : interrupt request by the No video detection
0 0xB9 0x00 0x00 2 : interrupt request by the Mute detection
3 : interrupt request by the Motion detection
4 : interrupt request by the Black detection
5 : interrupt request by the White detection
6 : ALINKO
IRQ_SEL [2:0] 7 : BNCO
When IRQ_MSB(BANK1,0xB9[4]) = 1,
0 : Novid | Motion interrupt request
1 : Novid | Black interrupt request
2 : Novid | White interrupt request
3 : Black | White interrupt request
4 : Black | Motion interrupt request
5 : White | Motion interrupt request
6 : Novid | Motion | Black interrupt request
7 : Black | White | Motion interrupt request

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 Registers to Show Locking Status (Read Only)
ADDRESS VALUE
Bank Addr 30P 25P
AGC_LOCK_04 [3]
AGC_LOCK_0x
: Video AGC Locking Status ( x = channel number )
AGC_LOCK_03 [2]
0xE0 Read Read
AGC_LOCK_02 [1]
0 : No Locking
1 : Locking
AGC_LOCK_01 [0]
CMP_LOCK_04 [3]
CMP_LOCK_0x
: Video CLAMP Locking status ( x = channel number )
CMP_LOCK_03 [2]
0 0xE1 Read Read
CMP_LOCK_02 [1]
0 : No Locking
1 : Locking
CMP_LOCK_01 [0]
H_LOCK_04 [3]
H_LOCK_0x
: Video Horizontal Locking status ( x = channel number )
H_LOCK_03 [2]
0xE2 Read Read
H_LOCK_02 [1]
0 : No Locking
1 : Locking
H_LOCK_01 [0]
 Registers to Show Chip Status (Read Only)

ADDRESS VALUE
Bank Addr 30P 25P
BW_04 [3]
BW_0x
BW_03 [2] : Black / White Detection status (x = channel number)
0 0xE7 Read Read
BW_02 [1] 0 : Color
1 : B/W
BW_01 [0]

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 Registers to read the FSC Status (Read Only)
ADDRESS VALUE
Bank Addr 30P 25P
0xE8 FSC_CHG_DONE_01
FSC_CHG_DONE _x
: A status which FSC changed done or not ( x = channel number )
0xE9 FSC_CHG_DONE_02
[3] Read Read
0xEA FSC_CHG_DONE_03
0: not changed 1: changed
0xEB FSC_CHG_DONE_04
0xE8 CKILL_01
CKILL _x
: color kill status ( x = channel number )
0xE9 CKILL_02
[2] Read Read
0xEA CKILL_03
0 : Color On 1 : Color Off
0xEB CKILL_04
0
0xE8 FSC_LOCK_DONE_01
0xE9 FSC_LOCK_DONE_02
FSC_LOCK_DONE_x
[1] Read Read
: FSC LOCK Detection Status (x = channel number)
0xEA FSC_LOCK_DONE_03
0xEB FSC_LOCK_DONE_04
0xE8 NOVIDEO_01
0xE9 NOVIDEO_02
NOVIDEO_x
[0] Read Read
: NOVIDEO Status (x=channel number)
0xEA NOVIDEO_03
0xEB NOVIDEO_04
 Registers to Show Chip Status (Read Only)

ADDRESS VALUE
Bank Addr 30P 25P
DEV_ID
0xF4 DEV_ID [7:0] Read Read
: It shows Device ID (NVP6134C = 0x90 )
0
REV_ID
0xF5 REV_ID [7:0] Read Read
: It shows Revision ID (0x01)

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6.2.4 AUDIO Registers
 Registers to Control Audio AFE and DFE

ADDRESS VALUE
Bank Addr 30P 25P
PD_AU_AFE
PD_AU_AFE [7] : Audio AFE LIVE CH1~CH4 and MIC1 Power Down Mode selection
0 : Operation 1 : Power Down
PD_AU_DAC
PD_AU_DAC [6] : Audio DAC Power Down Mode selection

0 : Operation 1 : Power Down
RM_PB_PIN
: Selection of clock and sync for ADATA_REC, ADATA_SP pin
0 : use ACLK_REC and ASYNC_REC as clock and sync for ADATA_REC,
RM_PB_PIN [3]
ADATA_SP pin
1 : use ACLK_PB and ASYNC_PB as clock and sync for ADATA_REC,
1 0x00 0x02 0x02 ADATA_SP pin
PB_RM_PIN
: Selection of clock and sync for ADATA_PB pin
PB_RM_PIN [2]
0 : use ACLK_PB and ASYNC_PB as clock and sync for ADATA_PB,
1 : use ACLK_REC and ASYNC_REC as clock and sync for ADATA_PB,
FILTER_ON
FILTER_ON [1] : Set ADC sampling rate
0 : Non-oversample (16KHz) 1 : Oversample (64KHz)
EN_32K_MODE
EN_32K_MODE [0] : Operate whole audio system as 32K mode
0 : 16K Mode 1 : 32K Mode
 Registers to Control Audio Input Gain

ADDRESS VALUE
Bank Addr 30P 25P
AIGAIN_x / MIGAIN_x
0x01 AIGAIN_01 [7:0]
: The gain of analog audio input AIN1-8 and MICIN1
0000 : mute 0001 : 0.125
0010 : 0.25 0011 : 0.375

0x02 AIGAIN_02 [7:0]
0100 : 0.5 0101 : 0.625
0110 : 0.75 0111 : 0.875
1000 : 1.0 1001 : 1.125

1 0x03 AIGAIN_03 [7:0] 0x08 0x08
1010 : 1.25 1011 : 1.375
1100 : 1.5 1101 : 1.625
1110 : 1.75 1111 : 1.875

0x04 AIGAIN_04 [7:0]
10000 : 2.0 10001 : 2.125
0x05 MIGAIN_01 [3:0] 10000 ~ 11111111 : step by about 0.125

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 Registers to Audio Interface
ADDRESS VALUE
Bank Addr 30P 25P
CAS_PB
: The Usage of Playback Data when Cascade Mode
CAS_PB [7]
0 : use multiple playback data, received through all stage
1 : use single playback data, received through last stage
TRANS_MODE
: Control the phase between transferred clock and cascade data
TRANS_MODE [6]
0 : Same phase 1 : Inverted phase
CAS_4CH
CAS_4CH [5] : Channel number of 1-chip for Audio Cascade.
0 : 8 Channels 1 : 4 Channels
0x06 0x3B 0x3B CAS_PIN
: Control the usage of ADATA_CASI and ADATA_CASO as cascade
CAS_PIN [4] transmitting
0 : Don't Use 1 : Use
CASCADE_MODE
: Set the chip position when it is cascaded.
CASCADE_MODE [3]
0 : ACLK/ASYNC/ADATA Use 1 : ALINKI/ALINKO Use
CHIP_STAGE
: Selection of chip state for cascade
CHIP_STAGE [1:0]
0 : middle stage 1 : last stage
2 : first stage 3 : single chip operation
RM_MASTER
: Selection of master & slave mode of ACLK_REC and ASYNC_REC
RM_MASTER [7]
1
0 : Slave mode operation 1 : Master mode operation
RM_CLK
: Set the relationship between audio signal outputted to ADATA_REC
RM_CLK [6] and clock outputted to ACLK_REC
0 : inverted clock 1 : non-inverted clock
RM_BITRATE
: Set the bit rate of audio signal outputted to ADATA_REC
RM_BITRATE [5:4]
0 : 256fs 1 : 384fs
2 : 320fs 3 : Don’t Use
RM_SAMRATE
: Set the sampling rate of data outputted to ADATA_REC
0x07 RM_SAMRATE [3] 0xC8 0xC8
0 : 8KHz 1 : 16KHz
RM_BITWID
: Set the bit width of data outputted to ADATA_REC
RM_BITWID [2]
0 : 16bits 1 : 8bits
RM_SSP
: Selection of DSP mode and SSP mode for ADATA_REC pin,
RM_SSP [1] when ASYNC_REC is DSP mode.
0 : DSP mode 1 : SSP mode
RM_SYNC
: Set the sync's mode inputted/outputted to ASYNC_REC.
RM_SYNC [0]
0 : I2S mode 1 : DSP mode

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 Registers to Control Audio interface
ADDRESS VALUE
Bank Addr 30P 25P
RM_BIT_SWAP
: Set the bit sequence of Audio Data for ADATA_REC
RM_BIT_SWAP [7]
0 : MSB first 1 : LSB first
RM_LAW_SEL
: Define the G.711 data format outputted to ADATA_REC
RM_LAW_SEL [6]
0 : u-law 1 : a-law
RM_FORMAT
: Define the data format outputted to ADATA_REC
1 0x08 0x03 0x03
RM_FORMAT [5:4]
0 : linear PCM 1 : Unsigned linear PCM
2 : G.711 format 3 : Don’t Use
R_ADATSP
: Selection of output data for ADATA_SP
R_ADATSP [2]
0 : Speaker data 1 : Record data
R_MULTCH
: Selection of number of Channel for ADATA_REC
R_MULTCH [1:0]
0 : 2ch 1 : 4ch
2 : 8ch 3 : 16ch
 Registers to Control Audio Interface

ADDRESS VALUE
Bank Addr 30P 25P
R_SEQ_01[4] [0] 0x0 0x0

R_SEQ
R_SEQ_02[4] [1] 0x0 0x0 : Sequence of Audio Data for ADATA_REC
R_SEQ_03[4] [2] 0x0 0x0 00000 : channel 1 data

0x09 00010 : channel 3 data
R_SEQ_05[4] [4] 0x0 0x0
00011 : channel 4 data
R_SEQ_07[4] [6] 0x0 0x0
1
R_SEQ_01[3:0] [3:0]
0x0A 0x10 0x10 01001 : channel 10 data
R_SEQ_02[3:0] [7:4] 01010 : channel 11 data

0x0B 0x32 0x32 01100 : channel 13 data
R_SEQ_04[3:0] [7:4]
0x0C 0x54 0x54 01111 : channel 16 data
R_SEQ_06[3:0] [7:4]
10000 : Mic input 1
R_SEQ_07[3:0] [3:0] 10001 : Mic input 2
0x0D 0x76 0x76
R_SEQ_08[3:0] [7:4]

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ADDRESS VALUE
Bank Addr 30P 25P
R_SEQ_09[4] [0] 0x0 0x0
R_SEQ_10[4] [1] 0x0 0x0

R_SEQ_xx / MIC_SEQ_0x. ( x = channel number )
R_SEQ_11[4] [2] 0x0 0x0 : Sequence of Audio Data for ADATA_REC

0x0E
R_SEQ_13[4] [4] 0x0 0x0
R_SEQ_16[4] [7] 0x0 0x0
1 0x0F 0x98 0x98
R_SEQ_10[3:0] [7:4]
0x10 0xBA 0xBA
R_SEQ_13[3:0] [3:0]
0x11 0xDC 0xDC
R_SEQ_15[3:0] [3:0]
0x12 0xFE 0xFE 10000 : Mic input 1
R_SEQ_16[3:0] [7:4] 10001 : Mic input 2
0x3C MIC_SEQ_01 [4:0] 0x10 0x10
0x3D MIC_SEQ_02 [4:0] 0x11 0x11

ADDRESS VALUE
Bank Addr 30P 25P
PB_MASTER
: Selection of master & slave mode of ACLK_PB and ASYNC_PB
PB_MASTER [7]
0 : Slave mode 1 : Master mode
PB_CLK
: Set the relationship between audio signal outputted to ADATA_PB and
PB_CLK [6] clock outputted to ACLK_PB
0 : inverted clock 1 : non-inverted clock
PB_BITRATE
: Set the bit rate of audio signal outputted to ADATA_PB
PB_BITRATE [5:4]
0 : 256fs 1 : 384fs
2 : 320fs
PB_SAMRATE
1 0x13 0x08 0x08 : Set the sampling rate of data outputted to ADATA_PB
PB_SAMRATE [3]
0 : 8KHz 1 : 16KHz
PB_BITWID
: Set the bit width of data outputted to ADATA_PB
PB_BITWID [2]
0 : 16bits 1 : 8bits
PB_SSP
: Set the position of data and sync signals inputted to ADATA_PB, when
PB_SSP [1] ASYNC_PB is DSP mode.
0 : DSP mode 1 : SSP mode
PB_SYNC
: Set the sync's mode inputted/outputted to ASYNC_PB.
PB_SYNC [0]
0 : I2S mode 1 : DSP mode

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ADDRESS VALUE
Bank Addr 30P 25P
PB_BIT_SWAP
: Set the bit sequence of Audio Data for ADATA_PB
PB_BIT_SWAP [7]
0 : MSB first 1 : LSB first
PB_SEL
: select the audio input channel for playback input
00 : channel 01 01 : channel 02
1 0x14 0x00 0x00
PB_SEL [4:0] 06 : channel 07 07 : channel 08
0A : channel 11 0B : channel 12
0C : channel 13 0D : channel 14
0E : channel 15 0F : channel 16
10 : Mic input 1 11 : Mic input 2

ADDRESS VALUE
Bank Addr 30P 25P
PB_FORMAT
: Define the data format inputted to ADATA_PB
PB_FORMAT [7:6]
0 : linear PCM 1 : Unsigned linear PCM
2 : G.711 format 3 : Don’t Use
1 0x15 0x00 0x00
PB_LAW_SEL
: Define the G.711 data format inputted to ADATA_PB
PB_LAW_SEL [3]
0 : u-law 1 : a-law
 Registers to Control Audio Mixing Gain

ADDRESS VALUE
Bank Addr 30P 25P
MIX_RATIO_01 [3:0]
0x16
MIX_RATIO_02 [7:4]
MIX_RATIO_03 [3:0]
0x17
MIX_RATIO_04 [7:4]
MIX_RATIO_x
MIX_RATIO_05 [3:0]
: Set the mixing gain for AIN1-15. ( x = channel number )
0x18
MIX_RATIO_06 [7:4]
MIX_RATIO_07 [3:0]
0x19
MIX_RATIO_08 [7:4]
1 0x88 0x88
MIX_RATIO_09 [3:0]
0x1A
0 : mute 1 : 0.25
MIX_RATIO_10 [7:4]
2 : 0.31 3 : 0.38
MIX_RATIO_11 [3:0] 4 : 0.5 5 : 0.63

0x1B 6 : 0.75 7 : 0.88
MIX_RATIO_12 [7:4] 8 : 1.0 9 : 1.25
10 : 1.5 11 : 1.75
MIX_RATIO_13 [3:0]
12 : 2.0 13 : 2.25
0x1C
MIX_RATIO_14 [7:4] 14 : 2.5 15 : 2.75
MIX_RATIO_15 [3:0]
0x1D
MIX_RATIO_16 [7:4]

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 Registers to Control Audio Mixing Gain
ADDRESS VALUE
Bank Addr 30P 25P
MIX_RATIO_M1 [3:0]
MIX_RATIO_Mx/ MIX_RATIO_Px
0x1E
: Set the mixing gain for MICIN1~2 / PBIN1~4. ( x = channel number )
MIX_RATIO_M2 [7:4]
MIX_RATIO_P1 [3:0] 0 : mute 1 : 0.25

0x20 0x88 0x88 2 : 0.31 3 : 0.38
4 : 0.5 5 : 0.63
MIX_RATIO_P2 [7:4]
6 : 0.75 7 : 0.88
8 : 1.0 9 : 1.25
MIX_RATIO_P3 [3:0] 10 : 1.5 11 : 1.75
0x21 12 : 2.0 13 : 2.25
14 : 2.5 15 : 2.75
MIX_RATIO_P4 [7:4]
1
AOGAIN
: The gain of analog audio output
0000 : mute 0001 : 0.125
0010 : 0.25 0011 : 0.375
0100 : 0.5 0101 : 0.625
0x22 AOGAIN [7:0] 0x08 0x08 0110 : 0.75 0111 : 0.875
1000 : 1.0 1001 : 1.125
1010 : 1.25 1011 : 1.375
1100 : 1.5 1101 : 1.625
1110 : 1.75 1111 : 1.875
10000 ~ 11111111 : step by about 0.125
 Registers to Control Audio Mixing Output Mode

ADDRESS VALUE
Bank Addr 30P 25P
MIX_DERATIO
: Selection of the mixing gain mode
MIX_DERATIO [5] 0: Apply the mixing gain for MIX_RATIO_01-P4 (BANK1,0x16~0x21 Addr)
separately
1: Apply all mixing gain as the same gain (x1).
MIX_OUTSEL
: Select the audio output for analog mixing out.
00 : Channel 1 0E : Channel 15
01 : Channel 2 0F : Channel 16
02 : Channel 3 10 : playback audio
03 : Channel 4 (first stage playback audio)

1 0x23 0x19 0x19
04 : Channel 5 11 : second playback audio
05 : Channel 6 (middle stage playback audio)

MIX_OUTSEL [4:0] 06 : Channel 7 12 : third playback audio
08 : Channel 9 13 : fourth playback audio
09 : Channel 10 (last stage playback audio)

0A : Channel 11 14 : Mic input 1
0B : Channel 12 15 : Mic input 2
0C : Channel 13 18 : Mixed audio
0D : Channel 14 Others : No audio output

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 Registers to Select Audio Output for ADATA_SP PIN
AD DRESS VALUE
Bank Addr 30P 25P
L_CH_OUTSEL / R_CH_OUTSEL
: Select Left/Right channel of the audio output for ADATA_SP pin
00 : Channel 1 0E : Channel 15
01 : Channel 2 0F : Channel 16
0x24 L_CH_OUTSEL 0x19 0x19
02 : Channel 3 10 : playback audio
03 : Channel 4 (first stage playback audio)

04 : Channel 5 11 : second playback audio

1 [4:0]
06 : Channel 7 12 : third playback audio
08 : Channel 9 13 : fourth playback audio
09 : Channel 10 (last stage playback audio)

0x25 R_CH_OUTSEL 0x19 0x19
0A : Channel 11 14 : Mic input 1
0B : Channel 12 15 : Mic input 2
0C : Channel 13 18 : Mixed audio
0D : Channel 14 Others : No audio output
 Registers to Control Audio Detection

ADDRESS VALUE
Bank Addr 30P 25P
MIX_MUTE_01 [0]
MIX_MUTE_02 [1]
MIX_MUTE_03 [2]
MIX_MUTE_04 [3]
0x26
MIX_MUTE_05 [4]
MIX_MUTE_06 [5]
MIX_MUTE_07 [6]
MIX_MUTE_08 [7]
MIX_MUTE_09 [0]
MIX_MUTE_10 [1] MIX_MUTE_x

: During mixing, selected channels are muted ( x = channel value )
MIX_MUTE_11 [2]
1 0x00 0x00
MIX_MUTE_12 [3]
0x27 0 : mixing data output
1 : mute for selected channel
MIX_MUTE_13 [4]
MIX_MUTE_14 [5]
MIX_MUTE_15 [6]
MIX_MUTE_16 [7]
MIX_MUTE_P1 [0]
MIX_MUTE_P2 [1]
MIX_MUTE_P3 [2]
0x28
MIX_MUTE_P4 [3]
MIX_MUTE_M1 [4]
MIX_MUTE_M2 [5]

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ADDRESS VALUE
Bank Addr 30P 25P
AUTO MUTE Detection

0 : Don’t use this function 1 : Use this function
AUTO_MUTE [7]
0 : Absolute amplitude detection mode
1 : Differential amplitude detection mode
ADET_FILT
1 0x29 0x88 0x88
: Set the time to decide the existence of audio signals.
0 : 16sec 1 : 15sec
ADET_FILT [2:0]
2 : 9sec 3 : 5sec
4 : 3sec 5 : 1sec
6 : 0.6sec 7 : 0.5sec

ADDRESS VALUE
Bank Addr 30P 25P
ADET_01 [0]
ADET_02 [1]
0x2A ADET_0x / ADET_Mx
0xFF 0xFF
1 ADET_03 [2] : Enable bit audio signal existence checking function for AIN1-4 and MICIN1.
(x = channel 1~4 )
ADET_04 [3]
0x2B ADET_M1 [6] 0x40 0x40
 Registers to Control Audio CLK

ADDRESS VALUE
Bank Addr 30P 25P
AUD_SW_RST
: Software Reset
1 0x38 AUD_SW_RST [4] 0x08 0x08
0 : Normal Operation 1 : Reset
 Registers to Control Audio DAC GAIN

ADDRESS VALUE
Bank Addr 30P 25P
A_DAC_GAIN
: Digital Input to Analog Output Gain Control
Analog output is 2Vpp when gain setting is 0dB and digital input is full scale
0: -3dB 8: 5dB
1: -2dB 9: 6dB
1 0x3A A_DAC_GAIN [3:0] 0x03 0x03
2: -1dB 10 : 7dB
3: 0dB 11 : 8dB
4: 1dB 12 : 9dB
5: 2dB 13 : 10dB
6: 3dB 14 : 11dB
7: 4dB 15 : 12dB

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 Registers to Control Audio AFE
ADDRESS VALUE
Bank Addr 30P 25P
A_GAIN_SEL(AUDIO AFE)
: Analog Gain Control for AIN 1 ~ 4, MicIN1
1 0x3B A_GAIN_SEL(AFE) [7:4] 0x3 0x3

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6.2.5 Power Down Registers
 Registers to Control Each Channel Reset

ADDRESS VALUE
Bank Addr 30P 25P
CH_RST_4 [3]
CH_RST_x
CH_RST_3 [2] : Each Video Channel Reset
1 0x97 0xF 0x0F ( x = channel number )

CH_RST_2 [1] 0 : Channel_x Reset
1 : Channel_x On
CH_RST_1 [0]
 Registers to Control CLK Power Down

ADDRESS VALUE
Bank Addr 30P 25P
PD_DEC_4 [3]
PD_DEC_x
: Each Decoder Clock Power Down
PD_DEC_3 [2]
0x98 0x00 0x00 ( x = channel number )
PD_DEC_2 [1] 0 : Decoder Clock Power On
1 : Decoder Clock Power Off
PD_DEC_1 [0]
1 AUD_RST
: Audio Reset
AUD_RST [4] 0x0 0x0
0 : Audio On
0x9A 1 : Audio Reset
PD_AUD
PD_AUD [0] 0x00 0x00 : Audio Clock Power Down

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6.2.6 MPP Control Registers
 Registers to Control MPP

ADDRESS VALUE
Bank Addr 30P 25P
MPP1_DIR [0]
MPPx_DIR
: MPPx pin direction control (x = MPP pin number)
MPP2_DIR [1]
0xB1 0x00 0x00
MPP3_DIR [2] 0 : Output Direction
1 : Input Direction
MPP4_DIR [3]
MPP1_CLK [0]
MPPx_CLK
: MPPx Clock Enable (x = MPP pin number)
MPP2_CLK [1]
1 0xB2 0x00 0x00
MPP3_CLK [2] 0 : MPP Signal out from MPPx_pin.
1 : Selected Clock among BANK1, 0xB4~BB Out from MPPx_pin
MPP4_CLK [7]
MPP1_INV [0]
MPP2_INV [1]
0xB3 MPPx_INV
0x00 0x00
: MPPx pin output signal inversion (x = MPP pin number)
MPP3_INV [2]
MPP4_INV [3]
 Registers to Control MPP

ADDRESS VALUE
Bank Addr 30P 25P
0xB4 MPP_CLK1_SEL
0xB5 MPP_CLK2_SEL MPP_CLKx_SEL (x = MPP Pin number)

[7:4] : The Same as VCLKx Condition
0xB6 MPP_CLK3_SEL ( VCLK = Bank1 0xCD/CE )
0xB7 MPP_CLK4_SEL
1 0x40 0x40
0xB4 MPP_CLK1_DLY_SEL
0xB5 MPP_CLK2_DLY_SEL MPP_CLKx_DLY_SEL (x = MPP Pin number)

[3:0] : The Same as VCLKx Condition
0xB6 MPP_CLK3_DLY_SEL ( VCLK = Bank1 0xCD/CE )
0xB7 MPP_CLK4_DLY_SEL

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6.2.7 Video Output Control Registers
 Registers to Select Video Output
ADDRESS VALUE
Bank Addr 30P 25P
VPORTx_SEQy
[3:0] : Select the type of output video signal through each video output port
VPORT1_SEQ1
(x = VDO output port number, y= channel count for 1 port)
0xC2 0x00 0x00
VPORT1_SEQ2 [7:4]

VPORT1_SEQ3 [3:0]
4 : Only Y Display of Channel 1
0xC3 0x00 0x00
VPORT1_SEQ4 [7:4] 6 : Only Y Display of Channel 3

1
8 : H_CIF Display of Channel 1
VPORT2_SEQ1 [3:0]
9 : H_CIF Display of Channel 2
0xC4 0x11 0x11 A : H_CIF Display of Channel 3
B : H_CIF Display of Channel 4

VPORT2_SEQ2 [7:4]
C : Only C Display of Channel 1
D : Only C Display of Channel 2
VPORT2_SEQ3 [3:0] E : Only C Display of Channel 3
F : Only C Display of Channel 4

0xC5 0x11 0x11
VPORT2_SEQ4 [7:4]
Etc.: Don’t use
 Registers to Select Video Output

ADDRESS VALUE
Bank Addr 30P 25P
VPORT_x_CH_OUT_SEL
0xC8 VPORT_1_CH_OUT_SEL [7:4] 0x2 0x2 : Select the output form of the data generated in case that the system is not
set at No Video. (x = VDO output port number)
1
0 : 1-Port 1CH data
0xC9 [3:0] 0x2 0x2 8 : 1-Port 4CH time-mixed data

VPORT_2_CH_OUT_SEL
Etc.: Don’t use
 Registers to Control Video Output Port Enable

ADDRESS VALUE
Bank Addr 30P 25P
VCLK_x_EN
VCLK_2_EN [6]
: Video Output Port_x CLK Enable (x = VDO output port number)
VCLK_1_EN [5] 0 : Disable 1 : Enable
1 0xCA 0x66 0x66

VDO_x_EN
VDO_2_EN [2]
: VDOx Port Enable (x = VDO output port number)
VDO_1_EN [1] 0 : Disable 1 : Enable

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 Registers to Control Data
ADDRESS VALUE
Bank Addr 30P 25P
OUT_DATA_x_INV
OUT_DATA_2_INV [2] : It sorts output video data inversely.
(0 : [7:0], 1 : [0:7])
1 0xCB 0x00 0x00
OUT_DATA_1_INV : VDO1 Port output order control

OUT_DATA_1_INV [1]
OUT_DATA_2_INV : VDO2 Port output order control
 Registers to Select Video Output Clock

ADDRESS VALUE
Bank Addr 30P 25P
0xCD VPORT_1_OCLK_SEL VPORT_x_OVCLK_SEL

: Select clock frequency and phase of each port. (x = Port number)
[7:4] 0~3 : PLL divided by 4 with phase#1~4 (74.25Mhz)

4~5 : PLL divided by 2 with phase#1~2 (148.5Mhz)
0xCE VPORT_2_OCLK_SEL 8~B : PLL divided by 8 with phase#1~4(37.125Mhz)
1 0x46 0x46
VPORT_x_OVCLK_DLY_SEL
0xCD VPORT_1_OCLK_DLY_SEL
: Delay the output clock in the unit of ≒ (VCLK / 16) ns. Can be delayed up
(x = Port number)
[3:0] .
0 : ≒ (VCLK / 16) * 0 ns.
4 : ≒ (VCLK / 16) * 4 ns
0xCE VPORT_2_OCLK_DLY_SEL
# Delay value = (VCLK / 16) * DLY_SEL Value ns

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6.2.8 MOTION Registers
 Registers to Detect Motion

ADDRESS VALUE
Bank Addr FHD HD
0x00 CH1_MOTION_OFF
CHx_MOTION_OFF
: Motion Detection On/Off Selection ( x = channel number )
0x07 CH2_MOTION_OFF
2 [0] 0xED 0x09
0 : Motion detection on
0x0E CH3_MOTION_OFF
1 : Motion detection off

0x15 CH4_MOTION_OFF

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6.2.9 COAXIAL Registers
- CH1 Coaxial Register : Bank3 0x00~0x7F

- CH2 Coaxial Register : Bank3 0x80~0xFF
- CH3 Coaxial Register : Bank4 0x00~0x7F
- CH4 Coaxial Register : Bank4 0x80~0xFF
 Registers to Control Baud Rate

ADDRESS VALUE
Bank Addr 30P 25P
0x00 CHx_BAUD (x = Channel Number)

/ CHx_BAUD [7:0] 0x27 0x27
: A-CP TX Baud Rate
0x80
3~4
0x02 CHx_PELCO_BAUD (x = Channel Number)
/ CHx_PELCO_BAUD [7:0] 0x1B 0x1B
: PELCO TX Baud Rate
0x82
Coaxial protocol 1H Line
 Registers to Control Start Point of VBI(Vertical Blank Interval)

ADDRESS VALUE
Bank Addr 30P 25P
0x04
/ CHx_BL_TXST[15:8] [7:0] 0x00 0x00
0x84 CHx_BL_TXST (x = Channel Number)
: A-CP Protocol TX start Line in VBI
0x03
/ CHx_BL_TXST[7:0] [7:0] 0x0E 0x0E
0x83
0x05 CHx_ACT_LEN (x = Channel Number)

3~4 / CHx_ACT_LEN [3:0] 0x03 0x03
: A-CP Line number
0x85
0x08
/ CHx_PELCO_TXST [15:8] [7:0] 0x00 0x00
0x88 CHx_PELCO_TXST (x = Channel Number)
: PELCO Protocol TX Start Line in VBI
0x07
/ CHx_PELCO_TXST [7:0] [7:0] 0x0E 0x0E
0x87
Coaxial protocol Active Start Point of VBI(Vertical Blank Interval)

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 Registers to Control Coaxial Protocol
ADDRESS VALUE
Bank Addr 30P 25P
CHx_COAX_SW_RST (x = Channel Number)

CHx_COAX_SW_RST [4]
: Coaxial Software Reset
0x09 CHx_CNT_MODE (x = Channel Number)

/ CHx_CNT_MODE [3] 0x08 0x08
: A-CP Protocol Enable Signal
0x89
CHx_TX_START (x = Channel Number)

CHx_TX_START [0]
: A-CP Protocol Enable Signal
0x0A CHx_TX_BYTE_LENGTH (x = Channel Number)

/ CHx_TX_BYTE_LENGTH [4:0] 0x03 0x03
: Transmission amount In A-CP Protocol
0x8A
CHx_PELCO_8BIT (x = Channel Number)

: Pelco Protocol 8Bit mode Selection
CHx_PELCO_8BIT [7]
0 : Pelco Protocol Exp mode
1 : Pelco Protocol 8bit mode
CHx_LINE_8BIT (x = Channel Number)

: A-CP Protocol Origin Mode Selection
CHx_LINE_8BIT [4]
0x0B 0 : Pelco Protocol Mode
3~4 / 0x10 0x10 1 : A-CP Protocol Origin Mode
0x8B
CHx_PACKET_MODE (x = Channel Number)
: Coaxial Protocol Type
CHx_PACKET_MODE [2:0] 2 : Pelco Protocol Origin Mode

4 : Pelco Protocol Exp mode(Pelco_32bit Mode)
Others : Manual
0x0C CHx_PELCO_CTEN (x = Channel Number)

/ CHx_PELCO_CTEN [0] 0x00 0x00
: PELCO Protocol Enable Bit (Active High)
0x8C
0x0E
/ CHx_BL_HSP [15:7] [7:0] 0x00 0x02
0x8E
CHx_BL_HSP (x = Channel Number)
: Start Point in Coaxial Protocol Active Line
0x0D
/ CHx_BL_HSP [7:0] [7:0] 0xB4 0x48
0x8D
0x0F CHx_PELCO_SHOT (x = Channel Number)

/ CHx_PELCO_SHOT [0] 0x00 0x00
: PELCO Protocol One Operation Enable signal
0x8F

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 Registers to Control Coaxial Data
ADDRESS VALUE
Bank Addr 30P 25P
0x10
/ CHx_TX_DATA_01 [7:0] 0x00 0x00
0x90
0x11
/ CHX_TX_DATA_02 [7:0] 0x10 0x10
0x91
CHx_TX_DATA_01 ~ CHx_TX_DATA_04 (x = Channel Number)
: 1st field Data in A-CP Protocol
0x12
/ CHX_TX_DATA_03 [7:0] 0x18 0x18
0x92
0x13
/ CHX_TX_DATA_04 [7:0] 0xFF 0xFF
0x93
0x14
/ CHX_TX_DATA_05 [7:0] 0xAA 0xAA
0x94
0x15
/ CHX_TX_DATA_06 [7:0] 0x3C 0x3C
0x95
: 2nd field Data in A-CP Protocol
0x16
0x96
0x17
0x97
3~4
0x18
0x98
0x19
/ CHX_TX_DATA_10 [7:0] 0x1B 0x1B
0x99
: 3rd field Data in A-CP Protocol
0x1A
/ CHX_TX_DATA_11 [7:0] 0x00 0x00
0x9A
0x1B
/ CHX_TX_DATA_12 [7:0] 0x00 0x00
0x9B
0x1C
0x9C
0x1D
/ CHX_TX_DATA_14 [7:0] 0x3B 0x3B
0x9D
: 4th field Data in A-CP Protocol
0x1E
/ CHX_TX_DATA_15 [7:0] 0x00 0x00
0x9E
0x1F
/ CHX_TX_DATA_16 [7:0] 0x00 0x00
0x9F
 Registers to Control Coaxial Data

ADDRESS VALUE
Bank Addr 30P 25P
0x20
/ CHx_PELCO_TXDAT_01 [7:0] 0x00 0x00
0xA0 CHx_PELCO_TXDAT_01 ~ CHx_PELCO_TXDAT_02
: 18th Line in PELCO Protocol
0x21 (x = Channel Number)
0xA1
3~4
0x22
0xA2 CHx_PELCO_TXDAT_03 ~ CHx_PELCO_TXDAT_04
: 19th Line in PELCO Protocol
0x23 (x = Channel Number)
0xA3

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ADDRESS VALUE
Bank Addr 30P 25P
0x2C CHx_VSO_INV (x = Channel Number)

/ CHx_VSO_INV [7:0] 0x00 0x00
0xAC : Vertical Sync Inverter (Active High)
0x2D CHx_HSO_INV (x = Channel Number)

3~4 / CHx_HSO_INV [7:0] 0x00 0x00
0xAD : Horizontal Sync Inverter (Active High)
0x2F
/ CHx_EVEN_SUM [7:0] 0x00 0x00 Control Protocol Active line on each field
0xAF

ADDRESS VALUE
Bank Addr 30P 25P
CHx_CLEAN (x = Channel Number)

0x3A : RX Register is Read Only. So it need clean Condition
3~4 / CHx_CLEAN [0] 0x00 0x00
0xBA First, this register set ON. Second, Read I2C Protocol 0x90.
And then Clean RX Registers.
 Registers to Read Coaxial Status

ADDRESS VALUE
Bank Addr 30P 25P
0x50
/ CHx_PELCO_8_00 [7:0] Read Read
0xD0
0x51
0xD1
0x52
0xD2
0x53
0xD3 CHx_PELCO_8_00 ~ CHx_PELCO_8_07 (x = Channel Number)
3~4
: Coaxial Output 8bit Data Read Register
0x54
0xD4
0x55
0xD5
0x56
0xD6
0x57
0xD7

ADDRESS VALUE
Bank Addr 30P 25P
0x5C CHx_RX_DONE (x = Channel Number)

3~4 / CHx_RX_DONE [0] Read Read
0xDC : Coaxial RX Request Done

ADDRESS VALUE
Bank Addr 30P 25P
0x5D CHx_RX_COAX_DUTY (x = Channel Number)

3~4 / CHx_RX_COAX_DUTY [7:0] Read Read
0xDD : Coaxial RX 8bit DUTY Read

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ADDRESS VALUE
Bank Addr 30P 25P
0x60 CHx_ DEVICE_ID (x = Channel Number)

/ CHx_ DEVICE_ID [7:0] 0x84 0x84
0xE0 : Define Device_ID in Protocol’s Header
0x62 CHx_RX_AREA (x = Channel Number)

/ CHx_RX_AREA [7:0] 0x06 0x06
0xE2 : Coaxial RX Area 8-bit
CHx_DELAY_ON (x = Channel Number)

3~4 CHx_DELAY_ON [4]
: Enable to use DELAY CNT Register
0x63
/ 0x01 0x01
0xE3
CHx_COMM_ON (x = Channel Number)
CHx_COMM_ON [0]
: Coaxial RX Software Reset
0x64 CHx_DELAY_CNT (x = Channel Number)

/ CHx_DELAY_CNT [7:0] 0x00 0x00
: How many delay input signal based clock
0xE4

ADDRESS VALUE
Bank Addr 30P 25P
0x65 CHx_ MSB (x = Channel Number)

/ CHx_ MSB [0] 0x01 0x01
0xE5 : Coaxial RX MSB Change Mode
0x66 CHx_A_DUTY_ON (x = Channel Number)

/ CHx_A_DUTY_ON [7] 0x80 0x80
0xE6 : Coaxial RX DUTY Mode
0x67 CHx_INT_MODE (x = Channel Number)

/ CHx_INT_MODE [0] 0x01 0x01
0xE7 : Coaxial RX Interrupt Mode
3~4
0x68 CHx_RX_SZ (x = Channel Number)
/ CHx_RX_SZ [7:4] 0x50 0x50
0xE8 : Coaxial RX Line MAX Set
0x69 CH1_M_DUTY (x = Channel Number)

/ CH1_M_DUTY [7:0] 0x00 0x00
: Coaxial RX DUTY Set
0xE9
0x6A CH1_RX_START_POSITION (x = Channel Number)

/ CH1_RX_START_POSITION [7:0] 0x00 0x00
: Coaxial RX Start Point in Line
0xEA

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ADDRESS VALUE
Bank Addr 30P 25P
0x6C
/ CHx_PELCO16_00 [7:0] [7:0] Read Read
0xEC CHx_PELCO16_00 (x = Channel Number)
0x6D : Coaxial Output 16bit Data1 Read Register
0xED
0x6E
0xEE CHx_PELCO16_01 (x = Channel Number)
0x6F : Coaxial Output 16bit Data2 Read Register
0xEF
0x70
0xF0 CHx_PELCO16_02 (x = Channel Number)
0x71 : Coaxial Output 16bit Data2 Read Register
0xF1
0x72
3~4
0xF3
0x74
0xF5
0x76
0xF7
0x78
0xF9
* Registers of Bank 5 ~ Bank 10 are not for users.

In this regard, please refer to the Guide note.

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Chapter 7
Guide Note
7.1 Video Format Setting Register
CH SP_MD SD_MD HD_MD ADC_CLK PRE_CLK DEC_CLK VCLK
1 0x85[3:0] 0x81[7:4] 0x81[3:0] 1x84[3:0] 1x8C[3:0] 1x8C[7:4] A: 1xCD[7:4]
Mode 2 0x86[3:0] 0x82[7:4] 0x82[3:0] 1x85[3:0] 1x8D[3:0] 1x8D[7:4] B: 1xCE[7:4]
3 0x87[3:0] 0x83[7:4] 0x83[3:0] 1x86[3:0] 1x8E[3:0] 1x8E[7:4]
4 0x88[3:0] 0x84[7:4] 0x84[3:0] 1x87[3:0] 1x8F[3:0] 1x8F[7:4]
1080P_30 0 0 2 0~3 0~3 4~5 4~5
1080P_25 0 0 3 0~3 0~3 4~5 4~5
720P_60 0 0 4 0~3 0~3 4~5 4~5
720P_50 0 0 5 0~3 0~3 4~5 4~5

AHD
720P_30 0 0 A 8~B 8~B 4~5 4~5
720P_25 0 0 B 8~B 8~B 4~5 4~5
SD_NT 0 C 0 6~7 6~7 4~5 4~5
SD_PAL 0 D 0 6~7 6~7 4~5 4~5
7.2 Each Format FSC Setting Register
CH Register BANK9
1 0x50 0x51 0x52 0x53
Mode 2 0x54 0x55 0x56 0x57
3 0x58 0x59 0x5A 0x5B
4 0x5C 0x5D 0x5E 0x5F
1080P_30 0x2C 0xF0 0xCA 0x52
1080P_25 0xAB 0x7D 0xC3 0x52
720P_60 0x2C 0xF9 0xC5 0x52
720P_50 0x2C 0xE7 0xCF 0x52

AHD
720P_30 0xED 0x00 0xE5 0x4E
720P_25 0x45 0x08 0x10 0x4F
SD_NT 0x1E 0x7C 0xF0 0x21
SD_PAL 0xCB 0x8A 0x09 0x2A

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7.3 When Auto Detection, Video Format Classifier
Read Register value
Resolution Field rate MODE
(Bank5~8 0xF0)
SD, 480i 60i 0x00 SD_480i60
SD, 576i 50i 0x10 SD_576i50
30 0x20 AHD_720p30
25 0x21 AHD_720p25
AHD, 720p
60 0x22 AHD_720p60
50 0x23 AHD_720p50
30 0x30 AHD_1080p30
AHD, 1080p
25 0x31 AHD_1080p25
7.4 Coaxial Setting Register
AHD
1080p 720p
bank addr description
30p 25p 30p 25p 60p 50p
5~8 0x7C COAX_RX_SYNC/SRC SEL 0x11 0x11 0x01
0x00/ 0x80 CHx_BAUD 0x27 0x15 0x1A
0x03/ 0x83 CHx_BL_TXST 0x0E 0x0D 0x0E 0x0D 0x0E 0x0D
0x0D/ 0x8D BL_HSP 0x48 0xB4 0x30 0x35 0x20 0x16
0x0E/ 0x8E BL_HSP 0x02 0x00 0x00 0x00
3~4
0x05/ 0x85 CHx_ACT_LEN 0x03 0x03 0x03
0x0A/ 0x8A CHx_TX_BYTE_LENGTH 0x03 0x03 0x03
0x0B/ 0x8B CHx_PELCO_8BIT 0x10 0x10 0x10
0x2F/ 0xAF CHx_EVEN_SUM 0x00 0x00 0x00
※ If you want to know about 3/4/5M NRT format, please contact us([email protected]).

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Chapter 8
ELECTRICAL CHARACTERISTICS
8.1 ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN. TYP. MAX. UNIT REMARKS

VDD1A/
1.2V Power Supply Voltage -0.5 - 1.8 V
VDD1D
VDD3A/
3.3V Power Supply Voltage -0.5 - 4.6 V
VDD3D
VDD3D+
Voltage for Digital Input pins VDl -0.5 - V
0.5
Voltage for Analog Input pins VAl -0.5 - 1.92 V
Storage Temperature TS -50 - 150 ℃
Junction Temperature TJ -40 - 125 ℃
Vapor phase soldering (15 Sec) TVSOL - - 220 ℃
* Note : This Device should be operated under recommended operating condition. Since, absolute maximum rating condition can
either cause device reliability problem or damage the device sufficiently to cause immediate failure.
8.2 RECOMMENDED OPERATING CONDITION

VDD1A/
1.2V Power Supply Voltage 1.1 1.2 1.3 V
VDD1D
VDD3A/
3.3V Power Supply Voltage 3.0 3.3 3.6 V
VDD3D
Ambient operating temperature VA 0 - 70 ℃
8.3 DC CHARACTERISTICS
Input Low Voltage VIL -0.3 - 0.8 V
Input High Voltage VIH 2 - VDD3D+0.3 V
Input Leakage Current IL - - ±10 uA
Input Capacitance CIN - 5 - pF
Output Low Voltage VOL - - 0.4 V
Output High Voltage VOH 2.4 - - V
Tri-State Output Leakage Current IOZ - - ±10 uA
Output Capacitance COUT - 5 - pF

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8.4 AC CHARACTERISTICS
( Power Supply Current )
1.2V Digital Power Supply Current IVDD1D - TBD - mA
3.3V Digital Power Supply Current IVDD3D - TBD - mA
1.2V Analog Power Supply Current IVDD1A TBD mA
3.3V Analog Power Supply Current IVDD3A - TBD - mA
( Clock Pin )
SYS_CLK frequency fSYS_CLK - 27.0 - MHz
SYS_CLK duty cycle fDUTY 45 - 55 %
( Reset Pin )
RSTB setup time tSU 1 uSec
RSTB pulse width low tPWL_rstb 1 uSec
RSTB release time (low to high) tREL_rstb 10 uSec
( Host Interface Pins )
SCL clock frequency fSCL - 100 400 kHz
Hold time(repeated) START condition. tHD:STA 0.6 - - uSec
LOW period of the SCL clock tLOW 1.3 - - uSec
HIGH period of the SCL clock tHIGH 0.6 - - uSec

Set-up time for a repeated START
tSU:STA 0.6 - - uSec
condition
Data hold time tHD_DAT 0 - 0.9 uSec
Data set-up time tSU_DAT 100 - - ns
Rise time of both SDA and SCL signals tr 20 - 300 ns
Fall time of both SDA and SCL signals tf 20 - 300 ns
Set-up time for STOP condition tSU:STO 0.6 - - uSec

Bus free time between a STOP and
tBUF 1.3 - - uSec
START condition
Capacitive load for each bus line Cb - - 400 pF
Figure 8.1 SCL and SDA Timing Diagram

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Chapter 9
AUDIO SYSTEM APPLICATIONS
9.1 AUDIO 4-Channel Mode
1 AIN1 ADATA_REC ADI_REC

2 AIN2
3 AIN3 HOST System
Master SYNC_REC SYNC_REC
4 AIN4 (REC Slave)
CLK_REC CLK_REC
DECODER
MIC 1 MICIN1
Speake
AOUT ADATA_PB ADO_PB HOST System
(Live, PB)
(PB Master)
Slave SYNC_PB SYNC_PB
CLK_PB CLK_PB
Figure 9.1 AUDIO 4-channel Mode

2 AIN2
3 AIN3 HOST System
4 AIN4 (REC Slave)
CLK_REC CLK_REC
MIC 1 MICIN1
DECODER_1
Speake AOUT ADATA_PB ADO_PB HOST System

(PB Master)
27MHz
SYS_CLK
OSC CLK_PB CLK_PB
ADATA_CASI
ADATA_CASO
5 AIN1
6 AIN2
7 AIN3
8 AIN4
MIC 2 MICIN1 DECODER_2
Speake AOUT
SYS_CLK

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2 AIN2
3 AIN3 HOST System
4 AIN4 (REC Slave)
CLK_REC CLK_REC
MIC 1 MICIN1
DECODER_1
Speake AOUT ADATA_PB ADO_PB HOST System

(PB Master)
27MHz
SYS_CLK
OSC CLK_PB CLK_PB
ADATA_CASI
ADATA_CASO
5 AIN1
6 AIN2
7 AIN3
8 AIN4
MIC 2 MICIN1 DECODER_2
Speake AOUT
SYS_CLK
ADATA_CASI
ADATA_CASO
9 AIN1
10 AIN2
11 AIN3
12 AIN4
DECODER_3
Speake AOUT
SYS_CLK
ADATA_CASI
ADATA_CASO
13 AIN1
14 AIN2
15 AIN3
16 AIN4
DECODER_4
Speake AOUT
SYS_CLK

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Chapter 10
PACKAGE INFORMATION
Figure 10.1 NVP6134C 76Pin Package Information

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NVP6134C Datasheet

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NVP6134C

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© Copyright Nextchip Corporations, Ltd., 2016

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Features 2. Audio Codec

Mute Cascade ADATA_CASO

2016.10.12 (REV 1.0) NVP6134C Data sheet

2016.10.12 (REV 1.0) NVP6134C Data sheet

2016.10.12 (REV 1.0) NVP6134C Data sheet

2016.10.12 (REV 1.0) NVP6134C Data sheet

Figure 1.1 Pin Assignments

2016.10.12 (REV 1.0) NVP6134C Data sheet

2016.10.12 (REV 1.0) NVP6134C Data sheet

2016.10.12 (REV 1.0) NVP6134C Data sheet

2.1 FUNCTIONAL OVERVIEW

Figure 2.1 Universal RX Video Processing of NVP6134C

2016.10.12 (REV 1.0) NVP6134C Data sheet

SPL_MD AHD_MD VIDEO_FORMAT

AHD_5M_12.5P 12.5 2592x1944 Flexible

AHD_4M_15P 15 2560x1440 Flexible 0x4 0x4

AHD_3M_18P 18 2048x1536 Flexible

AHD_1080_30 30 1920x1080 Flexible 0x2

AHD_1080_25 25 1920x1080 Flexible 0x3 Don’t care

AHD_720_60 60 1280x720 Flexible 0x4

AHD_720_30 30 1280x720 Flexible 0x6

AHD_720_25 25 1280x720 Flexible 0x7

Table 2.1 NVP6134C INPUT VIDEO IMAGE FORMATS

2016.10.12 (REV 1.0) NVP6134C Data sheet

Figure 2.2 Anti-aliasing Filter characteristic

2.4 GENLOCK (ROBUST SYNC DETECTION, ROBUST NO-VIDEO DETECTION)

2016.10.12 (REV 1.0) NVP6134C Data sheet

Figure 2.3 Band Split Filter Characteristic

2.6 LUMA PROCESSING

Figure 2.4 Peaking Filter Characteristic

2.7 CHROMA PROCESSING

Figure 2.5 Chroma Process

Figure 2.6 Chroma Low Pass filter Characteristic

2016.10.12 (REV 1.0) NVP6134C Data sheet

Address (Bank1) state Data Output of Port X

Table 2.2 Data Output Pin Order Control

Address (Bank1) state Data Output of Port X

Table 2.3 Output Clock and Data Direction Control

2016.10.12 (REV 1.0) NVP6134C Data sheet

2.9.1 ITU-R BT.656/BT.1120 FORMAT

EAV Code A SAV Code Active number of pixel Data

Figure 2.7 Region of active is constant

2.9.2 ITU-R BT.601 FORMAT

Figure 2.8 BT.601 Interface

2016.10.12 (REV 1.0) NVP6134C Data sheet

2.9.3.1 AHD720P @ 30P/25P, 60P/50P H/V Timing

EAV Code Blanking SAV Code

4 732 / 1392 4 2560

Figure 2.9 AHD720P@30P/25P, 60P/50P Horizontal Timing Diagram

Figure 2.10 AHD720P@30P/25P, 60P/50P Vertical Timing Diagram

2016.10.12 (REV 1.0) NVP6134C Data sheet

EAV Code Blanking SAV Code

4 552 / 1432 4 3840

Figure 2.11 AHD1080P@30P/25P Horizontal Timing Diagram

Figure 2.12 AHD1080P@30P/25P Vertical Timing Diagram