ROSA DW50 MB Troubleshooting Guide

2010.3.10

1. Foreword.................................................................................2

2. DW50 MB Composition Structure.......................................3

2.1 System working principle..............................................................4

2.2 System Architecture Diagram........................................................5

3. Troubleshooting by Error code............................................6

3.1 System can't power on – NP00......................................................6

3.2 Sound Function Test Bad (Audio Function NG) – SA00............18

3.3 Auto Power Shutdown – AP00....................................................24

3.4 LCD no display – ND00..............................................................34

3.5 LP00 – Internet dysfunction.........................................................46

 1. Foreword

As a FAE, I get a lot of Fail M/B every day, and our job is to find the problem accurately,
solve it quickly, and cooperate. Help other relevant departments to formulate long-term effective
countermeasures to achieve the goal of improving production line yield. M/B is tested according
to Fail phenomenon. Subdivided into many Error Codes. Below I will give a brief introduction to
some common Error Codes encountered in analysis and repair. Novice reference. (Note: Because
notebook is a complex system combining software and hardware with many aspects of expertise,
in this, it is a simple introduction from the perspective of maintenance. For in-depth understanding
and research, you can refer to professional information).

This Troubleshooting Guide is based on the DW50 composition architecture, working principle
and often encounter some major malfunctions.The maintenance experience of the image was written
to allow the novice to understand the structure and operation of the board, and system and logic
problem analysis steps and methods, and then efficient maintenance, to improve the quality of
maintenance and reduce the production of "iron plate" student; at the same time, using the
Troubleshooting Guide to quickly break down the maintenance judgment steps into Repair SOP
for RT novicesuse.
2. DW50 MB component architecture

DW50 MB is composed of CPU (CPU1), PCH (U2001), and graphics card (U8001). KBC (U3701),
BIOS (U6202), Clock chip (U701) and other peripheral components. CPU is mainly responsible for
execution and arithmetic logic operations, and through the DMI FDI Bus and PCH, through the CPU
to display the chip, memory body, PCH communication, and PCH in addition to storage devices
(HDD, CDROM, Card Reader), network, USB, Audio. In addition to the Codec link, it is linked to KBC
via LPC Bus.

M/B system main bus introduction:

1. DMI (Direct Media Interface) BUS:
DMI (Direct Media Interface), as a bus that connects the CPU to the PCH, uses a
serial point-to-point connection.The bandwidth of the transmission is 2.5 GT/s.
2. Main Memory BUS:
The memory bus (Channel A & Channel B) used to connect the CPU to the DIMM
Slot, its clock Arrandale. It is 800/1066MHz and Clarksfield is 1066/1333MHz.
3. FDI (Flexible Display Interface) BUS:
FDI stands for Flexible Display Interface. As a bus connected to the PCH, the
sequence is point-to-point. Connection method. The transmission bandwidth is
2.7GT/s.
4. PCI Express ( referred to as PCIe) BUS:
PCI Express is not a patent for high-performance graphics cards, it gradually
replaces the PCI interface on the existing South Bridge, its work. The clock is
100MHz and the transmission rate is 2.5Gbps.
5. USB 2.0 BUS:
The USB 2.0 controller integrated in the PCH chip is connected by a universal
serial bus, and its interface can be divided into standard USB and Mini USB
interface, standard USB interface for connecting Card Reader chip, USB port is
connected to Camera and Finger Printer Connector; the Mini USB interface is
used in Bluetooth. On the connector, the Mini USB differs from the standard
USB interface by adding an ID pin to the Mini USB. USB 2.0. The working clock
is 100MHz and the data transmission rate is 480Mbps.
6. LPC BUS:
LPC (Low Pin Count) busbar, replacing the ISA busbar on the previous Southbridge,
mainly PCH and KBC chips connected bus, operating at 33MHz. Also via KBC with
Touch Pad connector, keyboard connector, and KBC link.
7. SPI (Serial Peripheral Interface) BUS:
The bus that KBC uses to connect to the BIOS uses a 4-wire synchronous sequence
transmission with an operating frequency of 33MHz.
8. SATA (Serial ATA) BUS:
SATA controller integrated in the South Bridge chip, which uses serial transmission of
data and HDD Connector and CD-ROM Connector connection.
9. Azalia Link:
The Azalia controller integrated in the South Bridge chip is connected to the external
Audio Codec chip using Azalia Link. Its single channel transmission has a bandwidth
of 24M/s. In addition, Azalia Link supports multi-channel input and output.
 The principle of MB system operation, that is, the boot process is divided into hardware boot
and software boot. Hard boot refers to the action of POWER. The soft start part refers to
the POST process of the BIOS. First hardware startup and then software startup, understand the
boot process motherboard function maintenance is very important. First, the working power and
oscillation frequency should be provided to each part, and then the reset signal is the action to
reset the PCH and CPU is Power Sequence reference learning. Will go to the BIOS when the CPU
is reset to perform the POST (Power on self test) startup procedure, and POST will target the chipset
and I/O devices on the MB. (Display, Audio codec, LAN, CIR, Keyboard, Touch pad, Card reader,
USB), storage device (Memory, CD-ROM, HDD) and protection devices (FAN, Thermal) are tested,
and will not be opened until POST is correct. Start loading the operating system (DOS or Windows).
The Windows interface is currently factory import testing and Burn in and most the operating
system most commonly used by users. Before you officially start operating the system, Windows
must first drive the various parts. After the program is started, the main functions on the MB can be
started.

2.2 System Architecture Diagram

(DW50 MB Sistem Architecture Diagram)

 3. Troubleshooting by Error code

3.1 System can't power on - NP00

Definition: When the power switch is pressed, the power indicator does not light and the fan
does not rotate.

First of all, according to the definition of NP00, "the power LED does not light up", and the
fan does not turn, the LCD/CRT does not display, first go to the phase it should be confirmed that
the NP00 that the tester really means is still only a bad function of these functions. For example,
"Power LED light is not is "light" caused by NP00 or power lamp related circuit and signal fault?
(Refer to the maintenance of each Error Code).

3.1.1 Power On Sequence

Below we are going to discuss the real NP00 after the DW50 MB judgment. We have already
understood the NB MB whole system. Power on sequential timing and system power management
power on sequence for DW50 MB is as follows:
(DW50 MB Power on sequence)
3.1.2 M/B action principle

When the M/B is connected to the external power supply (Adaptor or Battery) without pressing
the Power Button, the circuit will immediately 5V_ALW2, 3.3V_RTC_LDO voltage, in particular, it
should be emphasized that: Adapter and Battery respectively, when the Power Button is not pressed.
There is a certain difference in the generation of pressure. When the party Adapter is connected,
DCBATOUT=19V will generate 5V_ALW2, 3.3V_RTC _LDO; then, with S5_Enable turned on,
TPS51125 will generate +5V_ALW, +3.3V_ALW and LAN in turn._S5 part of the voltage; and when
Battey is connected, +PWR_SRC = 14.5V, only 5V_ALW2, 3.3V_RTC_LDO voltage. And S5_Enable
is only sent after the Press Power Button, KBC will be sent. This part of the voltage is before booting.
The voltage is closely related to the corresponding PWM circuit in the system.

Press Power Button, a low level signal KBC_PWRBTN# is sent to KBC (U3701), then KBC sends
The signal PM_PWRBTN# notifies the PCH to start, and the south bridge sends the PM_SLP_S3# after
receiving the PM_PWRBTN# signal.Open each PWM and LDO circuit with PM_SLP_S4#, PM_SLP_S3#
and PM_SLP_S4# as Enable signalsThereby generating a basic point pressure. Basic point pressure in
the system (3.3V_RUN, 5V_RUN, 1.8V_RUN, 0.75V_DDR_VTTAfter 1.05V_RUN, 1.5V_RUN) has been
OK, generate RUNPWROK to PU4901 through an AND circuit

PU4901 will send +1.05V_VTT and VTT_PWRGD signals to PQ4901 after receiving
RUNPWROK.Switched to H_VTTPWRGD to PCH, PCH will send PM_PWROK to KBC when
receiving this signal, KBCWhen PM_PWROK is received, the corresponding IMVP_VR_ON
signal is sent to the VCC_CPU_CORE PWM circuit.The core operating voltage VCC_CORE of
the CPU is generated, so that all the voltages of the system are turned on. For details, please
refer to DW40System voltage block diagram.

(DW50 system voltage block diagram)

In summary, all NP00 can be divided into three situations:

1. S5 Voltage

First, the S5 voltage is the voltage that exists on the M/B when the Adapter is connected
without pressing the Power Button. Regardless ofWhether Adapt or Battery will generate a
DCBATOUT voltage through its own line, it will also generate3.3V_RTC_LDO and 5V_ALW2.
PU4504 After receiving this voltage, ACAV_IN (high) signal will be generated and passed.
The PQ4504 (N7002) converts it to AC_IN#(low) and sends it to the KBC to inform the system
that there is an Adapter access. KBCWhen the working conditions are sufficient, it will reset
ECRST#(high) and generate S5_Enable(high) to start.3V/5V_EN signal in the Controller
TPS51125. Generates 5V_ALW and 3.3V_ALW voltages through the PWM circuit.5V_ALW
and 3.3V_ALW voltages are generated when the EN (5V_EN and 3V_EN) signals are normal
in AC mode,Then 3.3V_ALW is converted to 3D3V_LAN through the LDO circuit, and
3.3V_ LAN is generated by the LDO circuit.+DVDD12 (1.2V) voltage.Please refer to Figure S5
for the working principle of voltage:

(S5 voltage block diagram)

2. S3 Voltage

The so-called S3 voltage refers to some voltages needed to save sleep related information
in addition to the S5 voltage on the system during sleep.Corresponding to the SUS voltage we
often talk about, ie +1.5V_SUS. He generated 5V_ALW through the PWM circuit, of course.To
be the correct EN signal, that is, the PM_SLP_S4# signal. Please refer to the block diagram of
voltage operation principle in Figure S3.

(S3 voltage block diagram)

3. S0 voltage and VCCCORE voltage

The so-called S0 voltage is Run Power, the voltage other than the S5 and S3 voltages
when the system is turned on. For thisPart of the voltage is basically achieved in the DW
series through the LDO circuit. Basically, the voltage is passed through a control signal.The
chip is directly converted and generated, the circuit is relatively simple and will not be
introduced here.The CPUCORE voltage is the last voltage on the main board. To be normal,
there is a condition that other S0 voltages are produced.After the OK, a RUNPWROK signa
will be sent. As long as there is a SUS or RUN voltage is abnormal, it is sent to the CPUCORE.
There is a problem with the EN signal of the chip, and the resulting PWM circuit is not normal,
so CPUCORE will have problems.

CPUCORE If the value is not normal, in addition to confirming the feedback circuit, also confirm
whether its VID signal is normal. SpecificPlease refer to the +VCC_CORE voltage working
principle block diagram.

(+VCC_CORE voltage working principle block diagram)

According to the action principle of the above DW50 MB Power part, for the novice in
the maintenance of the corresponding bad MB, the preferred dimensionRepair judgments
can be carried out in accordance with the above confirmation conditions. It is not difficult
to see the overall steps:The first step; checking whether the power supply of each main
IC is normal,Second step; checking each input signal,Third step; checking data and
feedback signals,The fourth step; check the part body.

In the DW50 MB Power section, whether it is the ALW part or SUS .RUN and part
of VCC_COREIt is composed of PWM or LDO circuit. No matter what voltage it outputs,
its circuit will not change at all.The flow chart of the PWM circuit and LDO circuit operation
can be referred to as follows:
(LDO circuit judgment flow chart)
 (PWM circuit judgment flow chart)

For detailed analysis, please refer to the following maintenance judgment process in order:

1. Judgment process:

Possible cause of abnormal voltage of S5.

a. s5 voltage impedance is abnormal, one by one from the relevant parts.
b. Check if 3V_EN and 5V_EN are normal. If not, please refer to the following judgment process.
1. Check its impedance to see if there is an abnormality.
2. Check if the supply voltage and VREF voltage of KBC are normal.
3. Check if AC_IN# is LOW.
4. Check if KBC's ECRST# is normal.
5. Check if the SPI bus and voltage between KBC and EC ROM are normal.
6. Check if the KBC and EC ROM bodies are OK.
7. Check the line for Open.
c. Check if the power supply voltage and REF voltage of the TPS51125 are normal.
d. Check that the TPS51125 generates a 3/5V_S5 PWM circuit.
e. TPS51125 body.
Refer to the relevant circuit diagram:

(S5_Enable related circuit not shown)

 (PU4603 supply voltage and REF voltage circuit)

2. Judgment process :

Possible cause of abnormal S3 voltage.

a. S3 voltage impedance is abnormal, and is excluded one by one from related parts.
b. Check if the input voltage PM_SLP_S4# of PU5002 is normal. If it is not normal, please
refer to the following judgment process.
1. Check if the PCH input voltages RSMRST#_KBC and PM_PWRBTN# are sent from KBC.
2. Check the RTC module of the PCH for any abnormalities.
c. Check if the PU5002 supply voltage and REF are normal.
d. Check if the PWM circuit that generates the S3 voltage of PU5002 is normal.
e. PU5002 body.

Refer to the relevant circuit diagram:

 (PCH input signal and RTC module diagram)

(Input of PU5002. Power supply. REF FB voltage circuit diagram)

3. Judgment process :

Possible cause of S0 voltage abnormality (take the +1.8V_Run LDO circuit as an example)
.a. S0 voltage impedance is abnormal, one by one from the relevant parts.
b. Check the input voltage of PM5102 PM_SLP_S3# to see if it is normal. If it is not normal, you
can judge the process in comparison with S3. bJudging process.
c. Check the power supply and output of the PU5102.
d. PU5102 ontology

Refer to the relevant circuit diagram:

(Several parts of the LDO circuit check)

3.2 bad sound function test (Audio Function NG) – SA00
Any bad phenomenon related to sound effects, SA00 This Error code is collectively
referred to, and SA00 will be based on variousDifferent bad phenomena are subdivided
into SA01 (internal speaker silence or abnormal sound), SA03 (microphone can not record
or abnormal sound), SA05 (outsideThe speaker is silent or abnormal), SA14 (the internal
speaker is silent) and so on.

Common audio function test (Audio Function NG) has the following conditions
1. SPK has no sound , abnormal sound , no sound on left or right channel
2. MIC cannot record

3.2.1 SPK has no sound or abnormal sound , no sound on left or right channel

The MB sound system mainly has the digital part IHDA (High Definition Audio) integrated
with the South Bridge (U2001).HDA BUS and independent linear Azalia Codec (Coder-Decoder)
U3001 (integrated amplifier)composition. The audio signal from Azalia Codec (U3001) pin40/41,
43/44 is output to SPEAKER CON, throughSpeaker outputs the sound. The following is the SPK
sound output block diagram:

The following are the first confirmation conditions for SPK no sound:

1. Azalia BUS

The sound system mainly integrates the digital part of the PCH IHDA (High Definition Audio)
through Azalia BUS and sound effects.

(CODEC) communication

PCH_AZ_CODEC_BITCLK Frequency
PCH_SDIN_CODEC Data input
PCH_SDOUT_CODEC Data output
PCH_AZ_CODEC_SYNC Synchronization signal
PCH_AZ_CODEC_RST# Reset signal
2. +AVDD +PVDD

Sound effect (CODEC) working voltage

3. AMP_MUTE#

When the AMP_MUTE# is high voltage 3.3V, the system turns off APM work.
When AMP_MUTE# is 2.6V low, the system starts APM work.
4. AUD_PC_BEEP

In addition, when the system receives some external or internal event alarm, the KBC
KBC_BEEP signal is synthesized.The AUD_PC_BEEP signal is sent to Azalia Codec;
the same south bridge will generate the ACZ_SPKR signal.AUD_PC_BEEP is sent to
Azalia Codec and will eventually generate a BeBe warning.

5. AUD_SPK_R+ AUD_SPK_R- AUD_SPK_L+ AUD_SPK_L-

In the analysis of maintenance SPK no sound according to the following flow chart.
No sound is judged according to the following flow chart:

Please refer to the following maintenance judgment process in order:

1. A judgment process : Reasons for Azalia BUS exception

1. First confirm whether the CODEC and South Bridge IHDA module lines have TRACE OPEN
2. The multimeter confirms the ground resistance of the Azalia BUS, and the difference cannot
exceed 10 ohms.
3. The oscilloscope measures whether the signal is abnormal, in which the waveform can not
have clutter, but also consider the peak value, as follows:

2. B judgment process: working voltage + AVDD + PVDD abnormal

1. Confirm that +5V_RUN is normal.

2. +AVDD is directly converted by the inductor L3002, abnormality can be checked l3002.c3015, c3016
3. +PVDD is converted by inductance L3003, L3001, check whether L3001, L3003, c3001,
c3014 are abnormal.
Refer to the relevant circuit diagram:

(+AVDD + PVDD power generation circuit )

3. C judgment process: AMP_MUTE# abnormal reason

1. Determine whether there is trace open condition u3001 (audio codec) 47# and u3701 (KBC) 30#
2. Determine if the PULL HIGH resistor r3004 is OK?

Refer to the relevant circuit diagram:

(Mute# control circuit )

4. D judgment process: AUD_SPK_R+ AUD_SPK_R- AUD_SPK_L+ AUD_SPK_L-Exception

1. Confirm that there is trace open condition according to the circuit.

2. Does the oscilloscope measure 2 sets of audio signals?
5. E judgment process: Protection circuit: Please refer to the following data

CAP+ CAP- CAP2 VREFFILT V- VREG

1.33V -1.31V 2.46 1.86V -2.66V 2.75V

3.2.2 MIC cannot be recorded

Make sure the SPK has sound, just can't record

Because the SPK is normal, for this case, it is only necessary to consider whether the sound
source obtained from the MIC is passed to the CODEC. OK, currently DW Mainboard

Both get the sound source from CAMERA, so we are considering the situation where CAMERA
works normally but cannot record

.For MIC not recording, first confirm the following conditions:

1. Is AUD_DMIC_IN0 abnormal?
2. Is AUD_DMIC_CLK_G abnormal?
3.3 automatic power-off / power off / power on
(Auto Power Shutdown) - AP00

When it is found that the system will automatically power off, shutdown and boot, etc., the
error code-AP00 as a general term,The part of the item can be subdivided into AP01 (Auto On
With Adapter), AP02 (Auto On With Battery), AP03 (fromWith Adapter), AP04 (Automatic
Shutdown With Battery). The system will automatically shut down and power off the problem,
generally returna number of possible conditions;
1. The temperature protection circuit on the MB starts and the entire system is forced to shut down.
2. The power supply circuit on the MB is shorted to ground, causing the MB to automatically power down.
3. An abnormality occurs in the power supply of a voltage module on the MB. Generally, the power supply
cannot be continuously supplied.
4. When a load is connected to a peripheral (such as ODD, HDD, USB, LCD...), the MB is automatically
powered off.
5. When an external input power (Adapter or Battery) is abnormal and does not supply power, the MB is
automatically powered off.
6. When the Cover switch is always enabled when it is powered on, it may cause the system to
automatically shut down
1. Auto Power On with Adapter - AP01

2. Auto Power Shutdown – AP03

From the first situation, MB does not detect the system temperature and control the
fan speed through the Thermal controllor.There is also a purely hardware-operated temperature
protection circuit to ensure that the Thermal Controllor on the system fails or fails to function.
At the time of the warmth, the protection mechanism can be used to protect the security of the
system. In the second situation, the power circuits on the MB are generally available.OCP and
OVP protection design, in order to prevent the abnormal power supply short circuit when MB
can start this mechanism withoutThe part on the board will be Damaged. Third, in four situations
one or more voltage modules appear in the power circuit on the MB.Can not continue to supply
power and cause automatic power off, mostly abnormalities in the PWM circuit. (Voltage IC and
upper and lower bridge MOS). Fifth, six shapesDue to external conditions, it is generally easie
to judge.
In addition to the automatic shutdown/power-down described above, this Error code
AP00 also includes an issue with automatic power-on. And usuallyThe reason for the system
to automatically power on, except that the RTC battery is dead, causes the power managemen
in the PCH to be set back to the initial value.When the ADT is inserted, causing the system to
boot up, it will be rare to cause the MB to automatically boot.

( DW50 Model System protection circuit block diagram)

Related signal explanation:

1.PWRBTN#
The PWRBTN key instantly pulls down the "PWRBTN" signal through a resistor R to convert
"KBC_PWRBTN# to the motherboard.Electricity.
2. RTCRST#
The Power Group explaining RTC to the system is ready.
3. PURE_HW_SHUTDOWN#
The temperature protection circuit will be powered off if the temperature control circuit has
serious problems before the system is started.
4. ECRST#
The Power Group explaining to the system KBC Chipset is ready.
5. BAT_IN#
The battery output BAT_IN# signal informs the KBC as a signal that the battery has been inserted.
6.AC_IN#
After the ADT is inserted, the charge IC will send an AC_IN# signal to the KBC when it receives
+DC_IN_SS, confirming that the external power supply is OK.
7.S5_ENABLE
KBC is issued to a required condition that produces a 3D3_S5&5V_S5 voltage chip.

1. Auto Power On With Adapter - AP01

AP01 is connected to the ADT system automatically, what we see is when access
What we see is that the PWR LED lights up when the ADT is connected, and the wind Fan turn.
To analyze the automatic boot, we will first look at the normal boot action: when accessing ADT
through START SOFT andAfter the PWM & MOSFET, the S5 voltage will be generated. When
the S5 voltage is available, it will be supplied to the KBC. After the KBC is received, it will be
sent out.“RSMRST#_KBC” converts “RSMRST#” to PCH1 through the regulator D1, and presses
when these signals are available.The PWRBTN key instantly pulls down the "PWRBTN" signal
and converts "KBC_PWRBTN#" through a resistor R. The signal is sent toAfter KBC, KBC will
issue "PM_PWRBTN#" signal to convert "PWRBTN#_ICH" to PCH1 through diode D.PCH1 issues
the "PM_SLP_S4#" & "PM_SLP_S3#" signals to turn on the S3&S0 voltage respectively, thus
giving each CHIPThe working voltage is supplied and the power is turned on normally. And the
ADT automatic boot is to disrupt the basic working sequence, in our absenceWhen the
"KBC_PWRBTN#" is triggered, the S3&S0 voltage is generated in advance, and we only need
to find out the fault point. RelatedThe working principle diagram is as follows:

(DW50 Model system boot block diagram)

1.1. When KBC_PWRBTN# will automatically boot when it is LOW

+3.3_RTC_LDO is LOW

Possible reasons for causing +3.3_RTC_LDO to be LOW:

1. CMOS battery is dead
2. The R3747 R3734 R6202 is abnormal. Please measure the impedance value
3. D6201 air welding or poor body
4. The RTC1 interface is poor and cannot be in good contact with the battery.
1.2. When PM_PWRBTN# will automatically start when it is LOW

Measure with an oscilloscope PM_PWRBTN#

Possible reasons for the PM_PWRBTN# signal not being output:

1. U3701 or U2001 body is bad
2. Confirm U3701, PIN117 to R2213 line is OK.
1.3. Sometimes it will automatically boot when the power is plugged in before the BIOS is swiped.
It will also automatically power on when plugged in before.
This is the mode that should be turned on for the power of the original version of the BIOS.
Just refresh the BIOS version.

2. Automatic power off (Auto Power Shutdown) – AP03

AP03 automatically power off, press the power button

When the power is turned off automatically, press the power button (or plug in the power) and the light
will be off when it is turned off.

2.1 When the power is turned off automatically after power-on, you can measure the voltage between
+3.3V_ALW/+5V_ALW and +1.05V_RUNP.

Whether the voltage is short-circuited or abnormal. For the M/B of the voltage problem,
the isolation between the front and rear machines is generally used to avoid the phase.
Mutual interference.

Judgment flow chart:

2.2 The following three figures are temperature protection circuits. If the temperature control
circuit has serious problems before the system is started, U3901.Pin12 hasEffect (becomes low)
causes PURE_HW_SHUTDOWN# to be pulled low, Q3702 turns ECRST# low, and D4201 is also
turned on3V_5V_EN pulls low. These two signals are sent to KBC at the same time to make M/B
unable to boot.
 (DW50 Model temperature protection circuit)

2.3 After power on, the temperature control chip U3901 detects the temperature on the M/B through
Q3901 and Q3905, Q3904, and passes the U3901.SMBUS and KBC communication. If any of
the three triodes are broken, it will also cause the power to be turned off or the power is turned
off.Electric. As shown below

(DW50 Model temperature detection circuit)

2.4. When the battery is automatically powered off after power-on, focus on the BATT_SENSE,
BAT_IN# signal, this signal is to tell KBC nowThe battery has been plugged in, and it will
automatically turn off if the system does not recognize the battery properly.

(DW50 Model battery detection circuit)

Possible causes of automatic power failure after the battery is turned on:
BATT_SENSE, BAT_IN# signal is abnormal.
1. Check if the PR4402, CON1 and KBC U3701 bodies are OK.
2. Check if the line between them is normal.'
3.4 LCD no display - ND00

When the power switch is pressed, the power indicator lights, the fan turns, and the hard
disk indicator flashes, but the LCD has no screen display.In the case of LCD no picture display,
the following two phenomena are generally encountered:
1. LCD has no image, but has backlight
2. LCD noImage, and there is no backlight.
Therefore, before the maintenance judgment, it should be differentiated before repairing.
(mentioned in the followingPCH, take Intel's PCH (Graphics and Memory Controller Hub)
to illustrate that this PCH has a built-in graphics controller)

1. When the phenomenon is that the LCD has no image but has backlight output:
First, the PCH reads the EDID value on the driver circuit through the SMBUS.
The purpose is to detect whether the LCD is saved.in. When it is confirmed that the
LCD is present, the signal of "LCDVDD_EN_PCH" will be sent to the switch IC, and
the switch IC will receive the signal.After that, the "LCDVDD" power supply will be
output to the LCD driver circuit; after the driver circuit receives the power, it will reset
and perform at the beginning.Start setting, then the Northbridge will pass the preset
value (LCD output) of the video output in the BIOS.The LVDS Transmitter transmits
the image from the LVDS BUS to the drive circuit of the LCD to complete the image
output. Related actionsFor the block diagram, please refer to the LCD image output block diagram.

LCDVDD_EN_PCH Switch IC +LCDVDD

D5407 U5403 Connector
LCD1

LCD Module

LVDS LVDS
LVDS BUS
Transmitter Receiver LCD screen

LDDC_DATE Drive circuit

PCH
U2001 SM BUS EDID
LDDC_CLK Backlight control circuit

EDID

(LCD image output block diagram)

According to the above, as long as the "+LCDVDD" signal is checked for output, it can be judged
that the LCD is not detected or has a detectThe LCD was detected, but the image was not transferred
from the LVDS BUS to the LCD, so the "+LCDVDD" signal was taken as the first check.Check the
location. For the detailed maintenance judgment process, please refer to the maintenance judgment
process of LCD without display.The following are the conditions for initial confirmation when the LCD
has no screen display:

1. LCDVDD :
This output power is used in the drive circuit inside the LCD. If the power is not output to the line on the LCD, the LCD
will not be displayed.

2. LCDVDD_EN_PCH :

When the Northbridge detects the LCD , it will send the LCDVDD_EN_PCH signal to the Power switch
circuit as the LCDVDD power output.Signal,
3. LDDC_DATA_CON, LDDC_CLK_CON :
The north bridge is used to detect the presence of the LCD unit. If the LCD unit is not detected, the LCDVDD
power will not be output.

4. BLON_OUT, PANEL_BKEN:
Sended by the KBC PCH as a control signal to turn on the LCD backlight.

5. GFX_PWR_LCD :

High voltage power supply to the LCD,

6. LVDS BUS:

The three primary colors and clock signals supplied to the LCD are sent by the PCH.

7. +3VS_VCCA_LVD :

As an analog and digital input power supply for the PCH internal LVDS controller,

8. 1.8VS_VCCTX_LVDS :

I/O power to the LVDS control chip in the PCH.

A judgment process :

Resulting in + LCDVDD possible cause of the anomaly :

1. LCDVDD_EN_PCH signal is not sent to D5407, please check U2001 body and U2001toR5423 and R5423to D5407 Trace

Whether Open Trace,

2 LCDVDD_EN_PCH signal is sent to D5407 Please check D5407 U5403 R5409 R5411 body,

3 Check if the line between +3.3V_RUN voltage and related components is ok.

4 Check if the line and ground impedance between U5403 PIN3 and LCD1 are OK.

Related circuit diagram reference(DW40 UMA MB + LCDVDD open circuit)

B judgment process :
Resulting in SM BUS ( LDDC_DATA_CON, LDDC_CLK_CON ) possible causes of abnormal signal output
Possible reasons for output anomalies :
1 U2001R5421 R5420 Poor body,
2 RN5404 Pull High Exclusion is abnormal,

3 Confirm that the lines of U2001to R5421 R5420 and R5421 R5420 to LCD1PIN13&14 are OK.
The relevant circuit diagram is shown in the figure below:
Related photo explanation:
When the data is being transmitted the normal waveform should look like the picture below.

LDDC_DATA_CON LDDC_CLK_CON

C judgment process :
Cause BLON_OUT possible causes no output signal
Possible reasons for no output :
1 If the KBC (U3701) body is confirmed, it is OK, and it is necessary to measure whether the required voltage is normal.

2 R5406 R5407 impedance is abnormal,

3 Check if the lines of U2601PIN27 to R5406 and R5406toLCD1 are OK.

The relevant circuit diagram is shown in the figure below:
D judgment process :
Possible reasons for the signal PANEL_BKEN not output :
1.PANEL_BKEN_PCH signal is not sent to U3701, please check U2001&D3712 body and U2001to D3712 Trace open

2. Confirm that the R2011R3739 body is OK.

3. Confirm if U3701 is ok.

The relevant circuit diagram is shown in the figure below:

E judgment process :
Cause GFX_PWR_LCD possible causes no output voltage
Possible reasons for no output :
1. Confirm whether the C5405 C5401 F5401 body and ground impedance are OK.
If there is any abnormality, follow the relevant circuit to track and repair it.
2. Confirm that the LCD1to F5401 line is OK.

The relevant circuit diagram is shown in the figure below:

F judgment process :
Cause LVDS BUS Possible causes no output signal
Possible reasons for no output :
1. Confirm that the R2002 RN2001 body is OK,
2. Use a multimeter to measure whether all LVDS BUSs on the LCD1 are normal to the ground. If there is
an abnormality, the analysis is U2001.
Poor body or LCD1 toR7409...R7415 or U2001to R7409...R7415 bad line,
3. Check if the voltage required for normal operation of U2001 is normal.
4. Confirm that the BIOS clock IC is OK.

5. Confirm that the LCD1 body is OK.

The relevant circuit diagram is shown in the figure below:
G judgment process :
Resulting in + 3VS_VCCA_LCD voltage Possible causes no output :
1. Confirm that the R2609 body is OK.
2. Confirm that +3.3V_RUN is OK.

3. Check if U2001 voltage is grounded to ground.

The relevant circuit diagram is shown in the figure below:

H judgment process :
Resulting in + 1.8VS_VCCTX_LVDS voltage Possible causes no output :
1. Confirm that the L2604 C2625 C2624 body is OK.

2. Confirm that +1.8V_RUN is OK.

3. Check if U2001 voltage is grounded to ground.

The relevant circuit diagram is shown in the figure above:

2. When the phenomenon is that the LCD has no backlight and no image output:

The PCH (U2001) on the M/B is responsible for the processing and output of the image.
The output of the image is not only through the LVDS interface to the LCD.It can also be switched
to the VGA Port via the RGB interface and connected to other external display devices (such as
CRT and projector). thereforeDuring the POST process, the BIOS will output the image according
to the settings of the screen display (LCD only, CRT only, Both).Go to the device. When the image
is to be switched to the display device, the display program of the device is executed, for example,
when the CRT is to be switchedWhen the LCD is displayed, the image output of the ADC is first
turned off, and then the image is output by the LVDS Transmitter.The North Bridge sends a
"GMCH BL_ON" signal to the KBC. After the KBC receives it, it sends a "BLON_OUT" to the LCD,
which will backlight.Turn on and let the LCD present the image. Related action block diagram LCD
no picture and backlight output block diagram.

ADC RGB VGA Port

Graphic
PCH Controller
LVDS BUS LCD Module
(U2001)
Connector
LVDS (LCD1)
Transmitter

BLON _OUT

PANEL_BKEN

KBC (U3701)
LPC BUS BIOS (U6203)
SPI BUS

Keyboard

(LCD no picture and backlight output block diagram)

According to the above, when using the "LCD&CRT" switch button on the keyboard to switch,
it is possible to initially judge the image because of the display.The fixed part, or the North Bridge,
has a problem in the image output. So use the toggle button for LCD&CRT switching, as the first A
check step. For the detailed maintenance judgment process, please refer to the LCD no-screen,
backlight maintenance judgment process.
 (Figure LCD no picture, backlight maintenance judgment)

3.4.2 CRT no display (CRT no display) - ND01

When the power switch is pressed, the power indicator light is on, the fan is turned, the hard disk
indicator is flashing, the LCD is displayed, but the CRT has no screen display.
The following are the conditions for the first confirmation when the CRT has no screen display:
1. 3.3V_CRT_LDO:
An analog input power supply to provide a DAC controller within the PCH,
2. JVGA_HS,JVGA_VS:
Used to control horizontal and vertical scanning signals,
3. 5V_CRT_RUN: the supply voltage of the CRT,
4. DDC_DATA_CON, DDC_CLK_CON: The detection signal of the CRT
The block diagram of the above related signals is shown below:

According to the above CRT, if there is a screen display, the main conditions to be judged are
to judge, firstly, the maintenance judgment is made, and the step-by-step approach is adopted.
Maintenance, so the first step is to check if the DAC voltage in the PCH chip is normal, and then
confirm other control signals.
Please refer to the following maintenance judgment flow chart for details.

A judgment process :
Possible cause of abnormality in +3.3V_CRT_LDO voltage output. Possible reasons for output anomalies :
1. Confirm that the U2001 L2603 R2602 C2603 C2604 C2605 body is OK,
2. Confirm that +3.3V_RUN is OK.
3. Check if U2001 voltage is grounded to ground.
The relevant circuit diagram is shown in the figure below:
B judgment process :
Cause JVGA_HS JVGA_VS signal output possible causes abnormal. Possible reasons for output anomalies :
1. U2001 R2004 U7408 RN7445 R7420 Poor body,
2. Check if the line of U2001to U7408 PIN2 PIN9 and RN7445 toCRT1PIN13&14 is OK.
The relevant circuit diagram is shown in the figure below:

Possible cause of C causing +5V_CRT_RUN voltage output abnormality.

Possible reasons for output anomalies :

1. Confirm that the D5504 C5510 body is OK.

2. Confirm that the +5V_RUN voltage value and the impedance to ground are OK.
3. Confirm that the CRT1 PIN9 to D5504 line is OK.
The relevant circuit diagram is shown in the figure below:
D judgment process :
Possible cause of DDC_DATA_CON DDC_CLK_CON signal output abnormality.
Possible reasons for output anomalies :
1. Confirm that the U2001 Q5517 R5593 R5592 body is OK.
2. RN5510 RN5513 Pull High Exclusion is abnormal,
3. Confirm that the CRT1 PIN12 PIN15 to Q5517 line is OK.
4. Confirm that the U2001to R5593 R5592 line is OK.
3.5 (LP00--- Internet dysfunction )

LP00 definition: press the power switch to display the boot, enter the test program of the
DOS environment, the program will ask for key-in OPCode and MAC Number (the MAC value
is unique, one-to-one with M/B 55Labley), then the system will write in andRead-out MAC Number
to do the check action. If the Check value is correct, it indicates MAC Pass, the program's reference
Under the guidance, connect the server G-Disk through LAN-Line. If there is an abnormality in this
process, we think it is LP00---networkMalfunction (LAN Function NG).

Common NG and maintenance judgment methods for LAN .

3.4.1. Brush LAN ID NG : Mainly check the working condition of LAN Chip (U3501) to see if it
really starts. USB barCode The gun is normal, and finally consider the communication
and body between PCH (U2001) and LAN Chip (U3501).
3.4.2. Unable to connect to the Internet : first press F12 to enter the boot option to see if there is
an Onboard INC item.The system does not actually detect the LAN Chip (U3501), starting
from the working conditions and the body of the LAN Chip (U3501).If there is an Onboard
NIC item, mainly check the connection between LAN inductor (XF6101) and LAN Chip
(U3501), and LAN.Inductance and RJ45 Conncetor (RJ45) connection.

The principle of the operation of the network link :

The operation principle of the network link: access the adpter or battery, by triggering
the kbc_pwrbtn# (low) signal,The KBC chip sends PM_LAN Enable(high) to turn on LAN_S5
power when all LAN_S5 voltages are working properly.After that, the LAN Chipset body will
send out the RSET signal to explain to the system that the Power Group of the LAN Chipset
is ready.At this time, 25Mhz Osil will drive the LAN Chipset at a 25Mhz oscillation frequency.
LOM_Disable#(low)Is a Lan Chipset shield selection signal, there are two states of "0", "1", the
"0" state indicates that the system is integrated inThe Mainboard's Lan Chipset is masked,
otherwise the "1" state tells the system that the LANChipset is unmasked.Enable state. For
Notebook, this signal is usually in the "1" usable state, considering integration and cost. Then
the CLK Generator will send a set of Clk_pcie_lan/Clk_pcie_lan# (100Mhz) oscillation frequencies
to the Lan Chipset to drivePCI-Express channel. The two sets of PCIE-bus are used to implemen
the modulation and demodulation between the south bridge (ICH) and the LAN Chipset.
The modulated or demodulated data signal is then transmitted to the RJ45 Interface via the LAN
inductor, using LAN-LINK as the medium.Realize network connection between terminals and
terminals, information sharing
 The following is a working block diagram via LAN:

(Working principle diagram)

It is the primary confirmation condition for LAN malfunction:

1. PM_LAN_ENABLE
Signal inverter for LAN shutdown, sent by the KBC chip PM_LAN Enable (high) to turn on+3.3V_LAN.

2. RSET
The Power Group that explains the LAN Chipset to the system is ready.
3.PLT_RST#:
Send a reset signal to the LAN chip for the system.
4. PCIE_IRXP3_LTXP3, PCIE_IRXN3_LTXN3; PCIE_ITXP3_LRXP3, PCIE_ITXN3_LRXN3.
Communication signal between PCH (U2001) and LAN Chip (U3501)
5.CLK_PCIE_LAN, CLK_PCIE_LAN#:
A set of PCH (U2001) chips to the Lan chip (U3501)PCIE clock signal.
6. NB_LOM_TRD0, NB_LOM_TRD0#; NB_LOM_TRD1, NB_LOM_TRD1#;
NB_LOM_TRD2, NB_LOM_TRD2#; NB_LOM_TRD3, NB_LOM_TRD3#

Four sets of communication signals for LAN chip (U3501) and LAN inductor (XF6101).

LAN common NG and maintenance judgment method.

1. Brush LAN ID NG: Mainly check the working condition of LAN Chip (U3501) to see if it
really starts. USB bar codeWhether the gun is normal, and finally consider the communication
and body between PCH (U2001) and LAN Chip (U3501)
2. Unable to connect to the Internet: First press the F12 to enter the boot option to see if there
is an Onboard INC item.There is no real frame measurement of the LAN Chip (U3501), starting
from the working conditions and the body of the LAN Chip (U3501), ifWith the Onboard NIC item
the main connection between the LAN inductor (XF6101) and the LAN Chip (U3501), and the
LAN is checked.Inductance and RJ45 Conncetor (RJ45) connection.

When we are unable to connect to the network, the first thing to consider is whether the voltage
working condition of the LAN Chip (U3501) is normal, ifThe normal LAN Chip (U3501) body will
automatically send a reset signal LANRSET to indicate the LAN working power to the system.
The pressure is normal. Therefore, the first point of analysis is to determine whether the LANRSET
body reset signal is OK. Then judge to be quietThe problem point of the state start or the problem
point after the dynamic start. The detailed analysis process is judged as shown below:
 (analysis and judgment flow chart)

1. Cause of no output of +3.3V_LAN voltage : Power of LAN Chipset: +3.3V_LAN

1. Is the I/O BOARD OK, and check if the small card is in good contact with CON1 and
CND1 on the large board.
2. PM_LAN_ENABLE signal is abnormal. u3701 solder ball soldering or U3701 single cell
defective. Use multimeterMeasure whether the U3701 is shorted, no output or Trace open
is not input to the Q3502)
3 Pin3, Pin3 Input power supply of Q3501 is abnormal (Trace open is not input to Q3501)
4 Q3501 Poor monomer or pin foot "high tilt", "empty welding" and other processes
5 R3517, R3501 The unit is abnormal. Please measure the impedance value is normal.
2. Causes the abnormality of RSET and RSET signals

1. U3501 solder ball soldering or U3501 monomer is bad.

2. The R3525 is abnormal. Please measure the impedance value.
3. Causes the abnormality of the 25 Mhz spectrum of X3502 PIN1 and PIN2 :

1 25Mhz spectrum anomaly X3502 solder ball soldering or X3502 monomer is bad.
2 C3521.C3522 The monomer is abnormal. Please measure the capacitance value.
3 U3501 solder ball soldering or U3501 single cell defect

4. Causes U3501 PIN17.PIN18.Clk_Pcie_Lan/Clk_Pcie_Lan# spectrum anomaly :

1. Is the I/O BOARD OK, and check if the small card is in good contact with CON1 and CND1
n the large board.
2. If abnormal Check RN2304 PIN3, PIN4 U2001 solder ball soldering or U2001 monomer is bad.
3. If there is no abnormality Check RN2304 PIN1, PIN2 TO Check U3501 PIN17, PIN18 is OPEN.
4. If OPEN U3501 solder ball soldering or U3501 monomer is not good.

5. Cause two sets of PCIE_IRXP3_LTXP3, PCIE_IRXN3_LTXN3;PCIE_ITXP3_LRXP3, PCIE_ITXN3_LRXN3 .

Reasons for signal anomalies :

 1 C3502.C3524 Air welding or poor monomer.
2 C2303.C2309 Air welding or poor monomer.
3 U3501 or U2001 bad body
4 Confirm whether the line of U3501 (PIN20 PIN21) to U2001 (AU30.AT30) C3502.C3524 is OK.
5 Confirm whether the line of U3501 (PIN15 PIN16) to U2001 (AU32.AV32) C2303.C2309 is OK

6. Use the oscilloscope to measure NB_LOM_TRD0, NB_LOM_TRD0#; NB_LOM_TRD1,

NB_LOM_TRD1#NB_LOM_TRD2, NB_LOM_TRD2#; NB_LOM_TRD3, NB_LOM_TRD3# .

Interface oscillation frequency . Abnormal Check LAN XF6101 inductance .

1 Confirm that the line of U3501 (PIN2 PIN3) to XF6101 (PIN12 PIN11) is OK.
2 Confirm that the line of U3501 (PIN5 PIN6) to XF6101 (PIN9 PIN8) is OK.
 3 Confirm that the line of U3501 (PIN8 PIN9) to XF6101 (PIN5 PIN6) is OK.
4 Confirm that the line of U3501 (PIN11 PIN12) to XF6101 (PIN3 PIN2) is OK.

7. Finally, there are abnormal reasons for the LAN part. There are also some abnormal reasons:
1 XF6101 solder ball soldering or XF6101 monomer is not good.
2 RJ45 interface body is bad, can not have good contact with the network cable.
3 R6102.R6104, R6103, R6101, EC6101 The unit is abnormal.
Please measure the resistance value is normal.

THE END