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CSNB123 - tutorial

Computer Organization (Universiti Tenaga Nasional)

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CSNB123 / CSNB2123
Computer Organization

Semester 1, 2020/2021

Tutorial 3

Instructions

Part A
Briefly Answer the following questions

1-explain principle of locality

Locality is a common behavior of all computational processes over prolonged time intervals,
they appear to refer repeatedly to subsets of their resources. System designers have exploited
this behavior in various ways to maximize performance, including caching, related object
clustering, search engines, database organization, spam filters, etc.

2-Differentiate between spatial and temporal locality.

-Spatial locality refers to the tendency of execution to involve a number of memory

locations that are clustered.

-Temporal locality It refers to the tendency for a processor to access recently used
memory locations.

3-For Cache mapping , what are the difference among direct mapping ,associative
mapping , and set-associative mapping in term of the fields of the main memory
address ?

For a direct-mapped cache , a main memory address is viewed as consisting of three fields.
List and define the three fields. The fields would be i, j, and m. I is the cache line number, j is
the main memory block number, and m is the number of lines in the cache .

For an associative cache , a main memory address is viewed as consisting of two fields.
List and define the two fields. Tag and Word fields. Tag field uniquely identifies a block of
main memory. The word is what is to be placed in the block of memory.

For a set-associative cache , a main memory address is viewed as consisting of three fields.
List and define the two fields. The fields are Tag, Set and Word The tag identifies a block of
main memory, the set specifies one of the 2^s blocks of main memory The word is what is to
be placed in the main memory.

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4- what is the difference between DRAM and SRAM in terms of characteristics such
as speed , size , cost ?

Speed , SRAM is faster

Size , SARM takes more space DRAM is denser
Cost, SRAM is more expensive than DRAM

5-Explain why one type of RAM is considered to be analog and the other digital .

-DRAM: analog device because it stores charge and uses a threshold to determine the binary
value

- SRAM: digital because it uses flip-flop logic gates

6-what is an odd parity bit ?

Basic method for detecting if an odd number of bits has been switched by accident.

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Part B

1-two-way set-associative cache has lines of 16 bytes and a total size of 8 Kbytes . The 64-
Mbyte main memory is byte addressable .Show the format of main memory addresses .

Set1 Block1 Block2

Set2 Block3 Block4
Set3 Block5 Block6
Set4 Block7 Block8
Set5 Block9 Block10
Set6 Block11 Block12
Set7 Block13 Block14
Set8 Block15 Block16

Total block in the cache =8kbytes /16 bytes=23 ×210 /24=29=512

Number of set = number of block in cache /2

Number of set =512/2

Number of set in cache =256

Number of set in cache =28

Number of set = 8

Size block =16=24

Size of memory = 26×220=226

Tag = size of memory – set-size of block

Tag =26-8-4

Tag=14

Tag Set Size of block

14 8 4

2-Consider a 32-bit microprocessor that has an on-chip 16- KByte four-way set-associative
cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram
of this cache showing its organization and how the different address fields are used to
determine a cache hit/miss.
Where in the cache is the word from memory location

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ABCDE8F8 mapped?

Size of address CPU=32bit

Total block in cache=16k/16
Total block in cache=24x210/24=210=1024
Number of set in cache=total block/4
Number of set in cache=1024/4
Number of set in cache=256=28
Size of block =16=24
Tag = size of address CPU-set -size of block
Tag =32-8-4=20
Tag Set Size of block
20 8 4

Where in the cache is the word from memory location

ABCDE8F8 mapped?

Tag 20 Set 8 Size of block 4

1010 1011 1100 1110 1000 1111 1000

So we select set 143 because the input to decoder is 10001111 and the output from decoder is
set 143.

Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 - 3
.bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine
(a) How many total bytes of memory can be stored in the cache? 28=255byte
(b) How is a 16-bit memory address divided into tag, line number, and byte number?
Tag Line Size
8 5 3

(b) Into what line would bytes with each of the following addresses be stored?

(i) 0001 0001 0001 1011 (ii)1100 0011 0011 0100 (iii) 1101 0000 0001 1101
(iv) 1010 1010 1010 1010

0001 0001 0001 1011 Line3

1100 0011 0001 0100 Line6
1101 0000 0001 1101 Line 3
1010 1010 1010 1010 Line 21

4. Design a 16-bit memory of total capacity 8192 bits using SRAM chips of size 64 *
1 bit. Give the array configuration of the chips on the memory
board showing all required input and output signals for assigning this memory to the
lowest address space. The design should allow for both byte
and 16-bit word accesses.

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5. Assume an 8-bit data word stored in memory is 11000010. Using the Hamming
algorithm, determine what check bits would be stored in memory with the data word.
Show how you got your answer.

Data bit with value 1 are in bit positions 12,11,5,4,2,and 1

poistio 12 11 10 9 8 7 6 5 4 3 2 1
n
Bits D8 D7 D6 D5 C8 D4 D3 D2 C4 D1 C2 C1
Block 1 1 0 0 0 0 1 0
Cods 110 101 010
0 1 1
The check bits are in bit numbers 8,4,2and1
Check bit 8 calculated by values in bit numbers 12,11,10and 9
Check bit 4calculated by values in bit numbers 12,7,6and 5
Check bit 2calculated by values in bit numbers 11,10,7and 3
Check bit 1calculated by values in bit numbers 11,9,7,5and 3
The check bits are 0010

6. For the 8-bit word 00111001, the parity bits of hamming code stored and sent
together is 0111. If the parity bits are then calculated to be 1101.
Fin the error and the location of the error.

7. How many check bits are needed if the Hamming error correction code is used to
detect single bit errors in a 1024-bit data word?

Need k check bits such that 2k-1 =1024 +k

The minimum value of k that satisfies this condition is 11.

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