Scribd Logo
Upload

Welcome to Scribd!

  • 31 views

    DCD Task - 5

    Uploaded by

    Cathrine Cruz
    This document contains Verilog code for several digital circuits including a zero detector, MOD 8 counter using T flip-flops, MOD 6 counter using JK flip-flops, test benches, and descriptions of D latches, D flip-flops, JK flip-flops, and T flip-flops. It also discusses behavioral modeling in Verilog and obtaining the sum function of a full adder using a 4:1 multiplexer.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    DCD Task - 5

    Uploaded by

    Cathrine Cruz
    31 views29 pages
    This document contains Verilog code for several digital circuits including a zero detector, MOD 8 counter using T flip-flops, MOD 6 counter using JK flip-flops, test benches, and descriptions of D latches, D flip-flops, JK flip-flops, and T flip-flops. It also discusses behavioral modeling in Verilog and obtaining the sum function of a full adder using a 4:1 multiplexer.

    Original Description:

    Original Title

    DCD TASK - 5.docx

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document contains Verilog code for several digital circuits including a zero detector, MOD 8 counter using T flip-flops, MOD 6 counter using JK flip-flops, test benches, and descriptions of D latches, D flip-flops, JK flip-flops, and T flip-flops. It also discusses behavioral modeling in Verilog and obtaining the sum function of a full adder using a 4:1 multiplexer.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    31 views29 pages

    DCD Task - 5

    Uploaded by

    Cathrine Cruz
    This document contains Verilog code for several digital circuits including a zero detector, MOD 8 counter using T flip-flops, MOD 6 counter using JK flip-flops, test benches, and descriptions of D latches, D flip-flops, JK flip-flops, and T flip-flops. It also discusses behavioral modeling in Verilog and obtaining the sum function of a full adder using a 4:1 multiplexer.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 29

    ECE2026 – DIGITAL CIRCUIT DESIGN

    TASK – 5

    CATHERINE CRUZ M – 19BML0048

    1) Using MODELSIM, carry out the simulation of the Zero detector


    discussed in laboratory class, with the help of a Verilog HDL code.

    CODE:
    module Mealy_zero_detector_XYZ(y_out,x_in,clk,rst);
    input x_in, clk, rst;
    output y_out;
    reg [1:0] state,next_state;
    reg y_out;
    parameter S0=2'b00, S1=2'b01, S2=2'b10, S3=2'b11;
    always @ (posedge clk, negedge rst)
    if(rst==0)state<=S0;
    else state <= next_state;
    always@(state,x_in)
    case(state)
    S0: if (x_in) next_state=S1; else next_state=S0;
    S1: if (x_in) next_state=S3; else next_state=S0;
    S2: if (~x_in) next_state=S0; else next_state=S2;
    S3: if (x_in) next_state=S2; else next_state=S0;
    endcase
    always @(state,x_in)
    case(state)
    S0: y_out =0;
    S1,S2,S3: y_out = ~x_in;
    endcase
    endmodule

    OUTPUT:
    2.
    A) Using MODELSIM, carry out the simulation of a MOD 8 counter using T
    flipflops.
    B) Accomplish 2A) using case statements

    CODE:
    module mod8_counter

    # (parameter N = 8,

    parameter WIDTH = 4)

    ( input clk,

    input rstn,

    output reg[WIDTH-1:0] out);


    always @ (posedge clk) begin

    if (!rstn) begin

    out <= 0;

    end else begin

    if (out == N-1)

    out <= 0;

    else

    out<=out+1;

    end

    end

    endmodule

    3) Design a MOD 6 counter using JK flipflops. Write a Verilog HDL


    code for accomplishing the same.
    module jkff (clock, j, k, q, qbar);

    input clock, j, k;
    output q, qbar;

    reg d = 1'b0;

    always @(posedge clock)


    begin
       if (j == 1'b0 && k == 1'b0)
           d <= d;
       else
           if (j == 1'b0 && k == 1'b1)
               d <= 1'b0;
           else
               if (j == 1'b1 && k == 1'b0)  
                   d <= 1'b1;
               else
                   if (j == 1'b1 && k == 1'b1)
                       d <= ~d;
    end

    assign q = d;
    assign qbar = ~d;

    endmodule

    module mod6_counter (clock, q2, q1, q0);

    input clock;
    output q2, q1, q0;

    wire [2:0] d, dbar;


    wire j2, k2, j1, k1, j0, k0;

    assign j2 = d[1] && d[0];


    assign k2 = d[0];
    assign j1 = ~d[2] && d[0];
    assign k1 = d[0];
    assign j0 = 1'b1;
    assign k0 = 1'b1;

    jkff uut0 (clock, j0, k0, d[0], dbar[0]);


    jkff uut1 (clock, j1, k1, d[1], dbar[1]);
    jkff uut2 (clock, j2, k2, d[2], dbar[2]);
    assign q2 = d[2];
    assign q1 = d[1];
    assign q0 = d[0];

    endmodule

    module jkff (clock, j, k, q, qbar);

    input clock, j, k;
    output q, qbar;

    reg d = 1'b0;

    always @(posedge clock)


    begin
       if (j == 1'b0 && k == 1'b0)
           d <= d;
       else
           if (j == 1'b0 && k == 1'b1)
               d <= 1'b0;
           else
               if (j == 1'b1 && k == 1'b0)  
                   d <= 1'b1;
               else
                   if (j == 1'b1 && k == 1'b1)
                       d <= ~d;
    end

    assign q = d;
    assign qbar = ~d;

    endmodule

    module mod6_counter (clock, q2, q1, q0);

    input clock;
    output q2, q1, q0;

    wire [2:0] d, dbar;


    wire j2, k2, j1, k1, j0, k0;

    assign j2 = d[1] && d[0];


    assign k2 = d[0];
    assign j1 = ~d[2] && d[0];
    assign k1 = d[0];
    assign j0 = 1'b1;
    assign k0 = 1'b1;

    jkff uut0 (clock, j0, k0, d[0], dbar[0]);


    jkff uut1 (clock, j1, k1, d[1], dbar[1]);
    jkff uut2 (clock, j2, k2, d[2], dbar[2]);

    assign q2 = d[2];
    assign q1 = d[1];
    assign q0 = d[0];

    endmodule

    TASK-4
    1. Write a test bench for verifying the functionality of any one
    combinational circuit in task III. Write few lines about the
    need for a test bench.
    2. Write a Verilog HDL code for a ‘D’ latch and ‘D’ flipflop.
    Verify its working using its function table. Mention its
    characteristics equation and excitation table. Mention few of
    its applications.
    ‘D’ LATCH:
    ‘D’ FLIPFLOP:
    3. Write a Verilog HDL code for a ‘JK’ and ‘T’ flipflop.
    Verify its working using its function table. Mention its
    characteristics equation and excitation table. Mention few of
    its applications.
    ‘JK’ FLIPFLOP:
    ‘T’ FLIPFLOP;
    4. Write a note on Behavioural modelling, the role
    of assignment operator and its proper usage.
    Illustrate with examples.
    CONTINUATI
    ON OF TASK – 3

    g) Obtain the ‘SUM’ function of the Full Adder using a 4:1


    Mux in d).

    You might also like