A Fully Isolated Amplifier Based On Charge-Balanced SAR Converters

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO.
6, JUNE 2018 1795
A Fully Isolated Amplifier Based on

Charge-Balanced SAR Converters
Shaoyu Ma , Member, IEEE, Jinghao Feng, Tianting Zhao, and Baoxing Chen
Abstract— A galvanic isolated amplifier based on SAR convert- by switching loads or faults, and surge withstand voltage
ers architecture is presented which realizes chip level isolation represents tolerance to a particular transient profile induced by
in both the power and signal domains. The compact IC package direct or indirect lightning strikes. At the same time, the iso-
contains an integrated isolated power converter which includes
on-chip transformer, oscillator and rectifier, digital isolators lation components such as the isolated amplifier must with-
based on on-chip transformers, a front-end programmable gain stand a continuous working voltage throughout its operating
amplifier, a SAR ADC, a complementary charge redistribution lifetime. Reliability over the required lifetime is very critical
DAC, and post filters to reconstruct and smooth the linear for the power conversion applications. Typically, the isolated
signal. The symmetric implementation of the SAR ADC and devices include an electrical isolation barrier and circuitry for
DAC realizes the charge balance between the input side and
the output side, where an inherent linear transfer function is transmitting and receiving the signal across this barrier.
achieved. The sampling clock comes from an on-chip oscillator There are multiple needs for current and voltage measure-
of poor jitter performance which limits the SNR performance of ments in a PV inverter system, as shown in Fig. 1. For
the ADC. With the correlated clock for the DAC reconstruction, example, the DC current and voltage are measured at the
the close-in phase noise from the clock generator is attenuated solar panel for Maximum Power Point Tracking (MPPT),
so that the SNR performance of the overall isolated amplifier
is not sensitive to the jitter from the sampling clock. This and the AC output currents of the inverter are fed into the
fully integrated solution displaces the traditional bulky hall-effect controller for grid integration. In particular, for AC output
sensors, and enables precise and fast isolated voltage or current current measurement, if the transformer is omitted to save
sensing applications such as photovoltaic inverters. The isolated cost, the inverter must also measure any dc component of
amplifier, with the ability to measure both large currents and the output current. The presence and magnitude of this dc
small dc injection currents in a single solution, can contribute
compactly and efficiently to smart grid integration circuitry. injection is a critical matter, as too much dc current injected
The system-in-package achieves less than 1 mV total offset and onto the grid may saturate any transformers in its path [2].
71.9 dBFS SNR in a bandwidth of 200 kHz. It achieves an Typically, the PV inverter needs to measure DC current on
isolation working voltage rating of 600 Vrms and 5 kVrms the order of tens to hundreds of milliamperes within up to
over 1 min duration. 50 A AC current that is injected to the utility grid of 110 V
Index Terms— Charge redistribution, current/voltage sensing, or 240V directly. This gives very demanding offset voltage
galvanic isolation, isolated amplifier, isolated power converter, requirement for the current sensing components. The sensors
on-chip transformer, PV inverters, SAR ADC.
must not only accurately measure both AC and DC currents,
I. I NTRODUCTION they must have high dynamic performance: fast response times
are needed to react quickly to any change in the grid, shutting
P OWER conversion applications such as PV inverters,
power system control and protection are required to meet
various stringent insulation and safety standards [1]. The
off or disconnecting the system in case of a short circuit (that
is, ground fault) or loss of grid connection (anti-islanding).
safety standards define a variety of parameters against different The high output bandwidth is also needed to measure high-
fault conditions such as 1-minute isolation withstand voltage frequency AC currents and harmonics at different points in the
which indicates tolerance to short duration overvoltage caused system. A 200 kHz measurement bandwidth allows the system
to react to these events fast enough to take necessary action
Manuscript received July 14, 2017; revised August 31, 2017 and before a fault causes a system failure.
October 3, 2017; accepted October 24, 2017. Date of publication Current transformers and Rogowski coils can only mea-
November 10, 2017; date of current version May 8, 2018. This paper was
recommended by Associate Editor Ahmed M. A. Ali. (Corresponding author: sure AC current. Hall-effect sensors are widely used in the
Shaoyu Ma.) applications where DC current needs to be measured [3], [4].
S. Ma is with Analog Devices Inc., Shanghai 201203, China (e-mail: Shunt resistor based current sensors are attractive in low
[email protected]).
J. Feng was with Analog Devices, Inc., Beijing 100192, China. He is power applications (less than 50 kW) because the shunt
now with RadRock Tech, Shenzhen 518000, China (e-mail: jinghao.feng@ resistors are physically small, can pass both AC and DC
outlook.com). signals, and are very cheap to manufacture. The shunt-based
T. Zhao is with Analog Devices Inc., Beijing 100192, China (e-mail:
[email protected]). solutions also provide high accuracy and high bandwidth
B. Chen is with Analog Devices, Inc., Wilmington, MA 01887 USA (e-mail: potentially. If a shunt resistor is used, the measurement IC
[email protected]). is directly connected to the high-voltage side, and must
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. therefore be electrically isolated from the low-voltage side.
Digital Object Identifier 10.1109/TCSI.2017.2767678 This is typically achieved using external isolation components
1549-8328 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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1796 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO. 6, JUNE 2018
Fig. 1. PV inverter system.
(optocouplers and transformers), which bear the burden of

meeting the insulation and safety standards. Meanwhile,
another dedicated power supply is required to power the
measurement IC which is typically realized using a traditional
transformer circuit. These external isolation elements not only
complicate the system design but also increase both the PCB
area and the system cost.
This paper presents a fully isolated, single-package mea-
surement IC which can amplify the voltage across the shunt
resistor on the high-voltage line and transfer data across the
internal isolation barriers to the low-voltage side. An isolated
power converter is also integrated into the package which com-
prises a high-voltage oscillator, an on-chip power transformer Fig. 2. Isolated amplifier SIP.
and a rectifier. Because it includes all of the isolation capability
within the package, no external components are needed. Very serialized digital data provide data word synchronization and
good offset and bandwidth are achieved for the emerging PV the data is protected by the following 6-bit Error Correction
inverter applications. Codes (ECC). The encoded and calibrated ADC output is
The paper is organized as follows. Section II describes the transmitted across the isolation barrier with inductive coupling
architecture of the isolated amplifier and the implemented of On-Off Keying (OOK) modulated carriers. The galvanic
building blocks. Section III addresses the isolated power con- isolation and unmatched common-mode transient immunity
verter and implementation aspects, and Section IV presented are achieved with the thick back-end polyimide insulation
measurement results. The paper is concluded in Section V. layer between the on-chip coils. The output section of the
isolated amplifier includes a charge redistribution DAC to
reconstruct the linear voltage and the following sample-and-
II. A RCHITECTURE OF THE I SOLATED A MPLIFIER hold (S&H) stage together with high order continuous-time
A. Overview low-pass filter serves to remove the undesired ripple com-
The main architectural decisions for this isolated amplifier ponent inherent in the conversion. Sample clock and system
are: isolated power converter, programmable gain amplifica- clock are generated by an on-chip oscillator and a phase locked
tion, signal digitization, data processing with offset and gain loop, respectively. There are two internal references for ADC
calibration, On-Off Keying modulation of a RF carrier across and DAC separately, whose matching defines the overall gain
a custom inductive isolation barrier, and analog reconstruction. accuracy.
As shown in the block diagram in Fig. 2, the system-in- DC injection to AC mains is a critical issue in transformer-
package (SIP) solution integrates an isolated power con- less grid-connected PV inverters, which requires minimizing
verter (comprising two dice – a high-voltage oscillator with the offset and its drift of the current measurement device.
on-chip power transformer, and a rectifier), and two dice for Therefore, various offset compensation techniques are applied
measured signal processing. to the circuits of the isolated amplifier, like auto zero and
A switched-capacitor front-end amplifier is used to sense digital calibration. The measured total offset is less 1 mV and
the voltage and provides programmable gains for different offset drift is less than 1.5 μV/°C.
input ranges. Then a low-power SAR ADC is adapted to
quantize analog signal to digital codes and the inherent B. Front-End Amplifier
data conditioning block in the ADC implements the gain The front-end amplifier provides the overall gain of
and offset calibration. 4-bit Manchester codes preceding the the isolated amplifier and also determines the offset and
MA et al.: FULLY ISOLATED AMPLIFIER BASED ON CHARGE-BALANCED SAR CONVERTERS 1797
ADC, so the Nyquist rate ADCs is preferred over delta-sigma

modulators. Thus, for this work, a charge-redistribution SAR
ADC [8] is chosen for a balance of bandwidth and power con-
sumption. As shown in Fig. 4, the ADC is composed of input
sampling circuits, charge-redistribution DAC, comparator, and
successive approximation (SA) control logic.
The analog reconstruction appears to be redundant as a
digitized version of the input signal already exists, but the most
simple and common interfaces to power conversion systems
mixed-signal micro-controller is still an analog signal. A dig-
ital interface is possible but would require a compatible inter-
face within the receiving micro-controller. The disadvantage of
Fig. 3. Correlated double sampling SC amplifier.
the analog interface consists in extra impairments (offset, noise
and distortion) introduced in the analog reconstruction circuits.
noise floor. Continuous time architectures are preferred for For delta-sigma modulator based solution, the isolated digital
high input signal bandwidth and they avoid the folding down bit stream is processed by a high-order analog filter which
of sampled noise. In the target power conversion application a removes the shaped quantization noise [9]. For this SAR con-
variety of interference sources can create noise and therefore, verter based solution, a complementary charge-redistribution
a switch-capacitor solution is more attractive. Also it is more DAC is implemented for analog reconstruction. The simplified
convenient to implement offset cancellation such as correlated circuits are shown in Fig. 4. The so called charge redistribution
double sampling (CDS) technique with switch-capacitor (SC) scheme is adapted which utilizes optimally the properties of
topologies [5]. CMOS technology: good switches and capacitors.
The SC front-end amplifier is shown in Fig. 3. During During the phase φ1 , the input voltage is sampled and stored
the φ1 = 1 period, the input capacitor C1 is charged to in the capacitor array Ci (where i = 0, 1 . . . 11) within the
Vin - Vos , and C2 to Vos . In this circuit, capacitors C1 and C2 SAR ADC. In the period of φ2 , the SAR bit trials are set
are always connected to the input of the operational transcon- to high one by one and the comparator determine the final
ductance amplifier (OTA), so if the input-referred offset volt- bits from MSB to LSB based on successive approximation
age is constant, and then when switches driven by φ2 close, algorithm, as shown in Fig. 5. The input voltage at the
the relationship between Vin and Vout is independent of Vos . comparator input approximates zero eventually, which gives:

Because of the capacitor C3 and its two associated switches −Vin Cin + Vre f Bi C i ≈ 0 (1)
which implement an elementary S&H branch, the output of the i
amplifier does not need to reset to Vos during φ1 . The circuit where Vre f = Vre f + − Vre f − and assume quantitation error
also reduces the effect of the OTA gain and hence allows more is small. So the input charge on Cin is represented by the
relaxed OTA specifications for low-frequency inputs. The input digital bits Bi associated with weighted capacitors Ci . The
capacitors are scalable to achieve the programmable gain of 1, digital bits are transmitted across the isolation barrier and are
2, 4 and 8 to accommodate different input ranges and meet applied to the same weighted capacitor array Ci receiver side.
the specified thermal noise (mainly KT/C noise) requirement. The same amount of charge to the input capacitor array Ci is
asserted in Ci at the end of φ2 . A DAC buffer is inserted to
C. SAR ADC and Complementary DAC drive the following sample and hold circuits. The charge on the
capacitor array Ci is transferred to the output capacitors C D AC .
Various techniques can be used to achieve a linear transfer
Particularly, the capacitor array Ci and C D AC are discharged
function across the isolation barrier, such as analog optocou-
initially, as shown in Fig. 5, and during the period φ2 , the
plers [6], but the accuracy of the transfer gain is limited
digital bits develop the charge on the capacitors C D AC ,
and very sensitive to the common mode transient across

i = V D AC C D AC
the isolation barrier. Transferring digital signals across the Vre f B i C (2)
i
isolation barrier is much more robust, but needs a modula-
tor or converter. Single-bit delta-sigma modulators are widely So that the charge balance is achieved assuming identical
used because of inherent robustness achieved by transferring reference voltages. Because the voltage can be represented by
only one bit per modulator at a time across the isolation the capacitor ratio for both input side and output side, it is
barrier [7]. However, delta-sigma modulator would require expected that the reconstructed analog output is proportional
a high oversampling ratio (OSR) to reduce the quantization to the ratio of the capacitor ratio:
noise to the required level, which limits the input bandwidth

Vre f i Bi Ci /C D AC
and implies higher power consumption. As will be seen in the V D AC ≈ Vin (3)
section of isolated power converter, the transmission of power Vre f i Bi Ci /Cin
across the isolation barrier needs to be coordinated with the As shown in Fig. 5, the comparator in SAR ADC is
ADC sampling instants to avoid disruptive influence of the approximating to zero step by step while the DAC output
power converter on ADC performance. The power converter is reconstructing the analog output proportional to the input
switching frequency limits the maximum sampling rate of the voltage correspondingly. The DAC output is approximating
Fig. 4. Simplified circuit for the SAR ADC and the complementary DAC.
Fig. 5. Operation of SAR ADC and the complementary DAC.
to the desired voltage from MSBs to LSBs so that the 5 bits for LSB side. The most significant 5 bits in MSB
settling requirement for the MSBs is reduced dramatically. segment and the most significant 3 bits in LSB segment use
For example, the MSB results in the largest swing and the thermometer codes to enhance linearity. The split reference
settling time for MSB is as large as 14 trial cycles. This allows sample technique [11] is used in both capacitor arrays without
for a low-power DAC buffer design. It should be noted that having to generate the input common mode voltages for the
the timing in Fig. 5 is greatly simplified to demonstrate the comparator and output buffer. An auto-zero comparator is used
principle how the linear transfer function is achieved based on to compensate for offset errors. The gain stage is connected
charge balance. In practical design, the output bits from the in the unit gain configuration and used to pre-charge the top
ADC is processed before feeding to the DAC at the receiver plate of the capacitor array to the offset voltage during the
side. sampling phase. The DAC output buffer at the receiver side
This symmetric implementation realizes the charge balance is also designed with auto-zero scheme. The similar approach
between the input side and output side so that linear transfer with the front-end amplifier is implemented to compensate the
function is built, which is stable over a wide temperature range. offset voltage and to reduce the effect of the OTA gain.
In practical design, a 12-bit SAR ADC running at 1 MS/s is
implemented with 1 redundant bit for error correction. The
additional capacitors provide extra weights within the array D. Sampling Clock for the ADC and DAC
and allow the successive approximation search to recover from As for a fully isolated amplifier, the sampling clocks for the
incorrect decisions [10]. The charge-redistribution DACs are ADC and DAC need to be generated on chip. It is well known
implemented with two segments, 7 bits for MSB side and that the phase noise from the sampling clock of the ADC
Fig. 8. Data Processing and transmission across transformer.
transfer function,
⎛ ⎞
ωin +∞
S N R = −20log 10 ⎝ 4si n 2 (π f t ) Sϕ ( f )d f ⎠ (5)
ωclk −∞
where t is the clock delay time from input side to the output
side. As shown in Fig. 6, the SNR is not sensitive to the
phase noise from the sampling clock, which allows for a low
power on-chip oscillator to generate the sampling clock of
the ADC. It is evidential from the silicon measurement that
the spectrum of the ADC output contains lots of close-in
noise which degrade the SNR of the ADC. As the correlated
Fig. 6. ADC SNR degradation due to clock phase noise. (a) The spectrum sampling clock is used for DAC reconstruction, the close-in
of the ADC input tone and the sampling clock. (b) The spectrum of the ADC noise at the ADC output is attenuated significantly and the
output. (c) The spectrum of the DAC output with correlated sampling.
SNR of the DAC output is recovered.
E. Data Processing and Communication Across Isolation

Digital communication across the isolation barrier presents
several challenges. The digital codes from the ADC are
processed to 1-bit data which can be transmitted across the
barrier with one isolated channel. Different from the inherent
1-bit stream from delta-sigma modulator, the output from
Fig. 7. Correlated Sampling Clock for the ADC and DAC. SAR ADC is binary weighted which complicates the data
processing.
The 13-bits ADC output is encoded in a serial frame
results in additional noise close to the input frequency [12], of 23 bits, as shown in Fig. 8. The data transmission uses
as shown in Fig. 6. This can be a limiting factor to SNR of widespread Non-Return-to-Zero (NRZ) format to minimize the
the ADC: bandwidth requirement and the 4 start bits use Manchester
⎛ ⎞ coding scheme which can be identified efficiently at the
ω +∞
receiver. In the target power conversion application, stability
S N R = −20log10 ⎝ Sϕ ( f )d f ⎠
in
(4)
ωclk −∞ of the system is a major concern – unexpected interfer-
ence or switching behavior may cause bit errors. To ensure
where ωclk and Sϕ( f ) are the frequency and the phase correct data transmission, 6-bits Error Correction Code (ECC)
noise of the sampling clock, respectively. Oversampling to are calculated based on 13-bits data. This allows for sin-
increase ωclk is the conventional mitigation, but suffers from gle error correction and simultaneously, double error detec-
higher power consumption. And oversampling can only reduce tion (SEC-DEC), which reduce the data error rate dramatically.
the white noise floor. For a free-run oscillator, the close- Without a galvanic connection, modulation and demodula-
in phase noise cannot be rejected by the loop filter as in tion schemes are typically used to send digital signals across
a phase-locked-loop. Correlated double sampling is widely the barrier when using capacitive coupling [13] or transformer
used to reject the low-frequency voltage noise. The same based inductive coupling. There are some limitations trans-
philosophy is applied here that a correlated clock is applied to ferring isolated signals using capacitors. Since a capacitor is
the reconstruction DAC, so that the close-in noise of the DAC a two-terminal device, both signal and common-mode noise
output is first-order rejected. are transferred through the capacitor simultaneously, leading
As shown in Fig. 7, the sampling clock generated at the to limited common-mode transient immunity. A transformer,
ADC side is also sent to the receiver side with a separated being a four-terminal device, couples the signals differentially
isolation channel so that the ADC and DAC sampling clocks and provides an inherently higher common mode noise rejec-
are correlated. When looking at the DAC output, the close-in tion and is better suited as an isolation coupling element for
phase noise from the oscillator is attenuated with a high-pass power conversion applications. However, driving transformers
Fig. 9. Block diagram of the digital isolator.
Fig. 10. Cross section of micro-transformer.

Fig. 11. Sample-and-Hold Block with Ping-Pong Operation. (a) The Circuit.
(b) The switch timing.
can also be problematic due to the low impedance levels
involved.
Different digital pulse communication schemes across discharge, these devices also exhibit good aging behavior and
isolation barriers have been previously developed based on work well under continuous AC voltage up to 600 Vrms.
inductive coupling. For example, one of the approaches is
to transmit the edge information and the output can be con-
structed accordingly through a bi-stable latch at the secondary F. Analog Reconstruction
side [14]. The leading edge is encoded as 2 consecutive For a delta-sigma modulator, a single-bit DAC contains
short pulses and a single short pulse is used to indicate a lot of quantization noise, and a high-order switched-capacitor
falling edge. In this work, On-Off keying (OOK) signaling is filter is needed to reduce the step size of DAC waveforms
used to improve propagation delay, noise immunity and EMI which is power consuming. Once the step size of the waveform
performance [15]. The input digital signal is used to modulate is small enough, such that the slew rate requirement for the
a high frequency signal, particularly, a RF signal is transmitted following continuous time (CT) processing is acceptably low,
while the input is high while the RF signal is off while input it can then be filtered by a CT filter. With the novel SAR
is low. As shown in Fig. 9, a LC tank consists of two pairs ADC and complementary DAC architecture, the analog output
of cross-coupled MOSFETs and the primary inductor of the that is proportional to input voltage is reconstructed without
on-chip transformer. On the receiver side, a squarer circuit additional noise. The DAC output is approximating the desired
rectifies the RF signal and a hysteresis comparator is used to voltage from MSB to LSB which allows for an alleviated
decode the logic signal. Because the oscillator frequency of the settling requirement for the DAC buffer. For example, there are
LC tank is as high as 700 MHz, the propagation delay of this more than 13 trial cycles for MSB settling, as shown in Fig. 5.
transformer data link with OOK signaling is less than 10 ns. To eliminate the non-linear settling process, a sample-and-
The on-chip transformers are implemented as stacked spirals hold circuit follows the DAC and then is filtered by a CT filter
and their cross-section is shown in Fig. 10. The thick plated to remove the sampling frequency components. Direct-charge-
Au is used for top spirals and Al is used for bottom spirals. transfer (DCT) topology is used to eliminate OTA-induced
Polyimide is chosen as the material for insulating layers transients representing nonlinear distortion [16], and the circuit
because it provides large breakdown strength, high thermal is shown in Fig. 11. The circuit is fully differential, and single-
and mechanical stability, excellent chemical resistance, good ended circuit is shown for simplicity. The DAC output is sam-
ESD performance and low relative permittivity. With a total pled and stored in C1 at the end of φ1 . As φ2 goes high, C1 is
thickness of 30 μm between coils, the polyimide layers enable connected a feedback branch. Since the right terminal of the
the devices to be able to survive over 12 kV instantaneous AC capacitor is floating at this time, no external charge enters the
voltage and over 5 kVrms for 1 minute. Because deposited branch during the charge transfer; in particular, the OTA does
polyimide films are free of voids and do not suffer from corona not need to contribute to the high impulsive current flowing.
Fig. 12. Continuous-time low-pass filter.
Thus, this transient is governed by a simple first-order differen- the offset of the low-pass filter stages. This resistive DAC
tial equation, with only the switch on-resistance and the capac- approach allows for simplified and robust calibration for the
itor C1 determining the time constant. This way, a fast and residue offset.
clean transient is obtained, which does not exhibit the slewing
and nonlinear settling behavior which the amplifier would III. I SOLATED P OWER C ONVERTER
normally exhibit. Note that the deglitching capacitor C3 does For the isolated amplifier applications, there is a need to
not play a role in the signal charge redistribution. Its purpose is transfer power from the low voltage system side to the isolated
to prevent glitches at the operational transconductance ampli- high voltage side. The on-chip coreless micro-transformers
fier (OTA) output by providing negative feedback during the is also used for isolated power conversion, which provides
intervals when the nonoverlapping clock phases are both low, an unmatched feature against other isolation technologies.
and the feedback path of the OTA is otherwise open-circuited. There are many challenges in using integrated micro-sized
The output of the Sample-and-hold stage can now be fed to transformers for isolated power conversion. One of the key
the continuous time filter. To minimize the offset correlated challenges is the small inductance. To maximize the quality
double sampling is also applied to the S&H circuits with factor Q, the on-chip transformers need to operate at a very
capacitor C2 and two associated switches. However, To inter- high frequency. However, to switch transformers at very high
face the continuous time filter, S&H block is needed to output frequencies, a standard power converter, such as flyback,
offset-free signal in both auto-zero phases. Traditional auto- will suffer from substantial switching and gate drive loss.
zero operation only can get one offset-free phase and in the A resonant transformer based oscillator is an energy-efficient
other phase the output will contain the offset. The Ping-Pong way to transfer power and minimize these losses at high
operation is implemented in S&H stage by using an auxiliary frequencies [17], [18].
amplifier which has a complementary auto-zero operation The architecture for the fully integrated, isolated DC-DC
with the main amplifier. As shown in Fig.11, main amplifier converter used in this work is shown in Fig. 13. Two high
provides the offset-free output during period φ3 . In the period voltage CMOS switches implemented in a cross-coupled
of φ1 the offset-free output is also sampled to capacitor C1 configuration together with the transformer form sustaining
and drive the output in a complementary period of φ3 . With oscillation. The transformer with its center tap connected to
this time sharing operation, in any auto-zero phase there is VDD is switched resonantly at 180 MHz to achieve efficient
one offset-free output which can drive the continuous time energy transfer. The integrated Schottky diodes are used as
low-pass filter and thus we can get offset-free signal in both rectification diodes, which turn on and recover fast enough
phases. for 180 MHz rectification. The diodes are sized such that they
The following continuous time filter needs to attenuate stay in Schottky region during rectification process to prevent
the mirror frequency components near switching frequency significant reverse recovery loss. To regulate the energy that
and eliminate the residue switching glitches. It is a cascaded is delivered, the LC oscillator is turned on and off via the
fourth-order active-RC circuit, as shown in Fig. 12. For this NMOS switching device M3 below the cross-coupled NMOS
continuous operation, CDS approach cannot be used here and devices M1 and M2 . That switch is controlled through negative
digital calibration is widespread adapted. Traditionally, current feedback based on the measured output voltage of the DC-DC
DACs are implemented to calibrate the offset of the amplifiers. converter. A modified Proportional plus Integral (PI) controller
However, the mismatch between the current DAC and bias together with a PWM comparator is used to generate the
current of the amplifiers causes thermal drift. In this work, two feedback control signal. The PWM signal is encoded, sent
programmable resistors at the input of the first OTA is used across the isolation barrier, and decoded by the isolated data
to compensate the overall offset voltage, which is controlled communication decoder. This approach essentially separates
by polysilicon fuse One Time Programmable (OTP) memory. the energy regulation from energy conversion allowing opti-
The current through the resistive DAC is used compensate mized power transfer and maintaining regulation.
Fig. 13. Isolated DC-DC converter.
Fig. 14. Isolated power converter cooperative timing.
The resonant DC-DC converter results in high-frequency

output ripple, which may degrade the performance of the
ADC. It is evidential that SAR ADC with redundancy is able
to accommodate significant supply noise during conversion
phase [19]. However, if the 180 MHz power transfer signals
are present and being rectified during ADC sampling instants,
then the ADC will convert corrupted signals. Consequently,
the transmission of power across the isolation barrier must be
coordinated with the ADC sampling instants. This is achieved
by synchronizing the PWM control signal of the isolated
power converter with the ADC sampling signal. The LC Fig. 15. Fully isolated amplifier SIP.
oscillator is turned off sufficiently before issuing the ADC
sampling edges to give the sampling process some “quiet time”
as shown in Fig. 14. The isolated power converter will work in
the IC die in a proprietary process. The isolated amplifier SIP
a built-in PWM control mode until the ADC sampling clock is
is powered by a 5V supply while drawing 50.3 mA. The DAC
ready, and the synchronized PWM signal takes over the power
die is powered by the 5V supply while drawing 11.2 mA
converter loop control.
and the ADC die draws 9 mA from the power converter
The power converter circuitry is designed to deliver a
at an efficiency of 23%. The on-chip isolation technology
5V regulated supply to power the ADC die. The ADC die
guarantee insulation specifications of 600 Vrms continuous
draws 9 mA from the power converter and the efficiency at
and 5 kVrms for one minute. The PV inverters need to meet
this output power is 23%.
the demanding DC injection to the AC mains, which requires
minimizing the offset and its drift of the isolated amplifier.
IV. M EASUREMENT R ESULTS The measured maximum input-referred offset is less 1mV and
The fully integrated isolated amplifier is designed for volt- offset drift is less than 1.5 μV/°C. The gain of the isolated
age and current measurement in power conversion applica- amplifier can be compensated at the ADC output, and the
tions. The four dice, which are fabricated in various IC residue gain error is less than 0.5%, which is basically limited
processes, are assembled into a SIP and shown in Fig. 15. by the voltage ratio between the two references. The drift
The ADC and DAC die are fabricated in a standard 0.18 μm from the two independent references also contributes to the
CMOS IC technology, and the isolated power converters chips gain error drift of 50 ppm/°C. The measured non-linearity
in 0.35 μm DMOS and the transformers are fabricated over error for an output voltage of ±2.4 V is shown in Fig. 16,
TABLE I
P ERFORMANCE S UMMARY
Fig. 16. Nonlinearity Error versus Output Voltage at various temperatures.
input voltage of ±300 mV yielding an SNR of 71.9 dB and an

SFDR of 84.6 dB in a bandwidth of 1 MHz is shown in Fig. 17.
The step response in Fig. 18 validates the propagation delay
of the isolated amplifier to a step change in the input voltage.
The measured output response time is 5 μs which allows for
fast actions to any over current conditions. Table I summarizes
the performance and the comparison with the state-of-the-art
current sense devices, a Hall Effect current transducers and
two commercial isolated amplifiers.
Fig. 17. Output spectrum from ±300 mV, 50 Hz input.
V. C ONCLUSION
The world’s first reported isolated amplifier based on
an SAR converter and a complementary DAC is presented
for voltage and current sensing applications with insulation
working voltage up to 600 Vrms. The isolated DC-DC
power converter is integrated to power the high side circuits
and co-packaged into an SIP. The fully integrated isolated
amplifier offers total offset less than 1mV and achieves
71.9 dB SNR and 84.6 dB SFDR in a bandwidth of 200 kHz.
ACKNOWLEDGMENT
The authors would like to thank their colleagues from
isolation team at Analog Devices, Inc., both in Wilmington,
MA, USA, and Beijing and Shanghai, China, for their help
during design, layout, and evaluation.
Fig. 18. Step Response and Propagation Delay time. R EFERENCES

[1] Safety of Power Converters for use in Photovoltaic Power Systems—
yielding a nonlinearity error of less than 200 ppm at various Part 1: General Requirements, Standard IEC 62109-1:2010, 2010.
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in Fig. 16. The spectrum of the isolated amplifier output for an Mar. 2015.
[3] S. Ziegler, R. C. Woodward, H. H.-C. Iu, and L. J. Borle, “Current sens- Jinghao Feng received the B.Sc. degree in micro-
ing techniques: A review,” IEEE Sensors J., vol. 9, no. 4, pp. 354–376, electronics from the University of Electronic Science
Apr. 2009. and Technology of China, Chengdu, in 2010, and
[4] LEM. Current Transducer HLSR-P Series Datasheet. Accessed: the M.Sc. degree in microelectronics from Fudan
Oct. 2017. [Online]. Available: http://www.lem.com University, Shanghai, China, in 2013.
[5] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects He was an Analog Design Engineer with the
of op-amp imperfections: Autozeroing, correlated double sampling, and ISO Team, Analog Devices Inc., Beijing, from
chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, 2013 to 2016 and involved on the isolated amplifier.
Nov. 1996. He is currently a Design Engineer with RadRock
[6] Broadcom. HCNR200 HCNR201 High-Linearity Analog Opto- Tech, Shenzhen, China. His current research
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http://www.broadcom.com techniques.
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binary-scaled error compensation,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, Feb. 2010, pp. 386–387. Tianting Zhao received the B.Sc. degree in elec-
[11] G. Carreau and B. Amazeen, “Method and apparatus for split reference trical engineering in 2001, and the M.Sc. degree
sampling,” U.S. Patent 7 167 121 B2, Jan. 23, 2007. in microelectronics from Nankai University, Tianjin,
[12] B. Brannon, “Sampled systems and the effects of clock phase noise and China, in 2004.
jitter,” Analog Devices, Norwood, MA, USA, Appl. Note AN-756, 2004. He is currently a Senior Staff Design Engineer
[13] Silicon Labs. Si8920 Data Sheet. Accessed: Oct. 2017. [Online]. Avail- and the Design Manager of Beijing ISO product
able: http://www.silabs.com line with Analog Devices Inc., Beijing, China. He is
[14] B. Chen, “Isolation in digital power supplies using micro-transformers,” involving on integrated isolated products. He holds
in Proc. APEC, Feb. 2009, pp. 2039–2042. three issued U.S. patents.
[15] R. Yun, J. Sun, E. Gaalaas, and B. Chen, “A transformer-based digital
isolator with 20kVPK surge capability and > 200kV/μS common mode
transient immunity,” in Proc. IEEE Symp. VLSI Circuits (VLSI-Circuits),
Honolulu, HI, USA, Jun. 2016, pp. 1–2.
[16] R. Schreier and G. C. Temes, Understanding Delta–Sigma Data Con-
verters, vol. 74. Piscataway, NJ, USA: IEEE, 2005.
[17] B. Chen, “Fully integrated isolated DC–DC converter using micro-
transformers,” in Proc. APEC, Feb. 2008, pp. 335–338.
[18] Z. Tan et al., “A fully isolated delta-sigma ADC for shunt based current
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[19] A. Shrivastava, “12-bit non-calibrating noise-immune redundant SAR Baoxing Chen received the B.S. degree in physics
ADC for system-on-a-chip,” in Proc. IEEE Int. Symp. Circuits Syst., from Nanjing University, Nanjing, China, in 1989,
May 2006, pp. 1515–1518. and the M.S. degree in electrical engineering and
the Ph.D. degree in physics from the University of
Michigan, Ann Arbor, MI, USA, in 1997.
Shaoyu Ma received the B.Sc. degree in electrical He joined Analog Devices Inc. in 1997. He pio-
engineering in 2003, and the Ph.D. degree in micro- neered the use of micro-transformers for transmitting
electronics from Zhejiang University, Hangzhou, signal and power through the isolation barrier, which
China, in 2008. has found broad adoption in many isolation appli-
He is currently a Senior Design Engineer of ISO cations with over 1.5 billion channels of isolation
Team with Analog Devices Inc., Shanghai, China. shipped. At ADI, he has been leading iCoupler and
He is involving on integrated isolated products for isoPower technology developments, including circuit architectures and process
power conversion applications. He holds an issued developments. He has authored or co-authored over 30 papers, and he holds
U.S. patent. over 25 U.S. patents. His current research interests include power supply
on-chip and chip-scale energy harvesting.
Dr. Chen is an ADI fellow.

A Fully Isolated Amplifier Based On Charge-Balanced SAR Converters

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A Fully Isolated Amplifier Based On Charge-Balanced SAR Converters

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 65, NO.

6, JUNE 2018 1795

A Fully Isolated Amplifier Based on

Fig. 1. PV inverter system.

(optocouplers and transformers), which bear the burden of

ADC, so the Nyquist rate ADCs is preferred over delta-sigma

Fig. 5. Operation of SAR ADC and the complementary DAC.

Fig. 8. Data Processing and transmission across transformer.

E. Data Processing and Communication Across Isolation

Fig. 9. Block diagram of the digital isolator.

Fig. 10. Cross section of micro-transformer.

Fig. 12. Continuous-time low-pass filter.

Fig. 13. Isolated DC-DC converter.

Fig. 14. Isolated power converter cooperative timing.

The resonant DC-DC converter results in high-frequency

Fig. 16. Nonlinearity Error versus Output Voltage at various temperatures.

input voltage of ±300 mV yielding an SNR of 71.9 dB and an

Fig. 18. Step Response and Propagation Delay time. R EFERENCES

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