ADS7807

AD S
780
7

ADS
780
7

SBAS022D – NOVEMBER 1992 – REVISED NOVEMBER 2006

Low-Power, 16-Bit, Sampling CMOS

ANALOG-to-DIGITAL CONVERTER

FEATURES DESCRIPTION
● 35mW max POWER DISSIPATION The ADS7807 is a low-power, 16-bit, sampling Analog-to-
● 50µW POWER-DOWN MODE Digital (A/D) converter using state-of-the-art CMOS struc-
tures. It contains a complete 16-bit, capacitor-based, Suc-
● 25µs max ACQUISITION AND CONVERSION
cessive Approximation Register (SAR) A/D converter with
● ±1.5LSB max INL sample-and-hold, clock, reference, and microprocessor inter-
● DNL: 16 Bits, No Missing Codes face with parallel and serial output drivers.
● 86dB min SINAD WITH 1kHz INPUT The ADS7807 can acquire and convert 16 bits to within
● ±10V, 0V TO +5V, AND 0V TO +4V INPUT RANGES ±1.5LSB in 25µs max while consuming only 35mW max.
Laser trimmed scaling resistors provide standard industrial
● SINGLE +5V SUPPLY OPERATION
input ranges of ±10V and 0V to +5V. In addition, a 0V to +4V
● PARALLEL AND SERIAL DATA OUTPUT range allows development of complete single-supply sys-
● PIN-COMPATIBLE WITH THE 12-BIT ADS7806 tems.
● USES INTERNAL OR EXTERNAL REFERENCE The ADS7807 is available in a 0.3" DIP-28 and SO-28, both
● 0.3" DIP-28 AND SO-28 fully specified for operation over the industrial –40°C to
+85°C temperature range.

R/C
Clock CS
Successive Approximation Register and Control Logic
BYTE
Power
Down

40kΩ CDAC
R1IN

BUSY
Parallel
Serial Data
20kΩ 40kΩ and
10kΩ Clock
R2IN Comparator Serial
Data Serial Data
CAP Out
Parallel Data
Buffer 8

6kΩ
Internal Reference
REF
+2.5V Ref Power-Down

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 1992-2006, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
Analog Inputs: R1IN ........................................................................... ±12V
R2IN .......................................................................... ±5.5V DISCHARGE SENSITIVITY
CAP .................................. VANA + 0.3V to AGND2 – 0.3V
REF ......................................... Indefinite Short to AGND2, This integrated circuit can be damaged by ESD. Texas Instru-
Momentary Short to VANA ments recommends that all integrated circuits be handled with
Ground Voltage Differences: DGND, AGND1, and AGND2 ............. ±0.3V
VANA ....................................................................................................... 7V appropriate precautions. Failure to observe proper handling
VDIG to VANA ...................................................................................... +0.3V and installation procedures can cause damage.
VDIG ........................................................................................................ 7V
Digital Inputs ............................................................. –0.3V to VDIG + 0.3V ESD damage can range from subtle performance degrada-
Maximum Junction Temperature ................................................... +165°C tion to complete device failure. Precision integrated circuits
Internal Power Dissipation ............................................................. 825mW may be more susceptible to damage because very small
Lead Temperature (soldering, 10s) ............................................... +300°C
parametric changes could cause the device not to meet its
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” published specifications.
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION(1)
MINIMUM
MAXIMUM SPECIFIED SIGNAL-TO-
INTEGRAL NO MISSING (NOISE + SPECIFIED
LINEARITY CODE LEVEL DISTORTION) PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT ERROR (LSB) (LSB) RATIO (DB) PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
ADS7807P ±3 15 83 DIP-28 NT –40°C to +85°C ADS7807P ADS7807P Tubes, 13
ADS7807PB ±1.5 16 86 " " " ADS7807PB ADS7807PB Tubes, 13
ADS7807U ±3 15 83 SO-28 DW –40°C to +85°C ADS7807U ADS7807U Tubes, 28
" " " " " " " " ADS7807U/1K Tape and Reel, 1000
ADS7807UB ±1.5 16 86 " " " ADS7807UB ADS7807UB Tubes, 28
" " " " " " " " ADS7807UB/1K Tape and Reel, 1000

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at
www.ti.com.

ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

ADS7807P, U ADS7807PB, UB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

RESOLUTION 16 ✻ Bits

ANALOG INPUT
Voltage Ranges ±10, 0 to +5, 0 to +4 V
Impedance (See Table I)
Capacitance 45 ✻ pF

THROUGHPUT SPEED
Conversion Time 20 ✻ µs
Complete Cycle Acquire and Convert 25 ✻ µs
Throughput Rate 40 ✻ kHz
DC ACCURACY
Integral Linearity Error ±3 ±1.5 LSB(1)
Differential Linearity Error +3, –2 +1.5, –1 LSB
No Missing Codes 15 16 Bits
Transition Noise(2) 0.8 ✻ LSB
Gain Error ±0.2 ±0.1 %
Full-Scale Error(3,4) ±0.5 ±0.25 %
Full-Scale Error Drift ±7 ±5 ppm/°C
Full-Scale Error(3,4) Ext. 2.5000V Ref ±0.5 ±0.25 %
Full-Scale Error Drift Ext. 2.5000V Ref ±0.5 ✻ ppm/°C
Bipolar Zero Error(3) ±10V Range ±10 ✻ mV
Bipolar Zero Error Drift ±10V Range ±0.5 ✻ ppm/°C
Unipolar Zero Error(3) 0V to 5V, 0V to 4V Ranges ±3 ✻ mV
Unipolar Zero Error Drift 0V to 5V, 0V to 4V Ranges ±0.5 ✻ ppm/°C
Recovery Time to Rated Accuracy 2.2µF Capacitor to CAP 1 ✻ ms
from Power-Down(5)
Power-Supply Sensitivity +4.75V < VS < +5.25V ±8 ✻ LSB
(VDIG = VANA = VS)

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ELECTRICAL CHARACTERISTICS (Cont.)
At TA = –40°C to +85°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

ADS7807P, U ADS7807PB, UB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

AC ACCURACY
Spurious-Free Dynamic Range fIN = 1kHz, ±10V 90 100 96 ✻ dB(6)
Total Harmonic Distortion fIN = 1kHz, ±10V –100 –90 ✻ –96 dB
Signal-to-(Noise + Distortion) fIN = 1kHz, ±10V 83 88 86 ✻ dB
–60dB Input 30 32 dB
Signal-to-Noise fIN = 1kHz, ±10V 83 88 86 ✻ dB
Usable Bandwidth(7) 130 ✻ kHz
Full-Power Bandwidth (–3dB) 600 ✻ kHz

SAMPLING DYNAMICS
Aperture Delay 40 ✻ ns
Aperture Jitter 20 ✻ ps
Transient Response FS Step 5 ✻ µs
Over-Voltage Recovery(8) 750 ✻ ns

REFERENCE
Internal Reference Voltage No Load 2.48 2.5 2.52 ✻ ✻ ✻ V
Internal Reference Source Current 1 ✻ µA
(Must use external buffer.)
Internal Reference Drift 8 ✻ ppm/°C
External Reference Voltage Range 2.3 2.5 2.7 ✻ ✻ ✻ V
for Specified Linearity
External Reference Current Drain External 2.5000V Ref 100 ✻ µA

DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.8 ✻ ✻ V
VIH(9) +2.0 VD + 0.3V ✻ ✻ V
IIL VIL = 0V ±10 ✻ µA
IIH VIH = 5V ±10 ✻ µA

DIGITAL OUTPUTS Parallel 16 bits in 2-bytes; Serial

Data Format Binary Two’s Complement or Straight Binary
Data Coding
VOL ISINK = 1.6mA +0.4 ✻ V
VOH ISOURCE = 500µA +4 ✻ V
Leakage Current High-Z State, ±5 ✻ µA
VOUT = 0V to VDIG
Output Capacitance High-Z State 15 ✻ pF

DIGITAL TIMING
Bus Access Time RL = 3.3kΩ, CL = 50pF 83 ✻ ns
Bus Relinquish Time RL = 3.3kΩ, CL = 10pF 83 ✻ ns
POWER SUPPLIES
Specified Performance
VDIG Must be ≤ VANA +4.75 +5 +5.25 ✻ ✻ ✻ V
VANA +4.75 +5 +5.25 ✻ ✻ ✻ V
IDIG 0.6 ✻ mA
IANA 5.0 ✻ mA
Power Dissipation VANA = VDIG = 5V, fS = 40kHz 28 35 ✻ ✻ mW
REFD HIGH 23 ✻ mW
PWRD and REFD HIGH 50 ✻ µW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻ ✻ °C
Derated Performance –55 +125 ✻ ✻ °C
Storage –65 +150 ✻ ✻ °C
Thermal Resistance (θJA)
DIP 75 ✻ °C/W
SO 75 ✻ °C/W
✻ Same specifications as ADS7807P, U.
NOTES: (1) LSB means Least Significant Bit. One LSB for the ±10V input range is 305µV.
(2) Typical rms noise at worst-case transition.
(3) As measured with fixed resistors, see Figure 7b. Adjustable to zero with external potentiometer.
(4) Full-scale error is the worst case of –Full-Scale or +Full-Scale untrimmed deviation from ideal first and last code transitions, divided by the
transition voltage (not divided by the full-scale range) and includes the effect of offset error.
(5) This is the time delay after the ADS7807 is brought out of Power-Down mode until all internal settling occurs and the analog input is acquired to
rated accuracy. A Convert command after this delay will yield accurate results.
(6) All specifications in dB are referred to a full-scale input.
(7) Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB.
(8) Recovers to specified performance after 2 • FS input overvoltage.
(9) The minimum VIH level for the DATACLK signal is 3V.

ADS7807 3
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PIN DESCRIPTIONS
DIGITAL
PIN # NAME I/O DESCRIPTION
1 R1IN Analog Input. See Figure 7.
2 AGND1 Analog Sense Ground.
3 R2IN Analog Input. See Figure 7.
4 CAP Reference Buffer Output. 2.2µF tantalum capacitor to ground.
5 REF Reference Input/Output. 2.2µF tantalum capacitor to ground.
6 AGND2 Analog Ground
7 SB/BTC I Selects Straight Binary or Binary Two’s Complement for Output Data Format.
8 EXT/INT I External/Internal data clock select.
9 D7 O Data Bit 7 if BYTE is HIGH. Data bit 15 (MSB) if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Leave
unconnected when using serial output.
10 D6 O Data Bit 6 if BYTE is HIGH. Data bit 14 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
11 D5 O Data Bit 5 if BYTE is HIGH. Data bit 13 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
12 D4 O Data Bit 4 if BYTE is HIGH. Data bit 12 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
13 D3 O Data Bit 3 if BYTE is HIGH. Data bit 11 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
14 DGND Digital Ground
15 D2 O Data Bit 2 if BYTE is HIGH. Data bit 10 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
16 D1 O Data Bit 1 if BYTE is HIGH. Data bit 9 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
17 D0 O Data Bit 0 (LSB) if BYTE is HIGH. Data bit 8 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
18 DATACLK I/O Data Clock Output when EXT/INT is LOW. Data clock input when EXT/INT is HIGH.
19 SDATA O Serial Output Synchronized to DATACLK
20 TAG I Serial Input When Using an External Data Clock
21 BYTE I Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH) on parallel output pins.
22 R/C I With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C
enables the parallel output.
23 CS I Internally OR’d with R/C. If R/C is LOW, a falling edge on CS initiates a new conversion. If EXT/INT is LOW, this same
falling edge will start the transmission of serial data results from the previous conversion.
24 BUSY O At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs
have been updated.
25 PWRD I PWRD HIGH shuts down all analog circuitry except the reference. Digital circuitry remains active.
26 REFD I REFD HIGH shuts down the internal reference. External reference will be required for conversions.
27 VANA Analog Supply. Nominally +5V. Decouple with 0.1µF ceramic and 10µF tantalum capacitors.
28 VDIG Digital Supply. Nominally +5V. Connect directly to pin 27. Must be ≤ VANA.

PIN CONFIGURATION ANALOG CONNECT R1IN CONNECT R2IN

INPUT VIA 200Ω VIA 100Ω
Top View DIP, SO RANGE TO TO IMPEDANCE
±10V VIN CAP 45.7kΩ
0V to 5V AGND VIN 20.0kΩ
R1IN 1 28 VDIG 0V to 4V VIN VIN 21.4kΩ

AGND1 2 27 VANA
TABLE I. Input Range Connections. See Figure 7.
R2IN 3 26 REFD

CAP 4 25 PWRD

REF 5 24 BUSY

AGND2 6 23 CS

SB/BTC 7 22 R/C
ADS7807
EXT/INT 8 21 BYTE

D7 9 20 TAG

D6 10 19 SDATA

D5 11 18 DATACLK

D4 12 17 D0

D3 13 16 D1

DGND 14 15 D2

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TYPICAL CHARACTERISTICS
At TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

FREQUENCY SPECTRUM FREQUENCY SPECTRUM

(8192 Point FFT; fIN = 1kHz, 0dB) (8192 Point FFT; fIN = 15kHz, 0dB)
0 0
–10 –10
–20 –20
–30 –30

Amplitude (dB)
Amplitude (dB)

–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
–110 –110
–120 –120
–130 –130
0 5 10 15 20 0 5 10 15 20
Frequency (kHz) Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY (fIN = 0dB) vs INPUT FREQUENCY AND INPUT AMPLITUDE
100 100

90 90
0dB
80 80
–20dB
70 70
SINAD (dB)
SINAD (dB)

60 60

50 50

40 40
–60dB
30 30

20 20

10 10
100 1k 10k 100k 1M 0 2 4 6 8 10 12 14 16 18 20
Input Signal Frequency (Hz) Input Signal Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE AC PARAMETERS vs TEMPERATURE

(fIN = 1kHz, 0dB; fS = 10kHz to 40kHz) (fIN = 1kHz, 0dB)
100 110 –80

SFDR
SFDR, SINAD, and SNR (dB)

95 105 –85
10kHz
30kHz
20kHz 100 –90
SINAD (dB)

90
THD (dB)

40kHz
95 –95
85 SNR THD
90 –100

80
85 –105
SINAD
75 80 –110
–75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C)

ADS7807 5
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, and using internal reference and fixed resistors (see Figure 7b), unless otherwise specified.

POWER-SUPPLY RIPPLE SENSITIVITY

LINEARITY ERROR vs CODE INL/DNL DEGRADATION PER LSB OF P-P RIPPLE
3 1
2
16-Bit (LSBs)

Linearity Degradation (LSB/LSB)

1
10–1
0
–1
–2 10–2
All Codes INL
–3 INL

3
10–3
2
16-Bit (LSBs)

1
0 10–4
–1
–2 DNL
All Codes DNL 10–5
–3
0 8192 16384 24576 32768 40960 49152 57344 65535 101 102 103 104 105 106 107
Decimal Code Power-Supply Ripple Frequency (Hz)

ENDPOINT ERRORS (20V Bipolar Range) ENDPOINT ERRORS (Unipolar Ranges)

mV From Ideal

mV From Ideal
3 3
2 BPZ Error 2 UPO Error
1 1
0 0
–1 –1
–2 –2
0.20 0.40
From Ideal

From Ideal
Percent

Percent

0 0.20
+FS Error +FS Error (4V Range)
–0.20 0
0.20 0.40
–FS Error –FS Error (5V Range)
From Ideal

From Ideal
Percent

Percent

0.20
0
0
–0.20
–75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C)

INTERNAL REFERENCE VOLTAGE vs TEMPERATURE CONVERSION TIME vs TEMPERATURE

2.520

2.515 19.4

2.510
Internal Reference (V)

Conversion Time (µs)

19.2
2.505

2.500 19

2.495
18.8
2.490

2.485 18.6
2.480
–75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C)

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BASIC OPERATION output valid data from the previous conversion on SDATA
(pin 19) synchronized to 16 clock pulses output on DATACLK
PARALLEL OUTPUT (pin 18). BUSY (pin 24) will go LOW and stay LOW until the
Figure 1a shows a basic circuit to operate the ADS7807 with conversion is completed and the serial data has been trans-
a ±10V input range and parallel output. Taking R/C (pin 22) mitted. Data will be output in BTC format, MSB first, and will
LOW for a minimum of 40ns (12µs max) will initiate a be valid on both the rising and falling edges of the data clock.
conversion. BUSY (pin 24) will go LOW and stay LOW until BUSY going HIGH can be used to latch the data. All convert
the conversion is completed and the output register is up- commands will be ignored while BUSY is LOW.
dated. If BYTE (pin 21) is LOW, the eight Most Significant The ADS7807 will begin tracking the input signal at the end
Bits (MSBs) will be valid when BUSY rises; if BYTE is HIGH, of the conversion. Allowing 25µs between convert com-
the eight Least Significant Bits (LSBs) will be valid when mands assures accurate acquisition of a new signal.
BUSY rises. Data will be output in Binary Two’s Complement The offset and gain are adjusted internally to allow external
(BTC) format. BUSY going HIGH can be used to latch the trimming with a single supply. The external resistors compen-
data. After the first byte has been read, BYTE can be toggled sate for this adjustment and can be left out if the offset and
allowing the remaining byte to be read. All convert com- gain will be corrected in software (refer to the Calibration
mands will be ignored while BUSY is LOW. section).
The ADS7807 will begin tracking the input signal at the end
of the conversion. Allowing 25µs between convert com-
mands assures accurate acquisition of a new signal. STARTING A CONVERSION
The offset and gain are adjusted internally to allow external The combination of CS (pin 23) and R/C (pin 22) LOW for a
trimming with a single supply. The external resistors compen- minimum of 40ns puts the sample-and-hold of the ADS7807
sate for this adjustment and can be left out if the offset and gain in the hold state and starts conversion ‘n’. BUSY (pin 24) will
will be corrected in software (refer to the Calibration section). go LOW and stay LOW until conversion ‘n’ is completed and
the internal output register has been updated. All new con-
SERIAL OUTPUT vert commands during BUSY LOW will be ignored. CS and/
or R/C must go HIGH before BUSY goes HIGH, or a new
Figure 1b shows a basic circuit to operate the ADS7807 with conversion will be initiated without sufficient time to acquire
a ±10V input range and serial output. Taking R/C (pin 22) a new signal.
LOW for 40ns (12µs max) will initiate a conversion and

Parallel Output Serial Output

200Ω
±10V
200Ω
1 28
0.1µF 10µF ±10V 1 28
2 27 + + +5V 0.1µF 10µF
66.5kΩ +5V
2 27 + +
3 26 66.5kΩ
100Ω +5V 3 26
4 25
2.2µF BUSY 100Ω
+ + 5 24 4 25
+5V 2.2µF 2.2µF BUSY
Convert Pulse
6 23 + + 5 24
R/C 2.2µF
7 22 Convert Pulse
ADS7807 6 23
BYTE
8 21 R/C
40ns min 7 22
9 20 ADS7807
8 21
10 19 40ns min
NC(1)
NC(1) 9 20
11 18
SDATA
12 17 NC(1) 10 19
DATACLK
13 16 NC(1) 11 18

14 15 NC(1) 12 17 NC(1)

NC(1) 13 16 NC(1)

Pin 21 B15 B14 B13 B12 B11 B10 B9 B8 14 15 NC(1)

LOW (MSB)

Pin 21 B7 B6 B5 B4 B3 B2 B1 B0
HIGH (LSB)

NOTE: (1) These pins should be left unconnected.

NOTE: (1) SDATA (pin 19) is always active. They will be active when R/C is HIGH.

FIGURE 1a. Basic ±10V Operation, both Parallel and Serial FIGURE 1b. Basic ±10V Operation with Serial Output.
Output.

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The ADS7807 will begin tracking the input signal at the end CS and R/C are internally OR’ed and level triggered. There
of the conversion. Allowing 25µs between convert com- is not a requirement which input goes LOW first when
mands assures accurate acquisition of a new signal. Refer to initiating a conversion. If, however, it is critical that CS or R/C
Tables II and III for a summary of CS , R/C, and BUSY states, initiates conversion ‘n’, be sure the less critical input is LOW
and Figures 2 through 6 for timing diagrams. at least 10ns prior to the initiating input. If EXT/INT (pin 8) is
LOW when initiating conversion ‘n’, serial data from conver-
CS R/C BUSY OPERATION sion ‘n – 1’ will be output on SDATA (pin 19) following the
1 X X None. Databus is in Hi-Z state.
start of conversion ‘n’. See Internal Data Clock in the Read-
ing Data section.
↓ 0 1 Initiates conversion ‘n’. Databus remains
in Hi-Z state. To reduce the number of control pins, CS can be tied LOW
0 ↓ 1 Initiates conversion ‘n’. Databus enters Hi-Z using R/C to control the read and convert modes. This will
state. have no effect when using the internal data clock in the serial
0 1 ↑ Conversion ‘n’ completed. Valid data from output mode. The parallel output and the serial output (only
conversion ‘n’ on the databus.
when using an external data clock), however, will be affected
↓ 1 1 Enables databus with valid data from
whenever R/C goes HIGH. Refer to the Reading Data
conversion ‘n’.
section.
↓ 1 0 Enables databus with valid data from
conversion ‘n – 1’(1). Conversion n in progress.
0 ↑ 0 Enables databus with valid data from
conversion ‘n – 1’(1). Conversion ‘n’ in progress.
READING DATA
0 0 ↑ New conversion initiated without acquisition The ADS7807 outputs serial or parallel data in Straight Binary
of a new signal. Data will be invalid. CS and/or (SB) or Binary Two’s Complement data output format. If
R/C must be HIGH when BUSY goes HIGH.
SB/BTC (pin 7) is HIGH, the output will be in SB format, and
X X 0 New convert commands ignored. Conversion
if LOW, the output will be in BTC format. Refer to Table IV for
‘n’ in progress.
ideal output codes.
NOTE: (1) See Figures 2 and 3 for constraints on data valid from
conversion ‘n – 1’. The parallel output can be read without affecting the internal
output registers; however, reading the data through the serial
TABLE II. Control Functions When Using Parallel Output
port will shift the internal output registers one bit per data
(DATACLK tied LOW, EXT/INT tied HIGH).

CS R/C BUSY EXT/INT DATACLK OPERATION

↓ 0 1 0 Output Initiates conversion ‘n’. Valid data from conversion ‘n – 1’ clocked out on SDATA.
0 ↓ 1 0 Output Initiates conversion ‘n’. Valid data from conversion ‘n – 1’ clocked out on SDATA.
↓ 0 1 1 Input Initiates conversion ‘n’. Internal clock still runs conversion process.
0 ↓ 1 1 Input Initiates conversion ‘n’. Internal clock still runs conversion process.
↓ 1 1 1 Input Conversion ‘n’ completed. Valid data from conversion ‘n’ clocked out on SDATA synchronized
to external data clock.
↓ 1 0 1 Input Valid data from conversion ‘n – 1’ output on SDATA synchronized to external data clock.
Conversion ‘n’ in progress.
0 ↑ 0 1 Input Valid data from conversion ‘n – 1’ output on SDATA synchronized to external data clock.
Conversion ‘n’ in progress.
0 0 ↑ X X New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C
must be HIGH when BUSY goes HIGH.
X X 0 X X New convert commands ignored. Conversion ‘n’ in progress.
NOTE: (1) See Figures 4, 5, and 6 for constraints on data valid from conversion ‘n – 1’.

TABLE III. Control Functions When Using Serial Output.

DESCRIPTION ANALOG INPUT DIGITAL OUTPUT

BINARY TWO’S COMPLEMENT STRAIGHT BINARY
Full-Scale Range ±10 0V to 5V 0V to 4V
(SB/BTC LOW) (SB/BTC HIGH)
Least Significant Bit (LSB) 305µV 76µV 61µV
HEX HEX
BINARY CODE CODE BINARY CODE CODE
+Full-Scale (FS – 1LSB) 9.999695V 4.999924V 3.999939V 0111 1111 1111 1111 7FFF 1111 1111 1111 1111 FFFF
Midscale 0V 2.5V 2V 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000
One LSB Below Midscale –305µV 2.499924V 1.999939V 1111 1111 1111 1111 FFFF 0111 1111 1111 1111 7FFF
–Full-Scale –10V 0V 0V 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000

TABLE IV. Output Codes and Ideal Input Voltages.

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clock pulse. As a result, data can be read on the parallel port PARALLEL OUTPUT (AFTER A CONVERSION)
prior to reading the same data on the serial port, but data After conversion ‘n’ is completed and the output registers
cannot be read through the serial port prior to reading the have been updated, BUSY (pin 24) will go HIGH. Valid data
same data on the parallel port. from conversion ‘n’ will be available on D7-D0 (pins 9-13 and
15-17). BUSY going high can be used to latch the data. Refer
PARALLEL OUTPUT to Table V and Figures 2 and 3 for timing constraints.
To use the parallel output, tie EXT/INT (pin 8) HIGH and
DATACLK (pin 18) LOW. SDATA (pin 19) should be left PARALLEL OUTPUT (DURING A CONVERSION)
unconnected. The parallel output will be active when R/C (pin After conversion ‘n’ has been initiated, valid data from con-
22) is HIGH and CS (pin 23) is LOW. Any other combination version ‘n – 1’ can be read and will be valid up to 12µs after
of CS and R/C will tri-state the parallel output. Valid conver- the start of conversion ‘n’. Do not attempt to read data
sion data can be read in two 8-bit bytes on D7-D0 (pins 9-13 beyond 12µs after the start of conversion ‘n’ until BUSY (pin
and 15-17). When BYTE (pin 21) is LOW, the 8 most signifi- 24) goes HIGH; this may result in reading invalid data. Refer
cant bits will be valid with the MSB on D7. When BYTE is to Table V and Figures 2 and 3 for timing constraints.
HIGH, the 8 least significant bits will be valid with the LSB on
D0. BYTE can be toggled to read both bytes within one
conversion cycle.
Upon initial power up, the parallel output will contain indeter-
minate data.

t1 t1

R/C

t3 t3
t4
BUSY t5

t6 t6
t7 t8

MODE Acquire Convert Acquire Convert

t12 t12
t11
t10
Parallel Previous Previous High Previous Low High Byte Low Byte High Byte
Hi-Z Not Valid Hi-Z
Data Bus High Byte Valid Byte Valid Byte Valid Valid Valid Valid
t2 t9
t9 t12 t12 t12 t12

BYTE

FIGURE 2. Conversion Timing with Parallel Output (CS and DATACLK tied LOW, EXT/INT tied HIGH).

t21 t21 t21 t21 t21 t21

R/C

t1
CS

t3
t4
BUSY

t21 t21 t21 t21

BYTE

DATA
Hi-Z State High Byte Hi-Z State Low Byte Hi-Z State
BUS
t12 t9 t12 t9

FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.

ADS7807 9
SBAS022D www.ti.com
 SYMBOL DESCRIPTION MIN TYP MAX UNITS
INTERNAL DATA CLOCK
(During a Conversion)
t1 Convert Pulse Width 0.04 12 µs
t2(1) Data Valid Delay after R/C LOW 18 20 µs To use the internal data clock, tie EXT/INT (pin 8) LOW. The
t3(1) BUSY Delay from combination of R/C (pin 22) and CS (pin 23) LOW will initiate
Start of Conversion 12 85 ns
conversion ‘n’ and activate the internal data clock (typically
t4(1) BUSY LOW 18 20 µs
t5 BUSY Delay after 90 ns 900kHz clock rate). The ADS7807 will output 16 bits of valid
End of Conversion data, MSB first, from conversion ‘n-1’ on SDATA (pin 19),
t6 Aperture Delay 40 ns synchronized to 16 clock pulses output on DATACLK (pin 18).
t7(1) Conversion Time 18 20 µs The data will be valid on both the rising and falling edges of the
t8(1) Acquisition Time 5 7 µs
internal data clock. The rising edge of BUSY (pin 24) can be
t9 Bus Relinquish Time 10 83 ns
t10 BUSY Delay after Data Valid 20 60 ns used to latch the data. After the 16th clock pulse, DATACLK will
t11(1) Previous Data Valid 12 18 µs remain LOW until the next conversion is initiated, while SDATA
after Start of Conversion will go to whatever logic level was input on TAG (pin 20) during
t12(1) Bus Access Time and BYTE Delay 10 83 ns the first clock pulse. Refer to Table V and Figure 4.
t13(1) Start of Conversion 2.4 µs
to DATACLK Delay
t14(1) DATACLK Period 0.6 0.82 0.85 µs EXTERNAL DATA CLOCK
t15(1) Data Valid to DATACLK 150 200 ns
HIGH Delay
To use an external data clock, tie EXT/INT (pin 8) HIGH. The
t16(1) Data Valid after DATACLK 150 200 ns external data clock is not a conversion clock; it can only be
LOW Delay used as a data clock. To enable the output mode of the
t17 External DATACLK Period 100 ns ADS7807, CS (pin 23) must be LOW and R/C (pin 22) must
t18 External DATACLK LOW 40 ns
be HIGH. DATACLK must be HIGH for 20% to 70% of the
t19 External DATACLK HIGH 50 ns
t20 CS and R/C to External 25 ns
total data clock period; the clock rate can be between DC and
DATACLK Setup Time 10MHz. Serial data from conversion ‘n’ can be output on
t21 R/C to CS Setup Time 10 ns SDATA (pin 19) after conversion ‘n’ is completed or during
t22(1) Valid Data after DATACLK HIGH 2 12 ns conversion ‘n + 1’.
t7 + t8 Throughput Time 25 µs
An obvious way to simplify control of the converter is to tie
DIP (NT) PACKAGE ONLY TIMING
CS LOW and use R/C to initiate conversions.
t2 Data Valid Delay after R/C LOW 19 20 µs
While this is perfectly acceptable, there is a possible problem
t3 BUSY Delay from 85 ns
Start of Conversion
when using an external data clock. At an indeterminate point
t4 BUSY LOW 19 20 µs from 12µs after the start of conversion ‘n’ until BUSY rises,
t7 Conversion Time 19 20 µs the internal logic will shift the results of conversion ‘n’ into the
t8 Acquisition Time 5 µs output register. If CS is LOW, R/C HIGH, and the external
t11 Previous Data Valid 12 19 µs
clock is HIGH at this point, data will be lost. So, with CS
after Start of Conversion
t12 Bus Access Time and BYTE Delay 83 ns
LOW, either R/C and/or DATACLK must be LOW during this
t13 Start of Conversion 1.4 µs period to avoid losing valid data.
to DATACLK Delay
t14 DATACLK Period 1.1 µs
t15 Data Valid to DATACLK 20 75 ns
EXTERNAL DATA CLOCK
HIGH Delay (After a Conversion)
t16 Data Valid after DATACLK 400 600 ns After conversion ‘n’ is completed and the output registers
LOW Delay
have been updated, BUSY (pin 24) will go HIGH. With CS
t22 Valid Data after DATACLK HIGH 25 ns
LOW and R/C HIGH, valid data from conversion ‘n’ will be
NOTE: (1) See the bottom part of this table if using the DIP (NT) package.
output on SDATA (pin 19) synchronized to the external data
TABLE V. Conversion and Data Timing. TA = –40°C to +85°C. clock input on DATACLK (pin 18). The MSB will be valid on
the first falling edge and the second rising edge of the
external data clock. The LSB will be valid on the 16th falling
SERIAL OUTPUT edge and 17th rising edge of the data clock. TAG (pin 20) will
Data can be clocked out with the internal data clock or an input a bit of data for every external clock pulse. The first bit
external data clock. When using serial output, be careful with input on TAG will be valid on SDATA on the 17th falling edge
the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these and the 18th rising edge of DATACLK; the second input bit
pins will come out of Hi-Z state whenever CS (pin 23) is LOW will be valid on the 18th falling edge and the 19th rising edge,
and R/C (pin 22) is HIGH. The serial output can not be tri- etc. With a continuous data clock, TAG data will be output on
stated and is always active. Refer to the Applications SDATA until the internal output registers are updated with
Information section for specific serial interfaces. the results from the next conversion. Refer to Table V and
Figure 5.

10
ADS7807
www.ti.com SBAS022D
 t7 + t8
CS or R/C(1)

t14

t13 1 2 3 15 16 1 2
DATACLK

t16
t15

MSB Valid Bit 14 Valid Bit 13 Valid Bit 1 Valid LSB Valid MSB Valid Bit 14 Valid
SDATA

(Results from previous conversion.)

BUSY

NOTE: (1) If controlling with CS , tie R/C LOW. Data bus pins will remain Hi-Z at all times.
If controlling with R/C, tie CS LOW. Data bus pins will be active when R/C is HIGH, and should be left unconnected.

FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).

t17
t18 t19
0 1 2 3 4 16 17 18

EXTERNAL
DATACLK
t20
t1 t20

CS t22

t21

R/C
t21
t3

BUSY

SDATA Bit 15 (MSB) Bit 14 Bit 1 Bit 0 (LSB) Tag 0 Tag 1

TAG Tag 0 Tag 1 Tag 2 Tag 15 Tag 16 Tag 17 Tag 18

FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT Tied HIGH) Read after Conversion.

ADS7807 11
SBAS022D www.ti.com
EXTERNAL DATA CLOCK INPUT RANGES
(During a Conversion)
The ADS7807 offers three input ranges: standard ±10V and
After conversion ‘n’ has been initiated, valid data from con-
0V-5V, and a 0V-4V range for complete, single-supply sys-
version ‘n – 1’ can be read and will be valid up to 12µs after
tems. See Figures 7a and 7b for the necessary circuit
the start of conversion ‘n’. Do not attempt to clock out data
connections for implementing each input range and optional
from 12µs after the start of conversion ‘n’ until BUSY (pin 24)
offset and gain adjust circuitry. Offset and full-scale error(1)
rises; this will result in data loss. NOTE: For the best possible
specifications are tested with the fixed resistors, see Figure
performance when using an external data clock, data should
7b. Adjustments for offset and gain are described in the
not be clocked out during a conversion. The switching noise
Calibration section of this data sheet.
of the asynchronous data clock can cause digital feedthrough
degrading the converter’s performance. Refer to Table V and The offset and gain are adjusted internally to allow external
Figure 6. trimming with a single supply. The external resistors compen-
sate for this adjustment and can be left out if the offset and
gain will be corrected in software (refer to the Calibration
TAG FEATURE
section).
TAG (pin 20) inputs serial data synchronized to the external
The input impedance, summarized in Table II, results from
or internal data clock.
the combination of the internal resistor network (see the front
When using an external data clock, the serial bit stream input page of this product data sheet) and the external resistors
on TAG will follow the LSB output on SDATA until the internal used for each input range (see Figure 8). The input resistor
output register is updated with new conversion results. See divider network provides inherent over-voltage protection to
Table V and Figures 5 and 6. at least ±5.5V for R2IN and ±12V for R1IN.
The logic level input on TAG for the first rising edge of the Analog inputs above or below the expected range will yield
internal data clock will be valid on SDATA after all 16 bits of either positive full-scale or negative full-scale digital outputs,
valid data have been output. respectively. Wrapping or folding over for analog inputs
outside the nominal range will not occur.
NOTE: (1) Full-scale error includes offset and gain errors measured at both
+FS and –FS.

t17
t18 t19

EXTERNAL
DATACLK
t20

CS t22

t21
t20

R/C

t1

t11

BUSY

t3

DATA Bit 15 (MSB) Bit 0 (LSB) Tag 0 Tag 1

TAG Tag 0 Tag 1 Tag 16 Tag 17 Tag 18

FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT tied HIGH) Read During a Conversion.

12
ADS7807
www.ti.com SBAS022D
CALIBRATION SOFTWARE CALIBRATION
To calibrate the offset and gain in software, no external
HARDWARE CALIBRATION
resistors are required. However, to get the data sheet speci-
To calibrate the offset and gain of the ADS7807 in hardware, fications for offset and gain, the resistors shown in Figure 7b
install the resistors shown in Figure 7a. Table VI lists the are necessary. See the No Calibration section for more
hardware trim ranges relative to the input for each input details on the external resistors. Refer to Table VIII for the
range. range of offset and gain errors with and without the external
resistors.
OFFSET ADJUST GAIN ADJUST
INPUT RANGE RANGE (mV) RANGE (mV) NO CALIBRATION
±10V ±15 ±60
Figure 7b shows circuit connections. Note that the actual
0 to 5V ±4 ±30 voltage dropped across the external resistors is at least two
0 to 4V ±3 ±30 orders of magnitude lower than the voltage dropped across
TABLE VI. Offset and Gain Adjust Ranges for Hardware the internal resistor divider network. This should be consid-
Calibration (see Figure 7a). ered when choosing the accuracy and drift specifications of
the external resistors. In most applications, 1% metal-film
resistors will be sufficient.

±10V 0V-5V 0V-4V

33.2kΩ
200Ω
200Ω 1
1 R1IN
VIN R1IN 1
R1IN
2 2 200Ω
AGND1 33.2kΩ AGND1
2
VIN AGND1
3 3
R2IN VIN R2IN
100Ω 100Ω 3
+5V R2IN
4 4 100Ω
33.2kΩ + CAP CAP +5V
+5V 2.2µF +
2.2µF 4
50kΩ + CAP
5 5 2.2µF
50kΩ REF
50kΩ REF 50kΩ
+ 50kΩ 5
1MΩ 2.2µF +
1MΩ 2.2µF REF
+5V 6 50kΩ +
AGND2 6 1MΩ 2.2µF
AGND2
6
AGND2

FIGURE 7a. Circuit Diagrams (With Hardware Trim).

±10V 0V-5V 0V-4V

33.2kΩ
200Ω 200Ω
1 1
VIN R1IN R1IN
1
R1IN
2 2 200Ω
AGND1 33.2kΩ AGND1
2
VIN AGND1
66.5kΩ
3 3
+5V R2IN VIN R2IN
100Ω 3
100Ω R2IN
4 4 100Ω
+ CAP + CAP
2.2µF 2.2µF 4
+ CAP
5 5 2.2µF
REF REF
+ + 5
2.2µF 2.2µF REF
6 6 +
AGND2 AGND2 2.2µF
6
AGND2

FIGURE 7b. Circuit Diagrams (Without Hardware Trim).

ADS7807 13
SBAS022D www.ti.com
The external resistors (see Figure 7b) may not be necessary which reduces the input signal to a 0.3125V to 2.8125V input
in some applications. These resistors provide compensation range at the Capacitor Digital-to-Analog Converter (CDAC).
for an internal adjustment of the offset and gain which allows The internal resistors are laser trimmed to high relative accu-
calibration with a single supply. Not using the external racy to meet full scale specifications. The actual input imped-
resistors will result in offset and gain errors in addition to ance of the internal resistor network looking into pin 1 or pin
those listed in the Electrical Characteristics section. Offset 3 however, is only accurate to ±20% due to process variations.
refers to the equivalent voltage of the digital output when This should be taken into account when determining the
converting with the input grounded. A positive gain error effects of removing the external resistors.
occurs when the equivalent output voltage of the digital
output is larger than the analog input. Refer to Table VII for
nominal ranges of gain and offset errors with and without the
REFERENCE
external resistors. Refer to Figure 8 for typical shifts in the The ADS7807 can operate with its internal 2.5V reference or
transfer functions which occur when the external resistors an external reference. By applying an external reference to
are removed. pin 5, the internal reference can be bypassed; REFD (pin 26)
To further analyze the effects of removing any combination of tied HIGH will power-down the internal reference reducing
the external resistors, consider Figure 9. The combination of the overall power consumption of the ADS7807 by approxi-
the external and the internal resistors form a voltage divider mately 5mW.

OFFSET ERROR GAIN ERROR

WITH RESISTORS WITHOUT RESISTORS WITH RESISTORS WITHOUT RESISTORS

INPUT
RANGE (V) RANGE (mV) RANGE (mV) TYP (mV) RANGE (% FS) RANGE (% FS) TYP

±10 –10 ≤ BPZ ≤ 10 0 ≤ BPZ ≤ 35 15 –0.4 ≤ G ≤ 0.4 –0.3 ≤ G ≤ 0.5 +0.05

0.15 ≤ G(1) ≤ 0.15 –0.1 ≤ G(1) ≤ 0.2 +0.05
0 to 5 –3 ≤ UPO ≤ 3 –12 ≤ UPO ≤ –3 –7.5 –0.4 ≤ G ≤ 0.4 –1.0 ≤ G ≤ 0.1 –0.2
0.15 ≤ G(1) ≤ 0.15 –0.55 ≤ G(1) ≤ –0.05 –0.2
0 to 4 –3 ≤ UPO ≤ 3 –10.5 ≤ UPO ≤ –1.5 –6 –0.4 ≤ G ≤ 0.4 –1.0 ≤ G ≤ 0.1 –0.2
–0.15 ≤ G(1) ≤ 0.15 –0.55 ≤ G(1) ≤ –0.05 –0.2
NOTE: (1) High Grade.

TABLE VII. Range of Offset and Gain Errors With and Without External Resistors.

(a) Bipolar (b) Unipolar

Digital Output Digital Output

+Full-Scale +Full-Scale

Analog Input

–Full-Scale

Analog Input
–Full-Scale

Typical Transfer Functions Typical Transfer Functions

With External Resistors Without External Resistors

FIGURE 8. Typical Transfer Functions With and Without External Resistors.

14
ADS7807
www.ti.com SBAS022D
 200Ω 39.8kΩ
VIN CDAC
(0.3125V to 2.8125V)

66.5kΩ 9.9kΩ 20kΩ 40kΩ

+5V

100Ω +2.5V

+2.5V

200Ω 39.8kΩ
CDAC
(0.3125V to 2.8125V)
33.2kΩ
100Ω 9.9kΩ 20kΩ 40kΩ
VIN

+2.5V +2.5V

200Ω 39.8kΩ
VIN CDAC
(0.3125V to 2.8125V)
33.2kΩ
100Ω 9.9kΩ 20kΩ 40kΩ

+2.5V +2.5V

FIGURE 9. Circuit Diagrams Showing External and Internal Resistors.

The internal reference has approximately an 8ppm/°C drift REF

(typical) and accounts for approximately 20% of the full-scale REF (pin 5) is an input for an external reference or the output
error (FSE = ±0.5% for low grade, ±0.25% for high grade). for the internal 2.5V reference. A 2.2µF tantalum capacitor
The ADS7807 also has an internal buffer for the reference should be connected as close as possible to the REF pin
voltage. Figure 10 shows characteristic impedances at the from ground. This capacitor and the output resistance of REF
input and output of the buffer with all combinations of power- create a low-pass filter to bandlimit noise on the reference.
down and reference down. Using a smaller value capacitor will introduce more noise to
the reference, degrading the SNR and SINAD. The REF pin
should not be used to drive external AC or DC loads, as
ZCAP shown in Figure 10.
CAP
CDAC The range for the external reference is 2.3V to 2.7V and
(Pin 4)
determines the actual LSB size. Increasing the reference
voltage will increase the full-scale range and the LSB size of
Buffer
the converter which can improve the SNR.
REF Internal
(Pin 5) Reference
ZREF CAP
CAP (pin 4) is the output of the internal reference buffer. A
PWRD 0 PWRD 0 PWRD 1 PWRD 1 2.2µF tantalum capacitor should be placed as close as
REFD 0 REFD 1 REFD 0 REFD 1
possible to the CAP pin from ground to provide optimum
ZCAP (Ω) 1 1 200 200 switching currents for the CDAC throughout the conversion
ZREF (Ω) 6k 100M 6k 100M cycle. This capacitor also provides compensation for the
output of the buffer. Using a capacitor any smaller than 1µF
FIGURE 10. Characteristic Impedances of Internal Buffer. can cause the output buffer to oscillate and may not have
sufficient charge for the CDAC. Capacitor values larger than
2.2µF will have little affect on improving performance. See
Figures 10 and 11.

ADS7807 15
SBAS022D www.ti.com
The output of the buffer is capable of driving up to 1mA of LAYOUT
current to a DC load. Using an external buffer will allow the
internal reference to be used for larger DC loads and AC POWER
loads. Do not attempt to directly drive an AC load with the For optimum performance, tie the analog and digital power
output voltage on CAP. This will cause performance degra- pins to the same +5V power supply and tie the analog and
dation of the converter. digital grounds together. As noted in the electrical character-
istics, the ADS7807 uses 90% of its power for the analog
circuitry. The ADS7807 should be considered as an analog
7000 component.
6000 The +5V power for the A/D converter should be separate
5000 from the +5V used for the system’s digital logic. Connecting
VDIG (pin 28) directly to a digital supply can reduce converter
4000
performance due to switching noise from the digital logic. For
µs

3000 best performance, the +5V supply can be produced from

2000
whatever analog supply is used for the rest of the analog
signal conditioning. If +12V or +15V supplies are present, a
1000
simple +5V regulator can be used. Although it is not sug-
0 gested, if the digital supply must be used to power the
0.1 1 10 100 converter, be sure to properly filter the supply. Either using a
“CAP” Pin Value (µF)
filtered digital supply or a regulated analog supply, both VDIG
and VANA should be tied to the same +5V source.
FIGURE 11. Power-Down to Power-Up Time vs Capacitor
Value on CAP. GROUNDING
Three ground pins are present on the ADS7807. DGND is the
digital supply ground. AGND2 is the analog supply ground.
REFERENCE AGND1 is the ground to which all analog signals internal to the
AND POWER-DOWN A/D converter are referenced. AGND1 is more susceptible to
current induced voltage drops and must have the path of
The ADS7807 has analog power-down and reference power least resistance back to the power supply.
down capabilities via PWRD (pin 25) and REFD (pin 26),
All the ground pins of the A/D converter should be tied to an
respectively. PWRD and REFD HIGH will power-down all
analog ground plane, separated from the system’s digital
analog circuitry maintaining data from the previous conver-
logic ground, to achieve optimum performance. Both analog
sion in the internal registers, provided that the data has not
and digital ground planes should be tied to the “system”
already been shifted out through the serial port. Typical
ground as near to the power supplies as possible. This helps
power consumption in this mode is 50µW. Power recovery is
to prevent dynamic digital ground currents from modulating
typically 1ms, using a 2.2µF capacitor connected to CAP.
the analog ground through a common impedance to power
Figure 11 shows power-down to power-up recovery time
ground.
relative to the capacitor value on CAP. With +5V applied to
VDIG, the digital circuitry of the ADS7807 remains active at all
times, regardless of PWRD and REFD states. SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS
PWRD A/D converters release a significant amount of charge injec-
tion which can cause the driving op amp to oscillate. The
PWRD HIGH will power-down all of the analog circuitry
amount of charge injection due to the sampling FET switch
except for the reference. Data from the previous conversion
on the ADS7807 is approximately 5% to 10% of the amount
will be maintained in the internal registers and can still be
on similar A/D converters with the charge redistribution
read. With PWRD HIGH, a convert command yields mean-
Digital-to-Analog Converter (DAC) CDAC architecture. There
ingless data.
is also a resistive front end which attenuates any charge
which is released. The end result is a minimal requirement for
REFD the drive capability on the signal conditioning preceding the
REFD HIGH will power-down the internal 2.5V reference. All A/D converter. Any op amp sufficient for the signal in an
other analog circuitry, including the reference buffer, will be application will be sufficient to drive the ADS7807.
active. REFD should be HIGH when using an external The resistive front end of the ADS7807 also provides a speci-
reference to minimize power consumption and the loading fied ±25V over-voltage protection. In most cases, this elimi-
effects on the external reference. See Figure 10 for the nates the need for external over-voltage protection circuitry.
characteristic impedance of the reference buffer’s input for
both REFD HIGH and LOW. The internal reference con-
sumes approximately 5mW.

16
ADS7807
www.ti.com SBAS022D
INTERMEDIATE LATCHES
The ADS7807 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will 581
be active during conversions. If the bus is not active during
conversion, the tri-state outputs can be used to isolate the
A/D converter from other peripherals on the same bus.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7807 has an internal LSB size of 38µV.
Transients from fast switching signals on the parallel port,
even when the A/D converter is tri-stated, can be coupled
through the substrate to the analog circuitry causing degra-
dation of converter performance.
173 176

APPLICATIONS INFORMATION
TRANSITION NOISE 52
Apply a DC input to the ADS7807 and initiate 1000 conver- 0 18 0
sions. The digital output of the converter will vary in output
FFFDH FFFEH FFFFH 0000H 0001H 0002H 0003H
codes due to the internal noise of the ADS7807. This is true
for all 16-bit SAR converters. The transition noise specifica-
tion found in the Electrical Characteristics section is a
statistical figure which represents the one sigma limit or rms FIGURE 12. Histogram of 1000 Conversions with Input Grounded.
value of these output codes.
Using a histogram to plot the output codes, the distribution
should appear bell-shaped with the peak of the bell curve
representing the nominal output code for the input voltage
value. The ±1σ, ±2σ, and ±3σ distributions will represent 5671
68.3%, 95.5%, and 99.7% of all codes. Multiplying TN by 6
will yield the ±3σ distribution or 99.7% of all codes. Statisti-
cally, up to 3 codes could fall outside the 5 code distribution
when executing 1000 conversions. The ADS7807 has a TN
of 0.8LSBs which yields 5 output codes for a ±3σ distribution.
Figures 12 and 13 show 1000 and 10000 conversion histo-
gram results.

AVERAGING 2010
1681
The noise of the converter can be compensated by averag- 176
ing the digital codes. By averaging conversion results, tran-
sition noise will be reduced by a factor of 1/√Hz where n is
438
the number of averages. For example, averaging four con-
18 182 0
version results will reduce the TN by 1/2 to 0.4LSBs. Aver-
aging should only be used for input signals with frequencies FFFDH FFFEH FFFFH 0000H 0001H 0002H 0003H
near DC.
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
FIGURE 13. Histogram of 10000 Conversions with Input Grounded.
manner to averaging: for every decimation by 2, the signal-
to-noise ratio will improve 3dB.

ADS7807 17
SBAS022D www.ti.com
QSPI™ INTERFACING
QSPI™ ADS7807
+5V
Figure 14 shows a simple interface between the ADS7807
and any QSPI equipped microcontroller. This interface as- PCS0 R/C EXT/INT
sumes that the convert pulse does not originate from the
PCS1 CS
microcontroller and that the ADS7807 is the only serial
peripheral. SCK DATACLK

MISO D7 (MSB)

Convert Pulse

BYTE
CPOL = 0
QSPI™ ADS7807
CPHA = 0

R/C QSPI is a registered trademark of Motorola.

PCS0/SS BUSY
FIGURE 15. QSPI Interface to the ADS7807. Processor
MOSI SDATA
Initiates Conversions.
SCK DATACLK

CS For both transfers, the DT register (delay after transfer) is

used to cause a 19µs delay. The interface is also set up to
EXT/INT
wrap to the beginning of the queue. In this manner, the QSPI
CPOL = 0 (Inactive State is LOW)
BYTE is a state machine which generates the appropriate timing for
CPHA = 1 (Data valid on falling edge)
QSPI port is in slave mode. the ADS7807. This timing is thus locked to the crystal-based
timing of the microcontroller and not interrupt driven. So, this
QSPI is a registered trademark of Motorola. interface is appropriate for both AC and DC measurements.
For the fastest conversion rate, the baud rate should be set
to 2 (4.19MHz SCK), DT set to 10, the first serial transfer set
FIGURE 14. QSPI Interface to the ADS7807.
to 8 bits, the second set to 16 bits, and DSCK disabled (in the
Before enabling the QSPI interface, the microcontroller must command control byte). This will allow for a 23kHz maximum
be configured to monitor the slave select line. When a conversion rate. For slower rates, DT should be increased.
transition from LOW to HIGH occurs on Slave Select (SS) Do not slow SCK as this may increase the chance of
from BUSY (indicating the end of the current conversion), the affecting the conversion results or accidently initiating a
port can be enabled. If this is not done, the microcontroller second conversion during the first 8-bit transfer.
and the A/D converter may be “out-of-sync”. In addition, CPOL and CPHA should be set to zero (SCK
Figure 15 shows another interface between the ADS7807 normally LOW and data captured on the rising edge). The
and a QSPI equipped microcontroller which allows the micro- command control byte for the 8-bit transfer should be set to
controller to give the convert pulses while also allowing 20H and for the 16-bit transfer to 61H.
multiple peripherals to be connected to the serial bus. This
interface and the following discussion assume a master clock SPI™ INTERFACE
for the QSPI interface of 16.78MHz. Notice that the serial
data input of the microcontroller is tied to the MSB (D7) of the The SPI interface is generally only capable of 8-bit data
ADS7807 instead of the serial output (SDATA). Using D7 transfers. For some microcontrollers with SPI interfaces, it
instead of the serial port offers tri-state capability which might be possible to receive data in a similar manner as
allows other peripherals to be connected to the MISO pin. shown for the QSPI interface in Figure 14. The microcontroller
When communication is desired with those peripherals, PCS0 will need to fetch the 8 most significant bits before the
and PCS1 should be left HIGH; that will keep D7 tri-stated. contents are overwritten by the least significant bits.

In this configuration, the QSPI interface is actually set to do A modified version of the QSPI interface shown in Figure 15
two different serial transfers. The first, an 8-bit transfer, causes might be possible. For most microcontrollers with SPI inter-
PCS0 (R/C) and PCS1 (CS ) to go LOW, starting a conver- face, the automatic generation of the start-of-conversion
sion. The second, a 16-bit transfer, causes only PCS1 (CS ) to pulse will be impossible and will have to be done with
go LOW. This is when the valid data will be transferred. software. This will limit the interface to ‘DC’ applications due
to the insufficient jitter performance of the convert pulse
QSPI is a registered trademark of Motorola.
itself.

SPI is a registered trademark of Motorola.

18
ADS7807
www.ti.com SBAS022D
DSP56000 INTERFACING
The DSP56000 serial interface has SPI compatibility mode
with some enhancements. Figure 16 shows an interface
between the ADS7807 and the DSP56000 which is very Convert Pulse
similar to the QSPI interface seen in Figure 14. As mentioned
in the QSPI section, the DSP56000 must be programmed to
enable the interface when a LOW to HIGH transition on SC1 DSP56000 ADS7807
is observed (BUSY going HIGH at the end of conversion).
R/C
The DSP56000 can also provide the convert pulse by includ-
ing a monostable multi-vibrator, as seen in Figure 17. The SC1 BUSY
receive and transmit sections of the interface are decoupled SRD SDATA
(asynchronous mode) and the transmit section is set to
SCO DATACLK
generate a word length frame sync every other transmit
frame (frame rate divider set to 2). The prescale modulus CS
should be set to 3. EXT/INT
The monostable multi-vibrator in this circuit will provide
BYTE
varying pulse widths for the convert pulse. The pulse width
will be determined by the external R and C values used with
SYN = 0 (Asychronous)
the multi-vibrator. The 74HCT123N data sheet shows that GCK = 1 (Gated clock)
the pulse width is (0.7) RC. Choosing a pulse width as close SCD1 = 0 (SC1 is an input)
SHFD = 0 (Shift MSB first)
to the minimum value specified in this data sheet will offer the
WL1 = 1 WL0 = 0 (Word length = 16 bits)
best performance. See the Starting A Conversion section
of this data sheet for details on the conversion pulse width.
The maximum conversion rate for a 20.48MHz DSP56000 is
exactly 40kHz. Note that this will not be the case for the
ADS7806. See the ADS7806 data sheet (SBAS021B) for FIGURE 16. DSP56000 Interface to the ADS7807.
more information.

+5V 74HCT123N +5V

DSP56000
R
B1 REXT1
C
SC2 CLR1 CEXT1 ADS7807

A1 Q1 R/C

SC0 DATACLK

SRD SDATA

CS

EXT/INT

BYTE

SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
SCD2 = 1 (SC2 is an output)
SHFD = 0 (Shift MSB first)
WL1 = 1 WL0 = 0 (Word length = 16 bits)

FIGURE 17. DSP56000 Interface to the ADS7807. Processor Initiates Conversions.

ADS7807 19
SBAS022D www.ti.com
 Revision History

DATE REVISION PAGE SECTION DESCRIPTION

2 Electrical Characteristics Changed Analog Input Capacitance from 35pF to 45pF.
11/06 D
10 Table V Updated Table V and added PDIP package timing; page layout reflowed.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

20
ADS7807
www.ti.com SBAS022D
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ADS7807U ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 ADS7807U

ADS7807U/1K ACTIVE SOIC DW 28 1000 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 ADS7807U

ADS7807UB ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 ADS7807U
B
ADS7807UBG4 ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 ADS7807U
B
ADS7807UE4 ACTIVE SOIC DW 28 20 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 ADS7807U

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7807U/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7807U/1K SOIC DW 28 1000 350.0 350.0 66.0

Pack Materials-Page 2
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