LM5026 Active Clamp Current Mode PWM Controller: 1 Features 3 Description
LM5026 Active Clamp Current Mode PWM Controller: 1 Features 3 Description
LM5026 Active Clamp Current Mode PWM Controller: 1 Features 3 Description
LM5026
SNVS363E – AUGUST 2005 – REVISED NOVEMBER 2015
CS
VCC CS
LM5026
VIN
UVLO OUT_A
TIME OUT_B
RES
REF ERROR
RT AMP and
COMP ISOLATION
DCL SYNC
SS
PGND AGND
SYNC I/O
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5026
SNVS363E – AUGUST 2005 – REVISED NOVEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 12
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 19
3 Description ............................................................. 1 8 Application and Implementation ........................ 20
4 Revision History..................................................... 2 8.1 Application Information............................................ 20
8.2 Typical Application ................................................. 25
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 29
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 29
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 29
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 30
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 31
6.5 Electrical Characteristics........................................... 5 11.1 Community Resources.......................................... 31
6.6 Typical Characteristics .............................................. 8 11.2 Trademarks ........................................................... 31
7 Detailed Description ............................................ 11 11.3 Electrostatic Discharge Caution ............................ 31
7.1 Overview ................................................................. 11 11.4 Glossary ................................................................ 31
7.2 Functional Block Diagram ....................................... 11 12 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
VCC 7 10 PGND
OUT_A 8 9 OUT_B
Pin Functions
PIN
TYPE (1) DESCRIPTION
NO. NAME
Input voltage source. Input to the start-up regulator. Operating input range is 13 V to 100 V
1 VIN I with transient capability to 105 V. For power sources outside of this range, the LM5026 can
be biased directly at VCC by an external regulator.
Line undervoltage lockout. An external voltage divider from the power source sets the
shutdown and standby comparator levels. When UVLO reaches the 0.4-V threshold the VCC
2 UVLO I
and REF regulators are enabled. At the 1.25-V threshold the SS pin is released and the
device enters the active mode.
Current Sense input for current mode control and current limit. If CS exceeds 0.5 V, the
3 CS I output pulse will be terminated, entering cycle-by-cycle current limit. An internal switch holds
CS low for 100 nS after OUT_A switches high to blank leading edge transients.
Restart Timer. If cycle-by-cycle current limit is reached during any cycle, a 10-µA current is
sourced to the RES pin capacitor. If the RES capacitor voltage reaches 2.5 V, the soft-start
4 RES I capacitor will be fully discharged and then released with a pullup current of 1 µA. After the
first output pulse at OUT_A (when SS = 1.4 V), the SS pin charging current will revert back
to 50 µA.
Gate drive overlap or deadtime control. An external resistor (RSET) sets either the overlap
time or deadtime for the active clamp output. An RSET resistor connected between TIME
5 TIME I and AGND produces in-phase OUT_A and OUT_B pulses with overlap. An RSET resistor
connected between TIME and REF produces out-of-phase OUT_A and OUT_B pulses with
deadtime.
Output of 5-V reference. Maximum output current is 10 mA. Locally decouple with a 0.1-µF
6 REF O
capacitor.
Output of the high voltage start-up regulator. The VCC voltage is regulated to 7.6 V. If an
7 VCC P auxiliary winding raises the voltage on this pin above the regulation setpoint, the internal
start-up regulator will shutdown, thus reducing the IC power dissipation.
Main output driver. Output of the main switch PWM gate driver. Capable of 3-A peak sink
8 OUT_A O
current.
Active clamp output driver. Output of the active clamp switch gate driver. Capable of 0.5-A
9 OUT_B O
peak source and sink current.
10 PGND G Power ground. Connect directly to analog cround.
11 AGND G Analog return. Connect directly to power cround.
Soft-start. An external capacitor and an internal 50-µA current source set the soft-start ramp.
12 SS I The SS current source is reduced to 1 µA following a restart event. The soft-stop discharge
current is 50 µA.
Input to the pulse width modulator. The external optocoupler connected to the COMP pin
sources current into an internal NPN current mirror. The PWM duty cycle is maximum with
13 COMP I
zero input current, while 1 mA reduces the duty cycle to zero. The current mirror improves
the frequency response by reducing the ac voltage across the optocoupler detector.
6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
See .
MIN MAX UNIT
VIN to GND –0.3 105 V
VCC to GND –0.3 16 V
CS to GND –0.3 1 V
COMP input current 10 mA
All other inputs to GND –0.3 7 V
Junction temperature 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) Minimum and maximum limits are 100% production tested at 25ºC. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). All
electrical characteristics having room temperature limits are tested during production with TA = TJ = 25°C. All hot and cold limits are
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) Device thermal limitations may limit usable range.
Copyright © 2005–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM5026
LM5026
SNVS363E – AUGUST 2005 – REVISED NOVEMBER 2015 www.ti.com
CURRENT LIMIT
OSCILLATOR
TJ = 25°C 200
Frequency1 RT = 30 kΩ over full operating junction kHz
180 220
temperature range
TJ = 25°C 590
Frequency2 RT = 10 kΩ over full operating junction kHz
520 660
temperature range
SYNC source current 200 µA
SYNC sink
Can sync up to 5 like controllers minimum 100 Ω
impedance
Sync threshold
1.4 V
(falling)
Sync pulse width
over full operating junction temperature range 15 ns
minimum
PWM COMPARATOR
Delay-to-output CS stepped, time to onset of OUT_A transition low 40 ns
Mimimum duty cycle ICOMP = 1 mA, over full operating junction temperature range 0%
Maximum duty cycle
UVLO = 1.3 V, COMP = open, VDCL = 2.5 V 80%
limit 1
Maximum duty cycle
UVLO = 1.3 V, COMP = open, VDCL = VRT × 0.875 70%
limit 2
16 10
14
VIN
8
12
10
6
VCC (V)
VCC (V)
8
VCC
6 4
4
2
2
0 0
0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 35
VIN (V) ICC (mA)
Figure 1. VCC Regulator Start-Up Characteristics, VCC vs VIN Figure 2. VCC vs ICC
6 54 1.4
48 1.1
3
46 1.0
2 RESTART
44 0.9
1 42 0.8
0 40 0.7
0 5 10 15 20 25 -50 -25 0 25 50 75 100 125 150
206
204
202
200
198
196
194
192
190
-50 0 50 100 150
TEMPERATURE (oC)
350 115
RSET to AGND
300 110
OVERLAP TIME (ns)
200 100
150 95
100 90
RSET = 34.8 k:
50 85
0 80
0 20 40 60 80 100 120 -50 -25 0 25 50 75 100 125 150
350 115
RSET to REF
300 110
DEADTIME (ns)
200 100
150 95
100 90
RSET = 30.0 k:
50 85
0 80
0 20 40 60 80 100 120 -50 -25 0 25 50 75 100 125 150
70 70
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Figure 11. Max Duty Cycle vs UVLO Figure 12. Max Duty Cycle vs DCL
600
125°C
500
400
300
-0.10 0.00 0.10 0.20 0.30 0.40 0.50
7 Detailed Description
7.1 Overview
The LM5026 PWM controller contains all of the features necessary to implement power converters utilizing the
active clamp reset technique with current mode control. With the active clamp reset, higher efficiencies and
greater power densities can be realized compared to conventional catch winding or RDC clamp reset techniques.
The LM5026 provides two control outputs, the main power switch control (OUT_A) and the active clamp switch
control (OUT_B). The device can be configured to drive either a P-Channel or N-Channel clamp switch. The
main switch gate driver features a compound configuration consisting of both MOS and bipolar devices, which
provide superior gate drive characteristics. The LM5026 can be configured to operate with bias voltages over a
wide input range from 8 V to 100 V. Additional features include programmable maximum duty cycle, line
undervoltage lockout, cycle-by-cycle current limit, hiccup mode fault protection with adjustable delays, PWM
slope compensation, soft-start, a 1-MHz capable oscillator with synchronization input and output capability,
precision reference, and thermal shutdown.
7.6V BIAS
VIN REGULATOR VCC
1.25V
LOGIC
HYSTERESIS (20 PA)
SHUTDOWN
VCC
THERMAL
0.4V/0.3V LIMIT
OUT_A
DRIVER
RT CLK
OSCILLATOR
AND
SYNC DUTY CYCLE
LIMITER
DCL DEADTIME TIME
OR
OVERLAP
CONTROL
S Q
SLOPE COMP
VCC
5V RAMP
45 PA R
0 OUT_B
5k DRIVER
COMP
2R
PWM PGND
1.4V R
1:1
AGND
SS CURRENT 5V
CS 2k LIMIT
CURRENT
LIMITING
0.5V (10 PA)
OUT_A + LEB
CURRENT LIMIT
RESTART RES
5V TIMER
5V &
SS CONTROL
RESTART
DELAY SOFT-START
(1 PA) NOT
SS (50 PA) CURRENT
SS LIMITING
(10 PA)
SOFT-STOP
(50 PA)
OUT_A
OUT_B
OUT_A
OUT_B
The rising edge overlap or deadtime and the falling edge overlap or deadtime are identical and are independent
of operating frequency or duty cycle. The magnitude of the overlap/deadtime can be calculated in Equation 1 and
Equation 2:
Overlap Time = 2.8 × RSET + 2
where
• RSET in kΩ
• overlap is in ns (1)
.
Deadtime = 2.9 × RSET + 14
where
• RSET in kΩ
• deadtime is in ns (2)
VCC
LM5026
PWM
OUT_A
PGND
5k
_ COMP 1.4V
2R PWM
COMPARATOR
Potential across Opto- R
LM431 coupler detector is 1:1
FB constant
SOFT-START
LM5026
For duty cycles greater than 50 percent, current mode control circuits are subject to sub-harmonic oscillation. By
adding an additional fixed slope voltage ramp signal (slope compensation) to the current sense signal, this
oscillation can be avoided. The LM5026 integrates this slope compensation by summing a current ramp
generated by the oscillator with the current sense signal. The PWM comparator ramp signal is a combination of
the current waveform at the CS pin, and an internally generated slope compensation ramp derived from the
oscillator. The internal ramp has an amplitude of 0 to 45 µA which is sourced into an internal 2-kΩ resistor, plus
the external impedance at the CS pin. Additional slope compensation may be added by increasing the source
impedance of the current sense signal.
RT
OSCILLATOR
FREQUENCY
RT1
INVERSELY
PROPORTIONAL DCL
TO: RT1 + RT2
AGND
LM5026
Figure 17. Programming Oscillator Frequency and Maximum Duty Cycle Clamp
Line Voltage Duty Cycle Limiter - The maximum duty cycle for the main output driver is also limited by the
voltage at the UVLO pin, which is normally proportional to VIN. The controller outputs are disabled until the
UVLO pin voltage exceeds 1.25 V. At the minimum operating voltage (when UVLO = 1.25 V) the maximum duty
cycle starts at the duty cycle clamp level programmed by the DCL pin voltage (80% or less). As the line voltage
increases, the maximum duty cycle decreases linearly with increasing UVLO voltage, as shown in Figure 18.
Ultimately the duty cycle of the main output is controlled to the least of the following three variables: the duty
cycle controlled by the PWM comparator, the programmable maximum duty cycle clamp, or the line voltage
dependent duty cycle limiter.
100
Programmable
MAXIMUM DUTY CYCLE (%)
60 Line Voltage
Duty Cycle Limiter
40
20
1.25V
0
0 1.0 2.0 3.0 4.0 5.0
RES
0V
5.0V
50 PA
SS
1 PA
# 1.4V
OUTA
t1 t2 t3
LM5026
SYNC
AGND
LM5026
SYNC
LM5026
SYNC
UP TO 5 TOTAL
DEVICES
Multiple LM5026 devices can be synchronized together simply by connecting the devices SYNC pins together as
shown in Figure 21. Take care to ensure the ground potential differences between devices are minimized. In this
configuration all of the devices will be synchronized to the highest frequency device. The internal block diagram
of the oscillator and synchronization circuit is shown in Figure 22. The SYNC I/O pin is a CMOS buffer with
pullup current limited to 200 µA. If an external device forces the SYNC pin low before the internal oscillator ramp
completes its charging cycle, the ramp will be reset and another cycle begins. If the SYNC pins of multiple
LM5026 devices are connected together, the first SYNC pin that pulls low will reset the oscillator RAMP of all
other devices. All controllers will operate in phase when synchronized using the SYNC I/O feature. Up to five
LM5026 devices can be synchronized using this technique.
SYNC
200P
I = f (RT)
2V
Q S
Q R
CLK
DEADTIME
ONE-SHOT
UVLO
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
50
VIN
0.1 PF
LM5026
8V - 15V (from
0.1 VIN VCC aux winding)
9V
C1
LM5026
where
• VPWR is the desired turnon voltage (7)
For example, if the LM5026 is to be enabled when VPWR reaches 33 V, and disabled when VPWR is decreased to
30 V, R1 calculates to 150 kΩ, and R2 calculates to 5.9 kΩ. The voltage at the UVLO pin should not exceed 6 V
at any time. Be sure to check both the power and voltage rating for the selected R1 resistor.
Remote configuration of the controller’s operational modes can be accomplished with open drain device(s)
connected to the UVLO pin as shown in Figure 27.
VPWR
LM5026 20 PA
R1
UVLO
Enable Output
Drivers 1.25V
R2
VPWR
LM5026 20 PA R1
UVLO
Enable
1.25V OFF
R2
STANDBY
Standby
0.4V
VIN
RF
CS
LM5026 R1
CF
AGND
Q1
Q2
OUTA
OUTB
Power
Transformer
VPWR
VIN
LM5026 Q1 Q2
OUTA
RF
CS
CF
R1
AGND
OUTB
R1A
LM5026
20 PA
R1B
UVLO Z1
1.25V R2
Max. Duty
Cycle Limiter
VPWR
Z1
LM5026 20 PA
R1
UVLO
1.25V R2
Max. Duty
Cycle Limiter
1
Input Voltage = 48VDC
Output Current = 5 A
Input Voltage = 78VDC Synchronous Rectifier, Q3 Gate V/div = 5 V Trance 1
Output Current = 25 A Synchronous Rectifier, Q3 Gate V/div = 5 V Trance 2
Trace 1: Q1 Drain Voltage V/div = 20 V Synchronous Rectifier, Q5 Gate V/div = 5 V
Horizontal Resolution = 1 µs/div Horizontal Resolution = 1 µs/div
10 Layout
REF decoupling
capacitor Connect the exposed
thermal pad to the
system ground plane
VCC decoupling
capacitor Short AGND and PGND
together as close as
possible to the pins
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 14-Aug-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 14-Aug-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 2
MECHANICAL DATA
NHQ0016A
SDA16A (Rev A)
www.ti.com
PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1 4.55
4.9
NOTE 3
8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 -8
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
14X (0.65)
8 9
(5.8)
4220204/A 02/2017
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
14X (0.65)
8 9
(5.8)
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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