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    HI-4850 RS-485/RS-422 Evaluation Board: August 4, 2011

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    Mx Zlr

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    HI-4850 RS-485/RS-422 Evaluation Board: August 4, 2011

    Uploaded by

    Mx Zlr
    51 views6 pages

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    Copyright:

    © All Rights Reserved
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    51 views6 pages

    HI-4850 RS-485/RS-422 Evaluation Board: August 4, 2011

    Uploaded by

    Mx Zlr

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 6

    QSG-4850

       HI-4850 RS-485/RS-422
    Evaluation Board
    August 4, 2011                      

    Introduction:
    The HI-4850 Evaluation Board allows the user to evaluate the Holt family of RS-485/RS-422
    high speed transceivers. The Evaluation Board features a 50MHz oscillator and a divider circuit
    so the transceivers can be driven at frequencies selectable from 12.2 KHz – 25 MHz.

    The transceiver Inputs and outputs are provided on terminal blocks for easy connection to
    external signals or cables. Termination resistors (120 ohm) are enabled by shunt jumpers for
    each of the transceiver inputs/outputs. The evaluation board requires external 3.3V or 5V
    power.

    Demonstration:

    A 50MHz oscillator and divider circuit provides clock signals to the transceivers to demonstrate
    the transmitters or receivers with a clock source. DIP switches allow disabling the clock signals
    going to each transceiver when an external user signal is applied. To provide a user test signal
    instead of the clock source, open the DIP switch for the desired transceiver and connect a
    signal on one or more of the DI_X pins on J2, J5, or J13 header connector. Refer to the
    schematic for circuit details.

      HOLT INTEGRATED CIRCUITS   
    QSG‐4850, Rev. NEW  1  07/11 
      QSG‐4850 

    Clock and Enables - SW1 Dip Switches


       
    SWITCH  FUNCTION  FACTORY DEFAULT 
    S1  U6 Driver Enable (DE) = Open  Open 
    S2  U3 Driver Enable (DE) = Open  Open 
    S3  U1 Driver Enable (DE) = Open  Open 
    S4  U6 Clock (DI) = Closed  Closed 
    S5  U5 Clock (DI) = Closed  Closed 
    S6  U3 Clock (DI) = Closed  Closed 
    S7  U1 Clock (DI) = Closed  Closed 
       

    DE and RE header connectors

    Three four pin headers (J2, J5 and J13) provide user connections to the DE and nRE signals for
    each transceiver. To disable any of the transmitters close the DIP switch or ground the DE
    signal on the corresponding header connector.

    PIN SIGNAL FUNCTION


    1 GND
    2 N.C
    3 DE_X High = Enables Transmitter
    4 nRE_X Low = Enables the Receiver

    Frequency Selection Jumpers

    Install one jumper select to the desired frequency. Frequencies are listed on the silkscreen next
    to the jumper headers.

    Termination Resistors

    J1, J4, J7, J9, J10 and J12 jumpers enable  120 ohm termination resistors on the transceiver 
    inputs/outputs.  

    Miscellaneous Connections:

    JUMPER  FUNCTION  FACTORY DEFAULT 


    JP1  Not Used = solder bridge  Closed  
    JP2  Disable 50 MHz Osc = solder bridge  Open 
     

      HOLT INTEGRATED CIRCUITS   
    2 
      QSG‐4850 

    Demonstration Example:

    This example configures U1 (4850/4853) as a transmitter and U3 (4850/4853) as a receiver.  The on‐ 
    board oscillator provides a 781 KHz clock source. The output of the transmitter is connected to the 
    receiver inputs using the terminal blocks.  

    Diagram of configured circuit:

     
     

      HOLT INTEGRATED CIRCUITS   
    3 
      QSG‐4850 

    1. DIP switch settings to configure U1 and U6: 

    SWITCH  FUNCTION  Demo 


    S2  U3 Driver Enable (DE) = Closed  U3 transmitter disabled 
    S3  U1 Driver Enable (DE) = Open  U1 configured as Transmitter 
    S7  U1 Clock (DI) = Closed  781KHz clock source for U1 
     

    2. Jumpers: 

    Install Jumper at J6 between posts 11‐12 for 781KHz. 

    Optionally install J4 jumper to enable R6 termination resistor on U3 receiver. 

    Both receivers will be enabled automatically since the nRE signals to the IC are pulled down 
    internally.  

    3. Connect two wires on the J3 terminal block to connect the transmitter to the receiver. 

        J3 Terminal Block Connections 
        Pin‐4 to pin‐2 (B) 
        Pin‐3 to pin‐1 (A) 
     
     
    4. Apply 3.3V or 5V at TP3 and Ground to TP2. 
     
     
    A 781KHz clock signal should be viewable at U1‐4 and on the A and B outputs of U1. The clock signal will 
    be also on the A and B inputs of U3 receiver. The receiver outputs ( RO) for both receivers will show the 
    output. This test configuration could have been duplicated easily using any pair of transceivers on the 
    board. 
     

    Conclusion:
    The Holt HI‐4850 Evaluation Board demonstrates the Holt family of RS‐485/422 transceivers and can be 
    configured for a variety of configurations to suit the user needs. 

      HOLT INTEGRATED CIRCUITS   
    4 
      QSG‐4850 

      HOLT INTEGRATED CIRCUITS   
    5 
      QSG‐4850 

    REVISION HISTORY
    P/N  Rev  Date  Description of Change
     

    QSG‐4850  NEW  08/4/11  Initial Release  


       
     
     
     

      HOLT INTEGRATED CIRCUITS   
    6 

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