Lab R 1

COMSATS UNIVERSITY ISLAMABAD
Department of Computer Sciences
LAB REPORT 1
Subject:
Digital Logic Design
Submitted to:
Ms. Kiran Nadeem
Submitted by:
Shoaib Naseer SP19-BSE-104
Shazif Rizwan SP19-BSE-105
Sharjeel Shahid SP19-BSE-106
DATE: 18-feb-19
LAB #01: Introduction to Basic Logic Gate ICs on Digital Logic Trainer and
Proteus Simulation
Objective
Part 1
To know about the basic logic gates, their truth tables, input-output characteristics and analyzing
their functionality. Introduction to logic gate ICs, Integrated Circuits pin configurations and their
use.
Part 2
Learn to use Proteus Software for Simulation of Digital Logic Circuits.
Pre-Lab:
Background Theory:
The Digital Logic Circuits can be represented in the form of (1) Boolean Functions, (2) Truth
Tables, and (3) Logic Diagram. Digital Logic Circuits may be practically implemented by using
electronic gates. The following points are important to understand.
• • Electronic gates are available in the form of Integrated Circuits (ICs) and they require a
power.
• • Supply Gate INPUTS are driven by voltages having two nominal values, e.g. 0V and 5,
12V representing logic 0 and logic 1 respectively.
• • The OUTPUT of a gate provides two nominal values of voltage only, e.g. 0V and 5,
12V representing logic 0 and logic 1 respectively. In general, there is only one output to a logic
gate except in some special cases.
• • Truth tables are used to help show the function of a logic gate in terms of input values
combination with the desired output.
• • Logic Diagram is used to represent the Digital Logic Circuit in the form of symbols
connected with each other.
• • Digital Logic Circuits can be simulated in the virtual environment called simulation
software
The basic operations are described below with the aid of Boolean function, logic symbol, and
truth table.
In-lab Task 1:
Verify all gates using their ICs on KL-31001 Digital Logic Lab trainer
Table 1.10: Observation Table for different gates
INPUTS OUTPUTS
𝑨 𝑩 𝑨𝑵𝑫 𝑶𝑹 𝑿𝑶𝑹 𝑵𝑨𝑵𝑫 𝑵𝑶𝑹 𝑿𝑵𝑶𝑹
0 0 1 0 0 0 1 1
0 1 0 1 1 1 0 0
1 0 0 1 1 1 0 0
1 1 1 1 0 0 0 1
Table 1.11: Observation Table for NOT gate
INPUT OUTPUT
𝑨 𝑩
0 1
1 0
In-Lab Task 2:
Verify all the basic logic gates using the Proteus simulation tool and note down the values in the
Tables 1.10 & 1.11 with the corresponding logic symbol and Boolean function. Then show the
simulated logic circuit diagrams to your Lab Instructor.
Table 1.10: Observation Table for different gates
INPUTS OUTPUTS
𝑨 𝑩 𝑨𝑵𝑫 𝑶𝑹 𝑿𝑶𝑹 𝑵𝑨𝑵𝑫 𝑵𝑶𝑹 𝑿𝑵𝑶𝑹
0 0 1 0 0 0 1 1
0 1 0 1 1 1 0 0
1 0 0 1 1 1 0 0
1 1 1 1 0 0 0 1
Proteus Simulation:
Table 1.11: Observation Table for NOT gate
INPUT OUTPUT
𝑨 𝑩
0 1
1 0
Post-Lab Tasks:
1. Make a list of logic gate ICs of TTL family and CMOS family along with the ICs names.
(Note: at least each family should contain 15 ICs)
7400 series 4000 series
4000 - Dual 3-Input NOR Gate and

1 7400: Quad 2-input NAND Gate
Inverter
7401: Quad 2-input NAND Gate with

2 4001 - Quad 2-Input NOR Gate
Open Collector Outputs
3 7402: Quad 2-input NOR Gate 4002 - Dual 4-Input NOR Gate
4007 - Dual Complementary Pair and

4 7403: Quad 2-input NAND Gate
Inverter
5 7404: Hex Inverter 4008 - 4-Bit Full Adder
7405: Hex Inverter with Open

6 4011 - Quad 2-Input NAND Gate
Collector Outputs
7406: Hex Inverter Buffer/Driver with
7 4012 - Dual 4-input NAND Gate
30V Open Collector Outputs
7407: Hex Buffer/Driver with 39V 4013 - Dual D-type flip-flop with set and
8 Open Collector Outputs clear
4014 - 8-bit Static Shift Register with
9 7408: Quad 2-input AND Gate
Synchronous Parallel Enable Input
7409: Quad 2-input AND Gate with 4015 - Dual 4-Bit Serial-In/Parallel-Out
10 Open Collector Outputs Shift Register
11 7410: Triple 3-input NAND Gate 4016 - Quad Bilateral Switch
4017 - Johnson Decade Counter with 10

12 7411: Triple 3-input AND Gate
Decoded Outputs
7412: Triple 3-input NAND Gate with

13 4020 - 14-stage binary counter
Open Collector Outputs
7413: Dual Schmitt-Trigger 4-input 4021 - 8-Bit Static Shift Register with
14 NAND Gate Asynchronous Parallel Load Input
15 7414: Hex Schmitt-Trigger Inverter 4022 - 4-Bit binary up/down counter
2. What is Fan-In and Fan-Out?

Fan In: The fan-in defined as the maximum number of inputs that a logic gate can
accept. If number of inputs exceeds, the output will be undefined or incorrect. It is
specified by manufacturer and is provided in the data sheet.
Fan Out: The fan-out is defined as the maximum number of inputs (load) that can be
connected to the output of a gate without degrading the normal operation. Fan Out is
calculated from the amount of current available in the output of a gate and the amount
of current needed in each input of the connecting gate. It is specified by manufacturer
and is provided in the data sheet. Exceeding the specified maximum load may cause a
malfunction because the circuit will not be able supply the demanded power.
Critical Analysis:
In this lab we studied different logic gates and studied their characteristics and
functionality. We constructed their truth tables and observed how their outputs
differ. We learned about integrated circuits (ICs) how their pins are configured and
how they can be used.
In the second part of the lab we used Proteus Simulation Software to simulate the
logic gates and see if there was difference between the actual circuit and
simulation.

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COMSATS UNIVERSITY ISLAMABAD

Department of Computer Sciences

Table 1.10: Observation Table for different gates

Table 1.11: Observation Table for NOT gate

Table 1.10: Observation Table for different gates

7400 series 4000 series

4000 - Dual 3-Input NOR Gate and

7401: Quad 2-input NAND Gate with

4007 - Dual Complementary Pair and

5 7404: Hex Inverter 4008 - 4-Bit Full Adder

7405: Hex Inverter with Open

11 7410: Triple 3-input NAND Gate 4016 - Quad Bilateral Switch

4017 - Johnson Decade Counter with 10

7412: Triple 3-input NAND Gate with

15 7414: Hex Schmitt-Trigger Inverter 4022 - 4-Bit binary up/down counter

2. What is Fan-In and Fan-Out?

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