Class D 2093
Class D 2093
Class D 2093
CAUTION:
International Rectifier suggests the following guidelines for safe operation and handling of
IRAUDAMP8 Demo board;
Applications
AV receivers
Home theater systems
Mini component stereos
Powered speakers
Sub-woofers
Musical Instrument amplifiers
Automotive after market amplifiers
Features
Specifications
General Test Conditions (unless otherwise noted) Notes / Conditions
Supply Voltages ±35V
Load Impedance 4Ω
Self-Oscillating Frequency 400kHz No input signal, Adjustable
Gain Setting 26.5dB 1Vrms input yields rated power
Physical Specifications
Dimensions 3.94”(L) x 2.83”(W) x 0.85”(H)
100 mm (L) x 72 mm (W) x 21.5 mm(H)
Weight 0.140kgm
VR1
IRS2093
IRF6665
Output Output
CH2 CH1 +B GND -B CH4 CH3
G 250W,4ΩNon-inductive
35 V, 10 A DC supply 35 V, 10 A DC supply
Connector Description
1. Connect 4-200 W dummy loads to 4 output connectors (P2 and P3 as shown on Fig 1)
and an Audio Precision analyzer (AP).
2. Connect the Audio Signal Generator to CN2 for CH1~CH4 respectively (AP).
3. Set up the dual power supply with voltages of ±35V; current limit to 10A.
4. TURN OFF the dual power supply before connecting to On of the unit under test (UUT).
5. Connect the dual power supply to P1. as shown on Fig 1
Power up:
6. Turn ON the dual power supply. The ±B supplies must be applied and removed at the
same time.
7. The Blue LED should turn ON immediately and stay ON
8. Quiescent current for the positive supply should be 100mA 10mA at +35V.
9. Quiescent current for the negative supply should be 115mA 10mA at –35V.
10. With an Oscilloscope, monitor the switching waveform at test points VS1~VS4. Adjust VR1
to set the self oscillating frequency to 400 kHz 25 kHz.
0.5
0.2
% 0.1
0.05
0.02
0.01
0.005
0.002
0.001
100m 200m 500m 1 2 5 10 20 50 100 200
W
.
+4
T
+3
+2
+1
-0
-1
d -2
B
r -3
A -4
-5
-6
-7
-8
-9
-10
20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 200k
Hz
.
+0
-10
-20
-30
-40
-50
d
-60
B
-70
-80
-90
-100
-110
-120
20 50 100 200 500 1k 2k 5k 10k 20k
Hz
Fig 9 shows efficiency characteristics of the IRAUDAMP8. The high efficiency is achieved by
following major factors:
1) Low conduction loss due to the DirectFETs offering low RDS(ON)
2) Low switching loss due to the DirectFETs offering low input capacitance for fast rise and
fall times
Secure dead-time provided by the IRS2093, avoiding cross-conduction
100%
90%
80%
Efficiency (%)
70%
60%
AMP8 35V 4ohms
50%
40%
30%
20%
10%
0%
0 50 100 150
Output power (W)
Fig 9, IRAUDAMP8 4 ohms load Stereo, ±B supply = ±35V
Thermal Considerations
With this high efficiency, the IRAUDAMP8 design can handle one-eighth of the continuous rated
power, which is generally considered to be a normal operating condition for safety standards,
without additional heatsinks or forced air-cooling.
**DirectFET’s height should be measured from PCB to the top of DirectFET after reflow. The
average height of IRF6665 is 0.6mm.
+0
-10
-20
-30
d -40
B
V -50
-60
-70
-80
-90
20 50 100 200 500 1k 2k 5k 10k 20k 40k
Hz
VS pin VS pin
Load current Load current
The IRAUDAMP8 features a 4CH self-oscillating type PWM modulator for the smallest space,
highest performance and robust design. This topology represents an analog version of a second-
order sigma-delta modulation having a Class D switching stage inside the loop. The benefit of the
sigma-delta modulation, in comparison to the carrier-signal based modulation, is that all the error
in the audible frequency range is shifted to the inaudible upper-frequency range by nature of its
operation. Also, sigma-delta modulation allows a designer to apply a sufficient amount of error
correction.
Integrator
Referring to Fig 15 below, the input operational amplifier of the IRS2093 forms a front-end second-
order integrator with R3, C2, C3, and R2. The integrator that receives a rectangular feedback
signal from the PWM output via R4 and audio input signal via R3 generates a quadratic carrier
signal at the COMP pin. The analog input signal shifts the average value of the quadratic
waveform such that the duty cycle varies according to the instantaneous voltage of the analog
input signal.
PWM Comparator
The carrier signal at the COMP pin is converted to a PWM signal by an internal comparator that
has a threshold at middle point between VAA and VSS. The comparator has no hysteresis in its
input threshold.
Level Shifters
The internal input level-shifter transfers the PWM signal down to the low-side gate driver section.
The gate driver section has another level-shifter that level shifts up the high-side gate signal to the
high-side gate driver section.
The received PWM signal is sent to the dead-time generation block where a programmable
amount of dead time is added into the PWM signal between the two gate output signals of LO and
HO to prevent potential cross conduction across the output power DirectFETs. The high-side level-
shifter shifts up the high-side gate drive signal out of the dead-time block.
Each channel of the IRS2093’s drives two DirectFETs, high- and low-sides, in the power stage
providing the amplified PWM waveform.
Output LPF
The amplified PWM output is reconstructed back to an analog signal by the output LC LPF.
Demodulation LC low-pass filter (LPF) formed by L1 and C13, filters out the Class D switching
carrier signal leaving the audio output at the speaker load. A single stage output filter can be used
with switching frequencies of 400 kHz and greater; a design with a lower switching frequency may
require an additional stage of LPF.
The IRAUDAMP8 uses the IRS2093, a 4 Channel high-voltage (up to 200 V), high-speed power
MOSFET driver with internal dead-time and protection functions specifically designed for Class D
audio amplifier applications. These functions include OCP and UVP. The IRS2093 integrates bi-
directional over current protection for both high-side and low-side MOSFETs. The dead-time can
be selected for optimized performance according to the size of the MOSFET, minimizing dead-
time while preventing shoot-through. As a result, there is no gate-timing adjustment required
externally. Selectable dead-time through the DT pin voltage is an easy and reliable function which
requires only two external resistors, R12 and R13 as shown on Fig 16 or Fig 22 below.
Self-oscillating frequency is determined by the total delay time along the control loop of the
system; the propagation delay of the IRS2093, the DirectFETs switching speed, the time-constant
of front-end integrator (R2, R3, R4, C2, C3 ). Variations in +B and –B supply voltages also affect
the self-oscillating frequency.
The self-oscillating frequency changes with the duty ratio. The frequency is highest at idling. It
drops as duty cycle varies away from 50%.
Use R2 to set different self-oscillating frequencies. The PWM switching frequency in this type of
self-oscillating switching scheme greatly impacts the audio performance, both in absolute
frequency and frequency relative to the other channels. In absolute terms, at higher frequencies,
distortion due to switching-time becomes significant, while at lower frequencies, the bandwidth of
the amplifier suffers. In relative terms, interference between channels is most significant if the
relative frequency difference is within the audible range.
Normally, when adjusting the self-oscillating frequency of the different channels, it is suggested to
either match the frequencies accurately, or have them separated by at least 25kHz. Under the
normal operating condition with no audio input signal, the switching-frequency is set around
400kHz in the IRAUDAMP8.
The dead-time of the IRS2093 is set based on the voltage applied to the DT pin. Fig 17 lists the
suggested component value for each programmable dead-time between 45 and 105 ns.
All the IRAUDAMP8 models use DT1 (45ns) dead-time.
Dead- time
IRS2093M
45nS
>0.5mA
Vcc
65nS
R1
85nS
DT
105nS
R2
0.23xVcc 0.36xVcc 0.57xVcc Vcc
VDT COM
The external shutdown circuit will disable the output by pulling down CSD pins, (Fig 19). If the
fault condition persists, the protection circuit stays in shutdown until the fault is removed.
R60
SD
15k
GND
Q5
MMBT5551
R54 Z4
10k R57 18V IC6
R51
R56 47k LM26CIM5-XHA
22k
47k 5 1
OS HT
R50 2
Z3 GND
47k R59 4 3
39V R53 VCC VT
22k
OTP
10k
R52
MMBT5551
15k
Q4 D51
MMBT5551 4.7V
Q3
R58
R55 47k
47k
OVP UVP
-B
The low-side current sensing feature protects the low side DirectFET from an overload condition
from negative load current by measuring drain-to-source voltage across RDS(ON) during its on state.
OCP shuts down the switching operation if the drain-to-source voltage exceeds a preset trip level.
The voltage setting on the OCSET pin programs the threshold for low-side over-current sensing.
When the VS voltage becomes higher than the OCSET voltage during low-side conduction, the
IRS2093 turns the outputs off and pulls CSD down to -VSS.
The high-side current sensing protects the high side DirectFET from an overload condition from
positive load current by measuring drain-to-source voltage across RDS(ON) during its on state. OCP
shuts down the switching operation if the drain-to-source voltage exceeds a preset trip level.
High-side over-current sensing monitors drain-to-source voltage of the high-side DirectFET during
the on state through the CSH and VS pins. The CSH pin detects the drain voltage with reference
to the VS pin, which is the source of the high-side DirectFET. In contrast to the low-side current
sensing, the threshold of the CSH pin to trigger OC protection is internally fixed at 1.2V. An
external resistive divider R15, R16 and R17 are used to program a threshold as shown in Fig 18.
An external reverse blocking diode D1 is required to block high voltage feeding into the CSH pin
during low-side conduction. By subtracting a forward voltage drop of 0.6V at D1, the minimum
threshold which can be set for the high-side is 0.6V across the drain-to-source.
OVP is provided externally to the IRS2093. OVP shuts down the amplifier if the bus voltage
between GND and -B exceeds 39V. The threshold is determined by a Zener diode Z3. OVP
protects the board from harmful excessive supply voltages, such as due to bus pumping at very
low frequency-continuous output in stereo mode.
UVP is provided externally to the IRS2093. UVP prevents unwanted audible noise output from
unstable PWM operation during power up and down. UVP shuts down the amplifier if the bus
voltage between GND and -B falls below a voltage set by Zener diode Z4.
The IRAUDAMP8 requires no output-offset adjustment. DC offsets are tested to be less than ±20
mV.
A Preset Thermostat IC, IC6 in Fig 17, is placed in close proximity to the heatsink which has 8
DirectFETs under it; and monitors heatsink temperature. If the heatsink temperature rises above
100 C, the OTP shuts down all 4 channels by pulling down the CSD pins of the IRS2093. OTP
recovers once the temperature has cooled down.
The internally-generated housekeeping power supplies include ±5V for analog signal processing,
and +12V supply (VCC) referred to the negative supply rail -B for DirectFET gate drive. The gate
driver section of the IRS2093 uses VCC to drive gates of the DirectFETs. VCC is referenced to –B
(negative power supply). D2, R18 and C10 form a bootstrap floating supply for the HO gate driver.
Bus Pumping
When the IRAUDAMP8 is running in stereo mode, the bus pumping effect takes place with low
frequency, high output. Since the energy flowing in the Class D switching stage is bi-directional,
there is a period where the Class D amplifier feeds energy back to the power supply. The majority
of the energy flowing back to the supply is from the energy stored in the inductor in the output LPF.
The OVP protects IRAUDAMP8 from failure in case of excessive bus pumping. One of the easiest
counter measures of bus pumping is to drive both of the channels in a stereo configuration out-of-
phase so that one channel consumes the energy flow from the other and does not return it to the
power supply. Bus voltage detection monitors only +B supply, assuming the bus pumping on the
supplies is symmetric in +B and -B supplies.
The IRAUDAMP8 has an RC network called a Zobel network (R21 and C14) to damp the
resonance and prevent peaking frequency response with light loading impedance. (Fig 21)
Gain Setting
The ratio of resistors R4A~D/R1A~D in Fig 22 sets voltage gain. The IRAUDAMP8 has no on board volume
control. To change the voltage gain, change the input resistor term R1A~D. Changing R4A~D affects PWM
control loop design and may result poor audio performance.
2.2K
GND CH3 OUTPUT 1
NC
R14A 4.7R D1B
GND 2
1N4148
C10B R16B GND 3
R10
R12
R17B D2B
22uF, 16V 3.9K CH4 OUTPUT CH4 OUTPUT 4
10K 1N4148
R15B 10K R18B
R22A
10K
R21A
R21B
0.47uF, 400V
0.47uF, 400V
GND
C9A
100K 1% 4.7R R20A Q1A
1K
IRF6665
C14A
C14B
22R
R11 8.2K
C13A
C13B
R13
R4A
100K 1% Q2A
R9A
22uF, 16V
IRF6665
47K
1N4148
36
35
34
33
32
31
30
29
28
27
26
25
22R
C10A
47K
R17A 10K
0.1uF, 63V
0.47uF, 400V
0.1uF, 63V
C19A R19A
R19B
0.47uF, 400V
C2A 2.2nF,50V C3A 2.2nF,50V
1R
1R
VCC
NC
COM
CSH4
VB4
HO4
VS4
VS3
HO3
OCSET
DT
VREF
R15A
R1A 22K
10K
R20B Q1B
R12A
C14D
C14C
C4A 37 IRF6665
R12B
0.1uF,100V
0.1uF,100V
C1A 100pF, 50V R2A 120R COMP3 24
C19B
1nF,50V VB3
D1A
R16A 22R
CH4 INPUT R3A 4.7K 38
C13D
C13C
IN3 23
10R,1W
10R,1W
2.2nF,50V CSH3 3.9K
C5A 10uF, 16V C2B C3B 2.2nF,50V GND
R21D
R21C
C12A 220pF 39 Q2B
R1B 22K R2B 120R COMP4 22 R18A R9B R24C 2.2K P2
R22D
10K
LO3 IRF6665
CN1 C1B 100pF, 50V C4B 40 D2A 4.7R CH2 OUTPUT CH1 OUTPUT 4CH2
GND IN4 21 22R
CH3 INPUT R3B 4.7K 1nF,50V LO4 1N4148 L2 GND 3
CH4 8 IC1
41 22uH GND 2
GND 7 C12B 220pF C5B 10uF, 16V R6 10R GND 20
C6 4.7uF,10V MLQP48_4CH COM2 GND CH2 OUTPUT 1CH1
CH3 6 VSS C9B
42 R24D 2.2K
GND 5 VSS -B 19 10uF,16V
0
GND NC
GND 4 VAA R14B CH1 OUTPUT
C12C 220pF C7 43 18
-B
CH2 3 R7 10R VAA NC
GND R3C 4.7K 4.7uF,10V
GND 2 4.7R
CH2 INPUT C2C R2C 44 17
CH1 1 C5C 10uF, 16V 1nF,50V C4C IN2 VCC2
R1C 22K R20C Q1C
120R C3C 45 16
C12D 220pF COMP2 LO2 R18D IRF6665
C1C 100pF, 50V 2.2nF,50V D2D
GND 2.2nF,50V 22R
R3D 4.7K 46 15 4.7R
R2D IN1 LO1
CH1 INPUT C2D C4D 1nF,50V 1N4148
C5D 10uF, 16V
1N4148
120R 47 14 Q2C
R1D 22K C3D COMP1 CSH1 R9C
2.2nF,50V R16D IRF6665
10K
C1D 100pF, 50V 2.2nF,50V 48 13 3.9K +B
47K
CSD VB1
47K
22R
CSH2
HO2
HO1
R23A C17A
VB2
VS2
VS1
R15D C17C
NC
NC
NC
NC
NC
NC
R19D
R19C
100k
22uF, 16V
10K 0.1uF,50V 1000uF,35V P1
R17D
1R
1R
D1D
R1 R20D Q1D
R22 +B 3
C10D
R12D
IRF6665
R12C
1
10
11
12
10R 22R GND GND 2
0.1uF,100V
0.1uF,100V
0R0 or N/A -B 1
CSD
R4D 1N4148
100K 1% R23B C17B
C19D
C19C
D3
Q2D
10uF, 16V
Q5
MMBT5551
+5v
C1 Q8 ZX5T853 R43
IC6
0.1uF,50V 510R,1W R51
LM26CIM5-XHA
22k
R45 5 1
OS HT
2
33k GND
R59 4 3
VCC VT
R3 Z5 22k
22k C40 5.6V
IC2 N/A R52
LTC1799
15k
VR1 1 5
VCC OUT C41 Z6 D51
10K 2
GND N/A 5.6V 4.7V
3 4
SET DIT R46
33k
Q9 R44
1 8 ZX5T953 510R,1W
1A VCC
-5v Z2
2 7 R36
1B 1Y
Z4 5.1k 15V
3 6 R54
2Y 2B 10k R57 18V R37
4 5 R56 47k IC9 47k
GND 2A 47k VCC Q1
R50 L5 220uH
1 8
IC8 Z3 47k C34 SW VIN
TC7W00FFCT-ND 39V R53 C35 R39 Q2
2 7
R31 2200pF,50V BST VCC 100k
10k 5.1k R42 MMBT5401
0.01uF, 25V 3 6
RCL RON/SD FX491
MMBT5551
3.3k
R41
4 5
120k RTN FB
C61 Q4 C32
D7
22uF, 16V
C37
0.01uF, 50V
R62 10k
GND GND
For EMI
4.5 3 3 4.5
16
10.5
1.6 12 14
12
8 27 27 10
Screw Screw
H343-ND H343-ND
Lock washer Thermal Pad Lock washer
Th l d
Screw Screw
H343-ND Stand Off 3 H343-ND Stand Off 2
1893K-ND
Lock washer Lock washer 1893K-ND
Lock washer
Lock washer
Screw Screw
Screw
Stand Off 4 Lock washers Stand Off 1
1893K-ND H729-ND 1893K-ND
Screws
H343-ND
All Gerber files stored in the attached CD-ROM were generated from Protel Altium Designer
Altium Designer 6. Each file name extension means the following:
Additional files for assembly that may not be related with Gerber files:
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 01/29/2009